LTC2414/LTC2418
8-/16-Channel
24-Bit No Latency ∆Σ™ ADCs
Features
Description
8-/16-Channel Single-Ended or 4-/8-Channel
Differential Inputs (LTC2414/LTC2418)
nn Low Supply Current (200µA, 4µA in Autosleep)
nn Differential Input and Differential Reference with
GND to VCC Common Mode Range
nn 2ppm INL, No Missing Codes
nn 2.5ppm Full-Scale Error and 0.5ppm Offset
nn 0.2ppm Noise
nn No Latency: Digital Filter Settles in a Single Cycle
Each Conversion Is Accurate, Even After a New
Channel Is Selected
nn Single Supply 2.7V to 5.5V Operation
nn Internal Oscillator—No External Components
Required
nn 110dB Min, 50Hz/60Hz Notch Filter
The LTC®2414/LTC2418 are 8-/16-channel (4-/8-differential) micropower 24-bit ∆∑ analog-to-digital converters.
They operate from 2.7V to 5.5V and include an integrated
oscillator, 2ppm INL and 0.2ppm RMS noise. They use
delta-sigma technology and provide single cycle settling
time for multiplexed applications. Through a single pin,
the LTC2414/LTC2418 can be configured for better than
110dB differential mode rejection at 50Hz or 60Hz ±2%,
or they can be driven by an external oscillator for a userdefined rejection frequency. The internal oscillator requires
no external frequency setting components.
nn
The LTC2414/LTC2418 accept any external differential
reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement applications. They
can be configured to take 4/8 differential channels or
8/16 single-ended channels. The full-scale bipolar input
range is from –0.5VREF to 0.5VREF. The reference common
mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set within GND to VCC.
The DC common mode input rejection is better than 140dB.
Applications
Direct Sensor Digitizer
Weight Scales
nn Direct Temperature Measurement
nn Gas Analyzers
nn Strain Gauge Transducers
nn Instrumentation
nn Data Acquisition
nn Industrial Process Control
nn
nn
The LTC2414/LTC2418 communicate through a flexible
4-wire digital interface that is compatible with SPI and
MICROWIRE protocols.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency �∑ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
Total Unadjusted Error
vs Input Voltage
2.7V TO 5.5V
THERMOCOUPLE
21 CH0
22 CH1
•
•
•
28 CH7
1 CH8
•
•
•
8 CH15
REF +
9
FO
16-CHANNEL
MUX
+
–
DIFFERENTIAL
24-BIT ∑ ADC
2
VCC
VCC
SDI
SCK
SDO
CS
19
20
18
17
16
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
4-WIRE
SPI INTERFACE
TUE (ppm OF VREF)
11
3
1µF
1
VCC = 5V
VREF = 5V
VINCM = VREFCM = 2.5V
FO = GND
TA = 25°C
0
TA = –45°C
–1
TA = 85°C
10 COM
–2
12 REF –
15
GND
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
LTC2418
241418 TA01a
2414/18 TA01b
241418fb
For more information www.linear.com/LTC2414
1
LTC2414/LTC2418
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC) to GND........................ –0.3V to 7V
Analog Input Voltage to GND.........–0.3V to (VCC + 0.3V)
Reference Input Voltage to GND....–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND........–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2414/LTC2418C................................... 0°C to 70°C
LTC2414/LTC2418I................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Pin Configuration
TOP VIEW
TOP VIEW
NC
1
28 CH7
CH8
1
28 CH7
NC
2
NC
3
27 CH6
CH9
2
27 CH6
26 CH5
CH10
3
NC
26 CH5
4
25 CH4
CH11
4
25 CH4
NC
5
24 CH3
CH12
5
24 CH3
NC
6
23 CH2
CH13
6
23 CH2
NC
7
22 CH1
CH14
7
22 CH1
NC
8
21 CH0
CH15
8
21 CH0
VCC
9
20 SDI
VCC
9
20 SDI
COM 10
19 FO
COM 10
19 FO
REF+ 11
18 SCK
REF+ 11
18 SCK
REF– 12
17 SDO
REF– 12
17 SDO
NC 13
16 CS
NC 13
16 CS
NC 14
15 GND
NC 14
15 GND
GN PACKAGE
28-LEAD PLASTIC SSOP
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
TJMAX = 125°C, θJA = 110°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2414CGN#PBF
LTC2414CGN#TRPBF
2414
28-Lead Plastic SSOP
0°C to 70°C
LTC2414IGN#PBF
LTC2414IGN#TRPBF
2414
28-Lead Plastic SSOP
–40°C to 85°C
LTC2418CGN#PBF
LTC2418CGN#TRPBF
2418
28-Lead Plastic SSOP
0°C to 70°C
LTC2418IGN#PBF
LTC2418IGN#TRPBF
2418
28-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
Electrical Characteristics
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5)
Integral Nonlinearity
4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
l
TYP
MAX
UNITS
24
Bits
l
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
l
2.5
10
µV
Offset Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC (Note 14)
Offset Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75 • REF+, IN– = 0.25 • REF+
Positive Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75 • REF+, IN– = 0.25 • REF+
Negative Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Total Unadjusted Error
4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V
3
3
6
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5V ≤ VCC ≤ 5.5V, REF+ = 5V, VREF– = GND,
GND ≤ IN– = IN+ ≤ 5V (Note 13)
1
µVRMS
20
2.5
l
nV/°C
12
0.03
2.5
l
ppm of VREF
ppm of VREF/°C
12
0.03
ppm of VREF
ppm of VREF/°C
converter Characteristics
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V (Note 5)
MIN
TYP
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V (Notes 5, 7)
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V (Notes 5, 8)
Input Normal Mode Rejection
60Hz ±2%
MAX
UNITS
l
130
140
l
140
dB
l
140
dB
(Notes 5, 7)
l
110
140
dB
Input Normal Mode Rejection
50Hz ±2%
(Notes 5, 8)
l
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
l
130
140
dB
Power Supply Rejection, DC
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
110
dB
Power Supply Rejection, 60Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND (Note 8)
120
dB
dB
241418fb
For more information www.linear.com/LTC2414
3
LTC2414/LTC2418
analog input and reference
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN +
Absolute/Common Mode IN+ Voltage
CONDITIONS
l
MIN
TYP
MAX
UNITS
GND – 0.3
VCC + 0.3
V
IN–
Absolute/Common Mode IN– Voltage
l
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range
(IN + – IN–)
l
–VREF/2
–VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
l
0.1
VCC
V
CS (IN+)
IN+ Sampling Capacitance
18
pF
CS (IN–)
IN– Sampling Capacitance
18
pF
CS
(REF+)
REF+ Sampling Capacitance
18
pF
CS
(REF–)
REF– Sampling Capacitance
18
pF
IDC_LEAK (IN+)
IN+ DC Leakage Current
CS = VCC = 5.5V, IN+ = GND
l
–10
1
10
nA
IDC_LEAK (IN –)
IN– DC Leakage Current
CS = VCC = 5.5V, IN– = 5V
l
–10
1
10
nA
IDC_LEAK (REF +)
REF+ DC Leakage Current
CS = VCC = 5.5V, REF+ = 5V
l
–10
1
10
nA
(REF –)
REF– DC Leakage Current
CS = VCC
l
–10
1
10
nA
Off Channel to In Channel Isolation
(RIN = 100Ω)
DC
1Hz
fS = 15,3600Hz
IDC_LEAK
= 5.5V, REF– = GND
tOPEN
MUX Break-Before-Make Interval
2.7V ≤ VCC ≤ 5.5V
IS(OFF)
Channel Off Leakage Current
Channel at VCC and GND
140
140
140
l
dB
dB
dB
70
100
300
ns
–10
1
10
nA
digital input and digital outputs
The l denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO, SDI
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
l
VIL
Low Level Input Voltage
CS, FO, SDI
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
l
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
l
IIN
Digital Input Current
CS, FO, SDI
0V ≤ VIN ≤ VCC
l
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
l
CIN
VOH
4
MIN
(Note 9)
High Level Output Voltage
SDO
IO = – 800µA
l
MAX
2.5
2.0
UNITS
V
V
0.8
0.6
2.5
2.0
V
V
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
Digital Input Capacitance
CS, FO, SDI
Digital Input Capacitance
SCK
TYP
VCC–0.5
10
pF
10
pF
V
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
digital input and digital outputs
The l denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
l
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
l
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
l
IOZ
Hi-Z Output Leakage
SDO
l
TYP
MAX
UNITS
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
power requirements
The l denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
l
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 12)
TYP
2.7
200
4
2
l
l
MAX
UNITS
5.5
V
300
10
µA
µA
µA
timing characteristics
The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
l
tHEO
External Oscillator High Period
l
tLEO
External Oscillator Low Period
l
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
l
l
l
130.86
157.03
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 9)
l
TYP
MAX
UNITS
2.56
500
kHz
0.25
390
µs
0.25
390
µs
133.53
136.20
160.23
163.44
20510/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
tLESCK
External SCK Low Period
(Note 9)
l
250
ns
tHESCK
External SCK High Period
(Note 9)
l
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
1.64
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
l
1.67
256/fEOSC (in kHz)
32/fESCK (in kHz)
1.70
ms
ms
ms
241418fb
For more information www.linear.com/LTC2414
5
LTC2414/LTC2418
timing characteristics
The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
t1
CS ↓ to SDO Low
t2
CS ↑ to SDO High Z
t3
CS ↓ to SCK ↓
(Note 10)
t4
CS ↓ to SCK ↑
(Note 9)
tKQMAX
SCK ↓ to SDO Valid
MIN
TYP
MAX
UNITS
l
0
200
ns
l
0
200
ns
l
0
200
ns
l
50
ns
220
l
ns
l
15
ns
SCK Set-Up Before CS ↓
l
50
ns
t6
SCK Hold After CS ↓
l
t7
SDI Setup Before SCK ↑
t8
SDI Hold After SCK ↑
tKQMIN
SDO Hold After SCK ↓
t5
(Note 5)
ns
(Note 5)
100
ns
(Note 5)
l
100
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF + – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN –,
VINCM = (IN + + IN –)/2, IN+ and IN– are defined as the selected positive and
negative input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ± 2%
(external oscillator).
6
50
l
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
Typical Performance Characteristics
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
3
3
0
TA = –45°C
–1
TA = 85°C
1
TA = 25°C
0
TA = 85°C
–1
TA = –45°C
–2
–2
–3
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
–3
–1.25
–0.75
1
8
FO = GND
6 VCC = 2.7V
VREF = 2.5V
= VREFCM = 1.25V
V
4 INCM
TA = –45°C
0
TA = 25°C
–1
TA = 85°C
–2
–2
–3
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
–3
–1.25
30
NUMBER OF READINGS (%)
10
5
–2
0.6
241418 G07
TA = 85°C
–6
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–8
–1.25
1.25
–0.75
10,000 CONSECUTIVE READINGS
FO = GND
12 T = 25°C
A
VCC = 2.7V
GAUSSIAN
10 VREF = 2.5V
DISTRIBUTION
VIN = 0V
m = –0.48ppm
σ = 0.375ppm
8 VINCM = 2.5V
6
241418 G06
1.0
RMS NOISE = 0.19ppm
FO = GND
VREF = 5V
TA = 25°C VIN = 0V
0.5 VCC = 5V
VINCM = 2.5V
0
–0.5
4
0
–2.4
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
Long Term ADC Readings
–1.0
2
–0.6
0
OUTPUT CODE (ppm OF VREF)
0
–4
14
15
TA = 25°C
2
Noise Histogram
(VCC = 2.7V, VREF = 2.5V)
10,000 CONSECUTIVE READINGS
FO = GND
25 TA = 25°C
VCC = 5V
GAUSSIAN
VREF = 5V
DISTRIBUTION
20 VIN = 0V
m = –0.24ppm
VINCM = 2.5V
σ = 0.183ppm
TA = –45°C
241418 G05
Noise Histogram
(VCC = 5V, VREF = 5V)
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
241418 G03
INL (ppm OF VREF)
TA = –45°C
INL (ppm OF VREF)
INL (ppm OF VREF)
0
–0.75
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
241418 G04
NUMBER OF READINGS (%)
–8
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
FO = GND
VCC = 5V
2 VREF = 2.5V
VINCM = VREFCM = 1.25V
TA = 25°C
TA = 25°C
–4
3
FO = GND
VCC = 5V
2 VREF = 5V
VINCM = VREFCM = 2.5V
TA = 85°C
TA = 85°C
–2
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
3
–1
0
241418 G02
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
1
2
–6
241418 G01
0
–1.2
TUE (ppm OF VREF)
TA = 25°C
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
FO = GND
TA = –45°C
6 VCC = 2.7V
VREF = 2.5V
= VREFCM = 1.25V
V
4 INCM
ADC READING (ppm OF VREF)
1
8
FO = GND
VCC = 5V
2 VREF = 2.5V
VINCM = VREFCM = 1.25V
TUE (ppm OF VREF)
TUE (ppm OF VREF)
FO = GND
VCC = 5V
2 VREF = 5V
VINCM = VREFCM = 2.5V
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
0
0.6
–1.8 –1.2 –0.6
OUTPUT CODE (ppm OF VREF)
1.2
241418 G08
–1.5
0
10
20
30
40
TIME (HOURS)
50
60
LTXXXX • TPCXX
241418fb
For more information www.linear.com/LTC2414
7
LTC2414/LTC2418
Typical Performance Characteristics
RMS Noise vs Input Differential
Voltage
RMS Noise vs VINCM
FO = GND
TA = 25°C
VCC = 5V
0.4 V
REF = 5V
VINCM = 2.5V
1.2
1.1
0.9
0.3
0.2
RMS NOISE (µV)
1.0
RMS NOISE (µV)
RMS NOISE (ppm OF VREF)
RMS Noise vs Temperature (TA)
1.0
0.5
0.8
FO = GND
TA = 25°C
VCC = 5V
REF+ = 5V
REF – = GND
VIN = 0V
VINCM = GND
0.7
0.6
0.1
0.5
0
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT DIFFERENTIAL VOLTAGE (V)
–1
1
0
3
2
VINCM (V)
4
5
0.9
0.8
FO = GND
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
0.7
0.6
0.5
–50
6
–25
0
25
50
TEMPERATURE (°C)
75
241418 G12
241418 G11
241418 G10
RMS Noise vs VREF
RMS Noise vs VCC
1.0
1.0
0.9
0.9
100
Offset Error vs VINCM
0
0.7
FO = GND
TA = 25°C
VIN = 0V
VINCM = GND
REF+ = 2.5V
REF – = GND
0.6
0.5
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
0.8
0.7
FO = GND
TA = 25°C
VCC = 5V
VIN = 0V
VINCM = GND
REF – = GND
0.6
0.5
5.5
1
0
3
2
VREF (V)
4
Offset Error vs Temperature
–0.5
–0.6
–0.3
–0.4
–0.8
–0.9
–1.0
FO = GND
0.8 TA = 25°C
V = 0V
0.6 VIN = GND
INCM
+
0.4 REF – = 2.5V
REF = GND
0.2
0
–0.8
90
241418 G16
3
2
VINCM (V)
4
5
–1.0
6
241418 G15
FO = GND
TA = 25°C
VCC = 5V
VIN = 0V
VINCM = GND
REF – = GND
0.8
–0.6
75
1
0
Offset Error vs VREF
–0.4
–0.6
–1
1.0
–0.2
–0.5
FO = GND
TA = 25°C
VCC = 5V
REF+ = 5V
REF – = GND
VIN = 0V
–0.7
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
–0.4
Offset Error vs VCC
FO = GND
–0.1 VCC = 5V
VREF = 5V
VIN = 0V
–0.2 VINCM = GND
8
–0.3
1.0
0
0 15 30 45 60
TEMPERATURE (°C)
–0.2
241418 G14
241418 G13
–0.7
–45 –30 –15
5
OFFSET ERROR (ppm OF VREF)
0.8
RMS NOISE (µV)
RMS NOISE (µV)
–0.1
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
241418 G17
–1.0
0
1
3
2
VREF (V)
4
5
241418 G18
241418fb
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LTC2414/LTC2418
Typical Performance Characteristics
Full-Scale Error vs Temperature
Full-Scale Error vs VCC
+FS ERROR
1
0
–1
–2
–FS ERROR
–3
–4
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
5
4
4
3
+FS ERROR
2
FO = GND
1 T = 25°C
A
0 VREF = 2.5V
VINCM = 0.5VREF
–1 REF – = GND
–FS ERROR
–2
–3
–4
–5
100
Full-Scale Error vs VREF
5
FULL-SCALE ERROR (ppm OF VREF)
FO = GND
4 VCC = 5V
= 5V
V
3 REF
VINCM = 2.5V
2
FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
5
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
241418 G19
–80
PSRR vs Frequency at VCC
FO = GND
T = 25°C
–20 VA = 4.1V ±1.4V
CC
DC
REF+ = 2.5V
–
–40 REF = GND
IN+ = GND
–
–60 IN = GND
SDI = GND
–80
–80
–100
–100
–120
–120
–120
10
–140
100 1000 10000 100000 1000000
FREQUENCY AT VCC (Hz)
0
60
120 150 180 210 240
FREQUENCY AT VCC (Hz)
30
90
170
160
–45 –30 –15
VCC = 3V
6
CS = GND
900 FO = EXT OSC
IN+ = GND
800 IN– = GND
SCK = NC
700 SDO = NC
600 SDI = GND
TA = 25°C
500 VREF = VCC
400
VCC = 5V
300
200
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
VCC = 5V
210
CS = GND
200 FO = GND
SCK = NC
190 SDO = NC
SDI = GND
180
Sleep Mode Current
vs Temperature
1000
VCC = 5.5V
75 90
100
5
10
15
20
25
OUTPUT DATA RATE (READINGS/SEC)
241418 G25
241418 G26
CS = VCC
FO = GND
SCK = NC
SDO = NC
SDI = GND
5
VCC = 5.5V
4
3
2
1
VCC = 3V
0
15450
241418 G24
Supply Current at Elevated
Output Rates (FO Over Driven)
240
220
15300
15350
15400
FREQUENCY AT VCC (Hz)
241418 G23
Conversion Current
vs Temperature
230
–140
15250
SLEEP-MODE CURRENT (μA)
1
241418 G22
CONVERSION CURRENT (μA)
FO = GND
TA = 25°C
VCC = 4.1VDC ±0.7VP-P
REF+ = 2.5V
–40 REF – = GND
IN+ = GND
–
–60 IN = GND
SDI = GND
–20
–100
–140
–FS ERROR
–2 FO = GND
T = 25°C
–3 A
VCC = 5V
–4 VINCM = 0.5VREF
REF – = GND
–5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
0
REJECTION (dB)
–60
0
–1
PSRR vs Frequency at VCC
REJECTION (dB)
REJECTION (dB)
–40
+FS ERROR
1
241418 G21
0
FO = GND
TA = 25°C
VCC = 4.1VDC
REF+ = 2.5V
REF – = GND
IN+ = GND
IN – = GND
SDI = GND
–20
2
241418 G20
PSRR vs Frequency at VCC
0
5.5
3
0
–45 –30 –15
VCC = 5V
VCC = 3V
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
75 90
241418 G27
241418fb
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9
LTC2414/LTC2418
Pin Functions
CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog
Inputs. May be programmed for single-ended or differential mode. CH8 to CH15 (Pin 1 to Pin 8) not connected
on the LTC2414.
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
VCC (Pin 9): Positive Supply Voltage. Bypass to GND
(Pin 15) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the
Data Output period. In External Serial Clock Operation
mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode
is determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
COM (Pin 10): The common negative input (IN–) for all
single-ended multiplexer configurations. The voltage on
Channel 0 to 15 and COM input pins can have any value
between GND – 0.3V and VCC + 0.3V. Within these limits,
the two selected inputs (IN+ and IN–) provide a bipolar input range (VIN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF.
Outside this input range, the converter produces unique
overrange and underrange output codes.
REF + (Pin 11), REF– (Pin 12): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the positive reference input, REF+,
is maintained more positive than the negative reference
input, REF –, by at least 0.1V.
GND (Pin 15): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 16): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 17): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
10
FO (Pin 19): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO is
driven by an external clock signal with a frequency fEOSC,
the converters use this signal as their system clock and the
digital filter first null is located at a frequency fEOSC/2560.
SDI (Pin 20): Serial Digital Data Input. During the Data
Output period, this pin is used to shift in the multiplexer
address started from the first rising SCK edge. During the
Conversion and Sleep periods, this pin is in the DON’T
CARE state. However, a HIGH or LOW logic level should
be maintained on SDI in the DON’T CARE mode to avoid
an excessive current in the SDI input buffers.
NC Pins: Do Not Connect.
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
functional Block Diagram
INTERNAL
OSCILLATOR
VCC
GND
CH0
CH1
CH15
COM
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF +
REF –
•
•
•
IN +
MUX
IN –
–
+
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
SERIAL
INTERFACE
SDI
SCK
SDO
CS
DECIMATING FIR
ADDRESS
241418 F01
Figure 1
Test Circuit
SDO
VCC
1.69k
CLOAD = 20pF
1.69k
SDO
241418 TA02
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
241418 TA03
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
Applications Information
Converter Operation
Converter Operation Cycle
The LTC2414/LTC2418 are multichannel, low power, deltasigma analog-to-digital converters with an easy-to-use
4‑wire serial interface (see Figure 1). Their operation is
made up of three states. The converter operating cycle
begins with the conversion, followed by the low power
sleep state and ends with the data input/output (see Figure 2). The 4-wire interface consists of serial data input
(SDI), serial data output (SDO), serial clock (SCK) and
chip select (CS).
Initially, the LTC2414 or LTC2418 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in the sleep state, power consumption
is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register
while the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the first rising edge of SCK, the device begins
outputting the conversion result and inputting channel
selection bits. Taking CS high at this point will terminate
the data output state and start a new conversion. The
channel selection control bits are shifted in through SDI
from the first rising edge of SCK and depending on the
For more information www.linear.com/LTC2414
241418fb
11
LTC2414/LTC2418
Applications Information
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2414/LTC2418 incorporate a highly accurate
on-chip oscillator. This eliminates the need for external
frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2414/
LTC2418 achieve a minimum of 110dB rejection at the
line frequency (50Hz or 60Hz ± 2%).
POWER UP
IN + = CH0, IN – = CH1
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
Ease of Use
TRUE
DATA OUTPUT
ADDRESS INPUT
241418 F02
Figure 2. LTC2414/LTC2418 State Transition Diagram
control bits, the converter updates its channel selection
immediately and is valid for the next conversion. The details
of channel selection control bits are described in the Input
Data Mode section. The output data is shifted out the SDO
pin under the control of the serial clock (SCK). The output
data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2414/LTC2418 offer several flexible modes of operation (internal or external SCK and free-running conversion
modes). These various modes do not require programming
configuration registers; moreover, they do not disturb the
cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing
Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or 60Hz
12
The LTC2414/LTC2418 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
The LTC2414/LTC2418 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with res
pect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2414/LTC2418 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface
mode selection. (See the 3-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2414/LTC2418 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2414/LTC2418 accept a truly differential external
reference voltage. The absolute/common mode voltage
241418fb
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LTC2414/LTC2418
Applications Information
specification for the REF + and REF – pins covers the entire
range from GND to VCC. For correct converter operation, the
REF + pin must always be more positive than the REF – pin.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
The LTC2414/LTC2418 can accept a differential reference
voltage from 0.1V to VCC. The converter output noise is
determined by the thermal noise of the front-end circuits,
and, as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will improve
the converter’s overall INL performance. A reduced reference voltage will also improve the converter performance
when operated with an external conversion clock (external
FO signal) at substantially higher output data rates.
Input Data Format
Input Voltage Range
The two selected pins are labeled IN+ and IN– (see Tables
1 and 2). Once selected (either differential or singleended multiplexing mode), the analog input is differential
with a common mode range for the IN+ and IN– input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2414/LTC2418 convert the bipolar differential input signal, VIN = IN + – IN–,
from – FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF–. Outside this range the converters indicate
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend
300mV below ground or above VCC. In order to limit
any fault current, resistors of up to 5k may be added
in series with the IN+ or IN– pins without affecting the
performance of the device. In the physical layout, it is
important to maintain the parasitic capacitance of the
connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
When the LTC2414/LTC2418 are powered up, the default
selection used for the first conversion is IN+ = CH0 and
IN– = CH1 (Address = 00000). In the data input/output
mode following the first conversion, a channel selection
can be updated using an 8-bit word. The LTC2414/LTC2418
serial input data is clocked into the SDI pin on the rising
edge of SCK (see Figure 3). The input is composed of an
8-bit word with the first 3 bits acting as control bits and
the remaining 5 bits as the channel address bits.
The first 2 bits are always 10 for proper updating operation. The third bit is EN. For EN = 1, the following 5 bits
are used to update the input channel selection. For EN =
0, previous channel selection is kept and the following bits
are ignored. Therefore, the address is updated when the 3
control bits are 101 and kept for 100. Alternatively, the 3
control bits can be all zero to keep the previous address.
This alternation is intended to simplify the SDI interface
allowing the user to simply connect SDI to ground if no
update is needed. Combinations other than 101, 100 and
000 of the 3 control bits should be avoided.
When update operation is set (101), the following 5 bits
are the channel address. The first bit, SGL, decides if the
differential selection mode (SGL = 0) or the single-ended
selection mode is used (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input; for SGL = 1, one of the 8 channels (CH0-CH7) for
the LTC2414 or one of the 16 channels (CH0-CH15) for
the LTC2418 is selected as the positive input and the COM
pin is used as the negative input. For the LTC2414, the
lower half channels (CH0-CH7) are used and the channel
address bit A2 should be always 0, see Table 1. While for
the LTC2418, all the 16 channels are used and the size
of the corresponding selection table (Table 2) is doubled
from that of the LTC2414 (Table 1). For a given channel
selection, the converter will measure the voltage between
the two channels indicated by IN+ and IN– in the selected
row of Tables 1 or 2.
241418fb
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13
LTC2414/LTC2418
Applications Information
CS
BIT31
SDO
Hi-Z
EOC
BIT30
DMY
BIT29
SIG
BIT28
BIT27
MSB
BIT26
BIT25
BIT24
BIT6
LSB
B22
CONVERSON RESULT
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SGL
ODD/
SIGN
A2
A1
A0
PARITY
ADDRESS CORRESPONDING TO RESULT
SCK
SDI
1
0
EN
SGL
ODD/
SIGN
A2
A1
A0
SLEEP
DON’T CARE
CONVERSION
DATA INPUT/OUTPUT
241418 F03a
Figure 3a. Input/Output Data Timing
CONVERSION RESULT
N
CONVERSION RESULT
N–1
SDO
CONVERSION RESULT
N+1
Hi-Z
Hi-Z
ADDRESS
N–1
Hi-Z
ADDRESS
N
ADDRESS
N+1
SCK
SDI
DON’T CARE
DON’T CARE
ADDRESS
N
OPERATION
ADDRESS
N+1
OUTPUT
N–1
CONVERSION N
ADDRESS
N+2
OUTPUT
N
CONVERSION N + 1
OUTPUT
N+1
241418 F03b
Figure 3b. Typical Operation Sequence
Table 1. Channel Selection for the LTC2414 (Bit A2 Should Always Be 0)
MUX ADDRESS
ODD/
SGL
SIGN A2 A1
* 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
*Default at power up
14
CHANNEL SELECTION
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
IN+
IN–
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
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LTC2414/LTC2418
Applications Information
Table 2. Channel Selection for the LTC2418
MUX ADDRESS
ODD/
SGL SIGN A2 A1
*0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
*Default at power up
CHANNEL SELECTION
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
IN+
IN–
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
Output Data Format
The LTC2414/LTC2418 serial output data stream is 32 bits
long. The first 3 bits represent status information indicating the sign and conversion state. The next 23 bits are the
conversion result, MSB first. The next 5 bits (Bit 5 to Bit 1)
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
indicate which channel the conversion just performed
was selected. The address bits programmed during this
data output phase select the input channel for the next
conversion cycle. These address bits are output during
the subsequent data read, as shown in Figure 3b. The last
241418fb
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15
LTC2414/LTC2418
Applications Information
bit is a parity bit representing the parity of the previous
31 bits. The parity bit is useful to check the output data
integrity especially when the output data is transmitted
over a distance. The third and fourth bits together are also
used to indicate an underrange condition (the differential
input voltage is below – FS) or an overrange condition (the
differential input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
I IN+
RSW (TYP)
20k
ILEAK
impedance result in only small errors. Such values for CIN
will deteriorate the converter offset and gain performance
without significant benefits of signal filtering and the user
is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input
multiplexers, wires, connectors or sensors, the LTC2414/
LTC2418 can maintain its exceptional accuracy while
operating with relative large values of source resistance
as shown in Figures 13 and 14. These measured results
may be slightly different from the first order approximation suggested earlier because they include the effect of
the actual second order input network together with the
nonlinear settling process of the input amplifiers. For
small CIN values, the settling on IN+ and IN – occurs almost
independently and there is little benefit in trying to match
the source impedance for the two pins.
2414/18 F11
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR
VIN = IN+ − IN−
IN+ − IN−
VINCM =
2
(
)
REQ = 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch (FO = HIGH)
REQ = 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch FO = LOW
(
)
REQ = 0.555 • 1012 / fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2414/LTC2418 Equivalent Analog Input Circuit
26
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241418fb
LTC2414/LTC2418
Applications Information
RSOURCE
VINCM + 0.5VIN
IN +
CIN
CPAR
≅ 20pF
RSOURCE
VINCM – 0.5VIN
LTC2414/
LTC2418
IN –
CIN
CPAR
≅ 20pF
2414/18 F12
Figure 12. An RC Network at IN+ and IN–
CIN = 0.001µF
40
CIN = 100pF
CIN = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
20
10
0
0
CIN = 0.01µF
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
50
1
10
100
1k
RSOURCE (Ω)
10k
100k
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
–10
–20
–30
CIN = 0.01µF
CIN = 0.001µF
–40
–50
CIN = 100pF
CIN = 0pF
1
10
100
1k
RSOURCE (Ω)
2414/18 F13
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm for each
ohm of source resistance driving IN+ or IN–. When FO =
HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 2.16MΩ which will generate
a gain error of approximately 0.23ppm for each ohm of
source resistance driving IN+ or IN–. When FO is driven
by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential
input resistance is 0.28 • 1012/fEOSCΩ and each ohm of
source resistance driving IN+ or IN– will result in
1.78 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and
IN– for large values of CIN are shown in Figures 15 and 16.
In addition to this gain error, an offset error term may
also appear. The offset error is proportional with the
mismatch between the source impedance driving the two
10k
100k
2414/18 F14
Figure 14. –FS Error vs RSOURCE
at IN+ or IN–
(Small CIN)
input pins IN+ and IN– and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large CIN
capacitor values, it is advisable to carefully match the source
impedance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch in
source impedance transforms a full-scale common mode
input signal into a differential mode input signal of 0.28ppm.
When FO = HIGH (internal oscillator and 50Hz notch), every
1Ω mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.23ppm. When FO is driven by an external
oscillator with a frequency fEOSC, every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
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27
LTC2414/LTC2418
Applications Information
+FS ERROR (ppm OF VREF)
300
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
240
180
1.78 • 10–6 • fEOSCppm. Figure 17 shows the typical offset error due to input common mode voltage for various
values of source resistance imbalance between the IN+
and IN– pins when large CIN values are used.
CIN = 1µF, 10µF
CIN = 0.1µF
120
CIN = 0.01µF
60
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F15
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
–FS ERROR (ppm OF VREF)
CIN = 0.01µF
–60
–120
–240
–300
CIN = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
–180
CIN = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F16
Figure 16. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
120
OFFSET ERROR (ppm OF VREF)
100
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
80
60
B
40
D
0
E
–20
F
–40
–60
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
–80
–100
–120
0
0.5
1
1.5
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
2 2.5 3
VINCM (V)
3.5
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
2414/18 F17
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
28
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are used
for the external source impedance seen by IN+ and IN–,
the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
values over the entire temperature and voltage range). Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
C
20
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
In a similar fashion, the LTC2414/LTC2418 samples the
differential reference pins REF+ and REF– transferring small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
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241418fb
LTC2414/LTC2418
Applications Information
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configurations. Such capacitors will average the reference sampling
charge and the external source resistance will see a quasi
constant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3MΩ which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF+ or REF–. When FO = HIGH (internal
oscillator and 50Hz notch), the typical differential reference resistance is 1.56MΩ which will generate a gain
error of approximately 0.32ppm for each ohm of source
resistance driving REF+ or REF–. When FO is driven by
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential reference resistance is 0.20 • 1012/fEOSCΩ and each ohm
of source resistance driving REF+ or REF– will result in
2.47 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with respect
to this gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+
and REF– pins and external capacitance CREF connected
to these pins are shown in Figures 18, 19, 20 and 21.
50
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
–10
–20
–30
CREF = 0.01µF
CREF = 0.001µF
–40
–50
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 100pF
CREF = 0pF
1
10
40
10k
CREF = 100pF
CREF = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
20
10
0
100
1k
RSOURCE (Ω)
CREF = 0.01µF
CREF = 0.001µF
100k
1
10
100
1k
RSOURCE (Ω)
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
450
CREF = 0.01µF
–90
–180
–270
–360
–450
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
100k
2414/18 F19
2414/18 F18
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
10k
CREF = 1µF, 10µF
270
180
90
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F20
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
360
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F21
Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
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29
LTC2414/LTC2418
Applications Information
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– translates into about 1.34ppm additional INL error. When FO
= HIGH (internal oscillator and 50Hz notch), every 100Ω
of source resistance driving REF+ or REF– translates into
about 1.1ppm additional INL error. When FO is driven by
an external oscillator with a frequency fEOSC, every 100Ω
of source resistance driving REF+ or REF– translates
into about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on
the two reference pins is additive with respect to this INL
error. In general, matching of source impedance for the
REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined
source impedance driving the REF+ and REF– pins rather
than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
15
12
RSOURCE = 1000Ω
INL (ppm OF VREF)
9
RSOURCE = 500Ω
6
3
0
–3
RSOURCE = 100Ω
–6
–9
–12
–15
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
– = GND
REF
TA = 25°C
2414/18 F22
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF– for
Large CREF Values (CREF ≥ 1µF)
30
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a onetime calibration operation may
be sufficient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2414/LTC2418
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (FO = LOW) and 6.25 readings per
second with a notch frequency of 50Hz (FO = HIGH). The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (FO connected
to an external oscillator), the LTC2414/LTC2418 output data
rate can be increased as desired up to that determined by
the maximum fEOSC frequency of 500kHz. The duration of
the conversion phase is 20510/fEOSC. If fEOSC = 153600Hz,
the converter behaves as if the internal oscillator is used
and the notch is set at 60Hz. There is no significant difference in the LTC2414/LTC2418 performance between
these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying
upon the LTC2414/LTC2418’s exceptional common mode
241418fb
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LTC2414/LTC2418
Applications Information
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the
output data rate) will start to decrease the effectiveness
of the internal autocalibration circuits. This will result in
a progressive degradation in the converter accuracy and
linearity. Typical measured performance curves for output
data rates up to 25 readings per second are shown in Figures 23, 24, 25, 26, 27, 28, 29 and 30. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 7.5 readings per second, the
user is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal Sinc4 digital filter
and of the analog and digital autocalibration circuits determines the LTC2414/LTC2418 input bandwidth. When
the internal oscillator is used with the notch set at 60Hz
(FO = LOW), the 3dB input bandwidth is 3.63Hz. When
the internal oscillator is used with the notch set at 50Hz
(FO = HIGH), the 3dB input bandwidth is 3.02Hz. If an
external conversion clock generator of frequency fEOSC
is connected to the FO pin, the 3dB input bandwidth is
0.236 • 10–6 • fEOSC.
OFFSET ERROR (ppm of VERROR)
160
120
80
40
TA = 25°C
0
TA = 85°C
–40
VCC = 5V
–80 V
REF = 5V
–120 VIN = 2.5V
VINCM = 2.5V
–160 SDI = GND
F = EXTERNAL OSCILLATOR
–200 O
10
0
5
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
2414/18 F23
Figure 23. Offset Error vs Output Data Rate and Temperature
2000
TA = 25°C
0
+FS ERROR (ppm of VREF)
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of fEOSC. If small external input and/or reference
capacitors (CIN, CREF) are used, the effect of the external
source resistance upon the LTC2414/LTC2418 typical
performance can be inferred from Figures 12, 13, 18 and
19 in which the horizontal axis is scaled by 153600/fEOSC.
200
TA = 85°C
–2000
–4000
–6000
VCC = 5V
–8000 VREF = 5V
VIN = 2.5V
–10000 VINCM = 2.5V
SDI = GND
FO = EXTERNAL OSCILLATOR
–12000
10
15
20
0
5
OUTPUT DATA RATE (READINGS/SEC)
25
2414/18 F24
Figure 24. +FS Error vs Output Data Rate and Temperature
12000
–FS ERROR (ppm of VREF)
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
VCC = 5V
VREF = 5V
10000 VIN = 2.5V
VINCM = 2.5V
8000 SDI = GND
FO = EXTERNAL OSCILLATOR
6000
4000
2000
TA = 85°C
0
–2000
TA = 25°C
0
15
20
10
5
OUTPUT DATA RATE (READINGS/SEC)
25
2414/18 F25
Figure 25. –FS Error vs Output Data Rate and Temperature
241418fb
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31
LTC2414/LTC2418
Applications Information
22
TA = 25°C
20
TA = 85°C
21
RESOLUTION (BITS)
RESOLUTION (BITS)
22
20
19
18
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
SDI = GND
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
12
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
200
TA = 25°C
TA = 85°C
18
RESOLUTION = LOG2(VREF/INLMAX)
16
14
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
SDI = GND
FO = EXTERNAL OSCILLATOR
12
10
8
25
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
2414/18 F26
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
22
RESOLUTION (BITS)
RESOLUTION (BITS)
VREF = 2.5V
19
18
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
SDI = GND
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
12
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
16
14
TA = 25°C
VCC = 5V
REF – = GND
VINCM = 0.5 • REF +
–0.5V • VREF < VIN < 0.5 • VREF
SDI = GND
FO = EXTERNAL OSCILLATOR
12
8
0
25
2414/18 F30
Figure 30. Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate and Reference Voltage
The conversion noise (1µVRMS typical for VREF = 5V) can
be modeled by a white noise source connected to a noise
25
–1.0
–1.5
–2.0
FO = HIGH
FO = LOW
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2414/LTC2418 input bandwidth is
shown in Figure 31 for FO = LOW and FO = HIGH. When
an external oscillator of frequency fEOSC is used, the shape
of the LTC2414/LTC2418 input bandwidth can be derived
from Figure 31, FO = LOW curve in which the horizontal
axis is scaled by fEOSC/153600.
32
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
0.0
RESOLUTION =
LOG2(VREF/INLMAX)
18
2414/18 F29
Figure 29. Resolution (NoiseRMS ≤ 1LSB) vs
Output Data Rate and Reference Voltage
0
–0.5
VREF = 5V
10
25
VREF = 2.5V
Figure 28. Offset Error vs Output
Data Rate and Reference Voltage
VREF = 2.5V
20
22
20
VREF = 5V
0
2414/18 F28
Figure 27. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
VREF = 5V
21
50
2414/18 F27
24
23
FO = EXTERNAL OSCILLATOR
VCC = 5V
REF – = GND
150 V = 0V
IN
VINCM = 2.5V
SDI = GND
100 TA = 25°C
–50
25
INPUT SIGNAL ATTENUATION (dB)
23
OFFSET ERROR (ppm of VREF)
24
–6.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F31
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
free converter. The noise spectral density is 78nV/√Hz for
an infinite bandwidth source and 107nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
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LTC2414/LTC2418
Applications Information
100
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
When external amplifiers are driving the LTC2414/
LTC2418, the ADC input referred system noise calculation
can be simplified by Figure 32. The noise of an amplifier
driving the LTC2414/LTC2418 input pin can be modeled
as a band limited white noise source. Its bandwidth can be
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency fi. The amplifier noise spectral
density is ni. From Figure 32, using fi as the x-axis selector,
we can find on the y-axis the noise equivalent bandwidth
freqi of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
be calculated as N = ni • √freqi. The total system noise
(referred to the LTC2414/LTC2418 input) can now be
obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2414/
LTC2418 internal noise (1µV), the noise of the IN + driving
amplifier and the noise of the IN– driving amplifier.
FO = LOW
10
FO = HIGH
1
0.1
0.1
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2414/18 F32
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
INPUT NORMAL MODE REJECTION (dB)
0
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if
the x-axis is scaled by fEOSC/153600. For large values of
the ratio fEOSC/153600, the Figure 32 plot accuracy begins
to decrease, but in the same time the LTC2414/LTC2418
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
–10
FO = HIGH
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F33
Normal Mode Rejection and Antialiasing
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2414/LTC2418’s autocalibration circuits further simplify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
0
INPUT NORMAL MODE REJECTION (dB)
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2414/LTC2418
significantly simplify antialiasing filter requirements.
FO = LOW OR
FO = EXTERNAL
OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F34
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
For more information www.linear.com/LTC2414
241418fb
33
LTC2414/LTC2418
Applications Information
The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure 34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for
the external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
Figure 36 (rejection at fS = 256fN) where fN represents
the notch frequency. These curves have been derived for
the external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
As a result of these remarkable normal mode specifications,
minimal (if any) antialias filtering is required in front of the
LTC2414/LTC2418. If passive RC components are placed
in front of the LTC2414/LTC2418, the input dynamic current should be considered (see Input Current section). In
cases where large effective RC time constants are used,
an external buffer amplifier may be required to minimize
the effects of dynamic input current.
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 37 and 38. Typical measured values
of the normal mode rejection of the LTC2414/LTC2418
operating with an internal oscillator and a 60Hz notch
setting are shown in Figure 37 superimposed over the
theoretical calculated curve. Similarly, typical measured
values of the normal mode rejection of the LTC2414/
LTC2418 operating with an internal oscillator and a 50Hz
notch setting are shown in Figure 38 superimposed over
the theoretical calculated curve.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2414/18 F36
2414/18 F35
Figure 35. Input Normal Mode Rejection
34
Figure 36. Input Normal Mode Rejection
241418fb
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LTC2414/LTC2418
Applications Information
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
SDI = GND
FO = GND
TA = 25°C
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2414/18 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
SDI = GND
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2414/18 F38
Figure 38. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)
241418fb
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35
LTC2414/LTC2418
Applications Information
Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The proprietary architecture used for the LTC2414/LTC2418 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is
not uncommon to have to measure microvolt level signals
superimposed over volt level perturbations and LTC2414/
LTC2418 is eminently suited for such tasks. When the
perturbation is differential, the specification of interest is
the normal mode rejection for large input signal levels.
With a reference voltage VREF = 5V, the LTC2414/LTC2418
has a full-scale differential input range of 5V peak-to-peak.
Figures 39 and 40 show measurement results for the
LTC2414/LTC2418 normal mode rejection ratio with a
7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full scale)
input signal. In Figure 39, the LTC2414/LTC2418 uses the
internal oscillator with the notch set at 60Hz (FO = LOW)
and in Figure 40 it uses the internal oscillator with the
notch set at 50Hz (FO = HIGH). It is clear that the LTC2414/
LTC2418 rejection performance is maintained with no
compromises in this extreme situation. When operating
with large input signal levels, the user must observe that
such signals do not violate the device absolute maximum
ratings.
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
SDI = GND
FO = GND
TA = 25° C
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2414/18 F39
Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
SDI = GND
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2414/18 F40
Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)
36
241418fb
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LTC2414/LTC2418
Applications Information
Bridge applications
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2414/LTC2418 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation
be limited to 5V. This gives only 10mV full scale input
signal, which can be resolved to 1 part in 10000 without
averaging. For many solid state sensors, this is still better
than the sensor. Averaging 64 samples however reduces
the noise level by a factor of eight, bringing the resolving
power to 1 part in 80000, comparable to better weighing
systems. Hysteresis and creep effects in the load cells
are typically much greater than this. Most applications
that require strain measurements to this level of accuracy
are measuring slowly changing phenomena, hence the
time required to average a large number of readings is
usually not an issue. For those systems that require accurate measurement of a small incremental change on a
significant tare weight, the lack of history effects in the
LTC2400 family is of great benefit.
For those applications that cannot be fulfilled by the
LTC2414/LTC2418 alone, compensating for error in
external amplification can be done effectively due to the
“no latency” feature of the LTC2414/LTC2418. No latency
operation allows samples of the amplifier offset and gain
to be interleaved with weighing measurements. The use
of correlated double sampling allows suppression of 1/f
noise, offset and thermocouple effects within the bridge.
Correlated double sampling involves alternating the polarity
of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be
increased to as much as ±10V, if one of several precision
attenuation techniques is used to produce a precision
divide operation on the reference signal. Another option
is the use of a reference within the 5V input range of the
LTC2414/LTC2418 and developing excitation via fixed
gain, or LTC1043 based voltage multiplication, along with
remote feedback in the excitation amplifiers, as shown in
Figures 46 and 47.
Figure 41 shows an example of a simple bridge connection.
Note that it is suitable for any bridge application where
measurement speed is not of the utmost importance.
For many applications where large vessels are weighed,
the average weight over an extended period of time is of
concern and short term weight is not readily determined
due to movement of contents, or mechanical resonance.
Often, large weighing applications involve load cells
located at each load bearing point, the output of which
can be summed passively prior to the signal processing
circuitry, actively with amplification prior to the ADC, or
can be digitized via multiple ADC channels and summed
mathematically. The mathematical summation of the output
of multiple LTC2414/LTC2418’s provides the benefit of a
root square reduction in noise. The low power consumption
of the LTC2414/LTC2418 makes it attractive for multidrop
communication schemes where the ADC is located within
the load-cell housing.
R1
0.1µF
+
LT1019
0.1µF
9
11
350Ω
BRIDGE
10µF
12
21
REF +
VCC
SDI
REF –
SCK
SDO
CH0
CS
20
18
17
16
LTC2414/
LTC2418
22
R2
CH1
GND
FO
19
15
2414/18 F41
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 41. Simple Bridge Connection
A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2414/LTC2418
exhibits extremely low temperature dependent drift. As a
result, exposure to external ambient temperature ranges
does not compromise performance. The incorporation of
any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature
coefficient of gain settling resistors all become factors.
241418fb
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37
LTC2414/LTC2418
Applications Information
The circuit in Figure 42 shows an example of a simple
amplification scheme. This example produces a differential output with a common mode voltage of 2.5V,
as determined by the bridge. The use of a true three
amplifier instrumentation amplifier is not necessary, as
the LTC2414/LTC2418 has common mode rejection far
beyond that of most amplifiers. The LTC1051 is a dual
autozero amplifier that can be used to produce a gain of
15 before its input referred noise dominates the LTC2414/
LTC2418 noise. This example shows a gain of 34, that is
determined by a feedback network built using a resistor
array containing 8 individual resistors. The resistors are
organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers
the low noise input stage from the transient load steps
produced during conversion.
the rationale. Achieving high gain accuracy and linearity
at higher gains may prove difficult, while providing little
benefit in terms of noise reduction.
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a
gain error of –158ppm. Worst-case gain error at a gain
of 34, is –54ppm. The use of the LTC1051A reduces the
worst-case gain error to –33ppm. The advantage of gain
higher than 34, then becomes dubious, as the input referred noise sees little improvement and gain accuracy is
potentially compromised.
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation amplifier
in that it does not have the high noise level common in
the output stage that usually dominates when and instrumentation amplifier is used at low gain. If this amplifier
is used at a gain of 10, the gain error is only 10ppm and
input referred noise is reduced to 0.1µVRMS. The buffer
stages can also be configured to provide gain of up to 50
with high gain stability and linearity.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor matching.
A gain of 34 may seem low, when compared to common
practice in earlier generations of load-cell interfaces,
however the accuracy of the LTC2414/LTC2418 changes
5VREF
0.1µF
5V
3
2
350Ω
BRIDGE
8
+
1
U1A
–
2
4
15
14
4
1
RN1
16
6
11
7
2
6
5
10
8
3
5
12
3
U1B
U2A
1
11
12
+
4
21
REF +
VCC
SDI
REF –
SCK
SD0
CH0
CS
13
7
5
+
2
8
–
9
6
–
0.1µF
0.1µF
5V
20
18
17
16
LTC2414/
LTC2418
–
U2B
7
22
CH1
+
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
GND
FO
19
15
2414/18 F42
Figure 42. Using Autozero Amplifiers to Reduce Input Referred Noise
38
241418fb
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LTC2414/LTC2418
Applications Information
Remote Half Bridge Interface
Figure 43 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resistors
which match the temperature coefficient of the load-cell
elements, good results can be achieved without the need
for resistors with a high degree of absolute accuracy. The
common mode voltage in this case, is again a function of
the bridge output. Differential gain as used with a 350Ω
bridge is AV = (R1+ R2)/(R1+175Ω). Common mode gain
is half the differential gain. The maximum differential signal
that can be used is 1/4 VREF, as opposed to 1/2 VREF in
the 2-amplifier topology above.
10µF
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For single
variable element bridges, the nonlinearity of the half bridge
output can be eliminated completely; if the reference arm
of the bridge is used as the reference to the ADC, as shown
in Figure 44. The LTC2414/LTC2418 can accept inputs up
to 1/2 VREF. Hence, the reference resistor R1 must be at
least 2x the highest value of the variable resistor.
In the case of 100Ω platinum RTD’s, this would suggest
a value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
0.1µF
5V
9
350Ω
BRIDGE
3
+
2
1µF
+
R1
4.99k
9
0.1µV
7
11
LTC1050S8
–
6
175Ω
1µF
4
12
+
20k
21
R2
46.4k
REF +
R1
25.5k
0.1%
VCC
REF –
22
CH1
PLATINUM
100Ω
RTD
R1 + R2
R1 + 175Ω
11 REF +
LTC2414/
LTC2418
12
REF –
22
CH0
CH1
GND
15
GND
15
(
VCC
21
CH0
LTC2414/
LTC2418
20k
AV = 9.95 =
VS
2.7V TO 5.5V
5V
+
)
2410 F50
2410 F49
Figure 43. Bridge Amplification Using a Single Amplifier
Figure 44. Remote Half Bridge Interface
241418fb
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39
LTC2414/LTC2418
Applications Information
The basic circuit shown in Figure 44 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however,
the reference inputs do not have the same rejection. If
60Hz or other noise is present on the reference input, a
low pass filter is recommended as shown in Figure 45.
Note that you cannot place a large capacitor directly at
the junction of R1 and R2, as it will store charge from
the sampling process. A better approach is to produce a
low pass filter decoupled from the input lines with a high
value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative reference
input is sampling the same external node as the positive
input and may result in errors if used with a long cable.
For short cable applications, the errors may be acceptably
low. If instead the single 25k resistor is replaced with a
10k 5% and a 10k 0.1% reference resistor, the noise level
introduced at the reference, at least at higher frequencies,
will be reduced. A filter can be introduced into the network,
in the form of one or more capacitors, or ferrite beads,
as long as the sampling pulses are not translated into an
error. The reference voltage is also reduced, but this is
not undesirable, as it will decrease the value of the LSB,
although, not the input referred noise level.
The circuit shown in Figure 45 shows a more rigorous
example of Figure 44, with increased noise suppression
and more protection for remote applications.
Figure 46 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043’s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used
at unity gain and introduce very little error due to gain
error or due to offset voltages. A 1µV/°C offset voltage
drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar
to bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error
will be a source of error. The fact that input offset voltage
has relatively little effect on overall error may lead one to
use low performance amplifiers for this application. Note
that the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
5V
R2
10k
0.1%
R1
10k, 5%
5V
R3
10k
5%
+
1µF
LTC1050
9
11
560Ω 12
–
PLATINUM
100Ω
RTD
REF +
VCC
REF –
LTC2414/
LTC2418
10k
21
10k
22
CH0
CH1
GND
15
2410 F51
Figure 45. Remote Half Bridge Sensing with Noise Suppression on Reference
40
241418fb
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LTC2414/LTC2418
Applications Information
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2414/LTC2418 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2VRMS.
Figure 47 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
15V
7
20Ω
Q1
2N3904
6
+
LTC1150
4
–
10V
3
2
200Ω
8
11
47µF
*
10V
LT1236-5
+
0.1µF
12
14
13
10µF
17
+
0.1µF
1k
5V
7
1µF
–15V
33Ω
350Ω
BRIDGE
15V
U1
4
LTC1043
15V
10V
5V
0.1µF
9
VCC
LTC2414/
LTC2418
11
REF +
12
REF –
–10V
33Ω
21
22
U2
LTC1043
15V
Q2
2N3906
20Ω
7
6
+
LTC1150
4
–15V
–
3
15
6
2
*
3
–15V
1k
CH1
GND
5
2
CH0
15
18
0.1µF
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
5V
U2
4
LTC1043
8
7
11
1µF
FILM
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
*
12
200Ω
13
14
–10V
17
–10V
2410 F52
Figure 46. LTC1043 Provides Precise 4X Reference for Excitation Voltages
241418fb
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41
LTC2414/LTC2418
Applications Information
15V
20Ω
Q1
2N3904
+
1/2
LT1112
1
–
C1
0.1µF
22Ω
5V
3
+
LT1236-5
C3
47µF
2
C1
0.1µF
RN1
10k
10V
1
2
3
4
350Ω BRIDGE
TWO ELEMENTS
VARYING
5V
9
RN1
10k
VCC
LTC2414/
LTC2418
11
REF +
12
REF –
21
–5V
22
8
RN1
10k
5
7
CH1
GND
15
6
15V
C2
0.1µF
33Ω
×2
Q2, Q3
2N3906
×2
RN1
10k
CH0
20Ω
7
8
–
6
+
5
1/2
LT1112
4
RN1 IS CADDOCK T914 10K-010-02
–15V
–15V
2410 F53
Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
MULTIPLE CHANNEL USAGE
The LTC2414/LTC2418 have up to sixteen input channels
and this feature provides a very flexible and efficient solution in applications where more than one variable need
to be measured.
Measurements of a Ladder of Sensors
In industrial process, it is likely that a large group of
real world phenomena need to be monitored where the
speed is not critical. One example is the cracking towers
in petroleum refineries where a group of temperature
measurements need to be taken and related. This is done
by passing an excitation current through a ladder of RTDs.
The configuration using a single LTC2418 to monitor up
to eight RTDs in differential mode is shown in Figure 48.
A high accuracy R1 is used to set the excitation current
and the reference voltage. A larger value of 25k is se-
42
lected to reduce the self-heating effects. R1 can also be
broken into two resistors, one 25k to set the excitation
current and the other a high accuracy 1k resistor to set
the reference voltage, assuming 100Ω platinum RTDs.
This results in a reduced reference voltage and a reduced
common mode difference between the reference and the
input signal, which improves the conversion linearity and
reduces total error.
Each input should be taken close to the related RTD to
minimize the error caused by parasitic wire resistance. The
interference on a signal transmission line from RTD to the
LTC2418 is rejected due to the excellent common mode
rejection and the digital LPF included in the LTC2418. It
should be noted that the input source resistance of CHO
can have a maximum value of 800Ω • 8 = 6.4k, so the
parasitic capacitance and resistance of the connection
wires need to be minimized in order not to degrade the
converter performance.
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
Applications Information
Figure 49 shows the 4-wire SPI connection between the
LTC2414/LTC2418 and a PIC16F84 microcontroller. The
sample program for CC5X compiler in Figure 50 can be
used to program the PIC16F84 to control the LTC2414/
LTC2418. It uses PORT B to interface with the device.
5V
0.1µF
+
R1
25k
0.1%
10µF
9
11
REF +
12
REF –
21
PT1
100Ω
RTD
22
23
PT2
100Ω
RTD
LTC2418
CH0
CH1
SDI
CH2
SCK
24
•
•
•
PT8
100Ω
RTD
VCC
CH3
•
•
•
7
CH14
8
CH15
SDO
CS
GND
FO
20
18
4-WIRE
SPI
17
16
19
15
2418 F48
Figure 48. Measurement of a Ladder of Sensors Using
Differential Mode
The program begins by declaring variables and allocating four memory locations to store the 32-bit conversion
result. In execution, it first initiates the PORT B to the
proper SPI configuration and prepares channel address.
The LTC2414/LTC2418 is activated by setting the CS low.
Then the microcontroller waits until a logic LOW is detected
on the data line, signifying end-of-conversion. After a
LOW is detected, a subroutine is called to exchange data
between the LTC2414/LTC2418 and the microcontroller.
The main loop ends by setting CS high, ending the data
output state.
The performance of the LTC2414/LTC2418 can be verified
using the demonstration board DC434A, see Figure 51 for
the schematic. This circuit uses the computer’s serial port
to generate power and the SPI digital signals necessary for
starting a conversion and reading the result. It includes a
Multichannel Bridge Digitizer and Digital Cold
Junction Compensation
The bridge application as shown in Figures 41, 42, and 43
can be expanded to multiple bridge transducers. Figure
54 shows the expansion for simple bridge measurement.
Also included is the temperature measurement.
In Figure 54, CH0 to CH13 are configured as differential
to measure up to seven bridge transducers using the
LTC2418. CH14 and CH15 are configured as single-ended.
CH14 measures the thermocouple while CH15 measures
the output of the cold junction sensor (diode, thermistor,
etc.). The measured cold junction sensor output is then
used to compensate the thermocouple output to find the
absolute temperature. The final temperature value may
then be used to compensate the temperature effects of
the bridge transducers.
Sample Driver for LTC2414/LTC2418 SPI Interface
PIC16F84
LTC2414/
LTC2418
SCK
SDI
SDO
CS
18
20
17
16
8
9
10
11
RB2
RB3
RB4
RB5
2414/18 F49
Figure 49. Connecting the LTC2414/LTC2418 to
a PIC16F84 MCU Using the SPI Serial Interface
LabVIEW™ application software program (see Figure 52)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and
with an external source linearity. As exemplified in the
schematic, the LTC2414/LTC2418 is extremely easy to
use. This demonstration board and associated software
is available by contacting Linear Technology.
The LTC2414/LTC2418 have a simple 4-wire serial interface and it is easy to program microprocessors and
microcontrollers to control the device.
241418fb
For more information www.linear.com/LTC2414
43
LTC2414/LTC2418
Applications Information
// LTC2418 PIC16F84 Interface Example
// Written for CC5X Compiler
// Processor is PIC16F84 running at 10 MHz
#include
#include
#pragma origin = 0x4
#pragma config |= 0x3fff, WDTE=off,FOSC=HS
// global pin definitions:
#pragma bit rx_pin
#pragma bit tx_pin
#pragma bit sck
#pragma bit sdi
#pragma bit sdo
#pragma bit cs_bar
@
@
@
@
@
@
PORTB.0
PORTB.1
PORTB.2
PORTB.3
PORTB.4
PORTB.5
//input
//output
//output
//output
//input
//output
// Global Variables
uns8 result_3;
uns8 result_2;
uns8 result_1;
uns8 result_0;
//
//
//
//
void shiftbidir(char nextch);
// function prototype
Conversion result MS byte
..
..
Conversion result LS byte
void main( void)
{
INTCON=0b00000000;
TRISA=0b00000000;
TRISB=0b00010001;
// no interrupts
// all PORTA pins outputs
// according to definitions above
char channel;
// next channel to send
while(1)
{
/* channel bit fields are 7:6, 10 always; 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */
channel = 0b10101000;
cs_bar=0;
while(sdo==1)
{
// CH0,1 DIFF.
// activate ADC
// test for end of conversion
// wait if conversion is not complete
}
shiftbidir(channel); // read ADC, send next channel
cs_bar = 1;
// deactivate ADC
/* At this point global variables result 3,2,1 contain the 24 bit conversion result. Variable result3
contains the corresponding channel information in the following fields:
bits 7:6, 00 always, 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */
} // end of loop
} // end of main
Figure 50. Sample Program in CC5X for PIC16F84
44
241418fb
For more information www.linear.com/LTC2414
LTC2414/LTC2418
Applications Information
////////// Bidirectional Shift Routine for ADC //////////
void shiftbidir(char nextch)
{
int i;
for(i=0;i
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