LTC2500-32
32-Bit Oversampling ADC
with Configurable Digital Filter
FEATURES
DESCRIPTION
±0.5ppm INL (Typ)
nn 104dB SNR (Typ) at 1Msps
nn 148dB Dynamic Range (Typ) at 61sps
nn Guaranteed 32-Bit No Missing Codes
nn Configurable Digital Filter with Synchronization
nn Relaxed Anti-Aliasing Filter Requirements
nn Dual Output 32-Bit SAR ADC
nn 32-Bit Digitally Filtered Low Noise Output
nn 24-Bit Differential + 7-Bit Common Mode 1Msps
Output with Overrange Detection
nn Wide Input Common Mode Range
nn Guaranteed Operation to 85°C
nn 1.8V to 5V SPI-Compatible Serial I/O
nn Low Power: 24mW at 1Msps
nn 24-Lead 7mm × 4mm DFN Packages
The LTC®2500-32 is a low noise, low power, high performance 32-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2500-32
features a fully differential input range up to ±VREF, with
VREF ranging from 2.5V to 5.1V. The LTC2500-32 supports
a wide common mode range from 0V to VREF simplifying
analog signal conditioning requirements.
nn
The LTC2500-32 simultaneously provides two output
codes: (1) a 32-bit digitally filtered high precision low
noise code, and (2) a 32-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and downsampling the stream of data
from the SAR ADC core, giving the 32-bit filtered output
code. The 32-bit composite code consists of an overrange
detection bit, a 24-bit code representing the differential
input voltage and a 7-bit code representing the common
mode input voltage. The 32-bit composite code is available
each conversion cycle, with no cycle of latency.
APPLICATIONS
Seismology
Energy Exploration
nn Automatic Test Equipment
nn High Accuracy Instrumentation
nn
The digital filter is highly configurable through the SPIcompatible interface and features many distinct filter types
that suit a variety of applications. The digital lowpass filter
relaxes the requirements for analog anti-aliasing. Multiple
LTC2500-32 devices can be easily synchronized using
the SYNC pin.
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9231611,
9054727, 9331709 and patents pending.
TYPICAL APPLICATION
Integral Nonlinearity vs
Output Code
1.8V TO 5.1V
2.5V
2.0
0.1µF
IN+, IN–
VREF
ARBITRARY
0V
VREF
DIFFERENTIAL
VREF
VDD
IN+
32-BIT
SAR ADC
CORE
0V
BIPOLAR
VREF
UNIPOLAR
LTC2500-32
PROGRAMMABLE
LOW PASS
WIDEBAND DIGITAL
FILTER
0V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
REF
2.5V TO 5.1V
32-BIT
24-BIT
IN –
0V
OVDD
GND
MCLK
BUSY
DRL
1.5
SAMPLE
CLOCK
SDI
SDOA
SCKA
RDLA
RDLB
SDOB
SCKB
250032 TA01
47µF
(X7R, 1210 SIZE)
1.0
INL ERROR (ppm)
10µF
0.5
0
–0.5
–1.0
–1.5
–2.0
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
5
250032 TA01b
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For more information www.linear.com/LTC2500-32
1
LTC2500-32
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Order Information.................................................................................................................. 3
Pin Configuration.................................................................................................................. 3
Electrical Characteristics......................................................................................................... 4
Converter Characteristics for Filtered Output (SDOA)........................................................................ 4
Dynamic Accuracy for Filtered Output (SDOA)................................................................................ 4
Converter Characteristics for No latency Output (SDOB).................................................................... 4
Dynamic Accuracy for No Latency Output (SDOB)............................................................................ 5
Reference Input.................................................................................................................... 5
Digital Inputs and Digital Outputs............................................................................................... 6
Power Requirements.............................................................................................................. 6
ADC Timing Characteristics...................................................................................................... 6
Typical Performance Characteristics........................................................................................... 8
Pin Functions......................................................................................................................11
Functional Block Diagram.......................................................................................................12
Timing Diagram...................................................................................................................12
Applications Information........................................................................................................13
Overview................................................................................................................................................................ 13
Converter Operation............................................................................................................................................... 13
Transfer Function................................................................................................................................................... 13
Analog Input.......................................................................................................................................................... 13
Input Drive Circuits................................................................................................................................................ 14
ADC Reference....................................................................................................................................................... 21
Dynamic Performance........................................................................................................................................... 22
Power Considerations............................................................................................................................................ 22
Timing and Control................................................................................................................................................ 23
Decimation Filters.................................................................................................................................................. 23
Digital Filter Types................................................................................................................................................. 26
Digital Interface..................................................................................................................................................... 33
Preset Filter Modes................................................................................................................................................ 36
Filtered Output Data............................................................................................................................................... 36
No Latency Output Data......................................................................................................................................... 45
Board Layout......................................................................................................................51
Package Description.............................................................................................................52
Revision History..................................................................................................................53
Typical Application...............................................................................................................54
Related Parts......................................................................................................................54
2
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LTC2500-32
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VDD)................................................2.8V
Supply Voltage (OVDD).................................................6V
Reference Input (REF)..................................................6V
Analog Input Voltage (Note 3)
IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2500C-32............................................ 0°C to 70°C
LTC2500I-32.........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
ORDER INFORMATION
TOP VIEW
RDLA 1
RDLB 2
VDD 3
GND 4
IN+ 5
IN– 6
GND 7
REF 8
REF 9
PRE 10
GND 11
GND 12
25
GND
24 GND
23 GND
22 OVDD
21 BUSY
20 SDOB
19 SCKB
18 SCKA
17 SDOA
16 SDI
15 DRL
14 SYNC
13 MCLK
DKD PACKAGE
24-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2500-32#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2500CDKD-32#PBF
LTC2500CDKD-32#TRPBF
250032
24-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC2500IDKD-32#PBF
LTC2500IDKD-32#TRPBF
250032
24-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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3
LTC2500-32
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
+
Absolute Input Range (IN+)
VIN–
Absolute Input Range (IN–)
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
VCM
Common Mode Input Range
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
MIN
MAX
UNITS
0
VREF
V
0
VREF
V
l
−VREF
VREF
V
l
0
VREF
V
(Note 5)
l
(Note 5)
l
TYP
10
nA
Sample Mode
Hold Mode
45
5
pF
pF
No Latency Output
VIN+ = VIN– = 4.5VP-P, 2kHz Sine
128
dB
CONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
(Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Resolution
32
Bits
No Missing Codes
l
32
Bits
Transition Noise
(Note 6) See Table 2
DF
Down-Sampling Factor
INL
Integral Linearity Error
(Notes 7, 8)
l
–2
ZSE
Zero-Scale Error
(Notes 7, 9)
l
13
Zero-Scale Error Drift
(Note 7)
FSE
TYP
l
4
Full-Scale Error
(Notes 7, 9)
Full-Scale Error Drift
(Note 7)
16384
±0.5
2
0
13
±7
l
–100
±10
ppm
ppm
ppb/°C
100
±0.05
ppm
ppm/°C
DYNAMIC ACCURACY FOR FILTERED OUTPUT (SDOA)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and
ssinc filter. (Notes 4, 9)
SYMBOL
PARAMETER
CONDITIONS
DR
Dynamic Range
DF = 4
IN+ = IN– = VCM, VREF = 5V, DF = 64
IN+ = IN– = VCM, VREF = 5V, DF = 1024
l
l
l
MIN
TYP
110
122
129.5
116
128
138
MAX
UNITS
dB
dB
dB
CONVERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
(Notes 4)
SYMBOL
PARAMETER
CONDITIONS
TYP
MAX
UNITS
Resolution:
Differential
Common Mode
l
l
24
7
Bits
Bits
No Missing Codes:
Differential
Common Mode
l
l
24
7
Bits
Bits
Transition Noise:
Differential
Common Mode
4
MIN
2.3
1
ppmRMS
LSBRMS
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LTC2500-32
CONVERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
(Notes 4)
SYMBOL
PARAMETER
CONDITIONS
INL
Integral Linearity Error:
Differential
Common Mode
7-Bit Output
Zero-Scale Error:
Differential
Common Mode
7-Bit Output
ZSE
MIN
TYP
MAX
l
–2
±0.5
±0.1
2
ppm
LSB
l
–13
0
±1
13
ppm
LSB
Zero-Scale Error Drift:
Differential
FSE
Full-Scale Error:
Differential
Common Mode
±7
l
7-Bit Output
–100
Full-Scale Error Drift:
Differential
±10
±1
UNITS
ppb/°C
100
±0.05
ppm
LSB
ppm/°C
DYNAMIC ACCURACY FOR NO LATENCY OUTPUT (SDOB)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and
AIN = –1dBFS. The specifications are for the differential output (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 2kHz, VREF = 5V
l
100
104
fIN = 2kHz, VREF = 5V
l
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
100
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
SFDR
Spurious Free Dynamic Range
fIN = 2kHz, VREF = 5V
l
UNITS
dB
104
–120
–120
dB
–114
–113
dB
dB
128
dB
–3dB Input Linear Bandwidth
34
MHz
Aperture Delay
500
ps
Aperture Jitter
4
Transient Response
115
MAX
Full-Scale Step
psRMS
125
ns
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Notes 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
VREF
Reference Voltage
(Note 5)
l
IREF
Reference Input Current
(Note 11)
l
TYP
MAX
5.1
V
0.9
1.4
mA
2.5
UNITS
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5
LTC2500-32
DIGITAL
INPUTS AND DIGITAL OUTPUTS
The
l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
l
VIL
Low Level Input Voltage
l
VIN = 0V to OVDD
MIN
TYP
MAX
UNITS
0.8 • 0VDD
V
V
10
µA
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500 µA
l
VOL
Low Level Output Voltage
IO = 500 µA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
l
–10
0.2 • OVDD
5
pF
OVDD – 0.2
V
–10
0.2
V
10
µA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.5
2.625
V
5.25
V
VDD
Supply Voltage
l
2.375
OVDD
Supply Voltage
l
1.71
IVDD
IOVDD
IPD
Supply Current
Supply Current
Power Down Mode
1Msps Sample Rate
1Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
PD
Power Dissipation
Power Down Mode
1Msps Sample Rate (IVDD)
Conversion Done (IVDD + IOVDD + IREF)
l
l
9.5
1
6
14
350
mA
mA
µA
24
15
35
875
mW
µW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
fDRA
fDRB
CONDITIONS
MIN
MAX
UNITS
l
1
Msps
Output Data Rate at SDOA
l
250
ksps
Output Data Rate at SDOB
l
1
Msps
tCONV
Conversion Time
tACQ
Acquisition Time
tCYC
Time Between Conversions
tMCLKH
Conversion High Time
tMCLKL
Minimum Low Time for MCLK
(Note 13)
tBUSYLH
MCLK to BUSY Delay
CL = 20pF
l
tACQ = tCYC – tCONV – tBUSYLH (Note 12)
TYP
l
600
l
327
660
ns
l
1000
ns
l
20
ns
l
20
ns
13
ns
ns
tQUIET
SCKA, SCKB Quiet Time from MCLK
(Note 12)
l
10
ns
tSCKA
SCKA Period
(Notes 13, 14)
l
10
ns
tSCKAH
SCKA High Time
l
4
ns
tSCKAL
SCKA Low Time
l
4
ns
tSSDISCKA
tHSDISCKA
SD1 Setup Time from SCKA
SD1 Hold Time from SCKA
(Note 13)
(Note 13)
l
l
4
1
ns
ns
tDSDOA
SDOA Data Valid Delay from SCKA
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
6
8.5
8.5
9.5
ns
ns
ns
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LTC2500-32
ADC
TIMING CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
tHSDOA
SDOA Data Remains Valid Delay from
SCKA
CL = 20pF (Note 12)
l
tDSDOADRLL
SDOA Data Valid Delay from DRL
CL = 20pF (Note 12)
l
5
ns
tENA
Bus Enable Time After RDLA
(Note 13)
l
16
ns
tDISA
Bus Relinquish Time After RDLA
(Note 13)
l
13
ns
(Notes 13, 14)
l
10
ns
l
4
ns
l
4
ns
1
UNITS
ns
tSCKB
SCKB Period
tSCKBH
SCKB High Time
tSCKBL
SCKB Low Time
tDSDOB
SDOB Data Valid Delay from SCKB
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
tHSDOB
SDOB Data Remains Valid Delay from
SCKB
CL = 20pF (Note 12)
l
tDSDOBBUSYL
SDOB Data Valid Delay from BUSY
CL = 20pF (Note 12)
l
5
ns
tENB
Bus Enable Time After RDLB
(Note 13)
l
16
ns
tDISB
Bus Relinquish Time After RDLB
(Note 13)
l
13
ns
8.5
8.5
9.5
1
ns
ns
ns
ns
Note 8: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 9: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111
1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error.
Note 10: All specifications in dB are referred to a full-scale ±5V input with
a 5V reference voltage.
Note 11: fSMPL = 1MHz, IREF varies proportionally with sample rate.
Note 12: Guaranteed by design, not subject to test.
Note 13: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 14: tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up
to 100MHz for rising edge capture.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latchup.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz.
Note 5: Recommended operating conditions.
Note 6: Transition noise is defined as the noise level of the ADC with IN+
and IN– shorted.
Note 7: The DC specifications at SDOA are measured and guaranteed at
SDOB. The operation of the digital filters is tested separately to guarantee
the same DC specifications at SDOA.
tWIDTH
0.8 • OVDD
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
250032 F01
Figure 1. Voltage Levels for Timing Specifications
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For more information www.linear.com/LTC2500-32
7
LTC2500-32
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, no latency output, unless otherwise noted.
Integral Nonlinearity vs Input
Voltage
Differential Nonlinearity vs Input
Voltage
2.0
1.0
1.5
0.8
0
–0.5
0.2
COUNTS
DNL (LSB)
INL ERROR (ppm)
0.4
0.5
0.0
–0.2
–0.8
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
–1.0
5
–5
250032 G01
DC Histogram Filtered Output,
DF = 4, SSINC Filter
1000
–2.5
0
2.5
INPUT VOLTAGE (V)
0
–15
5
1000
σ = 0.7ppm
DC Histogram Filtered Output,
DF = 1024, SSINC Filter
1000
σ = 0.17ppm
800
600
600
600
COUNTS
800
200
400
200
–4
–3
–2 –1
0
1
2
OUTPUT CODE (ppm)
3
0
4
–1
–0.5
0
0.5
OUTPUT CODE (ppm)
0
σ = 0.018ppm
200
0.4
250032 G07
8
0
–40
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
0
125
250
375
FREQUENCY (kHz)
SNR = 116dB
THD = –120dB
SINAD = 114dB
SFDR = 121dB
–20
–60
–180
0.4
128k Point FFT Filtered Output,
fIN = 2kHz, DF = 4, SSINC Filter
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
400
–0.2
0
0.2
OUTPUT CODE (ppm)
250032 G06
SNR = 104dB
THD = –120dB
SINAD = 104dB
SFDR = 121dB
–20
–40
–0.2
0
0.2
OUTPUT CODE (ppm)
0
–0.4
1
16k Point FFT fIN = 2kHz
800
0
–0.4
400
250032 G05
DC Histogram Filtered Output,
DF = 16384, SSINC Filter
600
σ = 0.049ppm
200
250032 G04
1000
15
250032 G03
800
400
–7.5
0
7.5
OUTPUT CODE (ppm)
250032 G02
DC Histogram Filtered Output,
DF = 64, SSINC Filter
COUNTS
COUNTS
4000
2000
–0.6
–1.5
COUNTS
6000
–0.4
–1.0
0
σ = 2.4ppm
8000
0.6
1.0
–2.0
DC Histogram
10000
500
250032 G08
–180
0
31
62
94
FREQUENCY (kHz)
125
250032 G09
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LTC2500-32
T
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, no latency output, unless otherwise noted.
0
128k Point FFT Filtered Output,
fIN = 200Hz, DF = 64, SSINC Filter
8k Point FFT Filtered Output,
fIN = 11Hz, DF = 16384, SSINC Filter
0
DR = 137dB
–20
–40
–60
–60
–100
–120
–140
AMPLITUDE (dBFS)
–40
–60
–80
–80
–100
–120
–140
–80
–100
–120
–140
–160
–160
–160
–180
–180
–180
–200
–200
4
6
FREQUENCY (kHz)
8
0
122
250032 G10
SNR, SINAD (dBFS)
DYNAMIC RANGE (dB)
100
105
–90
104
–95
103
140
130
SINC1
SINC2
SINC3
SINC4
SSINC
FLAT PASSBAND
4
10
100
1000
DOWNSAMPLING FACTOR
SNR
102
101
100
SINAD
99
98
97
96
95
16384
0
25
50
SNR, SINAD (dBFS)
SNR, SINAD (dBFS)
–110
–115
–120
–125
–130
25
50
75 100 125 150 175 200
FREQUENCY (kHz)
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
102
–120
SINAD
101
100
99
98
97
101
0
250032 G15
SNR
103
102
–125
–130
–135
THD
2ND
3RD
–140
96
100
–40
–30
–20
–10
INPUT LEVEL (dB)
0
250032 G16
250032 G12
–115
104
SNR
31
–105
–140
75 100 125 150 175 200
FREQUENCY (kHz)
105
103
–100
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
105
15
23
FREQUENCY (Hz)
THD
2ND
3RD
250032 G14
SNR, SINAD vs Input Level,
fIN = 2kHz
SINAD
8
–135
250032 G13
104
0
THD, Harmonics vs Input
Frequency
SNR, SINAD vs Input Frequency
150
110
–200
488
250032 G11
Filtered Output Dynamic Range
vs DF
120
244
366
FREQUENCY (Hz)
HARMONICS, THD (dBFS)
2
HARMONICS, THD (dBFS)
0
DR = 149dB
–20
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
DR = 128dB
–20
128k Point FFT Filtered Output,
fIN = 100Hz, DF = 1024, SSINC Filter
95
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
250032 G17
–145
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
250032 G18
250032fb
For more information www.linear.com/LTC2500-32
9
LTC2500-32
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 2.5V, 0VDD = 2.5V, VCM = 2.5V,
T
REF = 5V, fSMPL = 1Msps, no latency output, unless otherwise noted.
–110
THD, HARMONICS (dBFS)
SNR
104
SINAD
103
102
3
2
THD
–120
3RD
–125
–130
2ND
100
–40
–15
10
35
TEMPERATURE (°C)
60
85
–140
–40
Full-Scale Error vs Temperature
–15
10
35
TEMPERATURE ( °C)
60
–FS
10
35
TEMPERATURE (oC)
60
10
4
9
3
2
1
0
–1
–2
–3
–15
10
35
TEMPERATURE (°C)
60
250032 G22
20
10
0
–40
–15
10
35
TEMPERATURE (°C)
10
60
85
250032 G25
6
5
4
3
2
IREF
0
–40
85
–15
140
0.9
130
0.8
120
0.7
100
0.5
90
3.5
4
4.5
REFERENCE VOLTAGE (V)
60
85
5
250032 G26
VIN+ = V IN– = 4.5V P-P SINE
110
0.6
3
10
35
TEMPERATURE (°C)
CMRR vs Input Frequency
1.0
0.4
2.5
I OVDD
250032 G24
CMRR (dB)
REFERENCE CURRENT (mA)
POWER–DOWN CURRENT (µA)
30
7
Reference Current vs Reference
Voltage
40
85
8
250032 G23
Shutdown Current vs Temperature
60
IVDD
1
–5
–40
85
10
35
TEMPERATURE (°C)
Supply Current vs Temperature
5
–4
–15
–15
250032 G21
POWER SUPPLY CURRENT (mA)
ZERO-SCALE ERROR (ppm)
0
MIN INL
–4
–40
85
Offset Error vs Temperature
+FS
–10
–40
–1
250032 G20
10
5
MAX INL
0
–3
250032 G19
–5
1
–2
–135
101
FULL–SCALE ERROR (ppm)
INL vs Temperature
4
–115
105
SNR, SINAD (dBFS)
THD, Harmonics vs Temperature,
fIN = 100Hz
INL ERROR (ppm)
106
SNR, SINAD vs Temperature,
fIN = 2kHz
80
0.01
0.1
1
10
FREQUENCY (kHz)
100
500
250032 G27
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
PIN FUNCTIONS
RDLA (Pin 1): Read Low Input A (Filtered Output). When
RDLA is low, the serial data output A (SDOA) pin is enabled.
When RDLA is high, SDOA pin is in a high impedance
state. Logic levels are determined by OVDD.
DRL (Pin 15): Data Ready Low Output. A falling edge
on this pin indicates that a new filtered output code is
available in the output register of SDOA. Logic levels are
determined by OVDD.
RDLB (Pin 2): Read Low Input B (No Latency Output).
When RDLB is low, the serial data output B (SDOB) pin
is enabled. When RDLB is high, SDOB pin is in a high
impedance state. Logic levels are determined by OVDD.
SDI (Pin 16): Serial Data Input. Data provided on this line,
in synchrony with SCKA, can be used to program the digital
filter and DGC/DGE modes. Input data on SDI is latched on
rising edges of SCKA. Logic levels are determined by OVDD.
VDD (Pin 3): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic capacitor.
SDOA (Pin 17): Serial Data Output A (Filtered Output).
The filtered output code appears on this pin (MSB first)
on each rising edge of SCKA. The output data is in 2’s
complement format. Logic levels are determined by OVDD.
GND (Pins 4, 7, 11, 12, 23, 24): Ground.
IN+ (Pin 5): Positive Analog Input.
IN– (Pin 6): Negative Analog Input.
REF (Pins 8, 9): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X7R, 1210 size, 10V rating).
PRE (Pin 10): Preset Input. By setting PRE high, the SDI
pin is used to select between two preset digital filter modes.
Setting PRE low allows the digital filter to be configured
by entering a configuration word at SDI. Logic levels are
determined by REF, with range of REF being 2.5V to 5.1V.
MCLK (Pin 13): Master Clock Input. A rising edge on this
input powers up the part and initiates a new conversion.
Logic levels are determined by OVDD.
SYNC (Pin 14): Synchronization Input. A pulse on this
input is used to synchronize the phase of the digital filter.
When applied across multiple devices, a SYNC pulse synchronizes all the devices to the same phase. Logic levels
are determined by OVDD.
SCKA (Pin 18): Serial Data Clock Input A (Filtered Output).
When SDOA is enabled, the filtered output code is shifted
out (MSB first) on the rising edges of this clock. Logic
levels are determined by OVDD.
SCKB (Pin 19): Serial Data Clock Input B (No Latency
Output). When SDOB is enabled, the no latency output
code is shifted out (MSB first) on the rising edges of this
clock. Logic levels are determined by OVDD.
SDOB (Pin 20): Serial Data Output B (No Latency Output).
The 32-bit no latency composite output code appears on
this pin (MSB first) on each rising edge of SCKB. The
output data is in 2’s complement format. Logic levels are
determined by OVDD.
BUSY (Pin 21): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
OVDD (Pin 22): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V, or
5V). Bypass OVDD to GND (Pin 23) with a 0.1µF capacitor.
GND (Exposed Pad Pin 25): Ground. Exposed pad must
be soldered directly to the ground plane.
250032fb
For more information www.linear.com/LTC2500-32
11
LTC2500-32
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 2.5V TO 5.1V
OVDD = 1.8V TO 5V
LTC2500-32
SDI
IN+
SDOA
+
32-BIT
SAR ADC
IN–
DIGITAL
FILTER
SCKA
32
RDLA
SPI
PORT
–
SCKB
SDOB
24
RDLB
MCLK
BUSY
DRL
CONTROL LOGIC
SYNC
PRE
GND
250032 FBD
TIMING DIAGRAM
RDLA = RDLB = 0
MCLK
CONVERT
DRL
SCKA
DA30
DA28
DA26
DA24
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
SDOA
DA31
DA29
DA27
DA25
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DA5
DA3
DA1
CONVERT
POWER DOWN AND ACQUIRE
BUSY
SCKB
DB23
DB21
DB19
DB17
DB15
DB13
DB11
DB9
DB7
DB5
DB3
DB1
CB6
CB4
CB2
CB0
SDOB
OVRNG
12
DB22
DB20
DB18
DB16
DB14
DB12
DB10
DB8
DB6
DB4
DB2
DB0
CB5
CB3
CB1
250032 TD
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
The LTC2500-32 is a low noise, low power, high performance 32-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2500-32
features a fully differential input range up to ±VREF, with
VREF ranging from 2.5V to 5.1V. The LTC2500-32 supports
a wide common mode range from 0V to VREF simplifying
analog signal conditioning requirements.
The LTC2500-32 simultaneously provides two output
codes: (1) a 32-bit digitally filtered high precision low
noise code, and (2) a 32-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of data
from the SAR ADC core, giving the 32-bit filtered output
code. The 32-bit composite code consists of an overrange
detection bit, a 24-bit code representing the differential
input voltage and a 7-bit code representing the common
mode input voltage. The 32-bit composite code is available
each conversion cycle, with no cycle of latency.
The digital filter is highly configurable through the SPIcompatible interface and features many distinct filter types
that suit a variety of applications. The digital lowpass filter
relaxes the requirements for analog anti-aliasing. Multiple
LTC2500-32 devices can be easily synchronized using
the SYNC pin.
a 24-bit code representing the differential voltage and a
7-bit code representing the common mode voltage are
combined to form a 32-bit composite code. The 32-bit
composite code is available each conversion cycle, without
any cycle of latency.
TRANSFER FUNCTION
The LTC2500-32 digitizes the full-scale differential voltage
of 2 × VREF into 232 levels, resulting in an LSB size of 2.3nV
with a 5V reference. The ideal transfer function is shown
in Figure 2. The output data is in 2’s complement format.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/4294967296
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
250032 F02
Figure 2. LTC2500-32 Transfer Function
ANALOG INPUT
CONVERTER OPERATION
The LTC2500-32 operates in two phases. During the acquisition phase, a 32-bit charge redistribution capacitor
D/A converter (CDAC) is connected to the IN+ and IN– pins
to sample the analog input voltages. A rising edge on the
MCLK pin initiates a conversion. During the conversion
phase, the 32-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the
sampled inputs with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/4294967296).
At the end of conversion, the CDAC output approximates
the sampled analog input. The ADC control logic then
passes the 32-bit digital output code to the digital filter
for further processing. The LTC2500-32 also has an overrange detector. The overrange detector bit is flagged as
1 if the differential input exceeds ±VREF, and is updated
every conversion cycle. The 1-bit overrange detector bit,
The LTC2500-32 samples the voltage difference (IN+ –
IN–) between its analog input pins over a wide common
mode input range while attenuating unwanted signals
common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode input
range coupled with high CMRR allows the IN+/IN– analog
inputs to swing with an arbitrary relationship to each other,
provided each pin remains between GND and VREF. This
unique feature of the LTC2500-32 enables it to accept a
wide variety of signal swings, including traditional classes
of analog input signals such as pseudo-differential unipolar,
pseudo-differential bipolar, and fully differential, thereby
simplifying signal chain design.
In the acquisition phase, each input sees approximately
45pF (CIN) from the sampling circuit in series with 40Ω
(RON) from the on-resistance of the sampling switch.
250032fb
For more information www.linear.com/LTC2500-32
13
LTC2500-32
APPLICATIONS INFORMATION
The inputs draw a current spike while charging the CIN
capacitors during acquisition. During conversion, the
analog inputs draw only a small leakage current.
RON
40Ω
IN
REF
IN–
SINGLE-ENDEDINPUT SIGNAL LPF1
500Ω
REF
+
LPF2
RON
40Ω
CIN
45pF
6600pF
6800pF
10Ω
IN+
3300pF
10Ω
LTC2500-32
IN–
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 1.2MHz
CIN
45pF
BIAS
VOLTAGE
250032 F03
Figure 3. The Equivalent Circuit for the Differential Analog
Input of the LTC2500-32
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2500-32 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For
best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2500-32. The amplifier
provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs.
250032 F04
Figure 4. The Equivalent Input for the Differential Analog
Input of the LTC2500-32
with a low noise density must be selected to minimize
degradation of SNR.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Input Currents
The noise and distortion of the input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter (LPF1) shown in Figure 4 is sufficient
for many applications.
An important consideration when coupling an amplifier to
the LTC2500-32 is in dealing with current spikes drawn
by the ADC inputs at the start of each acquisition phase.
The ADC inputs may be modeled as a switched capacitor
load of the drive circuit. A drive circuit may rely partially
on attenuating switched-capacitor current spikes with
small filter capacitors CFILT placed directly at the ADC
inputs, and partially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance.
Amplifiers optimized for DC performance may not have
sufficient bandwidth to fully recover at the ADC’s maximum
conversion rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
A coupling filter network (LPF2) should be used between
the buffer and ADC input to minimize disturbances reflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
of the analog inputs. Therefore, LPF2 typically requires a
wider bandwidth than LPF1. This filter also helps minimize
the noise contribution from the buffer. A buffer amplifier
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is considerably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
Noise and Distortion
14
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
the input settles completely (to within the accuracy of the
LTC2500-32), the disturbance will not contribute any error.
Fully Averaged – If the coupling filter capacitors (CFILT) at
the ADC inputs are much larger than the ADC’s sample
capacitors (45pF), then the sampling glitch is greatly attenuated. The driving amplifier effectively only sees the
average sampling current, which is quite small. At 1Msps,
the equivalent input resistance is approximately 22kΩ
(as shown in Figure 5), a benign resistive load for most
precision amplifiers. However, resistive voltage division
will occur between the coupling filter’s DC resistance and
the ADC’s equivalent (switched-capacitor) input resistance,
thus producing a gain error.
IN
22k
(REQ)
IN–
4
DIFFERENTIAL
1
22k
(REQ)
COMMON
–2
–5
–40
–15
10
35
TEMPERATURE (°C)
60
85
250032 F06
Figure 6. Common Mode and Differential
Input Leakage Current Over Temperature
extremely small over the entire operating temperature
range. Figure 6 shows the input leakage currents over
temperature for a typical part.
Let RS1 and RS2 be the source impedances of the differential input drive circuit shown in Figure 7, and let IL1
and IL2 be the leakage currents flowing out of the ADC’s
analog inputs. The differential voltage error, VE, due to the
leakage currents can be expressed as:
R +R
I +I
VE = S1 S2 • (IL1 – IL2 ) + (R S1 –R S2 ) • L1 L2
2
2
RS1
LTC2500-32
+
CFILT>>45pF
VIN = VREF
7
INPUT LEAKAGE (nA)
Partially Settled – In this case, the beginning of acquisition causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switchedcapacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high frequency
energy before it reaches the amplifier.
10
IL1
+
VE
–
BIAS
VOLTAGE
RS2
IN+
LTC2500-32
IN–
IL2
250032 F07
Figure 7. Source Impedances of a Driver and Input
Leakage Currents of the LTC2500-32
CFILT>>45pF
250032 F05
1
REQ =
fSMPL • 45pF
Figure 5. Equivalent Circuit for the Differential
Analog Input of the LTC2500-32 at 1Msps
The input leakage currents of the LTC2500-32 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leakage
currents, both common mode and differential, are typically
The common mode input leakage current, (IL1 + IL2)/2, is
typically extremely small (Figure 6) over the entire operating temperature range and common mode input voltage
range. Thus, any reasonable mismatch (below 5%) of the
source impedances RS1 and RS2 will cause only a negligible
error. The differential leakage current is also typically very
small, and its nonlinear component is even smaller. Only
the nonlinear component will impact the ADC’s linearity.
250032fb
For more information www.linear.com/LTC2500-32
15
LTC2500-32
APPLICATIONS INFORMATION
For optimal performance, it is recommended that the
source impedances, RS1 and RS2, be between 5Ω and
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
RS1 and RS2 are usually not critical. The guaranteed AC
and DC specifications are tested with 5Ω source impedances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling.
Arbitrary Analog Input Signals
The wide common mode input range and high CMRR of
the LTC2500-32 allow analog inputs IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
that each pin remains between VREF and GND. This unique
feature of the LTC2500-32 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
Buffering AC Input Signals
It is recommended that the LTC2500-32 be driven using
the LT6203 configured as two unity gain buffers when
buffering high bandwidth input signals, as shown in
Figure 8a. The LT6203 combines fast settling and good DC
linearity with 1.9nV/RT(Hz) input-referred noise density,
enabling it to achieve the full ADC data sheet SNR and
THD specifications as shown in the FFT plot in Figure 8b.
Maximizing the SNR Using Fully Differential Input
Drive
In order to maximize the SNR, the input signal swing must
be maximized. A fully differential signal with a commonmode of VREF/2 maximizes the input signal swing. The
circuit in Figure 8a is capable of buffering such a signal.
1.8V TO 5.1V
2.5V
VIN+
+
10µF
10Ω
1/2 LT6203
–
0.1µF
VDD
1.2nF
OVDD
IN+
LTC2500-32
IN –
1.2nF
–
REF
10Ω
GND
1/2 LT6203
VIN–
2.5V
TO 5.1V
+
47µF
(X7R, 1210 SIZE)
250032 F08a
Figure 8a. Buffering Two Single-Ended Analog Input Signals
0
SNR = 103dB
THD = –126dB
SINAD = 103dB
SFDR = 128dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
125
250
375
FREQUENCY (kHz)
500
250032 F08b
Figure 8b. 128k Point FFT Plot with FIN = 2kHz for Circuit Shown in Figure 8a
16
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
If the input signal does not have a common-mode of
VREF/2 or is single-ended, the LTC6363 differential amplifier may be used in conjunction with the LT5400-4 precision resistors to produce a fully differential signal with a
common-mode of VREF/2. Figure 9a shows the LTC6363
buffering, level-shifting and performing a single-ended to
differential conversion on a ±5V single-ended true bipolar
input signal. The FFT in Figure 9b shows that near data sheet
performance is obtained with this driver solution. Though
not shown here, the LTC6363 may also be configured to
amplify or attenuate a signal to match the full scale input
range of the LTC2500-32.
Buffering DC Input Signals
The LTC2500-32 has excellent INL specifications. This
makes the LTC2500-32 ideal for applications which require high DC accuracy, including parameters such as
offset and offset drift. To maintain high accuracy over the
8V
LT5400-4
1k
0V
VCM
LTC6363
30.1Ω
–
1k
VIN+
30.1Ω
+
1k
0.1µF
–5V
6800pF
0.1µF
1k
5V
entire DC signal chain, amplifiers have to be selected very
carefully. A large-signal open-loop gain of at least 126dB
may be required to ensure 1ppm linearity for amplifiers
configured for a gain of negative 1. However, less gain is
sufficient if the amplifier’s gain characteristic is known to
be (mostly) linear. An amplifier’s offset versus signal level
must be considered for amplifiers configured as unity
gain buffers. For example, 1ppm linearity may require that
the offset is known to vary less than 5μV for a 5V swing.
However, greater offset variations may be acceptable if the
relationship is known to be (mostly) linear. Unity-gain buffer
amplifiers typically require substantial headroom to the
power supply rails for best performance. Inverting amplifier circuits configured to minimize swing at the amplifier
input terminals may perform better with less headroom
than unity-gain buffer amplifiers. The linearity and thermal
properties of an inverting amplifier’s feedback network
should be considered carefully to ensure DC accuracy.
IN+
6800pF
IN–
6800pF
0.1µF
–3V
250032 F09a
Figure 9a. Buffering and Converting a ±5V True Bipolar Input Signal to a Fully Differential Input
0
SNR = 103.3dB
THD = –122dB
SINAD = 103.2dB
SFDR = 124dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
250032 F09b
Figure 9b. 128k Point FFT Plot with FIN = 2kHz fSMPL = 800ksps for Circuit Shown in Figure 9a
250032fb
For more information www.linear.com/LTC2500-32
17
LTC2500-32
APPLICATIONS INFORMATION
Figure 10 shows a typical application where two single
ended analog input voltages are buffered using the
LTC2057. The LTC2057 is a high precision zero drift
amplifier which complements the low offset and offset
drift of the LTC2500-32. The LTC2057 is shown in a noninverting amplifier configuration. The LTC2500-32 has a
guaranteed maximum offset error of 130µV (typical drift
±0.007ppm/°C), and a guaranteed maximum full-scale
error of 150ppm (typical drift ±0.05ppm/°C). Low drift is
important to maintain accuracy over a wide temperature
range in a calibrated system.
VIN+
+
Buffering Single-Ended Analog Input Signals
While the circuits shown in Figures 8a and 10 are capable
of buffering single-ended input signals, the circuit shown
in Figure 11 is preferable when the single-ended signal
reference level is inherently low impedance and doesn’t
require buffering. This circuit eliminates one driver and
lowpass filter, reducing part count, power dissipation, and
SNR degradation due to driver noise.
–
1.8V TO 5.1V
2.5V
10Ω
LTC2057
10µF
4.7µF
0.1µF
VDD
0.047µF
OVDD
IN+
4.99k
LTC2500-32
4.99k
IN –
0.047µF
REF
2.5V TO 5.1V
–
47µF
(X7R, 1210 SIZE)
10Ω
LTC2057
VIN–
+
GND
4.7µF
250032 F10a
Figure 10. Buffering Two Single-Ended DC Analog Input Signals
2.5V 1.8V TO 5.1V
10µF
VIN+
0.1µF
VDD
+
LTC2057
–
10Ω
OVDD
IN+
LTC2500-32
4.7µF
IN –
0.047µF
GND
REF
2.5V TO 5.1V
4.99kΩ
47µF
(X7R, 1210 SIZE)
250032 F11
Figure 11. Buffering Single-Ended Signals
18
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
Using Digital Gain Compression for Single Supply
Operation
The LTC2500-32 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be between 10% and 90% of the ±VREF analog input range. This
feature allows the SAR ADC driver to be powered off of a
single positive supply since each input swings between
0.5V and 4.5V as shown in Figure 12, while maintaining
full-scale output codes. Needing only one positive supply
to power the SAR ADC driver results in additional power
savings for the entire system versus conventional systems
that have a negative supply for the ADC driver.
5V
4.5V
range of the LTC2500-32 when digital gain compression
is enabled. When paired with the LTC6655- 4.096 for the
reference, the entire signal chain solution can be powered
from a single 5V supply, minimizing power consumption
and reducing complexity. As shown in the FFT of Figure
13b, the single 5V supply solution can achieve up to 100dB
of SNR. To enable DGC, set DGC(C[9]) = 1 in the configuration word. The common-mode output is also subjected
to DGC, thereby limiting the input common mode of the
input to between 0.5V to 4.5V.
Using Digital Gain Expansion for System Calibration
The LTC2500-32 offers a digital gain expansion (DGE)
feature, allowing the differential full-scale input swing to
exceed the ±VREF analog input range by 0.78% before the
digital output code saturates. This is useful for system
0
SNR = 101dB
THD = –125dB
SINAD = 101dB
SFDR = 126dB
–20
AMPLITUDE (dBFS)
–40
0.5V
0V
250032 F12
Figure 12. Input Swing of the LTC2500-32 with Gain
Compression Enabled
–60
–80
–100
–120
–140
–160
With DGC enabled, the LTC2500-32 can be driven by the
low power LTC6362 differential driver which is powered
from a single 5V supply. Figure 13a shows how to configure
the LTC6362 to accept a ±3.28V true bipolar single-ended
input signal and level shift the signal to the reduced input
–180
0
125
250
375
FREQUENCY (kHz)
250032 F13b
Figure 13b. 128k Point FFT Plot with fIN = 2kHz for
Circuit Shown in Figure 13a
VIN
5V
1k
VCM
10µF
1k
3.28V
–3.28V
VCM
+
1
–
4
47µF
0.41V 35.7Ω
2
3300pF
1k
3.69V
6
6800pF
REF
VDD
LTC2500-32
IN–
35.7Ω
5
V–
2.5V
6800pF
IN+
LTC6362
1k
0V
8
VOUT_S
3.69V
3
V+
1k
LTC6655-4.096
VOUT_F
4.096V
1k
500
GND
250032 F13a
0.41V
Figure 13a. LTC6362 Configured to Accept a ±3.28V Input Signal While Running from a Single
5V Supply When Digital Gain Compression Is Enabled in the LTC2500-32
250032fb
For more information www.linear.com/LTC2500-32
19
LTC2500-32
APPLICATIONS INFORMATION
Table 1. Ideal Output Code vs Input Signal for Different DGC and DGE Conditions
DGC
DGE
OFF
OFF
ON
OFF
ON
ON
ANALOG INPUT VOLTAGE (VIN+ – VIN–)
≥ VREF
≤ –VREF
≥ 1.0078xVREF
VREF
–VREF
≤ 1.0078xVREF
≥ 0.8VREF
≤ –0.8VREF
≥ 0.80624VREF
0.8VREF
–0.8VREF
≤ 0.80624VREF
DOUTA (32-BIT)
7FFFFFFFh
80000000h
407FFFFFh
3FFFFFFFh
C0000000h
BF800000h
7FFFFFFFh
80000000h
407FFFFFh
3FFFFFFFh
C0000000h
BF800000h
calibration where a full-scale input voltage may need to be
measured, causing the digital output code to saturate. To
enable DGE, set DGE(C[8]) = 1 in the configuration word.
Figure 14 shows the ADC transfer function with DGE=0
and DGE=1. The DGE=0 is the nominal transfer function
OUTPUT
CODE(LSB)
DFS
2
–1.0078 × VREF
1.0078 ×
DGE = 0
–1
( )
DFS
4
–1
DGE = 1
–VREF
INPUT
VOLTAGE (V)
VREF
–1.0078 ×
–DFS
DFS
of the ADC, with a ±VREF full-scale analog input range.
A ±VREF full-scale analog input corresponds to digital
output codes ±DFS/2 respectively, with DFS being equal
to 232 or 224 depending on whether the output code is
read from the filtered output or the no latency output.
When DGE=1, the full-scale analog input range increases
to ±1.0078xVREF. To accommodate the increased analog
input range, the digital output is divided by a factor of 2.
Therefore, a ±1.0078xVREF analog input corresponds to
digital output codes of ±1.0078xDFS/4. Table 1 summarizes
the input voltages and their corresponding ideal digital
output codes for different DGE conditions with DGC turned
OFF. Note that the common-mode output does remains
unaffected by DGE.
Figure 15 shows a use case of the DGE feature, where an
ideal differential amplifier is driving the LTC2500-32. The
feedback resistors have a ±0.1% tolerance and the reference driving the REF is a 5V reference with a ±0.025%
1.0078 × VREF
4
FILTERED OUTPUT:
DFS = 232
NO LATENCY OUTPUT: DFS = 224
2
DOUTB (24-BIT)
7FFFFFh
800000h
407FFFh
3FFFFFh
C00000h
BF8000h
7FFFFFh
800000h
407FFFh
3FFFFFh
C00000h
BF8000h
250032 F14
Figure 14. ADC Transfer Functions with DGE = 0 and DGE = 1
5V SYSTEM
CALIBRATION
VOLTAGE
VIN–
VIN+
1.001 × RΩ
0.999 × RΩ
0.999 × RΩ
4.99875V
(5V REFERENCE – 0.025%)
+
IN+
–
IN–
REF
LTC2500-32
GND
250032 F15
1.001 × RΩ
DIFFERENTIAL AMPLIFIER
DESIGNED FOR NORMAL GAIN = 1
VIN = 1.002 × (VIN+ – VIN–)
ACTUAL GAIN = 1.002
Figure 15. LTC2500-32 Driven By an Ideal Differential Amplifier with 0.1% Resistors
20
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
tolerance. In a practical case where the resistors mismatch
and the reference is at the low end of its specified range
as shown, applying a 5V system calibration voltage results
in an analog input voltage to the ADC is 0.225% greater
than 5V, i.e. 5.01125V. With DGE=0, this input voltage
would saturate the digital output code of the LTC2500-32.
With DGE=1, however, the output code does not saturate
and the gain error due to non-idealities can be measured
and calibrated.
Using DGC and DGE Simultaneously
The LTC2500-32 allows for simultaneous operation of
the DGC and DGE features. With DGC feature turned ON
and DGE turned OFF, the input voltage range is limited to
±0.8VREF. Turning DGE ON, along with DGC, increases
this input voltage range by 0.78%, thereby resulting in
an input voltage range equal to ±0.8VREFx1.0078 (i.e.
±0.80624VREF). Table 1 also summarizes the input voltages and their corresponding ideal digital output codes
for this mode of operation.
ADC REFERENCE
An external reference defines the input range of the
LTC2500-32. A low noise, low temperature drift reference
is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2500-32. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
When choosing a bypass capacitor for the LTC6655-5, the
capacitor’s voltage rating, temperature rating, and package size should be carefully considered. Physically larger
capacitors with higher voltage and temperature ratings tend
to provide a larger effective capacitance, better filtering
the noise of the LTC6655-5, and consequently facilitating
a higher SNR. Therefore, we recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
The REF pin of the LTC2500-32 draws charge (QCONV) from
the 47μF bypass capacitor during each conversion cycle.
The reference replenishes this charge with an average
current, IREF = QCONV/tCYC. The current drawn from the
REF pin, IREF, depends on the sampling rate and output
code. If the LTC2500-32 continuously samples a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5ppm.
When idling, the REF pin on the LTC2500-32 draws only
a small leakage current (< 1μA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 16, IREF quickly goes from approximately
0μA to a maximum of 1mA at 1Msps. This step in average
current drawn causes a transient response in the reference that must be considered, since any deviation in the
reference output voltage will affect the accuracy of the
output code. In applications where the transient response
of the reference is important, the fast settling LTC6655-5
reference is also recommended.
Reference Noise
The dynamic range of the ADC will increase approximately
6dB for every 4× increase in the down-sampling factor
(DF). The SNR should also improve as a function of DF in
the same manner. For large input signals near full-scale,
however, any reference noise will limit the improvement
of the SNR as DF increases, because any noise on the
REF pin will modulate around the fundamental frequency
of the input signal. Therefore, it is critical to use a low
noise reference, especially if the input signal amplitude
MCLK
IDLE
PERIOD
IDLE
PERIOD
250032 F16
Figure 16. MCLK Waveform Showing Burst Sampling
250032fb
For more information www.linear.com/LTC2500-32
21
LTC2500-32
APPLICATIONS INFORMATION
approaches full-scale. For small input signals, the dynamic
range will improve as described earlier in this section.
DYNAMIC PERFORMANCE
Fast fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2500-32 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Dynamic Range
The dynamic range is the ratio of the RMS value of a full
scale input to the total RMS noise measured with the inputs
shorted to VREF/2. The dynamic range of the LTC250032’s 32-bit ADC core is 104dB. The dynamic range of the
filtered output improves by 6dB for every 4× increase in
the down-sampling factor.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 17 shows that the 32-bit ADC core of
the LTC2500-32 achieves a typical SINAD of 104dB at a
1MHz sampling rate with a 2kHz input.
0
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
125
250
375
FREQUENCY (kHz)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 17 shows
that the 32-bit ADC core of the LTC2500-32 achieves an
SNR of 104dB when sampling a 2kHz input at a 1MHz
sampling rate.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD = 20log
V2 2 + V3 2 + V4 2 +...+ VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2500-32 has two power supply pins: the 2.5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows
the LTC2500-32 to communicate with any digital logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems.
Power Supply Sequencing
SNR = 104dB
THD = –120dB
SINAD = 104dB
SFDR = 121dB
–20
Signal-to-Noise Ratio (SNR)
500
The LTC2500-32 does not have any specific power supply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described
in the Absolute Maximum Ratings section. The LTC250032 has a power-on-reset (POR) circuit that will reset the
LTC2500-32 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
250032 F17
Figure 17. 128k Point FFT Plot of the LTC2500-32 with,
fIN = 2kHz and fSMPL = 1MHz
22
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
12
until 200μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
SUPPLY CURRENT (mA)
10
TIMING AND CONTROL
MCLK Timing
A rising edge on MCLK will power up the LTC2500-32 and
start a conversion. Once a conversion has been started,
further transitions on MCLK are ignored until the conversion is complete. For best results, the falling edge of MCLK
should occur within 40ns from the start of the conversion,
or after the conversion has been completed. For optimum
performance, MCLK should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
Once the conversion has completed, the LTC2500-32
powers down and begins acquiring the input signal.
Internal Conversion Clock
The LTC2500-32 has internal timing circuity that is trimmed
to achieve a maximum conversion time of 660ns. With a
maximum sample rate of 1Msps, a minimum acquisition
time of 327ns is guaranteed without any external adjustments.
8
6
4
2
0
0
0.2
0.4
0.6
0.8
SAMPLING RATE (Msps)
1
250032 F18
Figure 18. Power Supply Current of the LTC2500-32
vs Sampling Rate
DECIMATION FILTERS
Many ADC applications use digital filtering techniques
to reduce noise. An FPGA or DSP is typically needed to
implement a digital filter. The LTC2500-32 features a highly
configurable integrated decimation filter that provides a
variety of filtering functions without any external hardware,
thus simplifying the application solution. Figure 19 shows
the LTC2500-32 digitally filtered output signal path, wherein
the output DADC(n) of the 32-bit SAR ADC core is passed
on to the integrated decimation filter.
INTEGRATED DECIMATION FILTER
VIN
Auto Power Down
The LTC2500-32 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of MCLK.
During power-down, data from the last conversion can be
clocked out. To minimize power dissipation during powerdown, disable SDOA, SDOB and turn off SCKA, SCKB. The
auto power-down feature will reduce the power dissipation of the LTC2500-32 as the sampling rate is reduced.
Since power is consumed only during a conversion, the
LTC2500-32 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown Figure 18.
IVDD
IOVDD
IREF
32-BIT DADC(n)
SAR ADC
CORE
DIGITAL
FILTER
D1(n)
DOWN
SAMPLER
DOUT(k)
250032 F19
Figure 19. LTC2500-32 Digitally Filtered Output Signal Path
Digital Filtering
The input to the LTC2500-32 is sampled at a rate fSMPL,
and digital words DADC(n) are transmitted to the digital
filter at that rate. Noise from the 32-bit SAR ADC core is
distributed uniformly in frequency from DC to fSMPL/2
Figure 20 shows the frequency spectrum of DADC(n) at the
DADC
fB
fSMPL/2
250032 F20
Figure 20. Frequency Spectrum of SAR ADC Core Output
250032fb
For more information www.linear.com/LTC2500-32
23
LTC2500-32
APPLICATIONS INFORMATION
output of the SAR ADC core. In this example, the bandwidth
of interest fB is a small fraction of fSMPL/2.
The digital filter integrated in the LTC2500-32 suppresses
out-of-band noise power, thereby lowering overall noise
and increasing the dynamic range (DR). The lower the filter
bandwidth, the lower the noise, and the higher the DR.
Figure 21 shows the corresponding frequency spectrum of
D1(n) at the output of the digital filter, where noise beyond
the cutoff frequency is suppressed by the digital filter.
(fO/2). The circles show the signal sampled at fO. Note that
the sampled signal is identical to that of sampling another
sinusoidal input signal of a lower frequency shown with the
dashed line. To avoid aliasing, it is necessary to band limit
an input signal to the Nyquist bandwidth before sampling.
A filter that suppresses spectral components outside the
Nyquist bandwidth is called an anti-aliasing filter (AAF).
INPUT SIGNAL
SAMPLED SIGNAL
(ALIASED)
D1
DIGITAL FILTER CUTOFF FREQUENCY
250032 F22
fB
fSMPL/2
250032 F21
Figure 21. Frequency Spectrum of Digital Filter Core Output
Down-Sampling
The output data rate of the digital filter is reduced by a
down-sampler without causing spectral interference in
the bandwidth of interest.
The down-sampler reduces the data rate by passing every DFth sample to the output, while discarding all other
samples. The sampling frequency fO at the output of the
down sampler is the ratio of fSMPL and DF, i.e., fO = fSMPL/
DF. DF is adjustable through the digital interface, allowing
the filter bandwidth to be tailored to the application.
Figure 22. Time Domain View of Aliasing
Anti-Aliasing Filters
Figure 23 shows a typical signal chain including a lowpass
AAF and an ADC sampling at a rate of fO. The AAF rejects
input signal components exceeding fO/2, thus avoiding
aliasing. If the bandwidth of interest is close to fO/2, then
the AAF must have a very steep roll-off. The complexity of
the analog AAF increases with the steepness of the roll-off,
and it may be prohibitive if a very steep filter is required.
The maximum bandwidth that a signal being sampled can
have and be accurately represented by its samples is the
Nyquist bandwidth. The Nyquist bandwidth ranges from
DC to half the sampling frequency (a.k.a. the Nyquist
frequency). An input signal whose bandwidth exceeds
the Nyquist frequency, when sampled, will experience
distortion due to an effect called aliasing.
Alternatively, a simple low order analog filter in combination
with a digital filter can be used to create a mixed-mode
equivalent AAF with a very steep roll-off. A mixed-mode
filter implementation is shown in Figure 24 where an
analog filter with a gradual roll-off is followed by the
LTC2500-32 sampling at a rate of fSMPL = DF • fO. The
LTC2500-32 has an integrated digital filter at the output
of the ADC core. The equivalent AAF, HEQ(f), is the product
of the frequency responses of the analog filter H1(f) and
digital filter H2(f), as shown in Figure 25. The digital filter
provides a steep roll-off, allowing the analog filter to have
a relatively gradual roll-off.
When aliasing, frequency components greater than the
Nyquist frequency undergo a frequency shift and appear
within the Nyquist bandwidth. Figure 22 illustrates aliasing
in the time domain. The solid line shows a sinusoidal input
signal of a frequency greater than the Nyquist frequency
The digital filter in the LTC2500-32 operates at the ADC
sampling rate fSMPL and suppresses signals at frequencies
exceeding fO/2. The frequency response of the digital filter
H2(f) repeats at multiples of fSMPL, resulting in unwanted
passbands at each multiple of fSMPL. The analog filter
Aliasing
24
For more information www.linear.com/LTC2500-32
250032fb
LTC2500-32
APPLICATIONS INFORMATION
f0
ANTI-ALIASING FILTER
VIN
DOUT (k)
ADC
f0/2
f0
250032 F23
Figure 23. ADC Signal Chain with AAF
fSMPL
LTC2500-32
ANALOG FILTER
DIGITAL FILTER
H1
H2
fSMPL – f0/2
VIN
f0/2
ADC
CORE
IMAGE
D1 (n)
fSMPL – f0/2
f0/2
fSMPL
DOWN-SAMPLER
DF
DOUT (k)
AT f0 (sps)
fSMPL
250032 F24
Figure 24. Mixed Mode Filter Signal Chain
H1
H2
ANALOG FILTER
DIGITAL FILTER
fSMPL – f0/2
f0/2
fSMPL
HEQ
fSMPL – f0/2
f0/2
fSMPL
EQUIVALENT AAF
VIN
TO ADC
f0/2
fSMPL
250032 F25
Figure 25. Mixed-Mode Anti-Aliasing Filter (AAF)
250032fb
For more information www.linear.com/LTC2500-32
25
LTC2500-32
APPLICATIONS INFORMATION
(C[3:0])
DADC(n)
FROM 32-BIT
SAR ADC CORE
SINC1
SINC2
SINC3
SINC4
(C[7:4])
DF
32-BIT
FILTERED
OUTPUT
SSINC
FLAT
PASSBAND
AVERAGING
FILTER TYPE
SERIAL
INTERFACE
TIMING
DF
250032 F26
DOWN-SAMPLING
FACTOR
Figure 26. Digital Filter Block Diagram
should be designed to provide adequate suppression of
the unwanted passbands, such that HEQ(f) has only one
passband corresponding to the frequency range of interest.
Larger DF settings correspond to less bandwidth of the
digital filter, allowing for the analog filter to have a more
gradual roll-off. A simple first- or second-order analog
filter will provide adequate suppression for most systems.
DIGITAL FILTER TYPES
The LTC2500-32 offers seven digital filter types that are
selected and configured through the digital interface with
the C[3:0] bits in the configuration word. The filter types
are: sinc1, sinc2, sinc3, sinc4, spread-sinc (ssinc), flat
passband and averaging as shown in Figure 26. The output
of the selected digital filter type is multiplexed into a downsampler with a programmable down-sampling factor (DF).
26
DF is set through the digital interface with the C[7:4] bits
in the configuration word for all of the filter types except
the averaging filter. The averaging filter determines DF
by how data is read from the device through the serial
interface. The configurability of the digital filter type and
down-sampling rates offered in the LTC2500-32 allows
the frequency response, filter settling time and output
data rate to be tailored to the application.
Frequency Response of the Digital Filters
All of the filter types available on the LTC2500-32 are
finite impulse response (FIR) filters with lowpass amplitude response and linear phase responses. The FIR filter
coefficients for each filter are available at www.linear.com/
docs/55712. The sections below describe the amplitude
response of each filter in more detail.
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
30
20
fO =
10
SINC1
SINC2
SINC3
SINC4
SSINC
fSMPL
DF
0
–10
MAGNITUDE (dB)
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
fO
2 • fO
3 • fO
4 • fO = fSMPL
FREQUENCY (Hz)
5 • fO
6 • fO
250032 F27
Figure 27. Magnitude of Frequency Response Overlay of Sinc Type Digital Filters with DF = 4
Sinc Filters
There are five types of sinc filters available on the
LTC2500-32: sinc1, sinc2, sinc3, sinc4 and spread-sinc
(ssinc). Figure 27 shows an overlay of the five sinc filter
amplitude responses with DF = 4 at a sampling rate of
fSMPL. In this case, fO is fSMPL/4. Note that nulls occur
in the amplitude responses of the sinc1, sinc2, sinc3 and
sinc4 filters at multiples of fO, except at multiples of fSAMP
where replicas of the passband reside. There is a large
suppression of frequencies at the nulls, making it possible
to reject specific frequencies by properly choosing fO. The
peaks in the amplitude response between nulls are often
referred to as side-lobes. The magnitude of the side-lobes
decreases with increasing filter order and provides at
most 45dB of attenuation with the sinc4 filter. This may
be an unacceptable level of attenuation if the analog input
contains unwanted signals in the side-lobe regions.
The spread-sinc (ssinc) filter is a composite sinc filter
with the nulls distributed or spread in such a way as to
minimize the magnitude of the side-lobes to at most 80dB,
providing substantially more attenuation of unwanted
signals outside of the passband.
Sinc filters are often used in data acquisition applications
where DC or low frequency signals are being digitized.
Sinc filters are also very often the first stage in multistage
digital decimation filters.
Averaging Filter
The frequency response of the averaging filter on the
LTC2500-32 is the same as that of a sinc1 filter. The DF of
the averaging filter ranges from 1 to 16384 and is adjustable
on the fly, providing more flexibility than the sinc1 filter.
250032fb
For more information www.linear.com/LTC2500-32
27
LTC2500-32
APPLICATIONS INFORMATION
Flat Passband Filter
Settling Time and Group Delay
Figure 28a shows the amplitude response of the flat passband filter with DF = 4 at a sampling rate of fSMPL. As in
the previous section, fO = fSAMPL/4. Note that a replica of
the passband occurs at fSMPL and multiples thereof.
The length of each digital filter’s impulse response determines it’s settling time. Linear phase filters exhibit constant
delay time versus input frequency (that is, constant group
delay). Group delay of the digital filter is defined to be the
delay to the center of the impulse response.
Figure 28b shows the amplitude response in the frequency
range from DC to fO. Labels are shown for four distinct
regions: a low ripple passband, a 3dB passband, a transition
band and a stopband. The low ripple passband ranges from
DC to fO/4 and provides a constant amplitude (±0.001dB)
as shown in Figure 28c. The 3dB passband ranges from
DC to fO/3 where the amplitude response has dropped by
3dB. The transition band is defined from fO/3 to fO/2 and is
where the magnitude of the amplitude response undergoes
a sharp decrease. At fO/2, the stopband begins. There is
a minimum of 65dB attenuation over the entire stopband
region for frequencies in the range of fO/2 to fSMPL - fO/2.
The minimum attenuation in the stopband improves to
80dB over the frequency range of 2fO/3 to fSMPL - 2fO/3.
The flatness of the flat passband filter lends itself to signal
processing applications where large bandwidth signals
are digitized.
The ssinc and flat passband filters unique to the LTC250032 are optimized for low latency and provide fast settling.
Figure 29 shows the output settling behavior of the sinc
type filters after a step change on the analog inputs of the
LTC2500-32. Figure 30 shows the output settling behavior
of the flat passband filter after a step change on the analog
inputs of the LTC2500-32. The X axis in both figures is
given in units of output sample number.
Digital Filter Summary
Table 2 summarizes various parameters of each digital
filter type across all down-sampling factors. When operating at 1.024Msps, the acquisition time (tACQ) of the
LTC2500-32 is reduced to 303.6ns and the output data
rate correspondingly increases. Note that the dynamic
range and noise values are not affected by sampling rate.
20
10
0
–10
MAGNITUDE (dB)
–20
HIGHLIGHTED AREA
SHOWN IN FIGURE 28b
–30
–40
–50
–60
–70
–80
–90
–100
0
fO
fSMPL/2
fSMPL
250032 F28a
FREQUENCY (Hz)
Figure 28a. Magnitude of Frequency Response of Flat Passband Filter with DF = 4
28
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
20
3dB PASSBAND
LOW RIPPLE
PASSBAND
10
STOPBAND
TRANSITION
BAND
0
–10
HIGHLIGHTED AREA
SHOWN IN FIGURE 28c
MAGNITUDE (dB)
–20
–30
65dB
80dB
–40
–50
–60
–70
–80
–90
–100
0
fO/4
fO/3
fO/2
2fO/3
fO
FREQUENCY (Hz)
250032 F28b
Figure 28b. Highlighted Portion of Frequency Response from Figure 28a
2
MAGNITUDE (mdB)
1
0
–1
–2
0
FREQUENCY (Hz)
fO/4
250032 F28c
Figure 28c. Low Ripple Passband Portion of Frequency Response from Figure 28b
250032fb
For more information www.linear.com/LTC2500-32
29
LTC2500-32
APPLICATIONS INFORMATION
1
ANALOG STEP INPUT SIGNAL
LTC2500-32 OUTPUT SAMPLES DOUT(k)
SINC1 FILTER OUTPUT D1(n)
SINC2 FILTER OUTPUT D1(n)
SINC3 FILTER OUTPUT D1(n)
SINC4 FILTER OUTPUT D1(n)
SSINC FILTER OUTPUT D1(n)
GROUP DELAY
GROUP DELAY
0
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
OUTPUT SAMPLE NUMBER
250032 F29
Figure 29. Overlaid Step Responses of Sinc Type Filters
1
ANALOG STEP INPUT SIGNAL
DIGITAL FILTER OUTPUT D1(n)
LTC2500-32 OUTPUT SAMPLES DOUT(k)
0
–2 –1 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
OUTPUT SAMPLE NUMBER
250032 F30
Figure 30. Step Response of Flat Passband Filter
30
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
Table 2. Digital Filter Parameters for Different Filter Types and Down-Sampling Factors
FILTER
TYPE
SINC1
SINC2
SINC3
DOWNSAMPLING
OUTPUT DATA RATE
–3dB BANDWIDTH
FACTOR
(DF)
fSMPL = 1Msps fSMPL = 1.024Msps fSMPL = 1Msps fSMPL = 1.024Msps
GROUP
DYNAMIC
FILTER
DELAY
RANGE NOISE (µV
LENGTH (fSMPL = 1Msps)
(dB)
RMS)
4
250ksps
256ksps
113.85kHz
116.58kHz
6
3µs
109.1
12.87
8
125ksps
128ksps
55.75kHz
57.08kHz
10
5µs
112.2
9.09
16
62.5ksps
64ksps
27.73kHz
28.40kHz
18
9µs
115.5
6.19
32
31.25ksps
32ksps
13.85kHz
14.18kHz
34
17µs
118.4
4.42
64
15.63ksps
16ksps
6.92kHz
7.09kHz
66
33µs
121.2
3.21
128
7.81ksps
8ksps
3.46kHz
3.54kHz
130
65µs
124
2.31
256
3.91ksps
4ksps
1.73kHz
1.77kHz
258
129µs
127.4
1.56
512
1.95ksps
2ksps
865.13Hz
885.89Hz
514
257µs
130.4
1.1
1024
977sps
1ksps
432.57Hz
442.95Hz
1026
513µs
133.1
0.81
2048
488sps
500sps
216.28Hz
221.47Hz
2050
1025µs
136
0.58
4096
244sps
250sps
108.14Hz
110.74Hz
4098
2049µs
138.3
0.44
8192
122sps
125sps
54.07Hz
55.37Hz
8194
4097µs
141.4
0.31
16384
61sps
62.5sps
27.04Hz
27.68Hz
16386
8195µs
143.3
0.25
4
250ksps
256ksps
82.16kHz
84.13kHz
9
4.5µs
111
10.37
8
125ksps
128ksps
40.16kHz
41.12kHz
17
8.5µs
114.3
7.14
16
62.5ksps
64ksps
19.97kHz
20.45kHz
33
16.5µs
117
5.21
32
31.25ksps
32ksps
9.97kHz
10.21kHz
65
32.5µs
120.2
3.59
64
15.6ksps
16ksps
4.98kHz
5.10kHz
129
64.5µs
123.3
2.51
128
7.8ksps
8ksps
2.49kHz
2.55kHz
257
128.5µs
125.9
1.86
256
3.9ksps
4ksps
1.25kHz
1.28kHz
513
256.5µs
128.9
1.31
512
1.95ksps
2ksps
622.89Hz
637.84Hz
1024
512.5µs
131.9
0.94
1024
977sps
1ksps
311.44Hz
318.92Hz
2049
1024.5µs
135
0.65
2048
488sps
500sps
155.72Hz
159.46Hz
4097
2048.5µs
137.6
0.48
4096
244sps
250sps
77.86Hz
79.73Hz
8193
4096.5µs
140.1
0.36
8192
122sps
125sps
38.93Hz
39.86Hz
16385
8192.5µs
142.5
0.27
16384
61sps
62.5sps
19.47Hz
19.93Hz
32769
16384.5µs
144.5
0.21
4
250ksps
256ksps
67.53kHz
69.15kHz
12
6µs
111.6
9.67
8
125ksps
128ksps
32.99kHz
33.78kHz
24
12µs
114.9
6.59
16
62.5ksps
64ksps
16.40kHz
16.80kHz
48
24µs
118.1
4.58
32
31.25ksps
32ksps
8.19kHz
8.39kHz
96
48µs
121.1
3.26
64
15.6ksps
16ksps
4.09kHz
4.19kHz
192
96µs
124.1
2.3
128
7.8ksps
8ksps
2.05kHz
2.10kHz
384
192µs
126.7
1.69
256
3.9ksps
4ksps
1.02kHz
1.05kHz
768
384µs
130.1
1.15
512
1.95ksps
2ksps
511.60Hz
523.88Hz
1536
768µs
132.9
0.82
1024
977sps
1ksps
255.80Hz
261.94Hz
3072
1536µs
135.6
0.61
2048
488sps
500sps
127.90Hz
130.97Hz
6144
3072µs
138.6
0.43
4096
244sps
250sps
63.95Hz
65.48Hz
12288
6144µs
140.9
0.33
8192
122sps
125sps
31.97Hz
32.74Hz
24576
12288µs
143
0.26
16384
61sps
62.5sps
15.99Hz
16.37Hz
49152
24576µs
145.2
0.2
250032fb
For more information www.linear.com/LTC2500-32
31
LTC2500-32
APPLICATIONS INFORMATION
Table 2. Digital Filter Parameters for Different Filter Types and Down-Sampling Factors
FILTER
TYPE
SINC4
SSINC
Flat
Passband
32
DOWNSAMPLING
OUTPUT DATA RATE
–3dB BANDWIDTH
FACTOR
(DF)
fSMPL = 1Msps fSMPL = 1.024Msps fSMPL = 1Msps fSMPL = 1.024Msps
GROUP
DYNAMIC
FILTER
DELAY
RANGE NOISE (µV
LENGTH (fSMPL = 1Msps)
(dB)
RMS)
4
250ksps
256ksps
58.68kHz
60.08kHz
15
7.5µs
112.7
8.56
8
125ksps
128ksps
28.66kHz
29.34kHz
31
15.5µs
115.8
5.97
16
62.5ksps
64ksps
14.25kHz
14.59kHz
63
31.5µs
118.6
4.34
32
31.25ksps
32ksps
7.11kHz
7.28kHz
127
63.5µs
121.8
2.98
64
15.6ksps
16ksps
3.56kHz
3.64kHz
255
127.5µs
124.7
2.15
128
7.8ksps
8ksps
1.78kHz
1.82kHz
511
255.5µs
127.4
1.56
256
3.9ksps
4ksps
888.72Hz
910.05Hz
1023
511.5µs
130.3
1.12
512
1.95ksps
2ksps
444.36Hz
455.02Hz
2047
1023.5µs
133.6
0.76
1024
977sps
1ksps
222.18Hz
227.51Hz
4095
2047.5µs
136
0.58
2048
488sps
500sps
111.09Hz
113.76Hz
8191
4095.5µs
139
0.41
4096
244sps
250sps
55.54Hz
56.88Hz
16383
8191.5µs
141.8
0.3
8192
122sps
125sps
27.77Hz
28.44Hz
32767
16383.5µs
143.3
0.25
16384
61sps
62.5sps
13.89Hz
14.22Hz
65535
32767.5µs
145.6
0.19
4
250ksps
256ksps
30.93kHz
31.67kHz
36
18µs
114.5
6.97
8
125ksps
128ksps
15.44kHz
15.81kHz
72
36µs
117.7
4.8
16
62.5ksps
64ksps
7.72kHz
7.90kHz
144
72µs
120.8
3.36
32
31.25ksps
32ksps
3.86kHz
3.95kHz
288
144µs
123.7
2.39
64
15.6ksps
16ksps
1.93kHz
1.98kHz
576
288µs
126.8
1.68
128
7.8ksps
8ksps
964.45Hz
987.59Hz
1152
576µs
129.7
1.2
256
3.9ksps
4ksps
482.21Hz
493.78Hz
2304
1152µs
132.9
0.83
512
1.95ksps
2ksps
241.10Hz
246.89Hz
4608
2304µs
135.9
0.59
1024
977sps
1ksps
120.55Hz
123.45Hz
9216
4608µs
138
0.46
2048
488sps
500sps
60.28Hz
61.72Hz
18432
9216µs
141.1
0.32
4096
244sps
250sps
30.14Hz
30.86Hz
36864
18432µs
142.7
0.27
8192
122sps
125sps
15.07Hz
15.43Hz
73728
36864µs
145.3
0.2
16384
61sps
62.5sps
7.53Hz
7.72Hz
147456
73728µs
147.6
0.15
4
250ksps
256ksps
85.74kHz
87.80kHz
140
70µs
110.7
10.69
8
125ksps
128ksps
42.92kHz
43.95kHz
280
140µs
114
7.34
16
62.5ksps
64ksps
21.47kHz
21.98kHz
560
280µs
116.8
5.33
32
31.25ksps
32ksps
10.73kHz
10.99kHz
1120
560µs
120
3.68
64
15.6ksps
16ksps
5.37kHz
5.50kHz
2240
1120µs
122.8
2.66
128
7.8ksps
8ksps
2.68kHz
2.75kHz
4480
2240µs
126.1
1.83
256
3.9ksps
4ksps
1.34kHz
1.37kHz
8960
4480µs
129
1.31
512
1.95ksps
2ksps
670.85Hz
686.95Hz
17920
8960µs
131.4
0.98
1024
977sps
1ksps
335.42Hz
343.47Hz
35840
17920µs
134
0.73
2048
488sps
500sps
167.71Hz
171.74Hz
71680
35840µs
136.8
0.53
4096
244sps
250sps
83.85Hz
85.87Hz
143360
71680µs
138.1
0.45
8192
122sps
125sps
41.93Hz
42.93Hz
286720
143360µs
139.8
0.37
16384
61sps
62.5sps
20.96Hz
21.47Hz
573440
286720µs
140.6
0.34
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
Table 2. Digital Filter Parameters for Different Filter Types and Down-Sampling Factors
FILTER
TYPE
Averaging
DOWNSAMPLING
OUTPUT DATA RATE
–3dB BANDWIDTH
FACTOR
(DF)
fSMPL = 1Msps fSMPL = 1.024Msps fSMPL = 1Msps fSMPL = 1.024Msps
2
500ksps
512ksps
227.34kHz
232.8
GROUP
DYNAMIC
FILTER
DELAY
RANGE NOISE (µV
LENGTH (fSMPL = 1Msps)
(dB)
RMS)
2
1µs
106.4
17.57
4
250ksps
256ksps
113.85kHz
116.58kHz
4
2µs
109.1
12.87
8
125ksps
128ksps
55.75kHz
57.08kHz
8
4µs
112.2
9.09
16
62.5ksps
64ksps
27.73kHz
28.40kHz
16
8µs
115.5
6.19
32
31.25ksps
32ksps
13.85kHz
14.18kHz
32
16µs
118.4
4.42
64
15.6ksps
16ksps
6.92kHz
7.09kHz
64
32µs
121.2
3.21
128
7.8ksps
8ksps
3.46kHz
3.54kHz
128
64µs
124
2.31
256
3.9ksps
4ksps
1.73kHz
1.77kHz
256
128µs
127.4
1.56
512
1.95ksps
2ksps
865.13Hz
885.89Hz
512
256µs
130.4
1.1
1024
977sps
1ksps
432.57Hz
442.95Hz
1024
512µs
133.1
0.81
2048
488sps
500sps
216.28Hz
221.47Hz
2048
1024µs
136
0.58
4096
244sps
250sps
108.14Hz
110.74Hz
4096
2048µs
138.3
0.44
8192
122sps
125sps
54.07Hz
55.37Hz
8192
4096µs
141.4
0.31
16384
61sps
62.5sps
27.04Hz
27.68Hz
16384
8192µs
143.3
0.25
DIGITAL INTERFACE
The LTC2500-32 features two digital serial interfaces.
Serial interface A is used to read the filtered output data.
Serial interface B is used to read the no latency output
data. Both interfaces support a flexible OVDD supply, allowing the LTC2500-32 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Serial interface A is enabled when RDLA is low and serial
interface B is enabled when RDLB is low. Serial data is
clocked out on the SDOA pin and serial configuration data is
clocked in at the SDI pin when an external clock is applied
to the SCKA pin if serial interface A is enabled. Serial data
is clocked out on the SDOB pin when an external clock
is applied to the SCKB pin if serial interface B is enabled.
Output data from serial interface A transitions on rising
C[11]
C[10]
C[9]
C[8]
X
X
DGC
DCE
C[7]
C[6]
edges of SCKA and output data from serial interface B
transitions on rising edges of SCKB. Serial input data at
SDI is latched on rising edges of SCKA.
The configuration of the LTC2500-32 is programmed
through serial interface A with a configuration word that
is input at SDI. The following sections describe the various
ways the LTC2500-32 can be configured and general use
of the LTC2500-32.
LTC2500-32 Control Word
The various modes of operation of the LTC2500-32 are
programmed by 10 bits of a 12-bit control word, C[11:0].
The control word is shifted in at SDI on the rising edges of
SCKA, MSB first. The control word is defined and shown
in Figure 31.
C[5]
C[4]
DOWN-SAMPLING FACTOR(DF)
C[3]
C[2]
C[1]
C[0]
FILTER TYPE
250032 F31
Figure 31. Control Word
250032fb
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33
LTC2500-32
APPLICATIONS INFORMATION
C[11] and C[10] are used during the programming of
the LTC2500-32 and do not control the configuration of
the digital filter or ADC. Bits C[3:0] select the filter type.
Bits C[7:4] select the down-sampling factor (DF). C[8]
enables/disables digital gain expansion (DGE) and C[9]
enables/disables digital gain compression (DGC). Table 3
summarizes the configuration options.
Table 3. Configuration Option Summary
BITS
VALUE
SETTING
C[3:0] = FILTER TYPE
0001
0010
0011
0100
0101
0110
0111
OTHER CODES
SINC1
SINC2
SINC3
SINC4
SSINC
FLAT PASSBAND
AVERAGING
INVALID CODE
C[7:4] = DF
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
OTHER CODES
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
INVALID CODE
C[8] = DGE
0
1
DGE OFF
DGE ON
C[9] = DGC
0
1
DGC OFF
DGC ON
Programming the Configuration
A transaction window opens at power-up, at the falling edge
of DRL, at the falling edge of a RDLA pulse, or when the
filter configuration is reset using a SYNC pulse. A transaction window opening allows the filter configuration of
the LTC2500-32 to be programmed. Once the transaction
window opens, the state machine controlling the programming of the configuration is in a reset state, waiting for a
control word to be shifted in at SDI on the first 12 SCKA
clock pulses. The transaction window closes at the start
of the next conversion when DRL transitions from low
to high as shown in Figure 32, or at the end of the 12th
SCKA pulse since the transition window opened. Serial
input data at SDI should be avoided when BUSY is high.
Input Control Word
The input control word is used to determine whether or
not the configuration is programmed. In many cases, the
user will simply need to configure the converter once for
their specific application after power-up and then drive
the SDI pin to GND. This will force the control word bits
to all zeros and the LTC2500-32 will operate with the
programmed configuration.
The control word is a 12-bit word as described in the
LTC2500-32 control word section. A valid input control
word is one where C[11:10] = 10 and the remaining lower
MCLK
DRL
250032 F32
TRANSACTION WINDOW
Figure 32. Sequencer Programming Transaction Window
34
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
MCLK
MCLK
DRL
DRL
RDLA
RDLA
SCKA
SDI
DOUTA
12
SCKA
C[10] C[9] C[8] C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
SDI
1
DON’T
CARE
Hi-Z
C[11]
2
DA30
3
4
5
DA28
6
7
DA26
8
9
DA24
DA22
10
11
1
DON’T
CARE
DA20
Hi-Z
DOUTA
DA31
DA29
DA25
DA27
START OF NEW
TRANSACTION
WINDOW
DA23
DA21
2
3
5
6
C[11] C[10]
7
8
9
10
11
12
DON’T CARE
DA30
DA28
DA26
DA24
DA22
DA20
DA31
DA29
DA19
DA25
DA27
DA23
DA21
DA19
250032 F33b
TRANSACTION
WINDOW CLOSED
START OF NEW
TRANSACTION
WINDOW
VALID CONTROL WORD ENTERED
FILTER CONFIGURATION UPDATED
NEW CONFIGURATION APPLIED
AT BEGINNING OF NEXT CONVERSION
4
250032 F33a
Figure 33a. Valid Control Word Successfully Programmed,
C[11:10] = 2`b10
Figure 33b. Invalid Control Word Entered, C[11:10] = 2`b11
DRL
RDLA
SCKA
SDI
1
2
3
4
1
5
DON’T
CARE
2
Hi-Z
4
5
6
7
8
9
10
11
12
DON’T CARE
PARTIAL FILTER
CONFIGURATION DISCARDED
DOUTA
3
DA30
DA28
VALID FILTER
CONFIGURATION ACCEPTED
DA26
DA31
DA29
START OF NEW
TRANSACTION
WINDOW
Hi-Z
DA30
DA28
DA29
DA27
TRANSACTION
WINDOW
CLOSED
DA26
DA24
DA22
DA20
DA31
DA27
DA25
START OF NEW
TRANSACTION
WINDOW
DA23
DA21
DA19
250032 F34
VALID FILTER CONFIGURATION ENTERED
FILTER CONFIGURATION UPDATED
AT BEGINNING OF NEXT CONVERSION
PARTIAL FILTER
CONFIGURATION DISCARDED
Figure 34. Truncated Programming Transaction Followed by the Successful Programming of One Configuration
10 bits, C[9:0], have been shifted in before the transaction window closes as shown in Figure 33a. When a valid
control word is successfully entered on the 12th rising
edge of SCKA, the digital filter is reset if the configuration
changes and is configured to operate as programmed
starting with the next conversion. The configuration of the
LTC2500-32 is only programmed by valid input control
words and discards control words that are partially written
or have C[11:10] ≠ 10. If C[11:10] ≠ 10, the LTC2500-32
closes the input transaction window until the next transaction window as shown in Figure 33b. Figure 34 shows a
truncated programming transaction where a partial input
control word is discarded and a second complete valid
input control word is successfully programmed.
250032fb
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35
LTC2500-32
APPLICATIONS INFORMATION
PRESET FILTER MODES
FILTERED OUTPUT DATA
The LTC2500-32 offers a preset mode that allows the user
to select one of two preset digital filter configurations using
the logic level of the SDI pin. The preset mode is entered
by tying the PRE pin to REF, thereby avoiding the need for
SPI programming. Once in preset mode, tying the SDI high
configures the digital filter to be an averaging filter with
DGC and DGE off. Tying SDI low configures the digital
filter to be an ssinc filter with a DF = 64 and both DGC and
DGE off. Table 4 lists the preset configurations and the
function of the SDI pin when PRE pin is tied high or low.
Figure 35 shows a typical operation for reading the filtered
output data for all filter modes with the exception of the
averaging filter. The filtered output register contains filtered
output codes DOUT(k) provided by the decimation filter.
DOUT(k) is updated once in every DF number of conversion cycles. A timing signal DRL indicates when DOUT(k)
is updated. DRL goes high at the beginning of every DFth
conversion, and it goes low when the conversion completes. The 32-bits of DOUT(k) can be read out before the
beginning of the next A/D conversion.
Table 4. Filter Configurations for Different PRE Pin and SDI Pin Configurations
PRE PIN
SDI
DIGITAL FILTER CONFIGURATION
0
Used to Configure the Digital Filter
Based on the SDI Configuration
1
1
Averaging Filter, with DGC and DGE Off
1
0
ssinc with DF = 64, with DGC and DGE Off
CONVERSION
NUMBER
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
(REGISTER UPDATED ONCE
EVERY DF CONVERSIONS)
1 32
DOUT(2)
1 32
DOUT(3)
1 32
SCKA
250032 F35
Figure 35. Typical Filtered Output Data Operation Timing
36
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Distributed Read
Synchronization
LTC2500-32 enables the user to read out the contents
of the filtered output register over multiple conversions.
Figure 36 shows a case where one bit of DOUT(k) is read
for each of 32 consecutive A/D conversions, enabling use
of a much slower serial clock (SCKA). Transitions on the
digital interface should be avoided during A/D conversion
operations (when BUSY is high).
The output of the digital filter D1(n) is updated every
conversion, whereas the down-sampler output DOUT(k)
is updated only once every DF number of conversions.
Synchronization is the process of selecting when the
output DOUT(k) is updated.
This is done by applying a pulse on the SYNC pin of the
LTC2500-32. The filtered output register for DOUT(k) is
updated at each multiple of DF number of conversions
after a SYNC pulse is provided, as shown in Figure 37.
A timing signal DRL indicates when DOUT(k) is updated.
DF NUMBER OF CONVERSIONS
CONVERSION
NUMBER 0
1
2
3
31
32
33
DF
DF+1
MCLK
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
1
2
3
(REGISTER UPDATED ONCE FOR
EVERY DF CONVERSIONS)
DOUT(1)
32
1
SCKA
1 SCKA
1 SCKA
1 SCKA
1 SCKA/CNV
1 SCKA
0 SCKA
32 SCKA
250032 F36
Figure 36. Reading Out Filtered Output Data with Distributed Read
CONVERSION
NUMBER
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DRL
SYNC
FILTERED OUTPUT
REGISTER
DF NUMBER
OF CONVERSIONS
DOUT(0)
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
DOUT(1)
DOUT(2)
DOUT(3)
250032 F37
Figure 37. Synchronization Using a Single SYNC Pulse
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LTC2500-32
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2
1
CONVERSION
NUMBER
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
3DF+1
MCLK
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
DRL
SYNC
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
DOUT(2)
DOUT(3)
250032 F38
Figure 38. Synchronization Using a Periodic SYNC Pulse
USER CONVERSION
NUMBER
1
2
DF–1
DF
DF+1
2DF–2
2DF–1
2DF
2DF+1
USER PROVIDED
MCLK
SYNCHRONIZATION
WINDOW
UNWANTED
GLITCH
CORRUPTED
MCLK
EXPECTED DRL
DRL W/O
PERIODIC SYNC
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
PERIODIC SYNC
EXPECTED DRL
CORRECTED DRL
DRL WITH
PERIODIC SYNC
250032 F39
Figure 39. Receiving Synchronization from Unexpected Glitch
The SYNC function allows multiple LTC2500 devices,
operated from the same master clock using a common
SYNC signal, to be synchronized with each other. This
allows each LTC2500 device to update its output register
at the same time. Note that all devices being synchronized
must operate with the same DF.
Periodic Synchronization
SYNC pulses that reinforce an existing synchronization
do not interfere with normal operation. Figure 38 shows
a case where a SYNC pulse is applied for each DF number
38
of conversions to continually reinforce a synchronization.
Figure 38 indicates synchronization windows when a
SYNC pulse may be applied to reinforce the synchronized
operation.
Self-Correcting Synchronization
Figure 39 shows a case where an unexpected glitch on
MCLK causes an extra A/D conversion to occur. This extra
conversion alters the update instants for DOUT(k). The
applied periodic SYNC pulse reestablishes the desired
synchronization and self corrects within one conversion
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cycle. Note that the digital filter is reset when the synchronization is changed (reestablished).
DIGITAL AVERAGING FILTER
COVERSION
RESULT
REGISTER
32-BIT
SAMPLING ADC
Configuration Word
An 8-bit configuration word, WA[7:0], is appended to the
32-bit output code on SDOA to produce a total output
word of 40 bits as shown in Figure 40. The configuration
word designates the downsampling factor (DF) and filter
type the digital filter is configured to operate with. Clocking out the configuration word is optional. Table 3 lists
the configuration summary for different filter types and
downsampling factors.
DIGITAL
SIGNAL
PROCESSING
FILTERED
OUTPUT
REGISTER
SDOA
250032 F41
MCLK
SCKA
Figure 41. Block Diagram with Digital Averaging Filter
Block Diagram
Figure 41 illustrates a block diagram of the digital averaging filter, including a conversion result register, the digital
signal processing (DSP) block, and a filtered output register.
The conversion result register holds the 32-bit conversion
result from the most recent sample taken at the rising
edge of MCLK. The DSP block provides an averaging
operation, loading average values of conversion results
into the filtered output register for the user to read through
the serial interface.
Averaging Filter (SINC1 Decimation Filter)
The averaging filter in the LTC2500-32 can be used to
average blocks of as few as N = 1 or as many as N = 16384
conversion results. The digital averaging filter described
in this section is also known as a SINC1 digital decimation
filter. A SINC1 digital decimation filter is an FIR filter with
N equal valued taps.
MCLK
CONVERT
DRL
SCKA
DA30
DA28
DA26
DA24
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
DA31
DA29
DA27
DA25
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DATA FROM CONVERSION
DA5
DA3
DA1
WA7
WA5
WA3
DOWNSAMPLING
FACTOR
WA1
250032 F40
FILTER TYPE
Figure 40. Filtered Output Data Formatting
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digital averaging filter will automatically average conversion results until a filtered output result is read out. When
a filtered output result is read out, the digital averaging
filter is reset and a new averaging operation starts with
the next conversion result.
Conventional SAR Operation (N = 1)
The digital filter of the LTC2500-32 may be operated like a
conventional no latency SAR as shown in Figure 42. Each
conversion result is read out via the serial interface before
the next conversion is initiated. Note how the contents of
the filtered output register track the contents of the conversion result register and that both registers contain a result
corresponding to a single conversion. The digital averaging filter is transparent to the user when the LTC2500-32
is operated in this way. No programming is required.
Simply read out each conversion result in each cycle. Ri
represents the 32-bit conversion result corresponding to
conversion number i. As few as 20 SCKs may be given in
each conversion cycle (instead of the 32 shown in Figure
42) to obtain a 20-bit accurate result. When the LTC250032 is configured to operate in the averaging filter mode,
DRL indicates when the conversion result register Ri is
updated, and is identical to BUSY.
In this example, filtered output results are read out after
conversion numbers 0, 4 and 8. The digital averaging
filter is reset after conversion number 0 and starts a new
averaging operation beginning with conversion number
1. The filtered output result (R1 + R2 + R3 + R4)/4 is read
out after conversion number 4, which resets the digital
averaging filter again. Since the digital averaging filter
automatically averages conversion results for each new
conversion performed, an arbitrary number of conversion
results, up to the upper limit of 16384, may be averaged
with no programming required.
Averaging Three Conversion Results
The filtered output result, when averaging N conversion
results for values of N that are not a power of two, will be
scaled by N/M, where M is a weighting factor that is the
next power of two greater than N (described later in the
weighting factor section). Figure 44 shows an example
where only three conversion results are averaged. The
filtered output result read out is scaled by N/M = 3/4.
Averaging Four Conversion Results
Digital averaging techniques are often employed to reduce
the uncertainty of measurements due to noise. Figure
43 shows a case where a filter output result is read out
once for every four conversions initiated. As shown, the
output result read out from the filtered output register is
the average of the four previous conversion results. The
1
CONVERSION 0
NUMBER
2
3
4
5
6
7
8
MCLK
DRL
CONVERSION
RESULT REGISTER
R0
R1
R2
R3
R4
R5
R6
R7
R8
FILTERED OUTPUT
REGISTER
R0
R1
R2
R3
R4
R5
R6
R7
R8
1
32
1
32
1
32
1
32
1
32
1
32
1
32
1
32
1
32
SCKA
250032 F42
Figure 42. Conventional SAR Operation Timing
40
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0
SCKA
1
32
R(–2)+R(–1)+R0
4
1
FILTERED OUTPUT
REGISTER
32
R0
1
CONVERSION
RESULT REGISTER
DRL
MCLK
CONVERSION
NUMBER
SCKA
R(–3)+R(–2)+R(–1)+R0
4
FILTERED OUTPUT
REGISTER
1
R0
0
CONVERSION
RESULT REGISTER
DRL
MCLK
CONVERSION
NUMBER
R1
R1
R1
R1
2
2
R1 + R2 + R3
4
R3
4
1
32
R1 + R2 + R3 + R4
4
R4
5
1
32
R1 + R2 + R3
4
R3
4
R4
R4
5
Figure 44. Averaging Three Conversion Results
R1 + R2
2
R2
3
Figure 43. Averaging Four Conversion Results
R1 + R2
2
R2
3
R4 + R5
2
R5
R5
R5
6
6
1
7
32
R4 + R5 + R6
4
R6
R5 + R6
2
R6
7
R7
R7
R5 + R6 + R7
4
R7
8
8
1
250032 F44
R7 + R8
2
R8
250032 F43
32
R5 + R6 + R7 + R8
4
R8
LTC2500-32
APPLICATIONS INFORMATION
250032fb
41
LTC2500-32
APPLICATIONS INFORMATION
Using the Digital Averaging Filter with Reduced Data Rate
from the filtered output register over multiple conversion
cycles, easing the speed requirements of the serial interface.
The examples given in Figures 42, 43 and 44 illustrate some
of the most common ways to use the digital averaging filter
in LTC2500-32. Simply read each individual conversion
result, or read an average of N conversion results. In each
case, the result is read out between two consecutive A/D
conversion (DRL) periods, thereby requiring a fast SCKA
signal to read out all the 32-bits.
A read is initiated by a rising edge of a first SCKA pulse and
it must be terminated before a next read can be initiated.
The digital averaging filter is reset upon the initiation of a
read wherein a new averaging operation begins. Conversions completed after the digital averaging filter is reset
will automatically be averaged until a new read is initiated.
Thus, the digital averaging filter will calculate averages of
conversion results from conversions completed between
a time when one read is initiated to when a next read is
initiated.
Distributed Read with Averaging Filter
Distributed read allows for the use of a slower SCKA
signal, while reading out all the 32-bits. Distributed reads
require that multiple conversion results be averaged. If at
least 1 but less than 20 SCKA pulses(0 < SCKAs < 20) are
given in a conversion cycle between 2 DRL falling edges
(see Figure 45), the filtered output register is not updated
with the output of the digital averaging filter, preserving
its contents. This allows a filtered output result to be read
CONVERSION
NUMBER
1
0
2
A read is terminated by providing either 0 or greater than 19
SCKA pulses (rising edges) in a conversion cycle between
2 DRL falling edges, allowing the filtered output register
to be updated with new averages from the output of the
digital averaging filter.
3
4
5
6
7
8
CNV
CONVERSIONS COMPLETED BETWEEN
INITIATION OF READS
DRL
CONVERSION
RESULT REGISTER
R0
R1
R2
R3
R4
R5
R6
R7
R8
BLOCK OF CONVERSION RESULTS AVERAGED FOR 1 MEASUREMENT
FILTERED OUTPUT R(–6)+R(–5)+R(–4)+R(–3)
REGISTER
4
R(–2) + R(–1) + R0 + R1
4
1
12
13
24
25
R2 + R3 + R4 + R5
4
32
1
12
13
24
25
32
SCKA
0 SCKAs
0 < SCKAs < 20 0 < SCKAs < 20 0 < SCKAs < 20
0 SCKAs
0 < SCKAs < 20 0 < SCKAs < 20
1ST READ
READ READ
TERMINATED INITIATED
0 < SCKAs < 20
0 SCKAs
2ND READ
READ READ
TERMINATED INITIATED
DIGITAL AVERAGING
FILTER RESETS
DIGITAL AVERAGING
FILTER RESETS
250032 F45
Figure 45. Averaging Four Conversion Results and Reading Out Data with a Distributed Read
42
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Averaging Four Conversions Using a Distributed Read
Averaging 33 Conversions Using a Distributed Read
Figure 45 shows an example where reads are initiated every
four conversion cycles, and the filtered output register is
read over three conversion cycles. This allows the serial
interface to run at 1/3 of the speed that it would otherwise
have to run. The first rising SCKA edge initiates a 1st
read, and three groups of 12, 12, 8-bits are read out over
three conversion cycles. No SCKA pulses are provided
between the DRL falling edges of conversion numbers 4
and 5, whereby the read is terminated at the completion
of conversion number 5. A second read is initiated after
conversion number 5, which results in (R2 + R3 + R4 +
R5)/4 being read out from the filtered output register since
conversion numbers 2, 3, 4 and 5 completed between the
initiation of the two reads shown.
Figure 46 shows an example where a read is initiated
every 33 conversion cycles, using a single SCKA pulse
per conversion cycle to read the output result from the
filtered output register. The first rising SCKA edge initiates a read where a single bit is then read out over the
next 31 conversion cycles. No SCKA pulses are provided
between the DRL falling edges of conversion numbers 33
and 34, whereby the read is terminated at the completion
of conversion number 34. A 2nd read is initiated after
conversion number 34, resulting in (R2 + R3 +…+ R25 +
R34)/64 being read out from the filtered output register.
Since 0 < SCKAs < 20 pulses are given each conversion
period during the read, the contents of the filtered output
register are not updated, allowing the distributed read to
occur without interruption.
CONVERSION
NUMBER 0
1
2
3
4
31
33
32
35
34
MCLK
CONVERSIONS COMPLETED BETWEEN
INITIATION OF READS
DRL
CONVERSION
RESULT REGISTER
R0
R1
FILTERED OUTPUT
REGISTER
R2
R3
R(–31) + R(–30) + ... + R0 + R1
64
1
2
R31
R32
R33
REPEATING READ PATTERN — AVERAGE OF 33 CONVERSION
RESULTS FROM 33 CONVERSIONS PRECEDING INITIATION OF READ
3
4
31
32
1 SCKA/MCLK
0 < SCKAs < 20 0 < SCKAs < 20
R34
R2 + R3 + ... + R33 + R34
64
1
SCKA
0 SCKAs
0 < SCKAs < 20 0 < SCKAs < 20 0 < SCKAs < 20
0 SCKAs
0 < SCKAs < 20
READ
250032 F45
Figure 46. Averaging 33 Conversion Results and Reading Out Data with a Distributed Read
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Minimum Shift Clock Frequency with Averaging Filter
Table 5. Weighing Factors and Throughput Rates for Various
Values of N
Requiring at least 1 SCKA pulse per conversion cycle while
performing a read sets a lower limit on the SCKA frequency
that can be used which is: fSCKA = fSMPL, the maximum
sampling frequency fSMPL(MAX) = 1Msps.
N
D= ∑
Ri
i=1 M
Table 5 illustrates weighting factors for any number of
averages, N, between 1 and 16384 and the resulting
data throughputs. Note that M reaches a maximum value
of 16384 when N = 16384. For N > 16384, the digital
averaging filter will continue to accumulate conversion
results such that N/M > 1. In such a case, if the ADC core
produces conversion results that have a non-zero mean,
the output result will eventually saturate at positive or
negative full-scale.
M
OUTPUT DATA RATE
(fSMPL = 1Msps)
1
1
1Msps
2
2
500ksps
3 to 4
4
333ksps to 250ksps
5 to 8
8
200ksps to 125ksps
9 to 16
16
111ksps to 62.5ksps
17 to 32
32
58.8ksps to 31.25ksps
Weighting Factor
When conversion results are averaged, the resulting
output code represents an equally weighted average of
the previous N samples if N is a power of 2. If N is not a
power of 2, a weighting factor, M, is chosen according to
Table 1. Specifically, if Ri represents the 32-bit conversion
result of the ith analog sample, then the output code, D,
representing N averaged conversion results is defined as:
N
33 to 64
64
30.3ksps to 15.6ksps
65 to 128
128
15.4ksps to 7.8ksps
129 to 256
256
7.8ksps to 3.9ksps
257 to 512
512
3.9ksps to 2ksps
513 to 1024
1024
2ksps to 1ksps
1025 to 2048
2048
976sps to 488sps
2049 to 4096
4096
488sps to 244sps
4097 to 8192
8192
244sps to 122sps
8193 to 16384
16384
122sps to 61sps
Count
As with other filter configurations, an 8-bit configuration
word, WA[7:0], is appended to the 32-bit output code on
SDOA. The digital averaging filter also outputs an additional
14-bit word, CO[13:0], that is appended to the configuration
word to produce a total output word of 54 bits, as shown
in Figure 47. CO[13:0] is the straight binary representation
(MSB first) of the number of samples averaged to produce
MCLK
CONVERT
DRL
1
2
3
4
5
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
SCKA
DA30
DA28
DA2
DA0
W6
W4
W2
W0
CO12
CO10
CO8
CO6
CO4
CO2
CO0
SDOA
DA31
DA29
DA27
DA1
W7
W5
W3
W1
CO13
CO11
CO9
CO7
CO5
CO3
CO1
250032 F47
Figure 47. Serial Output Code Formatting for Digital Averaging Filter
44
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the output result minus one. For instance, if N samples are
averaged to produce the output result, CO[13:0] will equal
N – 1. Thus, if N is 1 which is the case with no averaging,
CO[13:0] will always be 0. If N is 8192, then CO[13:0] will
equal 8191, and so on. If more than 16384 samples are
averaged, then CO[13:0] saturates at 16383.
sion result. The first bit represents the overrange bit. The
overrange bit is equal to 1 if the differential input to the
LTC2500-32 is greater than the digital saturation limit, as
described in Table 1. The following 24 bits of R(n) represent
the input voltage difference (IN+ – IN–), MSB first. The last
7 bits represent the common mode input voltage (IN+ +
IN–)/2, MSB first. Table 6 shows the output bit format for
the 32-bit no latency output data.
NO LATENCY OUTPUT DATA
Figure 48 shows a typical operation for reading the no
latency output data. The no latency I/O register holds a
32-bit composite code R(n) from the most recent converTable 6. Output Bit Format for the 32-Bit No Latency Output Data
DB[31]
Overrange Detection Bit
DB[30:7]
24-Bit Differential Output
1
CONVERSION 0
NUMBER
2
DB[6:0]
7-Bit Common Mode Output
3
4
5
6
MCLK
BUSY
NO LATENCY
OUTPUT REGISTER
R0
1
32
R1
1
32
R2
1
32
R3
1
32
R4
1
32
R5
1
32
R6
1
32
SCKB
250032 F48
Figure 48. Typical Nyquist Output Data Operation Timing
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Filtered Output Data, Single Device
is enabled and the MSB (DA31) of the output result is
available tDSDOBUSYL after the falling edge of DRL.
Figure 49 shows an LTC2500-32 configured to operate to
read out the filtered output. With RDLA grounded, SDOA
MASTER CLK
DIGITAL HOST
MCLK
RDLA
SEL0
SEL1
IRQ
DRL
LTC2500-32
DATA IN
SDOA
SCKA
CLK
RDLA = GND
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tCYC
tMCLKH
tMCLKL
MCLK
BUSY
tCONV
tBUSYLH
DRL
tDRLLH
tSCKA
SCKA
1
2
3
SDOA
30
31
32
tSCKAL
tHSDOA
tDSDOADRLL
tQUIET
tSCKAH
tDSDOA
DA31
DA30
DA29
DA1
DA0
250032 F49
Figure 49. Using a Single LTC2500-32 to Read Filtered Output
46
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Filtered Output Data, Multiple Devices
the RDLA input of each ADC must be used to allow only
one LTC2500-32 to drive SDOA at a time in order to avoid
bus conflicts. As shown in Figure 50, the RDLA inputs idle
high and are individually brought low to read data out of
each device between conversions. When RDLA is brought
low, the MSB of the selected device is output on SDOA.
Figure 50 shows two LTC2500-32 devices configured to
operate read out the filtered output, while sharing MCLK,
SYNC, SCKA and SDOA. By sharing MCLK, SYNC, SCKA
and SDOA, the number of required signals to operate
multiple ADCs in parallel is reduced. Since SDOA is shared,
SYNC
RDLAX
RDLAY
MASTER CLK
RDLA
SYNC
SEL0
SEL1
MCLK
LTC2500-32
X
SCKA
RDLA
SYNC
SEL0
SEL1
SDOA
DIGITAL HOST
MCLK
LTC2500-32
Y
SCKA
IRQ
DRL
DATA IN
SDOA
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
BUSY
tCONV
tBUSYLH
DRL
tDRLLH
RDLAX
RDLAY
SYNC
tSCKA
SCKA
1
tENA
SDOA
tHSDOA
tQUIET
tSCKAH
2
3
tSCKAL
tDSDOA
30
31
32
33
34
35
62
63
64
tDISA
Hi-Z
Hi-Z
Hi-Z
DA31X DA30X DA29X
DA1X DA0X
DA31Y DA30Y DA29Y
DA1Y DA0Y
250032 F50
Figure 50. Reading Filtered Output with Multiple LTC2500-32 Devices Sharing MCLK, SCKA and SDOA
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APPLICATIONS INFORMATION
enabled the overrange bit (OVRNG) of the output result is
available tDSDOBUSYL after the falling edge of BUSY.
No Latency Output Data, Single Device
Figure 51 shows a single LTC2500-32 configured to read
the no latency data out. With RDLB grounded, SDOB is
MASTER CLK
DIGITAL HOST
MCLK
RDLB
LTC2500-32
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tCYC
tMCLKH
tMCLKL
MCLK
tACQ = tCYC – tCONV – tBUSYLH
BUSY
tCONV
tACQ
tBUSYLH
tSCKBH
tSCKB
SCKB
1
2
3
SDOB
31
32
tSCKBL
tHSDOB
tDSDOBBUSYL
30
tQUIET
tDSDOB
OVRNG
DB23
DB22
CB1
CB0
250032 F51
Figure 51. Using a Simple LTC2500-32 to Read No Latency Output
48
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
APPLICATIONS INFORMATION
No Latency Output Data, Multiple Devices
Figure 52 shows multiple LTC2500-32 devices configured
to read no latency data out, while sharing MCLK, SCKB and
SDOB. By sharing MCLK, SCKB and SDOB, the number
of required signals to operate multiple ADCs in parallel is
reduced. Since SDOB is shared, the RDLB input of each
ADC must be used to allow only one LTC2500-32 to drive
SDOB at a time in order to avoid bus conflicts. As shown
in Figure 52, the RDLB inputs idle high and are individually brought low to read data out of each device between
conversions. When RDLB is brought low, the overrange
bit of the selected device is output on SDOB.
RDLBX
RDLBY
MASTER CLK
MCLK
RDLB
LTC2500-32
X
SCKB
DIGITAL HOST
MCLK
RDLB
SDOB
LTC2500-32
Y
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
BUSY
tCONV
tBUSYLH
RDLBX
RDLBY
tSCKB
SCKB
1
tENB
SDOB
tHSDOB
tQUIET
tSCKBH
2
3
tSCKBL
tDSDOB
30
31
32
33
34
35
62
63
64
tDISB
Hi-Z
Hi-Z
Hi-Z
OVRNGX DB23X DB22X
CB1X CB0X
OVRNGY DB23Y DB22Y
CB1Y CB0Y
250032 F52
Figure 52. Reading Filtered Output with Multiple LTC2500-32 Devices Sharing MCLK, SCKB and SDOB
250032fb
For more information www.linear.com/LTC2500-32
49
LTC2500-32
APPLICATIONS INFORMATION
Filtered Output Data, No Latency Data, Single Device
to drive the shared SDO bus at a time in order to avoid
bus conflicts. As shown in Figure 53, the RDLA and RDLB
inputs idle high and are individually brought low to read
data from each serial output when data is available. When
RDLA is brought low, the MSB of the filtered output data
from SDOA is output on the shared SDO bus. When RDLB
is brought low, the overrange (OVRNG) bit of the no latency
data output from SDOB is output on the shared SDO bus.
Figure 53 shows a single LTC2500-32 device configured to
read filtered output data and no latency output data, while
sharing SDOA with SDOB and SCLKA with SCKB. Sharing
signals reduces the total number of required signals to
read both the filtered and no latency data from the ADC.
Since SDOA and SDOB are shared, the RDLA and RDLB
inputs of the ADC must be used to allow only one output
RDLA
RDLB
MASTER CLK
DIGITAL HOST
MCLK
RDLA
RDLB
IRQ
DRL
LTC2500-32
SDOA
SEL0
SDOB
SEL1 SCKA
SCKB
DATA IN
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
DRL
tDRLLH
BUSY
tCONV
tBUSYLH
RDLA
RDLB
tSCKA
SCKA/
SCKB
1
2
3
tHSDOA
tENA
SDOA/
SDOB
Hi-Z
tSCKB
tSCKAH
30
31
tSCKAL
33
tENB
tDISA
tDSDOA
DA31 DA30 DA29
32
DA1
DA0
Hi-Z
tQUIET
tSCKBH
34
35
62
63
64
tSCKBL
tHSDOB
tDSDOB
OVRNG DB23 DB22
CB1
CB0
Hi-Z
250032 F53
Figure 53. Reading Filtered Output and No Latency Output by Sharing SCK and SDO
50
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
BOARD LAYOUT
To obtain the best performance from the LTC2500-32, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2222, the evaluation kit for the LTC2500-32.
250032fb
For more information www.linear.com/LTC2500-32
51
LTC2500-32
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2500-32#packaging for the most recent package drawings.
DKD Package
24-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1864 Rev Ø)
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
2.64 ±0.05
3.10 ±0.05
PACKAGE
OUTLINE
0.50 BSC
0.25 ±0.05
5.50 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
13
R = 0.115
TYP
24
R = 0.05
TYP
0.40 ±0.10
6.43 ±0.10
4.00 ±0.10
2.64 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
12
0.75 ±0.05
0.50 BSC
0.25 ±0.05
5.50 REF
BOTTOM VIEW—EXPOSED PAD
0.200 REF
(DKD24) DFN 0210 REV Ø
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
52
1
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
250032fb
For more information www.linear.com/LTC2500-32
LTC2500-32
REVISION HISTORY
REV
DATE
DESCRIPTION
A
6/17
Updated zero scale error drift
Corrected σ value on DC Histogram
Included filter values of 1.024Msps operation
B
01/18
Corrected preset filter mode SDI logic
PAGE NUMBER
4, 5
8
28, 31-33
36
250032fb
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license
is granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
For more
information
www.linear.com/LTC2500-32
53
LTC2500-32
TYPICAL APPLICATION
Buffering and Converting a ±10V True Bipolar Input Signal to a Fully Differential ADC Input
1k
8V
6800pF
0.1µF
2k
10V
0V
–10V
VREF/2
2k
VOCM
30.1Ω
+
LTC6363
–
VIN+
0.1µF
30.1Ω
IN+
5V
2.5V
REF
VDD
6800pF
LTC2500-32
IN–
GND
0.1µF
6800pF
–3V
1k
250032 TA02
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54
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250032fb
LT 0118 REV B • PRINTED IN USA
For more information www.linear.com/LTC2500-32
www.linear.com/LTC2500-32
ANALOG DEVICES, INC. 2018
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