LTC2508-32
32-Bit Oversampling ADC
with Configurable Digital Filter
FEATURES
DESCRIPTION
±0.5ppm INL (Typ)
nn 145dB Dynamic Range (Typ) at 61sps
nn 131dB Dynamic Range (Typ) at 4ksps
nn Guaranteed 32-Bits No Missing Codes
nn Configurable Digital Filter with Synchronization
nn Relaxed Anti-Aliasing Filter Requirements
nn Dual Output 32-Bit SAR ADC
nn 32-Bit Digitally Filtered Low Noise Output
nn 14-Bit Differential + 8-Bit Common Mode 1Msps
No Latency Output
nn Wide Input Common Mode Range
nn Guaranteed Operation to 85°C
nn 1.8V to 5V SPI-Compatible Serial I/O
nn Low Power: 24mW at 1Msps
nn 24-Lead 7mm × 4mm DFN Package
The LTC®2508-32 is a low noise, low power, high performance 32-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2508-32
features a fully differential input range up to ±VREF, with
VREF ranging from 2.5V to 5.1V. The LTC2508-32 supports
a wide common mode range from 0V to VREF simplifying
analog signal conditioning requirements.
nn
The LTC2508-32 simultaneously provides two output
codes: (1) a 32-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 32-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
APPLICATIONS
Seismology
Energy Exploration
nn Automated Test Equipment (ATE)
nn High Accuracy Instrumentation
nn
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 8576104,
8810443, 9054727, 9231611, 9331709 and patents pending.
TYPICAL APPLICATION
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configurations provide a dynamic range of 131dB at 3.9ksps and
145dB at 61sps. The digital lowpass filter relaxes the requirements for analog anti-aliasing. Multiple LTC2508-32
devices can be easily synchronized using the SYNC pin.
Integral Nonlinearity
vs Input Voltage
1.8V TO 5.1V
2.5V
2.0
0.1µF
IN+, IN–
VREF
ARBITRARY
0V
VREF
DIFFERENTIAL
VREF
VDD
IN+
32-BIT
SAR ADC
CORE
0V
BIPOLAR
VREF
UNIPOLAR
LTC2508-32
PIN SELECTABLE
LOW-PASS
32-BIT
WIDEBAND
DIGITAL FILTER
IN –
0V
0V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
14-BIT
GND
REF
2.5V TO 5.1V
OVDD
MCLK
BUSY
DRL
1.5
SAMPLE
CLOCK
SDOA
SCKA
RDLA
RDLB
SDOB
SCKB
1.0
INL ERROR (ppm)
10µF
0.5
0
–0.5
–1.0
–1.5
250832 TA01
47µF
(X7R, 1210 SIZE)
–2.0
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
5
250832 TA01a
250832fc
For more information www.linear.com/LTC2508-32
1
LTC2508-32
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VDD)................................................2.8V
Supply Voltage (OVDD).................................................6V
Reference Input (REF)..................................................6V
Analog Input Voltage (Note 3)
IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2508C-32............................................ 0°C to 70°C
LTC2508I-32.........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
ORDER INFORMATION
TOP VIEW
RDLA 1
RDLB 2
VDD 3
GND 4
IN+ 5
IN– 6
GND 7
REF 8
REF 9
REF 10
SEL0 11
SEL1 12
24 GND
23 GND
22 OVDD
21 BUSY
20 SDOB
19 SCKB
18 SCKA
17 SDOA
16 GND
15 DRL
14 SYNC
13 MCLK
25
GND
DKD PACKAGE
24-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2508-32#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2508CDKD-32#PBF
LTC2508CDKD-32#TRPBF
250832
24-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC2508IDKD-32#PBF
LTC2508IDKD-32#TRPBF
250832
24-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
(Note 5)
l
–
Absolute Input Range (IN–)
(Note 5)
VIN = VIN+ – VIN–
VIN
VIN+ – VIN– Input Differential Voltage Range
MIN
MAX
UNITS
0
TYP
VREF
V
l
0
VREF
V
l
–VREF
VREF
V
l
0
VREF
V
VCM
Common-Mode Input Range
IIN
Analog Input Leakage Current
10
nA
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
Filtered Output
VIN+ = VIN– = 4.5VP-P, 200Hz Sine
128
dB
2
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
CONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA)
The l denotes
the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
DF
PARAMETER
CONDITIONS
MIN
l
No Missing Codes
l
32
Down-sampling Factor
l
256
DF = 256 (Note 6)
DF = 1024
DF = 4096
DF = 16384
INL
Integral Linearity Error
(Note 7)
l
–3.5
ZSE
Zero-Scale Error
(Note 9)
l
–13
Bits
16384
ppm
ppm
ppm
ppm
0.5
3.5
0
13
±14
(Note 9)
l
–100
Full-Scale Error Drift
UNITS
Bits
0.095
0.055
0.03
0.02
Zero-Scale Error Drift
Full-Scale Error
MAX
32
Resolution
Transition Noise
FSE
TYP
±10
ppm
ppm
ppb/°C
100
±0.05
ppm
ppm/°C
DYNAMIC ACCURACY FOR FILTERED OUTPUT (SDOA)
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –20dBFS. (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
DR
Dynamic Range
VREF = 5V, DF = 256
IN+ = IN– = VCM, VREF = 5V, DF = 1024
IN+ = IN– = VCM, VREF = 5V, DF = 4096
IN+ = IN– = VCM, VREF = 5V, DF = 16384
THD
Total Harmonic Distortion
fIN = 200Hz, VREF = 2.5V, DF = 256
fIN = 200Hz, VREF = 5V, DF = 256
l
fIN = 200Hz, VREF = 2.5V, DF = 256
fIN = 200Hz, VREF = 5V, DF = 256
l
SFDR
l
MIN
TYP
125
131
136
141
145
–118
–118
MAX
UNITS
dB
dB
dB
dB
–108
dB
dB
118
118
dB
dB
–3dB Input Bandwidth
34
MHz
Aperture Delay
500
Aperture Jitter
4
Spurious Free Dynamic Range
Transient Response
Full-Scale Step
108
125
ps
psRMS
ns
250832fc
For more information www.linear.com/LTC2508-32
3
LTC2508-32
CONVERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)
The l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution:
Differential
Common Mode
l
l
14
8
Bits
Bits
No Missing Codes:
Differential
Common Mode
l
l
14
8
Bits
Bits
Transition Noise
Differential
Common Mode
(Note 6)
INL
Integral Linearity Error
Differential
Common Mode
(Note 7)
DNL
Differential Linearity Error
Differential
Common Mode
ZSE
FSE
1
1
LSBRMS
LSBRMS
±0.1
±0.1
LSB
LSB
±0.1
±0.1
LSB
LSB
Zero Scale Error
Differential
Common Mode
±1
±1
LSB
LSB
Zero Scale Error
Differential
Common Mode
±1
±1
LSB
LSB
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Notes 4, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
VREF
Reference Voltage
(Note 5)
l
IREF
Reference Input Current
(Note 11)
l
TYP
2.5
MAX
UNITS
5.1
0.7
1
V
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
MIN
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
l
TYP
l
UNITS
V
l
VIN = 0V to OVDD
MAX
0.8•OVDD
–10
0.2•OVDD
V
10
μA
5
pF
OVDD–0.2
V
–10
0.2
V
10
µA
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
4
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
OVDD
Supply Voltage
IVDD
IOVDD
IPD
Supply Current
Supply Current
Power Down Mode
1Msps Sample Rate
1Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
PD
Power Dissipation
Power Down Mode
1Msps Sample Rate (IVDD)
Conversion Done (IVDD + IOVDD + IREF)
MIN
TYP
MAX
UNITS
l
2.375
2.5
2.625
V
l
1.71
l
l
5.25
V
9.5
1
6
13
350
mA
mA
µA
24
15
32.5
875
mW
µW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
fDRA
fDRB
MAX
UNITS
l
1
Msps
Output Data Rate at SDOA
l
3.9
ksps
Output Data Rate at SDOB
l
1
Msps
tCONV
Conversion Time
tACQ
Acquisition Time
tCYC
Time Between Conversions
CONDITIONS
tACQ = tCYC – tCONV – tBUSYLH (Note 8)
MIN
TYP
l
578
l
335
652
ns
ns
l
1000
ns
tMCLKH
MCLK High Time
l
20
ns
tMCLKL
Minimum Low Time for MCLK
(Note 12)
l
20
ns
tBUSYLH
MCLK↑ to BUSY↑ Delay
CL = 20pF
l
tDRLLH
MCLK to DRL↑ Delay
CL = 20pF
l
tQUIET
SCKA, SCKB Quiet Time from MCLK↑
(Note 8)
l
10
ns
tSCKA
SCKA Period
(Notes 12, 13)
l
10
ns
tSCKAH
SCKA High Time
l
4
ns
tSCKAL
SCKA Low Time
l
4
ns
tDSDOA
SDOA Data Valid Delay from SCKA↑
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
tHSDOA
SDOA Data Remains Valid Delay from SCKA↑
CL = 20pF (Note 8)
l
tDSDOADRLL SDOA Data Valid Delay from DRL↓
13
18
8.5
8.5
9.5
1
ns
ns
ns
ns
ns
ns
CL = 20pF (Note 8)
l
5
ns
tENAA
Bus Enable Time After RDLA↓
(Note 12)
l
16
ns
tDISA
Bus Relinquish Time After RDLA↑
(Note 12)
l
13
ns
(Notes 12, 13)
tSCKB
SCKB Period
l
10
ns
tSCKBH
SCKB High Time
l
4
ns
tSCKBL
SCKB Low Time
l
4
ns
tDSDOB
SDOB Data Valid Delay from SCKB↑
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
tHSDOB
SDOB Data Remains Valid Delay from SCKB↑
CL = 20pF (Note 8)
l
8.5
8.5
9.5
1
ns
ns
ns
ns
250832fc
For more information www.linear.com/LTC2508-32
5
LTC2508-32
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
tDSDOBBUSYL
SDOB Data Valid Delay from BUSY↓
CL = 20pF (Note 8)
l
5
ns
tENB
Bus Enable Time After RDLB↓
(Note 12)
l
16
ns
tDISB
Bus Relinquish Time After RDLB↑
(Note 12)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz,
DF = 256.
Note 5: Recommended operating conditions.
Note 6: Transition noise is defined as the noise level of the ADC with IN+
and IN– shorted.
MIN
TYP
MAX
UNITS
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Guaranteed by design, not subject to test.
Note 9: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
0000 0000 0000 0000 and 1111 1111 1111 1111 1111 1111 1111
1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error.
Note 10: All specifications in dB are referred to a full-scale ±5V input with
a 5V reference voltage.
Note 11: fSMPL = 1MHz, IREF varies proportionally with sample rate.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 13: tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up
to 100MHz for rising edge capture.
0.8•OVDD
tWIDTH
0.2•OVDD
tDELAY
tDELAY
0.8•OVDD
0.2•OVDD
0.8•OVDD
0.2•OVDD
50%
50%
250832 F01
Figure 1. Voltage Levels for Specifications
6
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, DF = 256, Filtered Output, unless otherwise noted.
Integral Nonlinearity
vs Input Voltage
Integral Nonlinearity
vs Input Voltage
2.0
3.5
ARBITRARY DRIVE
IN+/IN– SWEPT 0 TO 5V
1.5
0
–0.5
–1.0
COUNTS
0.5
σ = 0.095ppm
800
1.8
INL ERROR (ppm)
INL ERROR (ppm)
1.0
DC Histogram, DF = 256
1000
0
–1.8
600
400
200
–1.5
–2.0
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
–3.5
5
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
250832 G01
DC Histogram, DF = 1024
σ = 0.055ppm
600
600
600
COUNTS
800
400
–0.2
0
0.2
OUTPUT CODE (ppm)
0
–0.4
0.4
250832 G05
128k Point FFT fSMPL = 1Msps,
fIN = 200Hz, DF = 256
0
400
–0.2
0
0.2
OUTPUT CODE (ppm)
0
–0.4
0.4
0
0
DR = 136dB
–20
–60
–80
–120
–140
AMPLITUDE (dBFS)
–40
–60
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–120
–140
–160
–180
–180
–180
0.5
1
1.5
FREQUENCY (kHz)
2
250832 G08
–200
0
122
244
366
FREQUENCY (Hz)
DR = 141dB
–80
–160
0
488
250832 G09
250832 G07
–100
–160
–200
0.4
32k Point FFT fSMPL = 1Msps,
fIN = 10Hz, DF = 4096
–20
–40
–100
–0.2
0
0.2
OUTPUT CODE (ppm)
250832 G06
128k Point FFT fSMPL = 1Msps,
fIN = 50Hz, DF = 1024
DR = 131dB
–20
σ = 0.02ppm
200
200
0
–0.4
AMPLITUDE (dBFS)
σ = 0.03ppm
800
200
0.4
250832 G04
DC Histogram, DF = 16384
1000
800
400
–0.2
0
0.2
OUTPUT CODE (ppm)
250832 G03
DC Histogram, DF = 4096
1000
COUNTS
COUNTS
1000
0
–0.4
5
–200
0
30
61
91
FREQUENCY (Hz)
122
250832 G09
250832fc
For more information www.linear.com/LTC2508-32
7
LTC2508-32
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, DF = 256, Filtered Output, unless otherwise noted.
8k Point FFT fSMPL = 1Msps,
fIN = 10Hz, DF = 16384
0
DR = 145dB
–20
DYNAMIC RANGE (dB)
–60
–80
–100
–120
–140
–160
150
0.10
145
0.08
140
0.06
135
0.04
0.02
130
DF=256
DF=1024
DF=4096
DF=16384
0
TRANSITION NOISE (ppm)
–40
AMPLITUDE (dBFS)
Frequency Response,
DF = 256, 1024, 4096, 16384
Dynamic Range, Transition Noise
vs DF
–50
–100
–180
–200
140
0
7
15
23
FREQUENCY (Hz)
31
125
256
250832 G10
1024
4096
DOWN SAMPLING FACTOR (DF)
–110
134
HARMONICS, THD (dBFS)
DR (dB)
130
SINAD
128
120
126
115
124
–30
–20
–10
INPUT LEVEL (dB)
0
122
2.5
250832 G13
Dynamic Range vs Temperature,
fIN = 100Hz, AIN = –20dBFS
fSMPL/512
3fSMPL/1024
fSMPL/256
250832 G12
THD, Harmonics vs Reference
Voltage, fIN = 200Hz,
AIN = –1dBFS
125
10
35
TEMPERATURE (oC)
60
85
3RD
–125
250832 G16
–110
20
10
–15
10
35
TEMPERATURE (°C)
60
2ND
3
3.5
4
REFERENCE (V)
4.5
85
250832 G17
5
250832 G15
250832 G14
30
0
–40
THD
–120
–130
2.5
5
40
130
–15
3.5
4
4.5
REFERENCE VOLTAGE (V)
–115
Shutdown Current vs Temperature
135
120
–40
3
HARMONICS, THD (dBFS)
125
POWER–DOWN CURRENT (µA)
SNR,SINAD (dBFS)
130
110
–40
DR (dB)
fSMPL/1024
132
SNR
8
0
250832 G11
Dynamic Range vs Reference
Voltage, fIN = 200Hz,
AIN = –20dBFS
SNR, SINAD vs Input level,
fIN = 200Hz
135
140
–150
0
16384
THD, Harmonics vs Temperature,
fIN = 200Hz, AIN = –1dBFS
THD
–120
3RD
2ND
–130
–140
–40
–15
10
35
TEMPERATURE (oC)
60
85
250832 G18
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, DF = 256, Filtered Output, unless otherwise noted.
INL vs Temperature
Full-Scale Error vs Temperature
Offset Error vs Temperature
10
4
5
4
MAX INL
1
0
–1
MIN INL
–2
5
ZERO–SCALE ERROR (ppm)
INL ERROR (ppm)
2
FULL–SCALE ERROR (ppm)
3
–FS
0
+FS
–5
–3
2
1
0
–1
–2
–3
–4
–15
10
35
60
TEMPERATURE (°C)
–10
–40
85
250832 G19
35
60
CMRR (dB)
5
4
150
125
3
100
IOVDD
I REF
10
60
85
250832 G21
0.9
6
–15
35
1.0
7
0
–40
10
TEMPERATURE (°C)
Reference Current
vs Reference Voltage
175
1
–15
250832 G20
200
8
2
–5
–40
85
Common Mode Rejection
vs Input Frequency
I VDD
9
10
TEMPERATURE (oC)
Supply Current vs Temperature
10
–15
REFERENCE CURRENT (A)
–4
–40
POWER SUPPLY CURRENT (mA)
3
35
TEMPERATURE (°C)
60
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
85
250832 G22
75
0.0001
0.001
0.01
0.1
FREQUENCY (MHz)
1 2
250832 G23
0
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
250832 G24
250832fc
For more information www.linear.com/LTC2508-32
9
LTC2508-32
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 1Msps, DF = 256, No Latency Output, unless otherwise noted.
No Latency Differential Output
128k Point FFT
0.5
SNR = 86dB
–20
0.4
–40
0.3
INL ERROR (LSB)
AMPLITUDE (dBFS)
0
No Latency Differential Output
INL vs Input Voltage
–60
–80
–100
0.1
0
–0.1
–120
–0.3
–140
–0.4
–160
0
125
250
375
FREQUENCY (kHz)
–0.5
500
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
250832 G26
No Latency Differential Output
DNL vs Input Voltage
5
250832 G27
No Latency Common Mode Output
128k Point FFT
0
0.5
0.4
SNR = 48dB
–20
AMPLITUDE (dBFS)
DNL ERROR (LSB)
0.3
0.1
0
–0.1
–40
–60
–80
–0.3
–100
–0.4
–0.5
10
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
5
–120
0
250832 G28
125
250
375
FREQUENCY (kHz)
500
250832 G29
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
PIN FUNCTIONS
RDLA (Pin 1): Read Low Input A (Filtered Output). When
RDLA is low, the serial data output A (SDOA) pin is enabled.
When RDLA is high, SDOA pin is in a high-impedance
state. Logic levels are determined by OVDD.
DRL (Pin 15): Data Ready Low Output. A falling edge
on this pin indicates that a new filtered output code is
available in the output register of SDOA. Logic levels are
determined by OVDD.
RDLB (Pin 2): Read Low Input B (No Latency Output).
When RDLB is low, the serial data output B (SDOB) pin
is enabled. When RDLB is high, SDOB pin is in a highimpedance state. Logic levels are determined by OVDD.
SDOA (Pin 17): Serial Data Output A (Filtered Output).
The filtered output code appears on this pin (MSB first)
on each rising edge of SCKA. The output data is in 2’s
complement format. Logic levels are determined by OVDD.
VDD (Pin 3): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic capacitor.
SCKA (Pin 18): Serial Data Clock Input A (Filtered Output).
When SDOA is enabled, the filtered output code is shifted
out (MSB first) on the rising edges of this clock. Logic
levels are determined by OVDD.
GND (Pins 4, 7, 16, 23, 24): Ground.
IN+ (Pin 5): Positive Analog Input.
IN– (Pin 6): Negative Analog Input.
REF (Pins 8, 9, 10): Reference Input. The range of REF
is 2.5V to 5.1V. This pin is referred to the GND pin and
should be decoupled closely to the pin with a 47µF ceramic
capacitor (X7R, 1210 size, 10V rating).
SEL0, SEL1 (Pins 11, 12): Down-Sampling Factor Select
Input 0, Down-Sampling Factor Select Input 1. Selects the
down-sampling factor for the digital filter. Down-sampling
factors of 256, 1024, 4096 and 16384 are selected for
[SEL0 SEL1] combinations of 00, 01, 10 and 11 respectively. Logic levels are determined by OVDD.
MCLK (Pin 13): Master Clock Input. A rising edge on this
input powers up the part and initiates a new conversion.
Logic levels are determined by OVDD.
SYNC (Pin 14): Synchronization Input. A pulse on this
input is used to synchronize the phase of the digital filter.
Logic levels are determined by OVDD.
SCKB (Pin 19): Serial Data Clock Input B (No Latency
Output). When SDOB is enabled, the no latency output
code is shifted out (MSB first) on the rising edges of this
clock. Logic levels are determined by OVDD.
SDOB (Pin 20): Serial Data Output B (No Latency Output).
The 22-bit no latency composite output code appears on
this pin (MSB first) on each rising edge of SCKB. The
output data is in 2’s complement format. Logic levels are
determined by OVDD.
BUSY (Pin 21): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
OVDD (Pin 22): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND (Pin 23) close to the pin with
a 0.1µF capacitor.
GND (Exposed Pad Pin 25): Ground. Exposed pad must
be soldered directly to the ground plane.
250832fc
For more information www.linear.com/LTC2508-32
11
LTC2508-32
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 5V
OVDD = 1.8V TO 5V
LTC2508-32
SCKA
IN+
SDOA
+
32-BIT
SAR ADC
IN–
DIGITAL
FILTER
RDLA
32
SPI
PORT
–
SCKB
SDOB
14
RDLB
MCLK
BUSY
DRL
CONTROL LOGIC
SYNC
SEL0
SEL1
GND
250832 FBD
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
RDLA = RDLB = 0
MCLK
CONVERT
DRL
SCKA
DA30
DA28
DA26
DA24
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
CONVERT
DA31
DA29
DA27
DA25
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DA5
DA3
DA1
WA7
WA5
WA3
WA1
POWER DOWN AND ACQUIRE
BUSY
SCKB
DB12
DB10
DB8
DB6
DB4
DB2
DB0
CB6
CB4
CB2
CB0
SDOB
DB13
12
DB11
DB9
DB7
DB5
DB3
DB1
CB7
CB5
CB3
CB1
250832 TD
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
APPLICATIONS INFORMATION
The LTC2508-32 is a low noise, low power, high-performance 32-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2508-32
features a fully differential input range up to ±VREF, with
VREF ranging from 2.5V to 5.1V. The LTC2508-32 supports
a wide common mode range from 0V to VREF simplifying
analog signal conditioning requirements.
The LTC2508-32 simultaneously provides two output
codes: (1) a 32-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 32-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configurations provide a dynamic range of 131dB at 3.9ksps and
145dB at 61sps. The digital lowpass filter relaxes the requirements for analog anti-aliasing. Multiple LTC2508-32
devices can be easily synchronized using the SYNC pin.
CONVERTER OPERATION
The LTC2508-32 operates in two phases. During the acquisition phase, a 32-bit charge redistribution capacitor
D/A converter (CDAC) is connected to the IN+ and IN– pins
to sample the analog input voltages. A rising edge on the
MCLK pin initiates a conversion. During the conversion
phase, the 32-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the
sampled inputs with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/4294967296). At
the end of conversion, the CDAC output approximates the
sampled analog input. The ADC control logic then passes
the 32-bit digital output code to the digital filter for further
processing. A 14-bit code representing the differential
voltage and an 8-bit code representing the common mode
voltage are combined to form a 22-bit composite code.
The 22-bit composite code is available each conversion
cycle, without any cycle of latency.
TRANSFER FUNCTION
The LTC2508-32 digitizes the full-scale differential voltage
of 2× VREF into 232 levels, resulting in an LSB size of 2.3nV
with a 5V reference. The ideal transfer function is shown
in Figure 2. The output data is in 2’s complement format.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/4294967296
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
250832 F02
Figure 2. LTC2508-32 Transfer Function
ANALOG INPUT
The LTC2508-32 samples the voltage difference (IN+ –
IN–) between its analog input pins over a wide common
mode input range while attenuating unwanted signals
common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode input
range coupled with high CMRR allows the IN+/IN– analog
inputs to swing with an arbitrary relationship to each other,
provided each pin remains between GND and VREF. This
unique feature of the LTC2508-32 enables it to accept a
wide variety of signal swings, including traditional classes
of analog input signals such as pseudo-differential unipolar, pseudo-differential true bipolar, and fully differential,
thereby simplifying signal chain design.
In the acquisition phase, each input sees approximately
45pF (CIN) from the sampling circuit in series with 40Ω
(RON) from the on-resistance of the sampling switch.
250832fc
For more information www.linear.com/LTC2508-32
13
LTC2508-32
APPLICATIONS INFORMATION
REF
RON
40Ω
IN+
REF
IN–
RON
40Ω
CIN
45pF
CIN
45pF
BIAS
VOLTAGE
of the analog inputs. Therefore, LPF2 typically requires
wider bandwidth than LPF1. This filter also helps minimize
the noise contribution from the buffer. A buffer amplifier
with a low noise density must be selected to minimize
degradation of SNR.
LPF2
6800pF
SINGLE-ENDEDINPUT SIGNAL LPF1
10Ω
500Ω
250832 F03
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2508-32
The inputs draw a current spike while charging the CIN
capacitors during acquisition. During conversion, the
analog inputs draw only a small leakage current.
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2508-32 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For
best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2508-32. The amplifier
provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs.
Noise and Distortion
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter (LPF1) shown in Figure 4 is sufficient
for many applications.
A coupling filter network (LPF2) should be used between
the buffer and ADC input to minimize disturbances reflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
14
IN+
3300pF
6600pF
10Ω
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 1.2MHz
LTC2508-32
IN–
250832 F04
Figure 4. Filtering Input Signal
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Input Currents
An important consideration when coupling an amplifier to
the LTC2508-32 is in dealing with current spikes drawn
by the ADC inputs at the start of each acquisition phase.
The ADC inputs may be modeled as a switched capacitor
load of the drive circuit. A drive circuit may rely partially
on attenuating switched-capacitor current spikes with
small filter capacitors CFILT placed directly at the ADC
inputs, and partially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance.
Amplifiers optimized for DC performance may not have
sufficient bandwidth to fully recover at the ADC’s maximum
conversion rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
250832fc
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LTC2508-32
APPLICATIONS INFORMATION
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is considerably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2508-32), the disturbance will not contribute any error.
Fully Averaged – If the coupling filter capacitors (CFILT) at
the ADC inputs are much larger than the ADC’s sample
capacitors (45pF), then the sampling glitch is greatly attenuated. The driving amplifier effectively only sees the
average sampling current, which is quite small. At 1Msps,
the equivalent input resistance is approximately 22kΩ
(as shown in Figure 5), a benign resistive load for most
precision amplifiers. However, resistive voltage division
will occur between the coupling filter’s DC resistance and
the ADC’s equivalent (switched-capacitor) input resistance,
thus producing a gain error.
The input leakage currents of the LTC2508-32 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leakage
currents, both common mode and differential, are typically
extremely small over the entire operating temperature
range. Figure 6 shows the input leakage currents over
temperature for a typical part.
22kΩ
(REQ)
CFILT>>45pF
22kΩ
(REQ)
IN–
BIAS
VOLTAGE
CFILT>>45pF
REQ =
1
fSMPL • 45pF
Figure 5. Equivalent Circuit for the Differential
Analog Input of the LTC2508-32 at 1Msps
10
VIN = VREF
7
INPUT LEAKAGE (nA)
Partially Settled – In this case, the beginning of acquisition causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switchedcapacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
LTC2508-32
IN+
4
DIFFERENTIAL
1
COMMON
–2
–5
–40
–15
10
35
TEMPERATURE (°C)
60
85
250832 F06
Figure 6. Common Mode and Differential Input
Leakage Current Over Temperature
Let RS1 and RS2 be the source impedances of the differential input drive circuit shown in Figure 7, and let IL1
and IL2 be the leakage currents flowing out of the ADC’s
analog inputs. The differential voltage error, VE, due to the
leakage currents can be expressed as:
VE =
RS1 +RS2
I +I
• (IL1 –IL2 ) + (RS1 –RS2 ) • L1 L2
2
2
The common mode input leakage current, (IL1 + IL2)/2, is
typically extremely small (Figure 6) over the entire operating temperature range and common mode input voltage
range. Thus, any reasonable mismatch (below 5%) of the
source impedances RS1 and RS2 will cause only a negligible
error. The differential leakage current is also typically very
small, and its nonlinear component is even smaller. Only
the nonlinear component will impact the ADC’s linearity.
250832fc
For more information www.linear.com/LTC2508-32
15
LTC2508-32
APPLICATIONS INFORMATION
RS1
IL1
+
VE
–
RS2
be (mostly) linear. An amplifier’s offset versus signal level
must be considered for amplifiers configured as unity
gain buffers. For example, 1ppm linearity may require that
the offset is known to vary less than 5μV for a 5V swing.
However, greater offset variations may be acceptable if the
relationship is known to be (mostly) linear. Unity-gain buffer
amplifiers typically require substantial headroom to the
power supply rails for best performance. Inverting amplifier circuits configured to minimize swing at the amplifier
input terminals may perform better with less headroom
than unity-gain buffer amplifiers. The linearity and thermal
properties of an inverting amplifier’s feedback network
should be considered carefully to ensure DC accuracy.
IN+
LTC2508-32
IN–
IL2
250832 F07
Figure 7. Source Impedances of a Driver and
Input Leakage Currents of the LTC2508-32
For optimal performance, it is recommended that the
source impedances, RS1 and RS2, be between 5Ω and
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
RS1 and RS2 are usually not critical. The guaranteed AC
and DC specifications are tested with 5Ω source impedances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling.
Buffering Input Signals
The wide common mode input range and high CMRR of
the LTC2508-32 allow analog inputs IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
that each pin remains between VREF and GND. This unique
feature of the LTC2508-32 enables it to accept a wide
variety of signal swings, simplifying signal chain design.
DC Accuracy
The LTC2508-32 has excellent INL specifications. This
makes the LTC2508-32 ideal for applications which require high DC accuracy, including parameters such as
offset and offset drift. To maintain high accuracy over the
entire DC signal chain, amplifiers have to be selected very
carefully. A large-signal open-loop gain of at least 126dB
may be required to ensure 1ppm linearity for amplifiers
configured for a gain of negative 1. However, less gain is
sufficient if the amplifier’s gain characteristic is known to
VIN+
+
LTC2057
Buffering DC Accurate Input Signals
Figure 8 shows a typical application where two analog
input voltages are buffered using the LTC2057. The LTC2057
is a high precision zero drift amplifier which complements
the low offset and offset drift of the LTC2508-32. The
LTC2057 is shown in a non-inverting amplifier configura-
–
1.8V TO 5.1V
2.5V
10Ω
4.7µF
10µF
0.1µF
VDD
0.047µF
OVDD
IN+
4.99k
LTC2508-32
4.99k
IN –
0.047µF
REF
–
2.5V TO 5.1V
10Ω
LTC2057
VIN–
+
GND
47µF
(X7R, 1210 SIZE)
4.7µF
250832 F08
Figure 8. Buffering Two Analog Input Signals
16
For more information www.linear.com/LTC2508-32
250832fc
LTC2508-32
APPLICATIONS INFORMATION
tion. The LTC2508-32 has a guaranteed maximum offset
error of 130µV (typical drift ±0.014ppm/°C), and a guaranteed maximum full-scale error of 150ppm (typical drift
±0.05ppm/°C). Low drift is important to maintain accuracy
over a wide temperature range in a calibrated system.
Buffering DC Accurate Single-Ended Input Signals
While the circuit shown in Figure 8 is capable of buffering
single-ended input signals, the circuit shown in Figure 9 is
preferable when the single-ended signal reference level is
inherently low impedance and doesn’t require buffering.
This circuit eliminates one driver and one lowpass filter,
reducing part count, power dissipation, and SNR degradation due to driver noise.
The LTC2057 has excellent DC characteristics, but limited
output current drive, leading to a degradation in THD as
the input frequency increases. Limit the input frequency
to 10Hz to maintain full data sheet specified THD.
2.5V 1.8V TO 5.1V
10µF
VIN+
0.1µF
VDD
+
LTC2057
–
10Ω
OVDD
IN+
Buffering AC Input Signals
Many driver circuits presented in this data sheet emphasize
performance for low bandwidth input signals, and the
amplifiers are chosen accordingly. While the LTC2057 is
characterized by excellent DC specifications, its output
current drive is limited. This limits the range of input frequencies that the LTC2057 can drive to the full data sheet
specifications of the LTC2508-32. The –3dB bandwidth of
the filtered output of the LTC2508-32, while operating with
a DF of 256, is equal to 480Hz. Therefore, an alternative
driver solution is required while driving input signals with
bandwidth greater than 10Hz.
The LTC6363 is a low power, low noise, fully differential op
amp, and can be used to drive input signals with bandwidth
greater than 10Hz. The LTC6363 may be configured to
convert a single-ended input signal to a differential output
signal or may be driven differentially.
Figure 10a shows the LTC6363 being used to buffer a
10V differential input signal. In this case, the amplifier
is configured as a unity gain buffer using the LT5400-4
precision resistors. As shown in the FFT of Figure 10b, the
LTC6363 drives the LTC2508-32 to near full data sheet
performance.
LTC2508-32
4.7µF
IN –
GND
REF
0.047µF
4.99kΩ
2.5V TO 5.1V
8V
LT5400-4
1k
47µF
(X7R, 1210 SIZE)
250832 F09
VIN–
VIN+
1k
30.1Ω
+
VCM
1k
LTC6363
–
1k
Figure 9. Buffering Single-Ended Signals
6800pF
0.1µF
0.1µF
30.1Ω
0.1µF
–3V
IN+
6800pF
IN–
6800pF
250832 F10a
Figure 10a. Buffering AC Inputs
250832fc
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17
LTC2508-32
APPLICATIONS INFORMATION
0
The reference replenishes this charge with an average
current, IREF = QCONV/tCYC. The current drawn from the
REF pin, IREF, depends on the sampling rate and output
code. If the LTC2508-32 continuously samples a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5ppm.
DR = 130dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
0.5
1
1.5
FREQUENCY (kHz)
2
250832 F10b
Figure 10b. 128k Point FFT with fIN = 200Hz
for Circuit Shown in Figure 10a
ADC REFERENCE
An external reference defines the input range of the
LTC2508-32. A low noise, low temperature drift reference
is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2508-32. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
When choosing a bypass capacitor for the LTC6655-5, the
capacitor’s voltage rating, temperature rating, and package size should be carefully considered. Physically larger
capacitors with higher voltage and temperature ratings tend
to provide a larger effective capacitance, better filtering
the noise of the LTC6655-5, and consequently facilitating
a higher SNR. Therefore, we recommend bypassing the
LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
The REF pin of the LTC2508-32 draws charge (QCONV) from
the 47μF bypass capacitor during each conversion cycle.
When idling, the REF pin on the LTC2508-32 draws only
a small leakage current (< 1μA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 11, IREF quickly goes from approximately
0μA to a maximum of 1mA at 1Msps. This step in average
current drawn causes a transient response in the reference that must be considered, since any deviation in the
reference output voltage will affect the accuracy of the
output code. In applications where the transient response
of the reference is important, the fast settling LTC6655-5
reference is also recommended.
Reference Noise
The dynamic range of the ADC will increase approximately
6dB for every 4× increase in the down-sampling factor
(DF). The SNR should also improve as a function of DF in
the same manner. For large input signals near full-scale,
however, any reference noise will limit the improvement
of the SNR as DF increases, because any noise on the REF
pin will modulate around the fundamental frequency of the
input signal. Therefore, it is critical to use a low-noise reference, especially if the input signal amplitude approaches
full-scale. For small input signals, the dynamic range will
improve as described earlier in this section.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
MCLK
IDLE
PERIOD
IDLE
PERIOD
250832 F11
Figure 11. MCLK Waveform Showing Burst Sampling
18
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
APPLICATIONS INFORMATION
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2508-32 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Dynamic Range
The dynamic range is the ratio of the RMS value of a full
scale input to the total RMS noise measured with the inputs
shorted to VREF/2. The dynamic range of the LTC2508-32
with DF = 256 is 131dB which improves with increase in
the down-sampling factor.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows that the LTC2508-32 achieves
a typical SINAD of 120dB at a 1MHz sampling rate with a
200Hz input, and DF = 256.
0
SNR = 128dB
–20
AMPLITUDE (dBFS)
–60
–80
–100
–120
–140
–160
–180
0
0.5
1
1.5
FREQUENCY (kHz)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
2
2
2
2
THD= 20LOG V2 + V3 + V4 +!+ VN
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2508-32 has two power supply pins: the 2.5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows
the LTC2508-32 to communicate with any digital logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems.
Power Supply Sequencing
–40
–200
Total Harmonic Distortion (THD)
2
250832 F12
Figure 12. 128k Point FFT Plot of LTC2508-32
with DF = 256, fIN = 200Hz and fSMPL = 1MHz
Signal-to-Noise Ratio (SNR)
The LTC2508-32 does not have any specific power supply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described
in the Absolute Maximum Ratings section. The LTC250832 has a power-on-reset (POR) circuit that will reset the
LTC2508-32 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 200μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and the
RMS amplitude of all other frequency components except
the first five harmonics and DC. Figure 12 shows that the
LTC2508-32 achieves an SNR of 128dB when sampling
a 200Hz input at a 1MHz sampling rate with DF = 256.
MCLK Timing
A rising edge on MCLK will power up the LTC2508-32
and start a conversion. Once a conversion has been
started, further transitions on MCLK are ignored until the
conversion is complete. For best results, the falling edge
250832fc
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LTC2508-32
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of MCLK should occur within 40ns from the start of the
conversion, or after the conversion has been completed.
For optimum performance, MCLK should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion
is in progress. Once the conversion has completed, the
LTC2508-32 powers down and begins acquiring the input
signal for the next conversion.
Digital Filtering
The input to the LTC2508-32 is sampled at a rate fSMPL,
and digital words DADC(n) are transmitted to the digital
filter at that rate. Noise from the 32-bit SAR ADC core is
distributed uniformly in frequency from DC to fSMPL/2.
Figure 15 shows the frequency spectrum of DADC(n) at the
output of the SAR ADC core. In this example, the bandwidth
of interest fB is a small fraction of fSMPL/2.
12
The LTC2508-32 has internal timing circuity that is trimmed
to achieve a maximum conversion time of 652ns. With a
maximum sample rate of 1Msps, a minimum acquisition
time of 335ns is guaranteed without any external adjustments.
10
SUPPLY CURRENT (mA)
Internal Conversion Clock
Auto Power Down
8
6
4
2
The LTC2508-32 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of MCLK.
During power-down, data from the last conversion can be
clocked out. To minimize power dissipation during powerdown, disable SDOA, SDOB and turn off SCKA, SCKB. The
auto power-down feature will reduce the power dissipation of the LTC2508-32 as the sampling rate is reduced.
Since power is consumed only during a conversion, the
LTC2508-32 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 13.
DECIMATION FILTERS
0
0
0.2
0.4
0.6
0.8
SAMPLING RATE (Msps)
1
250832 F13
Figure 13. Power Supply Current of
the LTC2508-32 vs Sampling Rate
INTEGRATED DECIMATION FILTER
32-BIT DADC(n)
SAR ADC
CORE
VIN
DIGITAL
FILTER
D1(n)
DOWN
SAMPLER
DOUT(k)
250832 F14
Figure 14. LTC2508-32 Digitally Filtered Output Signal Path
DADC
Many ADC applications use digital filtering techniques
to reduce noise. An FPGA or DSP is typically needed to
implement a digital filter. The LTC2508-32 features an integrated decimation filter that provides 4 selectable digital
filtering functions without any external hardware, thus
simplifying the application solution. Figure 14 shows the
LTC2508-32 digitally filtered output signal path, wherein
the output DADC(n) of the 32-bit SAR ADC core is passed
on to the integrated decimation filter.
20
IVDD
IOVDD
IREF
fB
fSMPL/2
250832 F15
Figure 15. Frequency Spectrum of SAR ADC Core Output
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Aliasing
D1
DIGITAL FILTER CUTOFF FREQUENCY
fSMPL/2
fB
250832 F16
Figure 16. Frequency Spectrum of Digital Filter Core Output
The digital filter integrated in the LTC2508-32 suppresses
out-of-band noise power, thereby lowering overall noise
and increasing the dynamic range (DR). The lower the filter
bandwidth, the lower the noise, and the higher the DR.
Figure 16 shows the corresponding frequency spectrum of
D1(n) at the output of the digital filter, where noise beyond
the cutoff frequency is suppressed by the digital filter.
Down-Sampling
The output data rate of the digital filter is reduced by a
down-sampler without causing spectral interference in
the bandwidth of interest.
The down-sampler reduces the data rate by passing every DF th sample to the output, while discarding all other
samples. The sampling frequency fO at the output of the
down sampler is the ratio of fSMPL and DF, i.e., fO = fSMPL/DF.
The maximum bandwidth that a signal being sampled can
have and be accurately represented by its samples is the
Nyquist bandwidth. The Nyquist bandwidth ranges from
DC to half the sampling frequency (a.k.a. the Nyquist
frequency). An input signal whose bandwidth exceeds
the Nyquist frequency, when sampled, will experience
distortion due to an effect called “Aliasing”.
When aliasing, frequency components greater than the
Nyquist frequency undergo a frequency shift and appear
within the Nyquist bandwidth. Figure 17 illustrates aliasing
in the time domain. The solid line shows a sinusoidal input
signal of a frequency greater than the Nyquist frequency
(fO/2). The circles show the signal sampled at fO. Note that
the sampled signal is identical to that of sampling another
sinusoidal input signal of a lower frequency shown with the
dashed line. To avoid aliasing, it is necessary to band-limit
an input signal to the Nyquist bandwidth before sampling
it. A filter that suppresses spectral components outside the
Nyquist bandwidth is called an “Anti-Aliasing Filter”(AAF).
Anti-Aliasing Filters
Figure 18 shows a typical signal chain including a lowpass
AAF and an ADC sampling at a rate of fO. The AAF rejects
input signal components exceeding fO/2, thus avoiding
aliasing. If the bandwidth of interest is close to fO/2, then
The LTC2508-32 enables the user to select DF according
to a desired bandwidth of interest. The 4 available configurations can be selected by pin strapping pins SEL0
and SEL1. Table 1 summarizes the different decimation
filter configurations and properties. When operating at
1.024Msps, the acquisition time (tACQ) of the LTC2508-32
is reduced to 308.5ns and the output data rate correspondingly increases. Note that the dynamic range is unchanged
as it is only affected by DF and not by sampling rate.
INPUT SIGNAL
SAMPLED SIGNAL
(ALIASED)
250832 F17
Figure 17. Time Domain View of Aliasing
Table 1. Properties of Filters in LTC2508-32
SEL1:SEL0
00
01
10
11
DOWN SAMPLING
FACTOR (DF)
256
1024
4096
16384
–3dB BANDWIDTH
fSMPL = 1Msps
480Hz
120Hz
30Hz
7.5Hz
fSMPL = 1.024Msps
491.5Hz
122.8Hz
30.7Hz
7.7Hz
OUTPUT DATA RATE (ODR)
fSMPL = 1Msps
3906sps
977sps
244sps
61sps
fSMPL = 1.024Msps
4000sps
1000sps
250sps
62.5sps
DYNAMIC RANGE
131dB
136dB
141dB
145dB
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the AAF must have a very steep roll-off. The complexity of
the analog AAF increases with the steepness of the roll-off,
and it may be prohibitive if a very steep filter is required.
Alternatively, a simple low-order analog filter in combination
with a digital filter can be used to create a mixed-mode
equivalent AAF with a very steep roll-off. A mixed-mode
filter implementation is shown in Figure 19 where an
analog filter with a gradual roll-off is followed by the
LTC2508-32 sampling at a rate of fSMPL = DF • fO. The
LTC2508-32 has an integrated digital filter at the output
of the ADC core. The equivalent AAF, HEQ(f), is the product
f0
ANTI-ALIASING FILTER
VIN
DOUT (k)
ADC
f0/2
of the frequency responses of the analog filter H1(f) and
digital filter H2(f), as shown in Figure 20. The digital filter
provides a steep roll-off, allowing the analog filter to have
a relatively gradual roll-off.
The digital filter in the LTC2508-32 operates at the ADC
sampling rate fSMPL and suppresses signals at frequencies
exceeding fO/2. The frequency response of the digital filter
H2(f) repeats at multiples of fSMPL, resulting in unwanted
passbands at each multiple of fSMPL. The analog filter
should be designed to provide adequate suppression of
the unwanted passbands, such that HEQ(f) has only one
passband corresponding to the frequency range of interest.
Larger DF settings correspond to less bandwidth of the
digital filter, allowing for the analog filter to have a more
gradual roll-off. A simple first- or second-order analog
filter will provide adequate suppression for most systems.
f0
250832 F18
Figure 18. ADC Signal Chain with AAF
fSMPL = DF × fO
LTC2508
ANALOG FILTER
DOWN-SAMPLER
DIGITAL FILTER
H1
H2
fSMPL – f0/2
VIN
f0/2
ADC
CORE
IMAGE
D1 (n)
fSMPL – f0/2
f0/2
fSMPL
DF
DOUT (k)
AT f0 (sps)
fSMPL
250832 F19
Figure 19. Mixed-Mode Filter Signal Chain
H1
H2
ANALOG FILTER
DIGITAL FILTER
fSMPL – f0/2
f0/2
fSMPL
HEQ
fSMPL – f0/2
f0/2
fSMPL
EQUIVALENT AAF
VIN
TO ADC
f0/2
fSMPL
250832 F20
Figure 20. Mixed-Mode Anti-Aliasing Filter (AAF)
22
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and detailed version of the frequency response of the 4
digital filter configurations are available at www.linear.com/
docs/52896. Table 2 lists the length and group delay of
each digital filter’s impulse response.
0
–50
Table 2. Length of Digital Filter
DOWN-SAMPLING
FACTOR (DF)
256
1,024
4,096
16,384
–100
–150
0
fSMPL/1024
fSMPL/512
3fSMPL/1024
fSMPL/256
LENGTH OF DIGITAL FILTER
IMPULSE RESPONSE
2,304
9,216
36,864
147,456
GROUP DELAY
(fSMPL = 1Msps)
1.2ms
4.6ms
18.4ms
73.7ms
250832 F21
Settling Time and Group Delay
Figure 21. Frequency Response of Digital Filter with DF = 256
The length of each digital filter’s impulse response determines its settling time. Linear phase filters exhibit constant
delay time versus input frequency (that is, constant group
delay). Group delay of the digital filter is defined to be the
delay to the center of the impulse response.
Frequency Response of Digital Filters
Figure 21 shows the frequency response of the digital
filter when the LTC2508-32 is configured to operate with
DF = 256 and sampling at fSMPL.
LTC2508-32 is optimized for low latency, and it provides fast settling. Figure 22 shows the output settling
behavior after a step change on the analog inputs of the
LTC2508-32. The X axis is given in units of output sample
number. The step response is representative for all values
of DF. Full settling is achieved in 10 output samples.
For each configuration of the LTC2508-32, the digital
filter is a lowpass finite impulse response (FIR) filter
with linear phase response. The bandwidth is inversely
proportional to the selected DF value. Each configuration
provides a minimum of 80dB attenuation for frequencies
in the range of fO/2 and fSMPL – fO/2. The filter coefficients
1
GROUP DELAY
ANALOG STEP INPUT SIGNAL
DIGITAL FILTER OUTPUT D1(n)
LTC2508 OUTPUT SAMPLES DOUT(k)
0
–2
–1
0
1
2
3
4
5
6
7
OUTPUT SAMPLE NUMBER
8
9
10
11
250832 F22
Figure 22. Step Response of LTC2508-32
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LTC2508-32
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DIGITAL INTERFACE
Filtered Output Data
The LTC2508-32 features two digital serial interfaces.
Serial interface A is used to read the filtered output data.
Serial interface B is used to read the no latency output
data. Both interfaces support a flexible OVDD supply, allowing the LTC2508-32 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Figure 23 shows a typical operation for reading the filtered
output data. The I/O register contains filtered output codes
DOUT(k) provided by the decimation filter. DOUT(k) is updated once in every DF number of conversion cycles. A
timing signal DRL indicates when DOUT(k) is updated. DRL
goes high at the beginning of every DFth conversion, and
it goes low when the conversion completes. The 32-bits
of DOUT(k) can be read out before the beginning of the
next A/D conversion.
CONVERSION
NUMBER
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
(REGISTER UPDATED ONCE
EVERY DF CONVERSIONS)
DOUT(2)
1 32
DOUT(3)
1 32
1 32
SCKA
250832 F23
Figure 23. Typical Filtered Output Data Operation Timing
DF NUMBER OF CONVERSIONS
CONVERSION
NUMBER 0
1
2
3
31
32
33
DF
DF+1
MCLK
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
1
2
3
(REGISTER UPDATED ONCE FOR
EVERY DF CONVERSIONS)
DOUT(1)
32
1
SCKA
1 SCKA
1 SCKA
1 SCKA
1 SCKA/CNV
1 SCKA
0 SCKA
32 SCKA
250832 F24
Figure 24. Reading Out Filtered Output Data with Distributed Read
24
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APPLICATIONS INFORMATION
Distributed Read
LTC2508-32 enables the user to read out the contents
of the I/O register over multiple conversions. Figure 24
shows a case where one bit of DOUT(k) is read for each
of 32 consecutive A/D conversions, enabling the use of
a much slower serial clock (SCKA). Transitions on the
digital interface should be avoided during A/D conversion
operations (when BUSY is high).
Synchronization
The output of the digital filter D1(n) is updated every
conversion, whereas the down-sampler output DOUT(k)
is updated only once every DF number of conversions.
Synchronization is the process of selecting when the
output DOUT(k) is updated.
CONVERSION
NUMBER
1
2
DF
DF+1
This is done by applying a pulse on the SYNC pin of the
LTC2508-32. The I/O register for DOUT(k) is updated at
each multiple of DF number of conversions after a SYNC
pulse is provided, as shown in Figure 25. A timing signal
DRL indicates when DOUT(k) is updated.
The SYNC function allows multiple LTC2508 devices,
operated from the same master clock that use common
SYNC signal, to be synchronized with each other. This
allows each LTC2508 device to update its output register
at the same time. Note that all devices being synchronized
must operate with the same DF.
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DRL
SYNC
FILTERED OUTPUT
REGISTER
DF NUMBER
OF CONVERSIONS
DOUT(0)
DF NUMBER
OF CONVERSIONS
DOUT(1)
DF NUMBER
OF CONVERSIONS
DOUT(2)
DOUT(3)
250832 F25
Figure 25. Synchronization Using a Single SYNC Pulse
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LTC2508-32
APPLICATIONS INFORMATION
Periodic Synchronization
Self-Correcting Synchronization
SYNC pulses that reinforce an existing synchronization do
not interfere with normal operation. Figure 26 shows a
case where a SYNC pulse is applied for each DF number
of conversions to continually reinforce a synchronization. Figure 26 indicates synchronization windows
when a SYNC pulse may be applied to reinforce the
synchronized operation.
Figure 27 shows a case where an unexpected glitch on
MCLK causes an extra A/D conversion to occur. This extra
conversion alters the update instants for DOUT(k). The
applied periodic SYNC pulse reestablishes the desired
synchronization and self corrects within one conversion
cycle. Note that the digital filter is reset when the synchronization is changed (reestablished).
1
CONVERSION
NUMBER
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
3DF+1
MCLK
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
DRL
SYNC
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
DOUT(2)
DOUT(3)
250832 F26
Figure 26. Synchronization Using a Periodic SYNC Pulse
USER CONVERSION
NUMBER
1
2
DF–1
DF
DF+1
2DF–1
2DF
2DF+1
2DF+2
USER PROVIDED
MCLK
UNWANTED
GLITCH
SYNCHRONIZATION
WINDOW
CORRUPTED
MCLK
EXPECTED DRL
DRL W/O
PERIODIC SYNC
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
PERIODIC SYNC
EXPECTED DRL
CORRECTED DRL
DRL WITH
PERIODIC SYNC
250832 F27
26
Figure 27. Recovering Synchronization from Unexpected Glitch
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250832fc
LTC2508-32
APPLICATIONS INFORMATION
1
CONVERSION 0
NUMBER
2
3
4
5
6
MCLK
BUSY
NO-LATENCY
OUTPUT REGISTER
R(0)
1
R(1)
22
1
R(2)
22
1
R(3)
22
1
R(4)
22
1
R(5)
22
1
R(6)
22
1
22
SCKB
250832 F28
Figure 28. Typical Nyquist Output Data Operation Timing
No Latency Output Data
50Hz and 60Hz Rejection
Figure 28 shows a typical operation for reading the no
latency output data. The no latency I/O register holds a
22-bit composite code R(n) from the most recent sample
taken of inputs IN+ and IN– at the rising edge of MCLK.
The first 14 bits of R(n) represent the input voltage difference (IN+ – IN–), MSB first. The last 8 bits represent
the common-mode input voltage (IN+ + IN–)/2 (in two’s
complement format), MSB first.
Figure 29 shows the frequency response of the digital filter
in the LTC2508-32 configured to operate with DF = 16384,
and fSMPL = 1Msps. As shown, at least 100dB simultaneous suppression of 50Hz and 60Hz is obtained. Note that
the frequency axis shown in Figure 29 scales with fSMPL.
Configuration Word
–60
An 8-bit configuration word, WA[7:0], is appended to the
32-bit output code on SDOA to produce a total output
word of 40 bits as shown in Figure 30. The configuration word designates which downsampling factor (DF)
the digital filter is configured to operate with. Clocking
out the configuration word is optional. Table 3 lists the
configuration words for each DF value.
–80
Table 3. Configuration WORD for Different DF Values
DF=16384
0
Magnitude (dB)
–20
–40
DF
256
1,024
4,096
16,384
–100
–120
0
10
20
30
40
Frequency (Hz)
50
60
250832 F29
WA[7:0]
10000101
10100101
11000101
11100101
Figure 29. Frequency Response of Digital Filter with DF = 16384
MCLK
CONVERT
DRL
SCKA
DA30
DA28
DA26
DA24
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
DA31
DA29
DA27
DA25
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DA5
DA3
DA1
WA7
WA5
WA3
WA1
250832 F30
Figure 30. Using LTC2508-3 to Read Filtered Output
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LTC2508-32
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Filtered Output Data, Single Device, DF = 256
Figure 31 shows an LTC2508-32 configured to operate
with DF = 256. With RDLA grounded, SDOA is enabled and
MSB (DA31) of the output result is available tDSDOADRLL
after the falling edge of DRL.
MASTER CLK
DIGITAL HOST
MCLK
RDLA
SEL0
SEL1
IRQ
DRL
LTC2508-32
DATA IN
SDOA
SCKA
CLK
RDLA = GND
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tCYC
tMCLKH
tMCLKL
MCLK
DRL
tCONV
tDRLLH
tSCKA
SCKA
1
2
3
SDOA
30
31
32
tSCKAL
tHSDOA
tDSDOADRLL
tQUIET
tSCKAH
tDSDOA
DA31
DA30
DA29
DA1
DA0
WA7
250832 F31
Figure 31. Using a Single LTC2508-32 with DF = 256 to Read Filtered Output
28
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Filtered Output Data, Multiple Devices, DF = 256
Figure 32 shows two LTC2508-32 devices configured to
operate with DF = 256, while sharing MCLK, SYNC, SCKA
and SDOA. By sharing MCLK, SYNC, SCKA and SDOA, the
number of required signals to operate multiple ADCs in
parallel is reduced. Since SDOA is shared, the RDLA input
of each ADC must be used to allow only one LTC2508-32
to drive SDOA at a time in order to avoid bus conflicts.
As shown in Figure 32, the RDLA inputs idle high and are
individually brought low to read data out of each device
between conversions. When RDLA is brought low, the
MSB of the selected device is output on SDOA.
SYNC
RDLAX
RDLAY
MASTER CLK
RDLA
SYNC
SEL0
SEL1
MCLK
LTC2508-32
X
SCKA
RDLA
SYNC
SEL0
SEL1
SDOA
DIGITAL HOST
MCLK
LTC2508-32
Y
SCKA
IRQ
DRL
DATA IN
SDOA
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
DRL
tCONV
tDRLLH
RDLAX
RDLAY
SYNC
tSCKA
SCKA
1
tENA
SDOA
tHSDOA
tQUIET
tSCKAH
2
3
tSCKAL
tDSDOA
30
31
32
33
34
35
62
63
64
tDISA
Hi-Z
Hi-Z
Hi-Z
DA31X DA30X DA29X
DA1X DA0X WA7X
DA31Y DA30Y DA29Y
DA1Y DA0Y WA7Y
250832 F32
Figure 32. Reading Filtered Output with Multiple Devices Sharing MCLK, SCKA and SDOA
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LTC2508-32
APPLICATIONS INFORMATION
No Latency Output Data, Single Device
Figure 33 shows a single LTC2508-32 configured to read
the no latency data out. With RDLB grounded, SDOB is
enabled and MSB (DB13) of the output result is available
tDSDOBBUSYL after the falling edge of BUSY.
MASTER CLK
DIGITAL HOST
MCLK
RDLB
LTC2508-32
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
RDLB = GND
CONVERT
POWER-DOWN AND ACQUIRE
tCYC
tMCLKH
tMCLKL
MCLK
tACQ = tCYC – tCONV – tBUSYLH
BUSY
tCONV
tACQ
tBUSYLH
tSCKBH
tSCKB
SCKB
1
2
3
SDOB
21
22
tSCKBL
tHSDOB
tDSDOBBUSYL
20
tQUIET
tDSDOB
DB13
DB12
DB11
CB1
CB0
250832 F33
Figure 33. Using a Single LTC2508-32 to Read No Latency Output
30
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No Latency Output Data, Multiple Devices
Figure 34 shows multiple LTC2508-32 devices configured
to read no latency data out, while sharing MCLK, SCKB and
SDOB. By sharing MCLK, SCKB and SDOB, the number
of required signals to operate multiple ADCs in parallel is
reduced. Since SDOB is shared, the RDLB input of each
ADC must be used to allow only one LTC2508-32 to drive
SDOB at a time in order to avoid bus conflicts. As shown
in Figure 34, the RDLB inputs idle high and are individually brought low to read data out of each device between
conversions. When RDLB is brought low, the MSB of the
selected device is output on SDOB.
RDLBX
RDLBY
MASTER CLK
MCLK
RDLB
LTC2508-32
X
SCKB
DIGITAL HOST
MCLK
RDLB
SDOB
LTC2508-32
Y
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
BUSY
tCONV
tBUSYLH
RDLBX
RDLBY
tSCKB
SCKB
1
tENB
SDOB
tHSDOB
tQUIET
tSCKBH
2
3
tSCKBL
tDSDOB
20
21
22
23
24
25
42
43
44
tDISB
Hi-Z
Hi-Z
Hi-Z
DB13X DB12X DB11X
CB1X CB0X
DB13Y DB12Y DB11Y
CB1Y CB0Y
250832 F34
Figure 34. Reading No Latency Output with Multiple Devices Sharing MCLK, SCKB and SDOB
250832fc
For more information www.linear.com/LTC2508-32
31
LTC2508-32
APPLICATIONS INFORMATION
Filtered Output Data, No Latency Data, Single Device
shared SDO bus at a time in order to avoid bus conflicts.
As shown in Figure 35, the RDLA and RDLB inputs idle
high and are individually brought low to read data from
each serial output when data is available. When RDLA
is brought low, the MSB of the filtered output data from
SDOA is output on the shared SDO bus. When RDLB is
brought low, the MSB of the no latency data output from
SDOB is output on the shared SDO bus.
Figure 35 shows a single LTC2508-32 configured to read
both filtered and no latency output data, while sharing
SDOA with SDOB and SCKA with SCKB. Sharing signals
reduces the total number of required signals to read both
the filtered and no latency data from the ADC. Since SDOA
and SDOB are shared, the RDLA and RDLB inputs of the
ADC must be used to allow only one output to drive the
RDLA
RDLB
MASTER CLK
DIGITAL HOST
MCLK
RDLA
RDLB
IRQ
DRL
LTC2508-32
SDOA
SEL0
SDOB
SEL1 SCKA
SCKB
DATA IN
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
DRL
tCONV
tDRLLH
BUSY
tCONV
tBUSYLH
RDLA
RDLB
tSCKA
SCKA/
SCKB
1
2
3
tHSDOA
tENA
SDOA/
SDOB
Hi-Z
tSCKB
tSCKAH
30
31
tSCKAL
33
DA1
DA0
34
WA7
Hi-Z
DB13
35
52
53
54
tSCKBL
tHSDOB
tDSDOB
tENB
tDISA
tDSDOA
DA31 DA30 DA29
32
tQUIET
tSCKBH
DB12 DB11
CB1
CB0
Hi-Z
250832 F35
Figure 35. Reading Filtered Output and No Latency Output by Sharing SCK, and SDO
32
For more information www.linear.com/LTC2508-32
250832fc
LTC2508-32
BOARD LAYOUT
To obtain the best performance from the LTC2508-32, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2222, the evaluation kit for the LTC2508-32. DC2222
is designed to achieve the full data sheet performance
of the LTC2508-32. Customer board layout should copy
DC2222 grounding, and placement of bypass capacitor
as closely as possible.
250832fc
For more information www.linear.com/LTC2508-32
33
LTC2508-32
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2508-32#packaging for the most recent package drawings.
DKD Package
24-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1864 Rev Ø)
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
2.64 ±0.05
3.10 ±0.05
PACKAGE
OUTLINE
0.50 BSC
0.25 ±0.05
5.50 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
13
R = 0.115
TYP
24
R = 0.05
TYP
0.40 ±0.10
6.43 ±0.10
4.00 ±0.10
2.64 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
12
0.75 ±0.05
0.50 BSC
0.25 ±0.05
5.50 REF
BOTTOM VIEW—EXPOSED PAD
0.200 REF
(DKD24) DFN 0210 REV Ø
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
34
1
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
250832fc
For more information www.linear.com/LTC2508-32
LTC2508-32
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/16
Corrected text in SNR and Digital Filtering sections
PAGE NUMBER
B
2/17
Corrected output data rate value in Table 1
21
C
4/17
Add operation for 1.024msps sample rate
21
19, 20
250832fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC2508-32
tion that the interconnection
of its
circuits as described
herein will not infringe on existing patent rights.
35
LTC2508-32
TYPICAL APPLICATION
Buffering and Converting a ±10V True Bipolar Input Signal to a Fully Differential ADC Input
1k
8V
6800pF
0.1µF
2k
2k
10V
0V
–10V
30.1Ω
+
VCM
VIN+
LTC6363
–
0.1µF
30.1Ω
IN+
5V
2.5V
REF
VDD
6800pF
LTC2508-32
IN–
GND
0.1µF
6800pF
–3V
1k
250832 TA02
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LTC6363
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Amplifier/Driver
Single 2.8V to 11V Supply, 1.9mA Supply Current, MSOP-8 and 2mm × 3mm
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REFERENCES
AMPLIFIERS
36
250832fc
LT 0417 REV C • PRINTED IN USA
For more information www.linear.com/LTC2508-32
www.linear.com/LTC2508-32
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