LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit
Rail-to-Rail DACs with
I2C Interface
Description
Features
Smallest Pin-Compatible Quad DACs:
LTC2609: 16 Bits
LTC2619: 14 Bits
LTC2629: 12 Bits
n Guaranteed Monotonic Over Temperature
n Separate Reference Inputs
n 27 Selectable Addresses
n 400kHz I2C™ Interface
n Wide 2.7V to 5.5V Supply Range
n Low Power Operation: 250µA per DAC at 3V
n Individual Channel Power Down to 1µA (Max)
n High Rail-to-Rail Output Drive (±15mA, Min)
n Ultralow Crosstalk Between DACs (5µV)
n LTC2609/LTC2619/LTC2629: Power-On Reset to
Zero-Scale
n LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset
to Mid-Scale
n Tiny 16-Lead Narrow SSOP Package
The LTC®2609/LTC2619/LTC2629 are quad 16-, 14- and 12bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a 16‑lead
SSOP package. They have built-in high performance output
buffers and are guaranteed monotonic.
n
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply, voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2609/LTC2619/LTC2629 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
The LTC2609/LTC2619/LTC2629 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero-scale; after power-up, they stay at
zero-scale until a valid write and update take place. The
power-on reset circuit resets the LTC2609-1/LTC2619‑1/
LTC2629-1 to mid-scale. The voltage outputs stay at midscale until a valid write and update take place.
Applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245. Patent pending.
Mobile Communications
n Process Control and Industrial Automation
n Automatic Test Equipment and Instrumentation
n
Block Diagram
REFLO
REFA
2
GND
1
VCC
16
REFD
15
VOUTD
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC B
REFB
DAC D
Differential Nonlinearity
(LTC2609)
14
1.0
VOUTB
5
INPUT
REGISTER
DAC A
DAC
REGISTER
VOUTA
4
DAC
REGISTER
3
VOUTC
DAC C
13
0.6
REFC
12
0.4
DNL (LSB)
6
VCC = 5V
VREF = 4.096V
0.8
CONTROL
LOGIC
0.2
0
–0.2
–0.4
32-BIT SHIFT REGISTER
CA0
11
SCL
8
SDA
9
I2C
INTERFACE
ADDRESS
DECODE
LOGIC
CA1
10
CA2
7
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2609 G02
2609 BD
26091929fb
LTC2609/LTC2619/LTC2629
Absolute Maximum Ratings
(Note 1)
Any Pin to GND............................................. –0.3V to 6V
Any Pin to VCC ............................................ –6V to 0.3V
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)................... 300°C
Operating Temperature Range:
LTC2609C/LTC2619C/LTC2629C
LTC2609C-1/LTC2619C-1/LTC2629C-1..... 0°C to 70°C
LTC2609I/LTC2619I/LTC2629I
LTC2609I-1/LTC2619I-1/LTC2629I-1.....–40°C to 85°C
TOP VIEW
GND
1
16 VCC
REFLO
2
15 REFD
REFA
3
14 VOUTD
VOUTA
4
13 VOUTC
VOUTB
5
12 REFC
REFB
6
11 CA0
CA2
7
10 CA1
SCL
8
9
SDA
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 135°C, θJA = 150°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2609CGN#PBF
LTC2609CGN#TRPBF
2609
16-Lead Plastic SSOP
0°C to 70°C
LTC2609CGN-1#PBF
LTC2609CGN-1#TRPBF
26091
16-Lead Plastic SSOP
0°C to 70°C
LTC2609IGN#PBF
LTC2609IGN#TRPBF
2609I
16-Lead Plastic SSOP
–40°C to 85°C
LTC2609IGN-1#PBF
LTC2609IGN-1#TRPBF
2619I1
16-Lead Plastic SSOP
–40°C to 85°C
LTC2619CGN#PBF
LTC2619CGN#TRPBF
2619
16-Lead Plastic SSOP
0°C to 70°C
LTC2619CGN-1#PBF
LTC2619CGN-1#TRPBF
26191
16-Lead Plastic SSOP
0°C to 70°C
LTC2619IGN#PBF
LTC2619IGN#TRPBF
2619I
16-Lead Plastic SSOP
–40°C to 85°C
LTC2619IGN-1#PBF
LTC2619IGN-1#TRPBF
2619I1
16-Lead Plastic SSOP
–40°C to 85°C
LTC2629CGN#PBF
LTC2629CGN#TRPBF
2629
16-Lead Plastic SSOP
0°C to 70°C
LTC2629CGN-1#PBF
LTC2629CGN-1#TRPBF
26291
16-Lead Plastic SSOP
0°C to 70°C
LTC2629IGN#PBF
LTC2629IGN#TRPBF
2629I
16-Lead Plastic SSOP
–40°C to 85°C
LTC2629IGN-1#PBF
LTC2629IGN-1#TRPBF
2629I1
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
26091929fb
LTC2609/LTC2619/LTC2629
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted.
SYMBOL PARAMETER
DC Performance
Resolution
Monotonicity
DNL
Differential Nonlinearity
INL
Integral Nonlinearity
Load Regulation
ZSE
VOS
GE
Zero-Scale Error
Offset Error
VOS Temperature
Coefficient
Gain Error
Gain Temperature
Coefficient
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CONDITIONS
l
(Note 2)
(Note 2)
(Note 2)
VREF = VCC = 5V, Mid-Scale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
VREF = VCC = 2.7V, Mid-Scale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
Code = 0
(Note 4)
l
12
12
14
14
16
16
UNITS
Bits
Bits
LSB
LSB
±0.5
±4
±4
±1
±16
±16
±1
±64
l
l
0.02 0.125
0.02 0.125
0.1
0.1
0.5
0.5
0.3
0.4
2
2
LSB/mA
LSB/mA
l
l
0.04
0.05
1.5
±1
±6
0.25
0.25
9
±9
0.2
0.2
1.5
±1
±6
1
1
9
±9
0.7
0.8
1.5
±1
±6
4
4
9
±9
LSB/mA
LSB/mA
mV
mV
µV/°C
±0.1
±3
±0.7
±0.1
±3
±0.7
±0.1
±3
±0.7
%FSR
ppm/°C
l
l
l
l
l
±1
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded,
unless otherwise noted. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PSR
Power Supply Rejection
VCC ±10%
ROUT
DC Output Impedance
VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.7V, Mid-Scale; –7.5mA ≤ IOUT ≤ 7.5mA
DC Crosstalk (Note 10)
Due to Full-Scale Output Change (Note 11)
Due to Load Current Change
Due to Powering Down (Per Channel)
Short-Circuit Output Current
VCC = 5.5V, VREF = 5.5V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
l
l
15
15
36
36
60
60
mA
mA
VCC = 2.7V, VREF = 2.7V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
l
l
7.5
7.5
22
30
50
50
mA
mA
l
0
VCC
V
l
88
160
kΩ
ISC
–80
0.030
0.035
l
l
dB
0.15
0.15
±5
±4
±4
Ω
Ω
µV
µV/mA
µV
Reference Input
Input Voltage Range
Resistance
Normal Mode
Capacitance
IREF
Reference Current, Power Down Mode
125
14
DAC Powered Down
l
0.001
pF
1
µA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
l
l
l
l
2.7
1.25
1
0.35
0.15
5.5
V
2
1.6
1
1
mA
mA
µA
µA
26091929fb
LTC2609/LTC2619/LTC2629
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted. (Note 9)
Digital I/O (Note 9)
VIL
Low Level Input Voltage
(SDA and SCL)
l
VIH
High Level Input Voltage
(SDA and SCL)
l
VIL(CAn)
Low Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
l
VIH(CAn)
High Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
l
RINH
Resistance from CAn (n = 0, 1, 2)
to VCC to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0, 1, 2)
to VCC or GND to Set CAn = Float
See Test Circuit 2
l
VOL
Low Level Output Voltage
Sink Current = 3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 7)
l
20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed by
Input Filter
l
0
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
1
µA
CIN
I/O Pin Capacitance
(Note 12)
l
10
pF
CB
Capacitive Load for Each Bus Line
l
400
pF
CCAX
External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
l
10
pF
0.3VCC
V
0.7VCC
V
0.15VCC
V
0.85VCC
V
2
MΩ
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded,
unless otherwise noted.
SYMBOL PARAMETER
AC Performance
Settling Time (Note 5)
tS
Settling Time for 1LSB Step
(Note 6)
en
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
Multiplying Bandwidth
Output Voltage Noise Density
Output Voltage Noise
CONDITIONS
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
At Mid-Scale Transition
At f = 1kHz
At f = 10kHz
0.1Hz to 10Hz
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX
7
7
9
2.7
2.7
4.8
0.7
1000
12
180
120
100
15
0.7
1000
12
180
120
100
15
7
9
10
2.7
4.8
5.2
0.7
1000
12
180
120
100
15
UNITS
µs
µs
µs
µs
µs
µs
V/µs
pF
nV • s
kHz
nV/√Hz
nV/√Hz
µVP-P
26091929fb
LTC2609/LTC2619/LTC2629
Timing
Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
l
0
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
µs
tLOW
Low Period of the SCL Clock Pin
l
1.3
µs
tHIGH
High Period of the SCL Clock Pin
l
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
µs
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time of Both SDA and SCL Signals
(Note 7)
l
20 + 0.1CB
300
tf
Fall Time of Both SDA and SCL Signals
(Note 7)
l
20 + 0.1CB
300
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
µs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
µs
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
l
400
ns
t2
LDAC Low Pulse Width
l
20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating.
Note 4: Inferred from measurement at code kL (see Note 2) and at full-Scale.
Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
0.9
µs
ns
ns
ns
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: CB = capacitance of one bus line in pF.
Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with VCC = 5V, REFA = REFB = REFC
= REFD = 4.096V, with the measured DAC at mid-scale, unless otherwise
noted.
Note 11: RL = 2kΩ to GND or VCC.
Note 12: Guaranteed by design and not production tested.
26091929fb
LTC2609/LTC2619/LTC2629
Typical Performance Characteristics
LTC2609
Integral Nonlinearity (INL)
32
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
24
16
0.4
–8
0.2
INL (LSB)
DNL (LSB)
0
0
–0.2
–0.4
–16
16384
32768
CODE
49152
–1.0
65535
0
16384
32768
CODE
49152
2609 G01
–10 10
30
50
TEMPERATURE (°C)
70
90
DNL vs VREF
1.5
VCC = 5.5V
24
0.6
VCC = 5.5V
1.0
16
0.4
DNL (POS)
0.2
INL (LSB)
DNL (LSB)
–30
2609 G03
INL vs VREF
32
VCC = 5V
VREF = 4.096V
0
–0.2
DNL (NEG)
–0.4
0.5
INL (POS)
8
0
–8
INL (NEG)
DNL (POS)
0
DNL (NEG)
–0.5
–16
–0.6
–1.0
–24
–0.8
–1.0
–50
INL (NEG)
–32
–50
65535
DNL (LSB)
0.8
–8
2609 G02
DNL vs Temperature
1.0
0
–24
–0.8
0
INL (POS)
8
–16
–0.6
–24
VCC = 5V
VREF = 4.096V
24
0.6
8
INL (LSB)
VCC = 5V
VREF = 4.096V
0.8
16
–32
INL vs Temperature
32
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
–32
0
2609 G04
1
2
3
VREF (V)
4
5
VOUT
100µV/DIV
2µs/DIV
VCC = 5V, VREF = 4.096V
1/4 SCALE TO 3/4 SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2
3
VREF (V)
4
5
2609 G06
Settling of Full-Scale Step
VOUT
100µV/DIV
SCL
2V/DIV
1
0
2609 G05
Settling to ±1LSB
9TH CLOCK
OF 3RD DATA
BYTE
–1.5
9.7µs
SCR
2V/DIV
2609 G07
12.3µs
9TH CLOCK OF
3RD DATA BYTE
5µs/DIV
2609 G08
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
26091929fb
LTC2609/LTC2619/LTC2629
Typical Performance Characteristics
LTC2619
Integral Nonlinearity (INL)
8
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
6
0.6
0.4
2
DNL (LSB)
INL (LSB)
VCC = 5V
VREF = 4.096V
0.8
4
0
–2
VOUT
100µV/DIV
0.2
0
SCL
2V/DIV
–0.2
–0.4
–4
–0.6
–6
–8
Settling to ±1LSB
4096
8192
CODE
12288
–1.0
16383
8.9µs
2µs/DIV
–0.8
0
9TH CLOCK
OF 3RD DATA
BYTE
0
4096
8192
CODE
12288
2609 G09
2609 G11
VCC = 5V, VREF = 4.096V
1/4 SCALE TO 3/4 SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
16383
2609 G10
LTC2629
Integral Nonlinearity (INL)
2.0
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
1.5
VCC = 5V
VREF = 4.096V
0.8
0.6
1.0
0.4
0.5
DNL (LSB)
INL (LSB)
Settling to ±1LSB
0
–0.5
0.2
0
SCL
2V/DIV
–0.2
–0.4
–1.0
–0.6
–1.5
–0.8
–2.0
–1.0
0
1024
2048
CODE
3072
4095
2609 G12
6.8µs
VOUT
1mV/DIV
9TH CLOCK
OF 3RD DATA
BYTE
2µs/DIV
0
1024
2048
CODE
3072
4095
2609 G14
VCC = 5V, VREF = 4.096V
1/4 SCALE TO 3/4 SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2609 G13
26091929fb
LTC2609/LTC2619/LTC2629
Typical Performance Characteristics
LTC2609/LTC2619/LTC2629
Current Limiting
0.08
CODE = MID-SCALE
0.8
VREF = VCC = 5V
0.06
ΔVOUT (mV)
0
VREF = VCC = 3V
–0.04
2
0.2
0
–0.2
VREF = VCC = 5V
–0.4
VREF = VCC = 5V
–0.06
CODE = MID-SCALE
0.4
0.02
–0.02
Offset Error vs Temperature
3
0.6
VREF = VCC = 3V
0.04
ΔVOUT (V)
Load Regulation
1.0
VREF = VCC = 3V
–0.6
–0.08
OFFSET ERROR (mV)
0.10
20
30
–1.0
–35
40
–25
–15
–5
5
IOUT (mA)
15
25
2609 G15
Zero-Scale Error vs Temperature
1.5
1.0
0.5
0.1
0
–0.1
–0.2
–30
–10 10
30
50
TEMPERATURE (°C)
70
2609 G18
–1
–3
2.5
90
3
3.5
4
VCC (V)
4.5
5
5.5
2609 G20
ICC Shutdown vs VCC
450
0.3
400
0.2
350
0.1
300
ICC (nA)
GAIN ERROR (%FSR)
0
2609 G19
Gain Error vs VCC
0
–0.1
250
200
150
–0.2
100
–0.3
–0.4
2.5
1
–2
–0.4
–50
90
90
2
0.2
–0.3
0.4
70
Offset Error vs VCC
OFFSET ERROR (mV)
GAIN ERROR (%FSR)
2.0
70
–10 10
30
50
TEMPERATURE (°C)
3
0.3
–10 10
30
50
TEMPERATURE (°C)
–30
2609 G17
Gain Error vs Temperature
2.5
ZERO-SCALE ERROR (mV)
–3
–50
35
0.4
–30
–1
2609 G16
3
0
–50
0
–2
–0.8
–0.10
10
–40 –30 –20 –10 0
IOUT (mA)
1
50
3
3.5
4
VCC (V)
4.5
5
5.5
2609 G21
0
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
2609 G22
26091929fb
LTC2609/LTC2619/LTC2629
Typical Performance Characteristics
LTC2609/LTC2619/LTC2629
Large-Signal Response
Mid-Scale Glitch Impulse
Power-On Reset Glitch
TRANSITION FROM
MS-1 TO MS
VOUT
10mV/DIV
VOUT
0.5V/DIV
SCL
2V/DIV
VREF = VCC = 5V
1/4 SCALE TO 3/4 SCALE
2609 G23
2.5µs/DIV
TRANSITION FROM
MS TO MS-1
2.5µs/DIV
Headroom at Rails
vs Output Current
4mV PEAK
VOUT
10mV/DIV
2609 G24
250µs/DIV
Power-On Reset to Mid-Scale
5.0
1.7
2.5
ICC (mA)
VOUT (V)
1.6
3V SOURCING
3.0
1V/DIV
2.0
1.5
1.4
1.3
1.5
1.0
5V SINKING
0.5
0
VCC = 5V
SWEEP SCL
AND SDA
0V TO VCC
AND VCC TO 0V
1.8
4.0
3.5
2609 G25
Supply Current vs Logic Voltage
1.9
VREF = VCC
5V SOURCING
4.5
9TH CLOCK
OF 3RD DATA
BYTE
VCC
1V/DIV
3V SINKING
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
10
2609 G26
VCC
1.2
VOUT
1.1
500µs/DIV
2606 G27
1.0
0
0.5
1
1.5 2 2.5 3 3.5 4 4.5
LOGIC VOLTAGE (V)
5
2609 G28
26091929fb
LTC2609/LTC2619/LTC2629
Typical Performance Characteristics
LTC2609/LTC2619/LTC2629
Output Voltage Noise,
0.1Hz to 10Hz
Multiplying Bandwidth
0
–3
–6
–9
–12
VOUT
10µV/DIV
dB
–15
–18
–21
–24
–27
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
–30
–33
–36
0
2
3
4 5 6
SECONDS
7
8
9
10
2609 G30
1M
10k
100k
FREQUENCY (Hz)
1k
1
2609 G29
Short-Circuit Output Current
vs VOUT (Sinking)
50
0
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
40
30
20
10
0
VCC = 5.5V
VREF = 5.6V
CODE = FULL-SCALE
VOUT SWEPT VCC TO 0V
–10
10mA/DIV
10mA/DIV
Short-Circuit Output Current
vs VOUT (Sourcing)
–20
–30
–40
0
1
2
3
1V/DIV
4
5
6
2609 G31
–50
0
1
2
3
1V/DIV
4
5
6
2609 G32
26091929fb
10
LTC2609/LTC2619/LTC2629
Pin Functions
GND (Pin 1): Analog Ground.
REFLO (Pin 2): Reference Low. The voltage at this pin
sets the zero-scale (ZS) voltage of all DACs. This pin can
be raised up to 1V above ground at VCC = 5V or 100mV
above ground at VCC = 3V.
REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage
Inputs for each DAC. REFx sets the full-scale voltage of
the DACs. REFLO ≤ REFx ≤ VCC .
VOUTA to VOUTD (Pins 4, 5, 13, 14): DAC Analog Voltage
Outputs. The output range is from REFLO to REFx.
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC , GND
or leave it floating to select an I2C slave address for the
part (Table 1).
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance pin while data is shifted in and is an
open-drain N-channel output during acknowledgment. SDA
requires a pull-up resistor or current source to VCC .
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC , GND
or leave it floating to select an I2C slave address for the
part (Table 1).
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
26091929fb
11
LTC2609/LTC2619/LTC2629
Block Diagram
REFLO
REFA
2
GND
1
VCC
16
REFD
15
VOUTD
DAC A
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC D
DAC B
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
VOUTA
4
DAC
REGISTER
3
DAC C
VOUTB
5
REFB
14
VOUTC
13
REFC
12
6
CONTROL
LOGIC
32-BIT SHIFT REGISTER
CA0
11
SCL
8
SDA
9
I2C
INTERFACE
ADDRESS
DECODE
LOGIC
CA1
10
CA2
7
2609 BD
26091929fb
12
LTC2609/LTC2619/LTC2629
Test Circuits
Test Circuit 1
Test Circuit 2
VDD
100Ω
RINH/RINL/RINF
CAn
CAn
VIH(CAn)/VIL(CAn)
GND
2609 TC
Timing Diagram
SDA
tf
tLOW
tSU(DAT)
tr
tf
tHD(STA)
tSP
tr
tBUF
SCL
S
tHD(STA)
tHD(DAT)
tHIGH
tSU(STA)
S
tSU(STO)
P
S
2609 F01
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
Figure 1
26091929fb
13
LTC2609/LTC2619/LTC2629
Operation
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero-scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619‑1/LTC2629-1 set the voltage outputs to mid-scale
when power is first applied.
For some applications, downstream circuits are active during DAC power-up and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2609/LTC2619/
LTC2629 contain circuitry to reduce the power-on glitch;
furthermore, the glitch amplitude can be made arbitrarily
small by reducing the ramp rate of the power supply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
during power-on. See Power-On Reset Glitch in the Typical
Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REFx ≤ VCC + 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at VCC (Pin 16) is
in transition. The REFx pins can be clamped to stay below
the maximum voltage by using Schottky diodes as shown
in Figure 2, thereby easing sequencing constraints.
VCC
LTC2609/
LTC2619/
LTC2629
REFA
REFB
REFC
REFD
16
3
6
12
15
VCC
REFA
REFB
REFC
REFD
2609 F02
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
Transfer Function
The digital-to-analog transfer function is:
k
VOUT (IDEAL) = [REFx – REFLO] + REFLO
2N
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
using the standard 2-wire I2C interface. The Timing Diagram
(Figure 1) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply and
can be obtained from the I2C specifications. For an I2C bus
operating in the fast mode, an active pull-up will be necessary
if the bus capacitance is greater than 200pF. The VCC power
should not be removed from the LTC2609/LTC2619/LTC2629
when the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629. The LTC2609/LTC2619/LTC2629 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
26091929fb
14
LTC2609/LTC2619/LTC2629
Operation
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2609/LTC2619/LTC2629 respond to a write by a
master in this manner. The LTC2609/LTC2619/LTC2629
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: VCC, GND or float. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Table 1. Slave Address Map
CA2
CA1
CA0
SA6 SA5 SA4 SA3 SA2 SA1 SA0
GND
GND
GND
0
0
1
0
0
0
0
GND
GND
FLOAT
0
0
1
0
0
0
1
GND
GND
VCC
0
0
1
0
0
1
0
GND
FLOAT
GND
0
0
1
0
0
1
1
GND
FLOAT
FLOAT
0
1
0
0
0
0
0
GND
FLOAT
VCC
0
1
0
0
0
0
1
GND
VCC
GND
0
1
0
0
0
1
0
GND
VCC
FLOAT
0
1
0
0
0
1
1
GND
VCC
VCC
0
1
1
0
0
0
0
FLOAT
GND
GND
0
1
1
0
0
0
1
FLOAT
GND
FLOAT
0
1
1
0
0
1
0
FLOAT
GND
VCC
0
1
1
0
0
1
1
FLOAT
FLOAT
GND
1
0
0
0
0
0
0
FLOAT
FLOAT
FLOAT
1
0
0
0
0
0
1
FLOAT
FLOAT
VCC
1
0
0
0
0
1
0
FLOAT
VCC
GND
1
0
0
0
0
1
1
FLOAT
VCC
FLOAT
1
0
1
0
0
0
0
FLOAT
VCC
VCC
1
0
1
0
0
0
1
VCC
GND
GND
1
0
1
0
0
1
0
VCC
GND
FLOAT
1
0
1
0
0
1
1
VCC
GND
VCC
1
1
0
0
0
0
0
VCC
FLOAT
GND
1
1
0
0
0
0
1
VCC
FLOAT
FLOAT
1
1
0
0
0
1
0
VCC
FLOAT
VCC
1
1
0
0
0
1
1
VCC
VCC
GND
1
1
1
0
0
0
0
VCC
VCC
FLOAT
1
1
1
0
0
0
1
VCC
VCC
VCC
1
1
1
0
0
1
0
1
1
1
0
0
1
1
GLOBAL ADDRESS
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2609, LTC2619 and
LTC2629 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins (CA0,
CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2609/
LTC2619/LTC2629 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2609/
LTC2619/LTC2629 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data. The LTC2609/LTC2619/LTC2629 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete
bytes of data, the LTC2609/LTC2619/LTC2629 executes the
command specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2609/LTC2619/LTC2629 do not
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
The format of the three data bytes is shown in Figure 3.
The first byte of the input word consists of the 4-bit command and 4-bit DAC address. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629
respectively). A typical LTC2609 write transaction is shown
in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
26091929fb
15
LTC2609/LTC2619/LTC2629
Operation
Write Word Protocol for LTC2609/LTC2619/LTC1629
S
SLAVE ADDRESS
W
A
1ST DATA BYTE
A
2ND DATA BYTE
C2
C1 C0
A3
A2
3RD DATA BYTE
A
P
INPUT WORD
Input Word (LTC2609)
C3
A
A1
A0 D15 D14 D13 D12 D11 D10 D9
1ST DATA BYTE
D8 D7 D6 D5
2ND DATA BYTE
D4
D3
D2
D1 D0
3RD DATA BYTE
Input Word (LTC2619)
C3
C2
C1 C0
A3
A2
A1
A0 D13 D12 D11 D10 D9
1ST DATA BYTE
D8
D7
D6 D5 D4 D3
2ND DATA BYTE
D2
D1
D0
X
X
X
X
3RD DATA BYTE
Input Word (LTC2629)
C3
C2
C1 C0
A3
A2
A1
A0 D11 D10 D9
1ST DATA BYTE
D8
D7
D6
D5
D4 D3 D2 D1
2ND DATA BYTE
D0
X
X
3RD DATA BYTE
2609 F03
Figure 3
Power-Down Mode
Table 2
COMMAND*
C3
C2
C1
C0
0
0
0
0
Write to Input Register n
0
0
0
1
Update (Power Up) DAC Register n
0
0
1
0
Write to Input Register n, Update (Power Up) All n
0
0
1
1
Write to and Update (Power Up) n
0
1
0
0
Power Down n
1
1
1
1
No Operation
ADDRESS (n)*
A3
A2
A1
A0
0
0
0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
1
1
1
1
All DACs
*Command and address codes not shown are reserved and should not be used.
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
For power-constrained applications, power-down mode can
be used to reduce the supply current whenever less than
four outputs are needed. When in power-down, the buffer
amplifiers, bias circuits and reference inputs are disabled,
and draw essentially zero current. The DAC outputs are
put into a high impedance state, and the output pins are
passively pulled to REFLO through individual 90k resistors. Input- and DAC-register contents are not disturbed
during power down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply current is reduced by
approximately 1/4 for each DAC powered down. The effective resistance at REFx (Pins 3, 6, 12 and 15) are at high
impedance (typically > 1GΩ) when the corresponding DACs
are powered down. Normal operation can be resumed by
executing any command which includes a DAC update,
as shown in Table 2.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than four DACs are in a powered-down state prior to
the update command, the power-up delay time is 5µs. If on
the other hand, all four DACs are powered down, then the
26091929fb
16
LTC2609/LTC2619/LTC2629
Operation
main bias generation circuit block has been automatically
shut down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power-up delay time is
12µs (for VCC = 5V) or 30µs (for VCC = 3V).
Voltage Output
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
2.7V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifier is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to system star ground
should be as low as possible. When a zero-scale DAC
output voltage of zero is desired, REFLO (Pin 2) should
be connected to system star ground.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full-scale when
the REF pins are tied to VCC. If REFx = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 4c. No full-scale
limiting can occur if REFx is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
26091929fb
17
18
X = DON’T CARE
2
1
SCL
3
SA4
4
SA3
SA3
5
SA2
SA2
6
SA1
SA1
SLAVE ADDRESS
SA4
7
SA0
SA0
8
WR
1
C3
2
C2
C2
3
C1
C1
4
C0
C0
5
A3
A3
COMMAND
6
A2
A2
7
A1
A1
8
A0
A0
9
ACK
1
D15
2
D14
3
D13
4
5
D11
MS DATA
D12
6
D10
7
D9
8
D8
9
ACK
1
D7
2
D6
3
D5
Figure 4. Typical LTC2609 Input Waveform—Programming DAC Output for Full-Scale
9
ACK
C3
4
5
D3
LS DATA
D4
6
D2
7
D1
8
D0
9
ACK
ZERO-SCALE
VOLTAGE 2609 F04
FULL-SCALE
VOLTAGE
STOP
Operation
VOUT
SA5
SA6
SA5
SDA
START
SA6
LTC2609/LTC2619/LTC2629
26091929fb
NEGATIVE
OFFSET
0V
OUTPUT
VOLTAGE
0
(5a)
32, 768
INPUT CODE
65, 535
(5c)
INPUT CODE
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (5a) Overall Transfer Function, (5b) Effect
of Negative Offset for Codes Near Zero-Scale, (5c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
(5b)
INPUT CODE
OUTPUT
VOLTAGE
REFx = VCC
REFx = VCC
2609 F05
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC2609/LTC2619/LTC2629
Operation
26091929fb
19
LTC2609/LTC2619/LTC2629
Typical Application
Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters
REFA
JP3
2
1
3
A
B
4
5
C
6
1
C1
VCC 0.1µF
REFB
JP4
REFC
JP5
2
1
3
A
B
4
5
C
6
REFD
JP6
2
1
3
A
B
4
5
C
6
ADC REF
JP7
2
1
3
A
B
4
5
C
6
VREF
2
3
A
B
5
C
6
4
VCC
5VREF
16
4.096VREF
VCC
11
10
7
9
I2C
8
REFLO
2
4
C6
0.1µF
3
C8
0.1µF
VIN
VOUT
NC
NC
6
5
GND GND
VIN
C10
0.1µF
E6
E7
E8
E9
VREF
C4
0.1µF
C3
100pF
C7
1µF
6.3V
4.096VREF
C9
1µF
6.3V
VCC
R5
7.5k
LTC2428CG
CH0
CH1
CH2
CH3
8-CHANNEL
CH4
MUX
CH5
CH6
CH7
ZSSET
+
–
20-BIT
ADC
GND GND GND GND GND GND GND
1
6
16
18
22
27
28
E11
C5
0.1µF
R8
22Ω
2 8
7
4
3
MUXOUT ADCIN FSSET VCC VCC
9
10
11
12
13
14
15
17
5
E10
CSADC
CSMUX
SCK
CLK
DIN
SD0
F0
VOUTA
REFA
VOUTB
REFB
VOUTC
REFC
VOUTD
REFD
GND
GND
JP2
VCC ON/OFF
DISABLE
ADC
23
20
25
19
21
24
R6
7.5k
CS
SCK
MOSI
MISO
SPI
BUS
26
R7
7.5k
2609 TA02
2
LT1790ACS6-2.048
6
4
VIN VOUT
3
5
NC
NC
GND GND
1
E5
1
2
LT1790ACS6-4.096
6
4
VIN VOUT
3
5
NC
NC
1
E4
GND
5VREF
GND GND
VIN
E3
GND
LT1790ACS6-5
1
E2
JP1 REFLO
EXT
EXT REFLO
REFLO
VIN
2.048VREF
LTC2609CGN
4
CA0
VOUTA
3
CA1
REFA
5
CA2
VOUTB
6
REFB
13
VOUTC
12
REFC
14
SDA
VOUTD
15
SCL
REFD
2.048VREF
C11
1µF
6.3V
2
26091929fb
20
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2609/LTC2619/LTC2629
Revision History
REV
DATE
DESCRIPTION
A
11/09
Update Manufacturer’s Information on Typical Application
1
Revise Receiver Input Hysteresis Conditions
3
Revise Block Diagram
7
Revise Figure 1.
8
Update Manufacturer’s Information on Figure 10
10
Update Tables 1 and 3
12
Revised C- and I-Grade Temperature Ranges in Order Information Section
2
B
3/10
PAGE NUMBER
26091929fb
21
LTC2609/LTC2619/LTC2629
Package Description
GN Package
16-Lead Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 p.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 p.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 p .004
s 45o
(0.38 p 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
TYP
GN16 (SSOP) 0204
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654
Dual 14-Bit Rail-to-Rail VOUT DAC
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
LTC1655/LTC1655L
Single 16-Bit VOUT DACs with Serial Interface in SO-8
VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L
Parallel 5V/3V 16-Bit VOUT DACs
Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665
Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610
LTC2620
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2601/LTC2611
LTC2621
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2602/LTC2612
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2604/LTC2614
LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
Output, SPI Serial Interface
LTC2605/LTC2615
LTC2625
Octal 16-/14-/12-Bit VOUT DACs with I2C Interface in 16-Lead SSOP 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output
LTC2606/LTC2616
LTC2626
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN with I2C Interface
270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
Output
26091929fb
22 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0310 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2005
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