LTC3883/LTC3883-1
Single Phase Step-Down DC/DC Controller with
Digital Power System Management
FEATURES
DESCRIPTION
PMBus/I2C Compliant Serial Interface
nn Telemetry Read-Back Includes V , I , V
IN IN OUT,
IOUT, Temperature and Faults
nn Programmable Voltage, Current Limit, Digital
Soft-Start/Stop, Sequencing, Margining, OV/UV/OC
and Frequency Synchronization (250kHz to 1MHz)
n ±0.5% Output Voltage Accuracy over Temperature
n Integrated 16-Bit ADC and 12-Bit DAC
n Integrated High Side Current Sense Amplifier
n Internal EEPROM with ECC and Fault Logging
n Integrated N-Channel MOSFET Gate Drivers
Power Conversion
n Wide V Range: 4.5V to 24V
IN
n V
Range:
0.5V to 5.4V
OUT
n Analog Current Mode Control Loop
n Accurate PolyPhase® Current Sharing for Up to 6 Phases
n Auto Calibration of Inductor DCR
n Minimum On Time 45ns
n Available in a 32-Lead (5mm × 5mm) QFN Package
nn AEC-Q100 Qualified for Automotive Applications
The LTC®3883/LTC3883-1 are PolyPhase capable DC/DC
synchronous step-down switching regulator controllers
with a PMBus compliant serial interface. The controllers
use a constant frequency, current mode architecture that
is supported by the LTPowerPlay™ software development
tool with graphical user interface (GUI).
n
APPLICATIONS
Switching frequency, output voltage, and device address
can be programmed using external configuration resistors.
Additionally, parameters can be set via the digital interface
or stored in on-chip EEPROM.
The LTC3883/LTC3883-1 can be configured for Burst
Mode® operation, discontinuous (pulse-skipping) mode or
continuous inductor current mode. The LTC3883 incorporates an internal 5V linear regulator while the LTC3883-1
uses an external 5V supply for minimum power loss.
The LTC3883/LTC3883-1 are available in a 32-lead 5mm
× 5mm QFN package.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 5408150,
6580258, 6304066, 7420359. Licensed under U.S. Patent 7000125 and other related patents
worldwide.
High Current Distributed Power Systems
Telecom Systems
n Intelligent Energy Efficient Power Regulation
n
n
TYPICAL APPLICATION
5mΩ
10µF
100Ω
D1
INTVCC
100Ω
TG
1µF
BOOST
VIN_SNS
SW
VIN
BG
100
M1
90
0.56µH
M2
1.4k
0.22µF
LTC3883*
PMBus
INTERFACE
FAULT
MANAGEMENT
TO/FROM
OTHER LTC DEVICES
WRITE PROTECT
SDA
SCL
ALERT
RUN
ISENSE+
ISENSE–
VSENSE
TSNS
GPIO
PGOOD
SHARE_CLK
WP
2200pF
ITH
VDD33
VDD25
10nF
4.99k
MMBT3906
VOUT
1.8V
20A
COUT
530µF
80
1µF
1µF
*SOME DETAILS OMITTED
FOR CLARITY
7
6
70
5
60
50
4
40
3
30
2
20
1
10
0
0.01
SGND
8
VIN = 12V
VOUT = 1.8V
fSW = 350kHz
POWER LOSS (W)
22µF
IIN_SNS
0.1µF
Efficiency and Power Loss
vs Load Current
10µF
1µF
EFFICIENCY (%)
VIN
6V TO 24V
1
0.1
10
LOAD CURRENT (A)
0
100
3883 TA01b
3883 TA01a
Rev. F
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1
LTC3883/LTC3883-1
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application......................................... 1
Description.................................................. 1
Table of Contents........................................... 2
Absolute Maximum Ratings............................... 4
Pin Configuration........................................... 4
Order Information........................................... 4
Electrical Characteristics.................................. 5
Typical Performance Characteristics................... 10
Pin Functions............................................... 14
Block Diagram.............................................. 16
Operation................................................... 17
Overview.................................................................. 17
Main Control Loop................................................... 17
EEPROM.................................................................. 18
Power Up and Initialization...................................... 18
Soft-Start................................................................. 19
Sequencing.............................................................. 19
Voltage-Based Sequencing......................................20
Shutdown................................................................20
Light Load Current Operation.................................. 21
Switching Frequency and Phase.............................. 21
Output Voltage Sensing...........................................22
Output Current Sensing...........................................22
Auto Calibration ......................................................22
Accurate DCR Temperature Compensation .............22
Input Current Sensing..............................................22
Load Sharing...........................................................23
External/Internal Temperature Sense.......................23
RCONFIG (Resistor Configuration) Pins................... 24
Fault Detection and Handling................................... 25
Internal Memory with CRC and ECC ...................26
Serial Interface........................................................26
Communication Failure .......................................26
Device Addressing...................................................26
Responses to VOUT and IOUT Faults......................... 27
Output Overvoltage Fault Response.................... 27
Output Undervoltage Response .......................... 27
Peak Output Overcurrent Fault Response............ 27
Responses to Timing Faults..................................... 28
Responses to VIN OV Faults..................................... 28
Responses to OT/UT Faults...................................... 28
Overtemperature Fault Response—Internal ....... 28
Overtemperature and Undertemperature
Fault Response—Externals ................................ 28
Responses To Input Overcurrent And Output
Undercurrent Faults.................................................29
Responses to External Faults ..................................29
Fault Logging...........................................................29
Bus Timeout Failure.................................................29
Similarity Between PMBus, SMBus and I2C
2-Wire Interface.......................................................29
PMBus Serial Digital Interface.................................30
PMBus Command Summary............................. 33
PMBus Commands..................................................33
*Data Format...........................................................38
Applications Information................................. 39
Current Limit Programming.....................................39
ISENSE+ and ISENSE– Pins..........................................39
Low Value Resistor Current Sensing........................40
Inductor DCR Current Sensing................................. 41
Slope Compensation and Inductor Peak Current..... 42
Inductor Value Calculation....................................... 42
Inductor Core Selection...........................................43
Power MOSFET and Schottky Diode (Optional)
Selection..................................................................43
Variable Delay Time, Soft-Start and Output Voltage
Ramping..................................................................44
Digital Servo Mode..................................................45
Soft Off (Sequenced Off).........................................45
INTVCC Regulator.....................................................46
Rev. F
2
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LTC3883/LTC3883-1
TABLE OF CONTENTS
Topside MOSFET Driver Supply (CB, DB)................. 47
Undervoltage Lockout.............................................. 47
CIN and COUT Selection............................................ 47
Fault Conditions.......................................................48
Open-Drain Pins...................................................... 49
Phase-Locked Loop and Frequency Synchronization...
49
Minimum On-Time Considerations..........................50
Input Current Sense Amplifier..................................50
RCONFIG (External Resistor
Configuration Pins).................................................. 51
Voltage Selection................................................. 51
Frequency and Phase Selection Using RCONFIG.53
Address Selection Using RCONFIG......................53
Efficiency Considerations........................................54
Checking Transient Response..................................54
PolyPhase Configuration.....................................55
PC Board Layout Checklist......................................56
PC Board Layout Debugging....................................58
Design Example.......................................................58
Connecting the USB to I2C/SMBus/PMBus Controller
to the LTC3883 In System.......................................60
Inductor DCR Auto Calibration ................................ 61
Accurate DCR Temperature Compensation..............62
LTpowerPlay: An Interactive GUI for Digital Power..63
PMBus Communication and Command Processing.64
PMBus Command Details................................ 66
Addressing and Write Protect..................................66
General Configuration COMMANDS......................... 67
On/Off/Margin.........................................................68
PWM Configuration................................................. 70
Voltage..................................................................... 72
Input Voltage and Limits...................................... 72
Output Voltage and Limits................................... 73
Current..................................................................... 76
Output Current Calibration .................................. 76
Output Current..................................................... 78
Input Current Calibration ....................................80
Input Current.......................................................80
Temperature.............................................................80
External Temperature Calibration........................80
External Temperature Limits................................ 81
Timing.....................................................................82
Timing—On Sequence/Ramp..............................82
Timing—Off Sequence/Ramp.............................83
Precondition for Restart......................................83
Fault Response........................................................84
Fault Responses All Faults...................................84
Fault Responses Input Voltage............................84
Fault Responses Output Voltage..........................85
Fault Responses Output Current.......................... 87
Fault Responses IC Temperature.........................88
Fault Responses External Temperature................89
Fault Sharing............................................................90
Fault Sharing Propagation...................................90
Fault Sharing Response.......................................92
Scratchpad..............................................................92
Identification............................................................92
Telemetry.................................................................98
NVM Memory Commands..................................... 102
Store/Restore.................................................... 102
Fault Logging..................................................... 104
Block Memory Write/Read................................ 107
Typical Applications..................................... 109
Package Description.................................... 114
Revision History......................................... 115
Typical Application...................................... 116
Related Parts............................................. 116
Rev. F
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3
LTC3883/LTC3883-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
VIN, SW....................................................... –0.3V to 28V
Topside Driver Voltage (BOOST)................. –0.3V to 34V
Switch Transient Voltage (SW)...................... –5V to 28V
EXTVCC, INTVCC, BG, (BOOST – SW) .......... –0.3V to 6V
VSENSE+, ISENSE+, ISENSE–.............................. –0.3V to 6V
RUN, SDA, SCL, ALERT.............................. –0.3V to 5.5V
FREQ_CFG, VOUT_CFG, V TRIM_CFG,
ASEL, VDD25............................................. –0.3V to 2.75V
VSENSE–...................................................... –0.3V to 0.3V
(VIN_SNS – VIN), (VIN – IIN_SNS)................. –0.3V to 0.3V
PGOOD, GPIO, SHARE_CLK, ITH,
VDD33, SYNC, WP...................................... –0.3V to 3.6V
INTVCC Peak Output Current.................................100mA
Operating Junction Temperature Range
(Note 2)................................................. –40°C to 125°C*
Storage Temperature Range................. –65°C to 150°C*
*See Derating EEPROM Retention at Temperature in the
Applications Information Section for Junction Temperatures
in Excess of 125°C.
PIN CONFIGURATION
LTC3883-1
PGND
BG
EXTVCC
VIN
ITH
TSNS
32 31 30 29 28 27 26 25
VSENSE+
TOP VIEW
PGND
BG
INTVCC
VIN
ITH
VSENSE+
VSENSE–
TSNS
TOP VIEW
VSENSE–
LTC3883
32 31 30 29 28 27 26 25
VIN_SNS 1
24 BOOST
VIN_SNS 1
24 BOOST
IIN_SNS 2
23 TG
IIN_SNS 2
23 TG
ISENSE+ 3
22 SW
ISENSE+ 3
22 SW
ISENSE– 4
21 VDD33
ISENSE– 4
33
GND
SYNC 5
20 SHARE_CLK
21 VDD33
33
GND
SYNC 5
20 SHARE_CLK
SCL 6
19 WP
SCL 6
19 WP
SDA 7
18 VDD25
SDA 7
18 VDD25
17 VTRIM_CFG
DNC
VOUT_CFG
FREQ_CFG
DNC
ASEL
GPIO
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
RUN
9 10 11 12 13 14 15 16
DNC
VOUT_CFG
FREQ_CFG
DNC
ASEL
RUN
GPIO
PGOOD
17 VTRIM_CFG
ALERT 8
9 10 11 12 13 14 15 16
PGOOD
ALERT 8
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 44°C/W, θJC = 7.3°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 44°C/W, θJC = 7.3°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3883EUH#PBF
LTC3883EUH#TRPBF
3883
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 105°C
LTC3883IUH#PBF
LTC3883IUH#TRPBF
3883
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3883EUH-1#PBF
LTC3883EUH-1#TRPBF
38831
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 105°C
LTC3883IUH-1#PBF
LTC3883IUH-1#TRPBF
38831
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
Rev. F
4
For more information www.analog.com
LTC3883/LTC3883-1
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
AUTOMOTIVE PRODUCTS**
LTC3883EUH#WPBF
LTC3883EUH#WTRPBF
3883
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 105°C
LTC3883IUH#WPBF
LTC3883IUH#WTRPBF
3883
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3883EUH-1#WPBF
LTC3883EUH-1#WTRPBF 38831
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 105°C
LTC3883IUH-1#WPBF
LTC3883IUH-1#WTRPBF
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
38831
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL
PARAMETER
Input Voltage
VIN
Input Voltage Range
IQ
Input Voltage Supply Current
Normal Operation
VUVLO
TINT
Undervoltage Lockout Threshold
when VIN > 4.2V
Initialization Time from VIN Applied Until the
TON_DELAY Timer Starts
Control Loop
VOUTR0
Full-Scale Voltage Range 0
Set Point Accuracy (0.6V to 5V)
Resolution
LSB Step Size
VOUTR1
Full-Scale Voltage Range 1
Set Point Accuracy (0.6V to 2.5V)
Resolution
LSB Step Size
VLINEREG
Line Regulation
VLOADREG
Load Regulation
gm
IISENSE
VSENSERIN
VIlLIMIT
Error Amplifier gm
Input Current
VSENSE Input Resistance to Ground
Resolution
VILIMMAX
VILIMMIN
CONDITIONS
MIN
(Note 12)
(Note 14)
VRUN = 3.3V, No Caps on TG and BG
VRUN = 0V
VINTVCC/VEXTVCC Falling
VINTVCC/VEXTVCC Rising
MFR_CONFIG_ALL Bit 4 = 0
MFR_CONFIG_ALL Bit 4 = 1
l
VOUT_COMMAND = 5.500V (Note 9)
l
l
VOUT_COMMAND = 2.75V (Note 9)
TYP
4.5
MAX
24
30
20
3.7
3.95
80
35
l
l
6V < VIN < 24V
∆VITH = 1.35V – 0.7V
∆VITH = 1.35V – 2.0V
ITH =1.22V
VISENSE = 5.5V
0V ≤ VPIN ≤ 5.5V
l
Hi Range
Lo Range
Hi Range
Lo Range
l
l
5.422
–0.5
2.711
–0.5
l
l
l
68
44
12
1.375
12
0.6875
0.01
–0.01
3
±1
47
3
75
50
37.5
25
UNITS
V
mA
mA
V
V
ms
ms
5.576
0.5
2.788
0.5
±0.02
0.1
–0.1
±2
82
56
V
%
Bits
mV
V
%
Bits
mV
%/V
%
%
mmho
µA
kΩ
bits
mV
mV
mV
mV
Rev. F
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5
LTC3883/LTC3883-1
The
l denotes the specifications which apply over the specified operating
ELECTRICAL
CHARACTERISTICS
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL
PARAMETER
Gate Driver
TG
TG Transition Time:
tr
Rise Time
Fall Time
tf
BG
BG Transition Time:
tr
Rise Time
Fall Time
tf
TG/BG t1D
Top Gate Off to Bottom Gate On Delay Time
BG/TG t2D
Bottom Gate Off to Top Gate On Delay Time
tON(MIN)
Minimum On-Time
OV/UV Output Voltage Supervisor
N
Resolution
VRANGE0
Voltage Range
VRANGE1
Voltage Range
VOUSTP0
Step Size
VOUSTP1
Step Size
VTHACC0
Threshold Accuracy 2V < VOUT < 5V
VTHACC1
Threshold Accuracy 0.9V < VOUT < 2.5V
tPROPOV1
OV Comparator to GPIO Low Time
tPROPUV1
UV Comparator to GPIO Low Time
VIN Voltage Supervisor
N
Resolution
VINRANGE
Full-Scale Voltage
VINSTP
Step Size
VINTHACC
Threshold Accuracy 8.75V < VIN < 20V
tPROPVIN
Comparator Response Time
(VIN_ON and VIN_OFF)
Output Voltage Readback
N
Resolution
LSB Step Size
VF/S
Full-Scale Sense Voltage
VOUT_TUE
Total Unadjusted Error
VOS
Zero-Code Offset Voltage
tCONVERT
Conversion Time
VIN Voltage Readback
N
Resolution
VF/S
Full-Scale Input Voltage
VIN_TUE
Total Unadjusted Error
CONDITIONS
MIN
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
(Note 4)
CLOAD = 3300pF
CLOAD = 3300pF
(Note 4) CLOAD = 3300pF
(Note 4) CLOAD = 3300pF
TYP
ns
ns
20
20
10
30
45
ns
ns
ns
ns
ns
8
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
Range Value = 0
Range Value = 1
VOD = 10% of Threshold
VOD = 10% of Threshold
1
0.4
5.5
2.7
22
11
±2
±2
35
35
l
l
8
4.5
20
82
±2.5
100
l
VOD = 10% of Threshold
(Note 10) VRUN = 0V (Note 8)
TJ = 25°C, VOUT > 0.6V
(Note 8)
16
244
8
0.2
l
l
(Note 6)
10
38.91
IF/S
IOUT_TUE
Full-Scale Input Current
Total Unadjusted Error
(Note 6)
(Note 5)
0V ≤ |VISENSE+ – VISENSE–| < 16mV
16mV ≤ |VISENSE+ – VISENSE–| < 32mV
32mV ≤ |VISENSE+ – VISENSE–| < 63.9mV
63.9mV ≤ |VISENSE+ – VISENSE–| < 127.9mV
(Note 7) RISENSE = 1mΩ
(Note 8) VISENSE > 6mV
0.5
±500
80
(Note 5)
(Note 11)
TJ = 25°C, VVIN > 4.5V
0.4
2
80
10
15.25
31.25
62.5
125
±128
l
UNITS
30
30
l
tCONVERT
Conversion Time
Output Current Readback
N
Resolution
LSB Step Size
MAX
±1
bits
V
V
mV
mV
%
%
µs
µs
bits
V
mV
%
µs
Bits
µV
V
%
%
µV
ms
Bits
V
%
%
ms
Bits
µV
µV
µV
µV
A
%
Rev. F
6
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LTC3883/LTC3883-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL
PARAMETER
VOS
Zero-Code Offset Voltage
tCONVERT
Conversion Time
Input Current Readback
N
Resolution
LSB Step Size
IIN_TUE
CONDITIONS
(Note 6)
(Note 5)
8x Gain, 0V ≤ |VIN_SNS – IIN_SNS| ≤ 8mV
4x Gain, 0V ≤ |VIN_SNS – IIN_SNS| ≤ 20mV
2x Gain, 0V ≤ |VIN_SNS – IIN_SNS| ≤ 50mV
8x Gain, VISENSE > 2.5mV (Note 8)
4x Gain, VISENSE > 4mV (Note 8)
2x Gain, VISENSE > 6mV (Note 8)
Total Unadjusted Error
VOS
Zero-Code Offset Voltage
tCONVERT
Conversion Time
Supply Current Readback
N
Resolution
LSB Step Size
ICHIP_TUE
Total Unadjusted Error (LTC3883 Only)
Total Unadjusted Error (LTC3883-1 Only)
tCONVERT
Conversion Time
Duty Cycle Readback
D_RES
Resolution
D_TUE
Total Unadjusted Error
tCONVERT
Conversion Time
Temperature Readback (T0, T1)
TRES_T
Resolution
T0_TUE
External TSNS TUE
TI_TUE
Internal TSNS TUE
tCONVERT_T
Update Rate
INTVCC Regulator
VINTVCC
Internal VCC Voltage No Load (LTC3883 Only)
VLDO_INT
INTVCC Load Regulation (LTC3883 Only)
VDD33 Regulator
VDD33
Internal VDD33 Voltage
ILIM
VDD33 Current Limit
VDD33_OV
VDD33 Overvoltage Threshold
VDD33_UV
VDD33 Undervoltage Threshold
VDD25 Regulator
VDD25
Internal VDD25 Voltage
ILIM
VDD25 Current Limit
Oscillator and Phase-Locked Loop
fOSC
Oscillator Frequency Accuracy
VTH,SYNC
SYNC Input Threshold
VOL,SYNC
ILEAKSYNC
SYNC Low Output Voltage
SYNC Leakage Current in Slave Mode
MIN
TYP
MAX
±28
80
10
15.26
30.52
61
±2.0
±1.5
±1.2
l
l
l
±50
160
(Note 6)
(Note 5)
10
122
±5
±200
l
l
(Note 6)
160
(Note 5)
16.3% Duty Cycle
(Note 6)
10
–3
3
80
0.25
∆VTSNS = 72mV (Note 8)
VRUN = 0.0V, fSYNC = 0kHz (Note 8)
(Note 6)
±3
l
±1
80
UNITS
µV
ms
Bits
µV
µV
µV
%
%
%
µV
ms
Bits
µV
%
µA
ms
Bits
%
ms
°C
°C
°C
ms
6V < VIN < 24V
ICC = 0mA to 50mA
4.8
5
0.5
5.2
±2
V
%
4.5V < VINTVCC/VEXTVCC
VDD33 = GND, VIN = INTVCC = 4.5V
3.2
3.3
100
3.5
3.1
3.4
V
mA
V
V
2.25
2.5
80
2.75
V
mA
±7.5
%
0.4
±5
V
V
V
µA
VDD25 = GND, VIN = INTVCC = 4.5V
250kHz < fSYNC < 1MHz Measured Falling
Edge-to-Falling Edge of SYNC with
SWITCH_FREQUENCY = 250.0.and 1000.0
VCLKIN Falling
VCLKIN Rising
ILOAD = 3mA
0V ≤ VPIN ≤ 3.6V
l
l
1
1.5
0.2
Rev. F
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7
LTC3883/LTC3883-1
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL
SYNC-
PARAMETER
SYNC to Channel Phase Relationship Based
on the Falling Edge of Sync and Rising Edge
of TG
EEPROM Characteristics
Endurance
(Note 13)
Retention
Mass_Write
(Note 13)
Mass Write Operation Time
CONDITIONS
MFR_PWM_CONFIG_LTC3883[2:0] = 0
MFR_PWM_CONFIG_LTC3883[2:0] = 1
MFR_PWM_CONFIG_LTC3883[2:0] = 2
MFR_PWM_CONFIG_LTC3883[2:0] = 3
MFR_PWM_CONFIG_LTC3883[2:0] = 4
MFR_PWM_CONFIG_LTC3883[2:0] = 5
MFR_PWM_CONFIG_LTC3883[2:0] = 6
MFR_PWM_CONFIG_LTC3883[2:0] = 7
0°C < TJ < 85°C During EEPROM Write
Operations
TJ < 125°C
STORE_USER_ALL, 0°C < TJ ≤ 85°C
During EEPROM Write Operations
Digital Inputs SCL, SDA, RUN, GPIO
VIH
Input High Threshold Voltage
SCL, SDA, RUN, GPIO
VIL
Input Low Threshold Voltage
SCL, SDA, RUN, GPIO
VHYST
Input Hysteresis
SCL, SDA
CPIN
Input Capacitance
Digital Input WP
IPUWP
Input Pull-Up Current
WP
Open-Drain Outputs SCL, SDA, GPIO, ALERT, RUN, SHARE_CLK, PGOOD
VOL
Output Low Voltage
ISINK = 3mA
Digital Inputs SHARE_CLK, WP
VIH
Input High Threshold Voltage
VIL
Input Low Threshold Voltage
Leakage Current SDA, SCL, ALERT, RUN
IOL
Input Leakage Current
0V ≤ VPIN ≤ 5.5V
Leakage Current GPIO, PGOOD
IGL
Input Leakage Current
0V ≤ VPIN ≤ 3.6V
Digital Filtering of GPIO
IFLTG
Input Digital Filtering GPIO
Digital Filtering of RUN
IFLTG
Input Digital Filtering RUN
PMBus Interface Timing Characteristics
fSCL
Serial Bus Operating Frequency
tBUF
Bus Free Time Between Stop and Start
tHD,STA
Hold time After Repeated Start Condition.
After this Period, the First Clock is Generated
tSU,STA
Repeated Start Condition Setup Time
tSU,STO
Stop Condition Setup Time
tHD,DAT
Data Hold Time
Receiving Data
Transmitting Data
MIN
l
10,000
l
10
TYP
0
90
180
270
60
120
240
300
4100
1.35
l
l
UNITS
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Deg
Cycles
440
l
MAX
0.8
0.08
10
10
Years
ms
V
V
V
pF
µA
0.4
V
1.8
V
V
l
±5
µA
l
±2
µA
l
l
l
l
l
l
0.6
10
1.3
0.6
l
0.6
0.6
l
l
0
0.3
l
1.5
1.0
3
µs
10
µs
400
kHz
µs
µs
µs
µs
0.9
µs
µs
Rev. F
8
For more information www.analog.com
LTC3883/LTC3883-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL
tSU,DAT
PARAMETER
Data Setup Time
Receiving Data
tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
tLOW
Serial Clock Low Period
tHIGH
Serial Clock High Period
CONDITIONS
MIN
l
MAX
0.1
Measured from the Last PMBus Start Event
32
150
l
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3883/LTC3883-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LTC3883E/LTC3883E-1 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 105°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3883I/LTC3883I-1 are guaranteed over the full –40°C to 125°C operating
junction temperature range. TJ is calculated from the ambient temperature,
TA, and power dissipation, PD, according to the following formula:
TJ = TA + (PD • θJA)
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
TYP
1.3
0.6
10000
UNITS
µs
ms
ms
µs
µs
Note 6: The data conversion is done in round robin fashion. All inputs
signals are continuously converted for a typical latency of 80ms.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as
read from READ_IOUT in amperes.
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 •
[Zero Code Offset + ADC Linearity Error]/Actual Value.
Note 9: All VOUT commands assume the ADC is used to auto-zero the
output to achieve the stated accuracy. LTC3883 is tested in a feedback
loop that servos VOUT to a specified value.
Note 10: The maximum VOUT voltage is 5.5V.
Note 11: The maximum VIN voltage is 28V.
Note 12: When VIN < 6V, INTVCC must be tied to VIN.
Note 13: EEPROM endurance is guaranteed by design, characterization
and correlation with statistical process controls. Data retention is
production tested via a high temperature bake at wafer level. The minimum
retention specification applies for devices whose EEPROM has been cycled
less than the minimum endurance specification. The RESTORE_USER_ALL
command (NVM read) is valid over the entire operating temperature range.
Note 14: The LTC3883-1 quiescent current (IQ) equals the IQ of VIN plus
the IQ of EXTVCC.
Note 15: The LTC3883 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Rev. F
For more information www.analog.com
9
LTC3883/LTC3883-1
TYPICAL PERFORMANCE CHARACTERISTICS
80
80
70
70
60
VIN = 12V
VOUT = 1.8V
fSW = 350kHz
L = 0.56µH
DCR = 1.8mΩ
CCM
DCM
BM
40
30
20
10
0
0.01
0.1
1
10
LOAD CURRENT (A)
EFFICIENCY (%)
90
EFFICIENCY (%)
EFFICIENCY (%)
100
90
60
50
VIN = 12V
VOUT = 3.3V
fSW = 350kHz
L = 0.56µH
DCR = 1.8mΩ
CCM
DCM
BM
40
30
20
10
0
0.01
100
0.1
1
10
LOAD CURRENT (A)
3883 G01
92
4.0
90
3.5
88
3.0
86
2.5
84
2.0
82
1.5
80
100
5
10
Load Step
(Forced Continuous Mode)
ILOAD
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
VOUT
100mV/DIV
AC-COUPLED
VOUT
100mV/DIV
AC-COUPLED
VIN = 12V
50µs/DIV
VOUT = 1.8V
0.3A TO 5A STEP
Inductor Current at Light Load
Burst Mode
OPERATION
2A/DIV
PULSE-SKIPPING
MODE
2A/DIV
1µs/DIV
3883 G05
VIN = 12V
50µs/DIV
VOUT = 1.8V
0.3A TO 5A STEP
Start-Up into a Pre-Biased Load
FORCED
CONTINUOUS
MODE
2A/DIV
3883 G07
RUN
2V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
5ms/DIV
3883 G08
3883 G06
Soft-Start Ramp
RUN
2V/DIV
tRISE = 10ms
tDELAY = 5ms
VOUT = 2V
1.0
Load Step
(Pulse-Skipping Mode)
ILOAD
5A/DIV
3883 G04
25
3883 G03
ILOAD
5A/DIV
VIN = 12V
VOUT = 1.8V
ILOAD = 100µA
20
3883 G02
Load Step
(Burst Mode Operation)
VIN = 12V
50µs/DIV
VOUT = 1.8V
0.3A TO 5A STEP
15
VIN (V)
POWER LOSS (W)
100
50
Efficiency and Power Loss
vs Input Voltage (LTC3883)
Efficiency vs Load Current,
VOUT = 3.3V (LTC3883)
Efficiency vs Load Current,
VOUT = 1.8V (LTC3883)
tRISE = 10ms
tDELAY = 5ms
5ms/DIV
3883 G09
Rev. F
10
For more information www.analog.com
LTC3883/LTC3883-1
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
1V/DIV
tFALL = 5ms
tDELAY = 10ms
5ms/DIV
3883 G10
CURRENT LIMIT (A) WITH 1mΩ SENSE RESISTOR
RUN
2V/DIV
60
50
40
30
20
10
0
–10
–20
VSENSE 50mV
VSENSE 25mV
0
0.5
1
1.5
VITH (V)
2
MAXIMUM CURRENT SENSE THRESHOLD (mV)
Current Sense Threshold
vs ITH Voltage (Low Range)
Soft-Off Ramp
2.5
55
Maximum Current Sense Threshold
vs Duty Cycle, VOUT = 0V
50mV SENSE CONDITION
54
53
52
51
50
49
48
47
46
45
30
0
70
50
DUTY CYCLE (%)
90
3883 G12
3883 G11
51.5
Regulated Output
vs Temperature
110
0.5020
SHARE_CLK FREQUENCY (kHz)
0.5015
0.5010
51.0
50.5
0.5005
0.5000
0.4995
0.4990
0.4985
105
100
95
0.4980
50.0
0
1
3
4
2
COMMON MODE VOLTAGE (V)
5
0.4975
–50 –25
0
90
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3883 G14
3883 G13
SHARE-CLK Frequency vs VIN
3883 G15
Quiescent Current vs Temperature
VOUT Measurement Error vs VOUT
0.40
25
101.0
100.5
100.0
99.5
MEASSURED ERROR (mV)
0.30
QUIESCENT CURRENT (mA)
SHARE_CLOCK FREQUENCY (kHz)
SHARE_CLK Frequency
vs Temperature
0.5025
50mV SENSE CONDITION
VOUT (V)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
Maximum Current Sense Threshold
vs Common Mode Voltage
20
15
0.20
0.10
0
–0.10
–0.20
–0.30
99.0
6
8 10 12 14 16 18 20 22 24 26 28
VIN (V)
3883 G16
10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3883 G17
–0.40
0.5
1
1.5
2
2.5 3 3.5
VOUT (V)
4
4.5
5
5.5
3883 G18
Rev. F
For more information www.analog.com
11
LTC3883/LTC3883-1
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Command DNL
INTVCC Line Regulation
0.3
5.25
1.5
0.2
5.00
1.0
0.1
0.5
0
0
–0.1
–0.5
–0.2
–1.0
0.5 1 1.5
2 2.5 3 3.5
VOUT (V)
4 4.5
5
–0.3
5.5
4.75
INTVCC (V)
DNL (LSBs)
INL (LSBs)
VOUT Command INL
2.0
3.75
0.5 1 1.5
2 2.5 3 3.5
VOUT (V)
4 4.5
5
3.50
5.5
4.03
4V OV THRESHOLD (V)
2V OV THRESHOLD (V)
1V OV THRESHOLD (V)
2.01
2.00
1.99
0
3.98
MEASUREMENT ERROR (mA)
0.4
0.2
0
–0.2
–0.4
–0.6
100
125
25 50 75 100 125 150
TEMPERATURE (°C)
IIN Error vs IIN Room Temperature
8
5
6
4
4
2
0
–2
–4
–6
–0.8
0
3883 G24
MEASUREMENT ERROR (mA)
0.8
MEASUREMENT ERROR (°C)
3.99
IOUT Error vs IOUT Room
Temperature
1.0
25
0
75
50
TEMPERATURE (°C)
4.00
3883 G23
External Temperature Error
vs Temperature
–25
4.01
3.96
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3883 G22
–1.0
–50
4.02
3.97
1.97
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
–8
25
4.04
1.98
0.6
20
VOUT OV Threshold
vs Temperature (4V Target)
2.02
0.995
15
3883 G21
2.03
1.010
1.000
10
VIN (V)
VOUT OV Threshold
vs Temperature (2V Target)
1.005
5
3883 G20
VOUT OV Threshold
vs Temperature (1V Target)
0
4.25
4.00
3883 G19
0.990
–50 –25
4.50
3
2
1
0
–1
–2
0
10
5
15
OUTPUT CURRENT (A)
20
0
1
2
3
INPUT CURRENT (A)
3883 G26
3883 G25
–3
3883 G27
Rev. F
12
For more information www.analog.com
LTC3883/LTC3883-1
TYPICAL PERFORMANCE CHARACTERISTICS
DC Output Current Matching in a
2-Phase System (LTC3883)
Dynamic Current Sharing During a
Load Transient in a 2-Phase System
Dynamic Current Sharing During a
Load Transient in a 2-Phase System
25
CHANNEL CURRENT (A)
20
CURRENT
5A/DIV
15
10
VIN = 12V
VOUT = 1.8V
fSW = 500kHz
L = 0.4µH
15A TO 5A LOAD STEP
5µs/DIV
3883 G29
CURRENT
5A/DIV
VIN = 12V
VOUT = 1.8V
fSW = 500kHz
L = 0.4µH
5A TO 15A LOAD STEP
5µs/DIV
3883 G30
5
0
CHAN 0
CHAN 1
0
5
25 30
10 15 20
TOTAL CURRENT (A)
35
40
3883 G28
Rev. F
For more information www.analog.com
13
LTC3883/LTC3883-1
PIN FUNCTIONS
VIN_SNS (Pin 1): Input Current Sense Comparator Input.
The (–) input to the input current comparator is normally
connected to the supply side of the input current sense
resistor through a 100Ω resistor. If the input current
sense amplifier is not used, this pin must be shorted to
the IIN_SNS and VIN pins.
IIN_SNS (Pin 2): Input Current Sense Comparator Input.
The (+) input to the input current comparator is normally
connected to the power stage side of the input current
sense resistor through a 100Ω resistor. If the input current
sense amplifier is not used, this pin must be shorted to
the VIN_SNS and VIN pins.
ISENSE+ (Pin 3): Current Sense Comparator Input. The (+)
input to the current comparator is normally connected
to the DCR sensing network or current sensing resistor.
ISENSE– (Pin 4): Current Sense Comparator Input. The (–)
input is connected to the output.
SYNC (Pin 5): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse width to ground. A resistor pull-up to 3.3V is required
in the application.
SCL (Pin 6): Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
SDA (Pin 7): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
ALERT (Pin 8): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin.
GPIO (Pin 9): Digital Programmable General Purpose
Inputs and Outputs. Open-drain output.
PGOOD (Pin 10): Digital Power Good Indicator. Open-drain
output. The PGOOD pin is based on comparator outputs
and may be used for sequencing.
RUN (Pin 11): Enable Run Input. Logic high on this pin
enables the controller. This pin requires a resistor pullup to 3.3V in the application and should be driven by an
open-drain digital output.
DNC (Pins 12, 16): Do Not Connect to This Pin.
ASEL (Pin 13): Serial Bus Address Configuration Input.
Connect a ±1% resistor divider between the chip VDD25
ASEL and GND in order to select the 4LSBs of the serial bus
interface address. A resistor divider on ASEL is required
if there are more than one LTC3883 on the same board
to assure the user can independently program each IC. If
the pin is left open, the IC will use the value programmed
in the NVM. Minimize capacitance when the pin is open
to assure accurate detection of the pin state.
FREQ_CFG (Pin 14): Frequency or Phase Set/Select Pin.
Connect a ±1% resistor divider between the chip VDD25
FREQ_CFG and GND in order to select switching frequency
or phase. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
VOUT_CFG (Pin 15): Output Voltage Select Pin. Connect a
±1% resistor divider between the chip VDD25, VOUT_CFG
and SGND in order to select output voltage. This voltage
can be adjusted with the VTRIM_CFG pins. If the pin is left
open, the IC will use the value programmed in the NVM.
Minimize capacitance when the pin is open to assure accurate detection of the pin state.
VTRIM_CFG (Pin 17): Voltage Trim Select Pin. Connect a
±1% resistor divider between the chip VDD25, VTRIM_CFG
and SGND in order to adjust the output voltage set point.
The VTRIM_CFG settings in conjunction with the VOUT_CFG
setting adjusts the voltage set point. If the pin is left open,
the IC will either not modify the VOUT_CFG setting or use
NVM. Minimize capacitance when the pin is open to assure
accurate detection of the pin state.
VDD25 (Pin 18): Internally Generated 2.5V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capacitor. Do not load this pin with external current.
WP (Pin 19): Write Protect Pin Active High. An internal
10µA current source pulls the pin to VDD33. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 20): Share Clock, Bidirectional OpenDrain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple LTC3883s. Tie all the
SHARE_CLK pins together. All LTC3883s will synchronize
to the fastest clock. An equivalent pull-up resistance of
5.49k to VDD33 is required.
Rev. F
14
For more information www.analog.com
LTC3883/LTC3883-1
PIN FUNCTIONS
VDD33 (Pin 21): Internally Generated 3.3V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capacitor. Do not load this pin with external current.
SW (Pin 22): Switch Node Connection to the Inductor.
Voltage swings at the pins are from a Schottky diode
(external) voltage drop below ground to VIN.
EXTVCC (Pin 27, LTC3883-1): External Regulator 5V
input. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor.
TG (Pin 23): Top Gate Driver Output. This is the output of
the floating driver with a voltage swing equal to INTVCC
superimposed on the switch node voltage.
VIN (Pin 28): Main Input Supply. Decouple this pin to PGND
with a capacitor (0.1µF to 1µF). For applications where
the main input power is 5V, tie the VIN and INTVCC pins
together. If the input current sense amplifier is not used,
this pin must be shorted to the VIN_SNS and IIN_SNS pins.
BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor connects to this pin.
This pin swings from a diode voltage drop below INTVCC
up to VIN + INTVCC.
VSENSE+ (Pin 30): Positive Voltage Sense Input.
PGND (Pin 25): Power Ground Pin. Connect this pin closely
to the source of the bottom N-channel MOSFET, the (–)
terminal of CINTVCC and the (–) terminal of CIN.
BG (Pin 26): Bottom Gate Driver Output. This pin drives
the gates of the bottom N-channel MOSFET between
PGND and INTVCC.
INTVCC (Pin 27, LTC3883): Internal Regulator 5V Output. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7μF low
ESR tantalum or ceramic capacitor.
ITH (Pin 29): Current Control Threshold and Error Amplifier Compensation Node. The current comparator tripping
threshold increases with the ITH voltage.
VSENSE– (Pin 31): Negative Voltage Sense Input.
TSNS (Pin 32): External Diode Temperature Sense. Connect to the anode of a diode-connected PNP transistor and
star connect the cathode to GND in order to sense remote
temperature. If an external temperature sense element is not
installed, short pin to ground and set the UT_FAULT_LIMIT
to –275°C, set the UT_FAULT_RESPONSE to ignore, and
set IOUT_CAL_GAIN_TC to 0.
GND (Exposed Pad Pin 33): Ground. All small-signal and
compensation components should connect to this ground,
which in turn connects to PGND at one point.
Rev. F
For more information www.analog.com
15
LTC3883/LTC3883-1
BLOCK DIAGRAM
RIINSNS
VIN
+
RVIN
VIN
CIN
1Ω
28
CVIN
IIN_SNS
VIN_SNS
1
2
5V REG
LTC3883
ONLY
INTVCC/EXTVCC (LTC3883-1)
INTVCC /EXTVCC
27
+ –
VDD33
3.3V
SUBREG
IIN
19.5R
R
S
R Q
PWM_CLOCK
ICMP
38R
R
–
+
3k
+
–
VDD33
21
BOOST
DB
24
IREV
TG
23
FCNT
SWITCH
LOGIC
AND
ANTISHOOTTHROUGH
UV
UVLO
SS
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.5
M1
SW
22
ON
REV
CB
ISENSE+
3
ISENSE–
+
4
RUN
BG
OV
VOUT
COUT
M2
26
CINTVCC
25
SLOPE
COMPENSATION
VSTBY
1.22V
INTVCC
REF
GND
ITH
UVLO
ACTIVE
CLAMP
1
71.1k
16-BIT
ADC
ILIM DAC
(3 BITS)
29
2µA
RC
CC1
+ –
33
GND
+
–
BURST
+ –
+
EA
+ –
30µA
+
–
–
+
+
–
+
8:1 –
+
MUX –
+
–
+
–
+
–
PGND
R
R
–
AO
+
R
R
PWM0
PWM1
+ –
VSENSE+
30
TSNS
OV
UV
31
VSENSE–
TMUX
+ –
32
9R
0.56V
GND
2R
GND
8-BIT
VIN_ON
THRESHOLD DAC
12-BIT
SET POINT
DAC
8-BIT
OV
DAC
8-BIT
UV
DAC
M2
VCO
PHASE SELECTOR
VDD33
SHARE_CLK 20
WP 19
SCL 6
SDA 7
PMBus
INTERFACE
(400kHz
COMPATIBLE)
RUN 11
MAIN
CONTROL
PGOOD 10
GPIO 9
CHANNEL
TIMING
MANAGEMENT
GND
VDD33
VDD25
2.5V
SUBREG
SLAVE
MISO
CLK MOSI
MASTER
SINC3
UVLO
18 VDD25
OSC
(32MHz)
15 VOUT_CFG
CONFIG
DETECT
SYNC
PROGRAM
ROM
RAM
EEPROM
17 VTRIM_CFG
14 FREQ_CFG
13 ASEL
3883 F01
Figure 1. Block Diagram
16
PWM
CLOCK
CLOCK DIVIDER
VDD33
COMPARE
ALERT 8
5 SYNC
PHASE DET
For more information www.analog.com
Rev. F
LTC3883/LTC3883-1
OPERATION
OVERVIEW
Average PWM Duty Cycle
n
The LTC3883 is a constant frequency, analog current mode
controller for DC/DC step-down applications with a digital
interface. The LTC3883 digital interface is compatible with
PMBus which supports bus speeds of up to 400kHz. A
typical application circuit is shown on the first page of this
data sheet. Major features include:
Programmable Output Voltage
n
Average Output Voltage
n
Average Input Voltage
n
Average Input Current
n
Configurable, Latched and Unlatched Individual Fault
and Warning Status
n
Fault reporting and shutdown behavior are fully configurable using the GPIO output (GPIO). A dedicated pin for
ALERT is provided. The shutdown operation also allows
all faults to be individually masked and can be operated
in either unlatched (hiccup) or latched modes.
Programmable Input Voltage Comparator
n
Programmable Current Limit
n
Programmable Switching Frequency
n
Programmable OV and UV Comparators
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
n
Programmable On and Off Delay Times
n
Programmable Output Rise/Fall Times
n
Output Undervoltage/Overvoltage
Phase-Locked Loop for Synchronous, Polyphase Operation (2, 3, 4 or 6 Phases)
n
Input and Output Voltage/Current, Temperature and
Duty Cycle Telemetry
n
n
n
Input Undervoltage/Overvoltage
n
Input and Output Overcurrent
Internal Overtemperature
n
Fully Differential Load Sense
n
Integrated Gate Drivers
n
External Overtemperature
n
Communication, Memory or Logic (CML) Fault
n
Non-Volatile Configuration Memory with ECC
n
Optional External Configuration Resistors for Key
Operating Parameters
n
Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
n
Fault Logging
n
WP Pin to Protect Internal Configuration
n
Standalone Operation After User Factory Configuration
n
PMBus, 400kHz Compliant Interface
n
The PMBus interface provides access to important power
management data during system operation including:
Internal Controller Temperature
n
External System Temperature via Optional Diode Sense
Elements
n
Average Output Current
n
MAIN CONTROL LOOP
The LTC3883 is a constant frequency, current mode stepdown controller that operates at a user-defined relative
phasing. During normal operation the top MOSFET is
turned on when the clock for that channel sets the RS latch,
and turned off when the main current comparator, ICMP ,
resets the RS latch. The peak inductor current at which
ICMP resets the RS latch is controlled by the voltage on the
ITH pin which is the output of the error amplifier, EA. The
EA negative terminal is equal to the VSENSE voltage divided
by 5.5 (2.75 if range = 1). The positive terminal of the EA is
connected to the output of a 12-bit DAC with values ranging
from 0V to 1.024V. The output voltage, through feedback
of the EA, will be regulated to 5.5 times the DAC output
(2.75 times if range = 1). The DAC value is calculated by
the part to synthesize the users desired output voltage.
The output voltage is programmed by the user either
Rev. F
For more information www.analog.com
17
LTC3883/LTC3883-1
OPERATION
with the resistor configuration pins detailed in Tables 12
and 13 or by the VOUT command (either from NVM or
by PMBus command). Refer to the PMBus command
section of the data sheet or the PMBus specification for
more details. The output voltage can be modified by the
user at any time with a PMBus VOUT_COMMAND. This
command will typically have a latency less than 10ms.
The user is encouraged to reference the PMBus Power
System Management Protocol Specification to understand
how to program the LTC3883. This specification can be
found at http://www.pmbus.org/specs.html.
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable when the die temperature exceeds the internal overtemperature fault limit.)
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimensionless acceleration factor using the following equation:
AF = e
⎡⎛ Ea ⎞ ⎛
⎞⎤
1
1
–
⎢⎜ ⎟•⎜
⎟⎥
⎣⎝ k ⎠ ⎝ TUSE +273 TSTRESS +273 ⎠⎦
where:
Continuing the basic operation description, the current
mode controller will turn off the top gate when the peak
current is reached. If the load current increases, VSENSE
will slightly droop with respect to the DAC reference.
This causes the ITH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on. In continuous conduction mode, the bottom MOSFET
stays on until the end of the switching cycle.
AF = acceleration factor
Ea = activation energy = 1.4eV
K = 8.617 • 10–5 eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
EEPROM
TSTRESS = 130°C
The LTC3883 contains internal EEPROM, also referred
to as NVM (nonvolatile memory) , with Error Correction
Coding (ECC) to store configuration settings and fault log
information. EEPROM endurance retention and mass write
operation time are specified in the Electrical Characteristics
and Absolute Maximum Ratings sections. Write operations above TJ = 85°C or below 0°C are possible although
the Electrical Characteristics are not guaranteed and the
EEPROM will be degraded. Read operations performed at
temperatures between 85°C and 125°C will not degrade
the EEPROM. Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics. The
fault logging function, which is useful in debugging system
problems that may occur at high temperatures, only writes
to fault log EEPROM locations. If occasional writes to these
registers occur above 85°C, the slight degradation in the
data retention characteristics of the fault log will not take
away from the usefulness of the function.
TUSE = 125°C
It is recommended that the EEPROM not be written
when the die temperature is greater than 85°C. If the die
temperature exceeds 130°C, the LTC3883 will disable all
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
AF= e[(1.4/8.617 • 10
–5)
• (1/398 – 1/403)] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
POWER UP AND INITIALIZATION
The LTC3883 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 24V)
while three on-chip linear regulators generate internal
2.5V, 3.3V and 5V. If VIN is below 6V, the INTVCC and VIN
pins must be tied together. The controller configuration
is initialized by an internal threshold based UVLO where
VIN must be approximately 4V and the 5V, 3.3V and 2.5V
linear regulators must be within approximately 20% of
Rev. F
18
For more information www.analog.com
LTC3883/LTC3883-1
OPERATION
the regulated values. The LTC3883-1 does not have an
internal 5V linear regulator. The EXTVCC pin is driven by
an external regulator to improve efficiency of the circuit
and minimize power on the LTC3883. The EXTVCC pin
must exceed approximately 4V before the internal UVLO
is exceeded. To minimize application power, the EXTVCC
pin can be supplied by a switching regulator.
During initialization, the external configuration resistors
are identified and/or contents of the NVM are read into
the controller’s commands. The BG, TG and RUN pins
are held low. The GPIO pin is in high impedance mode.
The LTC3883 will use the contents of Tables 12 to 15 to
determine the resistor defined parameters. See the Resistor Configuration section for more detail. The resistor
configuration pins only control some of the preset values
of the controller. The remaining values are programmed
in NVM either at the factory or by the user.
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_
ALL_LTC3883 configuration command), the LTC3883 will
use only the contents of NVM to determine the DC/DC
characteristics. The ASEL value read at power-up or reset
is always respected unless the pin is open. The ASEL will
use the MSB from NVM and the LSB from the detected
threshold. See the Applications Information section for
more detail.
After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before
the output power sequencing can begin. After VIN is initially
applied, the part will typically require 80ms to initialize and
begin the TON_DELAY timer if MFR_CONFIG_ALL bit 4
is set to a 0. The time is reduced to approximately 35ms
if MFR_CONFIG_ALL bit 4 is set to a 1. The readback of
voltages and currents may require an additional 80ms.
SOFT-START
The part must enter the run state prior to soft-start. The
run pin is released by the LTC3883 after the part initializes
and VIN is greater than the VIN_ON threshold. If multiple
LTC3883s are used in an application, they all hold their
respective run pins low until all devices initialize and
VIN exceeds the VIN_ON threshold for every device. The
SHARE_CLK pin assures all the devices connected to the
signal use the same time base. The SHARE_CLK pin is held
low until the part has initialized after VIN is applied. The
LTC3883 can be set to turn off (or remain off) if SHARE_CLK
is low (set bit 2 of MFR_CHAN_CONFIG_LTC3883 to a
1). This allows the user to assure synchronization across
numerous ADI ICs even if the RUN pins can not be connected together due to board constraints. In general, if
the user cares about synchronization between chips it is
best to connect all the respective RUN pins together and
to connect all the respective SHARE_CLK pins together
and pull up to VDD33 with a 10k resistor. This assures all
chips begin sequencing at the same time and use the
same time base.
After the RUN pin releases and prior to entering a constant
output voltage regulation state, the LTC3883 performs a
monotonic initial ramp or “soft-start”. Soft-start is performed by actively regulating the load voltage while digitally
ramping the target voltage from 0V to the commanded
voltage set-point. Once the LTC3883 is commanded to turn
on, (after power up and initialization) the controller waits
for the user specified turn-on delay (TON_DELAY) prior
to initiating this output voltage ramp. The rise time of the
voltage ramp can be programmed using the TON_RISE
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting the value of TON_RISE to any value less than
0.25ms. The LTC3883 PWM always uses discontinuous
mode during the TON_RISE operation. In discontinuous
mode, the bottom gate is turned off as soon as reverse
current is detected in the inductor. This will allow the
regulator to start up into a pre-biased load. When the
TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode or burst, if so programmed. If
TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
mode after TON_RISE completes and VOUT has exceeded
the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. Setting TON_MAX_FAULT_LIMIT to a value of 0 is
not recommended. This described method of start-up
sequencing is time based.
SEQUENCING
The default mode for sequencing the output on and off is
time based. The output is enabled after waiting TON_DELAY
Rev. F
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19
LTC3883/LTC3883-1
OPERATION
amount of time following either the RUN pin going high, a
PMBus command to turn on, or the VIN pin voltage rising
above a preprogrammed voltage. Off sequencing is handled
in a similar way. To assure proper sequencing, make sure
all ICs connect the SHARE_CLK pins together and RUN pins
together. If the RUN pins can not be connected together for
some reason, set bit 2 of MFR_CHAN_CONFIG_LTC3883
to a 1. This bit requires the SHARE_CLK pin to be clocking
before the power supply output can start. When the RUN pin
is pulled low, the LTC3883 will hold the pin low for the MFR_
RESTART_DELAY. The minimum MFR_RESTART_DELAY
is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures
proper sequencing of all rails. The LTC3883 calculates
this delay internally and will not process a shorter delay.
However, a longer commanded MFR_RESTART_DELAY
will be used by the part. The maximum allowed value is
65.52 seconds.
VOLTAGE-BASED SEQUENCING
The GPIO pin can be asserted when the UV threshold is
exceeded. It is possible to feed the GPIO pin from one
LTC3883 into the RUN pin of the next LTC3883 in the
sequence. To use the GPIO pin for voltage based sequencing, set bit 12 of the MFR_GPIO_PROPAGATE_LTC3883
command = 1. Bit 12 is the VOUT_UVUF which is the
deglitched VOUT_UV comparator. Using the deglitched
VOUT_UV fault limit is recommended because there is
little appreciable time delay between the comparator
crossing the UV threshold and the GPIO pin releasing
This can be implemented across multiple LTC3883s.
The VOUT_UVUF has a 70µs minimum pulse width filter.
Voltage Based Sequencing by Cascading GPIOs into RUN Pins
START
RUN
LTC3883
GPIO = VOUT_UVUF
RUN
LTC3883
GPIO = VOUT_UVUF
3883 F02
TO NEXT CHANNEL
IN THE SEQUENCE
Figure 2. Event (Voltage) Based Sequencing
If the GPIO_FAULT_RESPONSE command is not set to
ignore, the part will latch off and never be able to start.
If the VOUT voltage bounces around the UV threshold for
a long period of time it is possible for the GPIO output
to toggle more than once. To minimize this problem, set
the TON_RISE time under 100ms. If a fault in the string
of rails is detected, only the faulted rail and downstream
rails will fault off. The rails in the string of devices in front
of the faulted rail will remain on unless commanded off.
SHUTDOWN
The LTC3883 supports two shutdown modes. The first
mode is closed-loop shutdown response, with userdefined turn-off delay (TOFF_DELAY) and ramp down
rate (TOFF_FALL). The controller will maintain the mode
of operation for TOFF_FALL. In discontinuous conduction
mode, the controller will not draw current from the load
and the fall time will be set by the output capacitance and
load current.
The other shutdown mode occurs in response to a fault
condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_
CONFIG_LTC3883 is set to a 1) or VIN falling below the
VIN_OFF threshold or GPIO pulled low externally (if the
MFR_GPIO_RESPONSE is set to inhibit). Under these
conditions the power stage is disabled in order to stop
the transfer of energy to the load as quickly as possible.
The shutdown state can be entered from the soft-start or
active regulation states either through user intervention
(deasserting RUN or the PMBus OPERATION command)
or in response to a detected fault or an external fault via
the bidirectional GPIO pin, or loss of SHARE_CLK (if bit
2 of MFR_CHAN_CONFIG_LTC3883 is set to a 1) or VIN
falling below the VIN_OFF threshold.
In hiccup mode, the controller responds to a fault by
shutting down and entering the inactive state for a
programmable delay time (MFR_RETRY_DELAY). This
delay minimizes the duty cycle associated with autonomous retries if the fault that caused the shutdown disappears once the output is disabled. The retry delay time
is determined by the longer of the MFR_RETRY_DELAY
command or the time required for the regulated output
to decay below 12.5% of the programmed value. If
multiple outputs are controlled by the same GPIO pin,
Rev. F
20
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LTC3883/LTC3883-1
OPERATION
the decay time of the faulted output determines the retry
delay. If the natural decay time of the output is too long,
it is possible to remove the voltage requirement of the
MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3883. Alternatively, the controller can be configured so that it remains latched-off following a fault and clearing requires user intervention such
as toggling RUN or commanding the part OFF then ON.
LIGHT LOAD CURRENT OPERATION
The LTC3883 has three modes of operation including high
efficiency Burst Mode operation, discontinuous conduction mode or forced continuous conduction mode. Mode
selection is done using the MFR_PWM_MODE_LTC3883
command (discontinuous conduction is always the startup mode, forced continuous is the default running mode).
conduction mode may result in reverse inductor current,
which can cause the input supply to boost. The VIN_OV_
FAULT_LIMIT can detect this and turn off the offending
channel. However, this fault is based on an ADC read and
can take up to 80ms to detect. If there is a concern about
the input supply boosting, keep the part in discontinuous
conduction or Burst Mode operation.
If the part is set to Burst Mode operation, as the inductor
average current increases, the controller will automatically modify the operation from Burst Mode operation,
to discontinuous mode to continuous mode.
SWITCHING FREQUENCY AND PHASE
In Burst Mode operation the peak current in the inductor
is set to approximately one-third of the maximum sense
voltage even though the voltage on the ITH pin indicates a
lower value. If the average inductor current is higher than
the load current, the error amplifier, EA, will decrease the
voltage on the ITH pin. When the ITH voltage drops below
approximately 0.5V, the internal Burst Mode operation asserts and both external MOSFETS are turned off. In Burst
Mode operation, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA output
begins to rise. When the output voltage drops sufficiently,
Burst Mode operation is deasserted, and the controller
resumes normal operation by turning on the top external
MOSFET on the next PWM cycle.
The switching frequency of the LTC3883’s controller can
be established with internal clock references or with an
external time-base. The LTC3883 can be configured for
an external clock input through the programmed value in
NVM, a PMBus command or setting the RBOTTOM resistor
of the FREQ_CFG pin to 0Ω and the RTOP to open. The
PMBus command FREQUENCY_SWITCH is set to external clock. The MFR_PWM_CONFIG_LTC3883 command
determines the relative phasing. The RCONFIG input can
set the relative phasing with respect to the falling edge of
SYNC. The master should be selected to be out of phase
with the slave. The RUN pin must be low before the
FREQUENCY and MFR_PWM_CONFIG_LTC3883 commands can be written to the LTC3883. The relative phasing of all devices in a PolyPhase rail should be optimally
phased. The relative phasing of each rail is 360/n where
n is the number of phases in the rail.
If a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse
current comparator, IREV , turns off the bottom gate external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller can operate in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined solely
by the voltage on the ITH pin. In this mode, the efficiency
at light loads is lower than in Burst Mode operation. However, continuous mode exhibits lower output ripple and
less interference with audio circuitry. Forced continuous
If the LTC3883 is configured as the oscillator output on
SYNC, the switching frequency source can be selected with
either external configuration resistors or through serial
bus programming. The FREQ_CFG configuration resistor
pin can be used to select the FREQUENCY_SWITCH
and MFR_PWM_CONFIG_LTC3883 values as outlined
in Table 14. Otherwise, the FREQUENCY_SWITCH and
MFR_PWM_CONFIG_LTC3883 PMBus commands can
be used to select PWM switching frequency and the PWM
channel phase relationship. The phase and frequency
relationships are completely independent of each other
providing the numerous application options for the user.
If the LTC3883 is configured to drive the SYNC pin using
Rev. F
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21
LTC3883/LTC3883-1
OPERATION
the programmed FREQUENCY_SWITCH command value,
the SYNC pin will pull low at the desired clock rate with
500ns low pulse. Care must be taken in the application to
assure the capacitance on SYNC is minimized to assure
the pull-up resistor versus the capacitor load has a low
enough time constant for the application. In addition,
a phase-locked loop (PLL) is available to synchronize
the internal oscillator to an external clock source that is
connected to the SYNC pin. All phase relationships are
between the falling edge of SYNC and the rising edge
of the LTC3883 TG output. Multiple LTC3883s can be
synchronized in order to realize PolyPhase arrays.
OUTPUT VOLTAGE SENSING
The differential amplifier allows remote, differential sensing of the load voltage with VSENSEn pins. The telemetry
ADC is fully differential and makes measurements of the
output voltage at the VSENSEn pins.
OUTPUT CURRENT SENSING
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the FET side of the
inductor while the capacitor is tied to the load side of the
inductor as shown in Figure 3. If the RC values are chosen such that the RC time constant matches the inductor
time constant (L/DCR, where DCR is the inductor series
resistance), the resultant voltage (VDCR) appearing across
the capacitor will equal the voltage across the inductor
series resistance and thus represent the current flowing
through the inductor. The RC calculations are based on
the room temperature DCR of the inductor.
The RC time constant should remain constant, as a function of temperature. This assures the transient response of
the circuit is the same regardless of the temperature. The
DCR of the inductor has a large temperature coefficient,
approximately 3900ppm/°C. The temperature coefficient
of the inductor must be written to the MFR_IOUT_CAL_
GAIN_TC command. The external temperature is sensed
near the inductor and is used to modify the internal current
limit circuit to maintain an essentially constant current
limit with temperature. In this application, the ISENSE+
pin is connected to the FET side of the capacitor while
22
the ISENSE– pin is placed on the load side of the capacitor.
The current sensed from the input is then given by the
expression VDCR/DCR. VDCR is digitized by the LTC3883’s
telemetry ADC with an input range of ±128mV, a noise
floor of 7µVRMS, and a peak-peak noise of approximately
46.5µV. The LTC3883 computes the inductor current
using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value is
returned by the READ_IOUT command.
AUTO CALIBRATION
Using a patent pending auto-calibration routine, the
LTC3883 can measure the actual DC resistance for DCR
current sense applications. The measured value is used
in READ_IOUT measurements and eliminates the need
for the user to know the actual resistance of the inductor.
Reference the subsection titled Inductor DCR Calibration
in the Applications Information section for further detail.
ACCURATE DCR TEMPERATURE COMPENSATION
The LTC3883 uses a patent pending algorithm to dynamically model the temperature rise from the external
temperature sensor to the inductor core. Refer to the
Accurate DCR Temperature Compensation subsection in
the Applications Information section for complete details.
INPUT CURRENT SENSING
To sense the total input current consumed by the LTC3883
and the power stage, a resistor is placed between the supply voltage and the drain of the top N-channel MOSFET.
The VIN_SNS and IIN_SNS pins are connected to the sense
resistor through 100Ω filter resistors. Both pins need to be
decoupled to GND. A filter capacitor needs to be connected
across the VIN_SNS and IIN_SNS pins. Refer to Figure 25,
Low Noise Input Current Sense Circuit for further details.
The filtered voltage is amplified by the internal high side
current sense amplifier and digitized by the LTC3883’s
telemetry ADC. The input current sense amplifier has
three gain settings of 2x, 4x, and 8x set by the bits 5:4 of
the MFR_PWM_MODE command. The maximum input
sense voltage for the three gain settings is 50mV, 20mV,
and 8mV respectively. The LTC3883 computes the input
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Rev. F
LTC3883/LTC3883-1
OPERATION
current using the R value stored in the IIN_CAL_GAIN
command. The resulting measured powerstage current
is returned by the READ_IIN command.
The MFR_READ_IIN_CHAN command returns the calculated powerstage current based on the READ_IOUT value
multiplied by the READ_DUTY_CYCLE value.
The LTC3883 uses an internal 1Ω sense resistor to measure the VIN pin supply current being consumed by the
LTC3883. This value is returned by the MFR_READ_ICHIP
command. Refer to the subsection titled Input Current
Sense Amplifier in the Applications Information section
for further detail.
LOAD SHARING
Multiple LTC3883’s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 3 illustrates the shared connections required
for load sharing.
The frequency must only be programmed on one of the
LTC3883s. The other(s) must be programmed to External
Clock.
EXTERNAL/INTERNAL TEMPERATURE SENSE
External temperature can be best measured using a remote
diode-connected PNP transistor such as the MMBT3906.
The emitter should be connected to the TSNS pin while the
base and collector terminals of the PNP transistor should
be returned to the LTC3883’s GND pin, preferably using
a star connection. It is possible to connect the collector
of the PNP to the source of the bottom MOSFET. This may
optimize board layout allowing the PNP closer proximity
to the power FETs. The base of the PNP must still be tied to
ground. For best noise immunity, the connections should be
routed differentially and a 10nF capacitor should be placed
LTC3883 + POWER STAGE
VIN
POWER STAGE
VSUPPLY
100Ω
ITH
100Ω
IIN_SNS
VIN_SNS
CONTROL
SMBALERT
FAULT
PWM CLOCK
SHARE CLOCK
100Ω
RUN
ALERT
GPIO
SYNC
SHARE_CLK
GND
ISENSE+
ISENSE–
VSENSE+
VSENSE–
PGND
LTC3883 + POWER STAGE
ITH
VIN
POWER STAGE
ISENSE+
ISENSE–
100Ω
NOTE: SOME CONNECTORS
AND COMPONENTS OMITTED
FOR CLARITY
IIN_SNS
VIN_SNS
RUN
ALERT
GPIO
SYNC
SHARE_CLK
GND
VSENSE+
VSENSE–
LOAD
3883 F03
PGND
Figure 3. Load Sharing Connections for 2-Phase Operation
Rev. F
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23
LTC3883/LTC3883-1
OPERATION
RCONFIG (RESISTOR CONFIGURATION) PINS
TSNS
LTC3883
GND
GND
10nF
MMBT3906
3883 F04
Figure 4. Temperature Sense Circuit
in parallel with the diode connected PNP. Two different currents are applied to the diode (nominally 2µA and 32µA) and
the temperature is calculated from the ∆VBE measurement.
The external transistor temperature is digitized by the telemetry ADC, and the value is returned by the PMBus READ_
TEMPERATURE_1 command.
The READ_TEMPERATURE_2 command returns the
junction temperature of the LTC3883 using an on-chip
diode. The slope of the external temperature sensor can be
modified with the temperature slope coefficient stored in
MFR_TEMP_1_GAIN. Typical PNPs require temperature
slope adjustments slightly less than 1. The MMBT3906 has
a recommended value in this command of approximately
MFR_TEMP_1_GAIN = 0.991 based on the ideality factor
of 1.01. Simply invert the ideality factor to calculate the
MFR_TEMP_1_GAIN. Different manufacturers and different lots may have different ideality factors. Consult with
the manufacturer to set this value.
The offset of the external temperature sense can be adjusted
by MFR_TEMP_1_OFFSET. A value of 0 in this command
sets the temperature offset to –273.15°C.
If the PNP cannot be placed in direct contact with the
inductor, the slope or offset can be increased to account
for temperature mismatches. If the user is adjusting the
slope, the intercept point is at absolute zero, –273.15°C, so
small adjustments in slope can change the apparent measured temperature significantly. Another way to artificially
increase the slope of the temperature term is to increase
the MFR_IOUT_CAL_GAIN_TC term. This will modify the
temperature slope with respect to room temperature.
If an external temperature sense element is not used, the
TSNS pin must be shorted to GND. The UT_FAULT_LIMIT
must be set to –275°C, and the UT_FAULT_RESPONSE
must be set to ignore. The user also needs to set the
IOUT_CAL_GAIN_TC to a value of 0.
The pins FREQ_CFG, VOUT_CFG and VTRIM_CFG can be
used to select important operating parameters without
programming the configuration EEPROM. Connecting
these pins to external resistor dividers selects the switching
frequency, output voltage and basic power management
supervisor parameters. The ASEL pin is used to select the
unique device bus address. Connect this pin to an external
resistor divider to select the device address. Always use
a resistor divider to select the device address. Setting
the device address in EEPROM is allowed, but can create
problems if the device address is somehow lost by the
host. It is safe and prudent to use the ASEL pin to set the
device address. If RCONFIG pins are floated, the value
stored in the corresponding NVM command is used. If
bit 6 of the MFR_CONFIG_ALL_LTC3883 configuration
command is asserted in NVM, the resistor inputs are
ignored upon power-up except for ASEL which is always
respected. The resistor configuration pins are only measured during a power-up reset or after an MFR_RESET
command is executed.
The VOUT_CFG and VTRIM pin settings are described in Tables
12 and 13. These pins select the output voltage for the
LTC3883’s analog PWM controller. If both pins are open,
the VOUT_COMMAND command is loaded from NVM to
determine the output voltage.
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determined
output voltage:
n
n
n
n
n
n
n
n
n
VOUT_OV_FAULT_LIMIT..................................... +10%
VOUT_OV_WARN_LIMIT................................... +7.5%
VOUT_MAX....................................................... +7.5%
VOUT_MARGIN_HIGH..........................................+5%
POWER_GOOD_ON..............................................–7%
POWER_GOOD_OFF.............................................–8%
VOUT_MARGIN_LOW...........................................–5%
VOUT_UV_WARN_LIMIT...................................–6.5%
VOUT_UV_FAULT_LIMIT.......................................–7%
The FREQ_CFG pin settings are described in Table 14. This
pin selects the switching frequency and phase relationship
between the PWM channel and SYNC pin. To synchronize
to an external clock, the part must be put into external clock
Rev. F
24
For more information www.analog.com
LTC3883/LTC3883-1
OPERATION
mode (FREQ_CFG pin shorted to ground). If no external
clock is supplied, the part will clock at the lowest freerunning frequency of the internal PWM oscillator. This low
clock rate will increase the ripple current of the inductor
possibly producing undesirable operation. If the external
SYNC signal is missing or misbehaving, a “PLL Lock Status” fault will be indicated in the STATUS_MFR_SPECIFIC
command. If the user does not wish to see the PLL_FAULT
even if there is not a valid synchronization signal at power
up, bit 3 of the MFR_CONFIG_ALL_LTC3883 command
must be asserted. If the SYNC pin is connected between
multiple ICs only one of the ICs can be the oscillator, all
other ICs must be configured to external clock.
The ASEL pin settings are described in Table 15. This
pin selects the bottom 4 bits of the slave address for the
LTC3883. The three most significant bits are retrieved from
the NVM MFR_ADDRESS command. If the pin is floating,
the 7-bit value stored in NVM MFR_ADDRESS command
is used to determine the slave address. For more detail,
refer to Table 15a.
Note: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
Input OV/FAULT Protection and UV Warning
n
Average Input OC Warn
n
Output OV/UV Fault and Warn Protection
n
Output OC Fault and Warn Protection
n
Internal and External Overtemperature Fault and Warn
Protection
n
External Undertemperature Fault and Warn Protection
n
CML Fault (Communication, Memory or Logic)
n
External Fault Detection via the Bidirectional GPIO Pin.
n
In addition, the LTC3883 can map any combination of
fault indicators to the GPIO pin using the propagate GPIO
response commands, MFR_GPIO_PROPAGATE_LTC3883.
Typical usage of the GPIO pin is as a driver for an external
crowbar device, overtemperature alert, overvoltage alert
or as an interrupt to cause a microcontroller to poll the
fault commands. Alternatively, the GPIO pin can be used
as an input to detect external faults downstream of the
controller that require an immediate response.
As described in the Soft-Start section, it is possible to control start-up through concatenated events. If GPIO is used
to drive the RUN pin of another controller, the unfiltered
VOUT_UV fault limit should be mapped to the GPIO pin.
Any fault or warning event will cause the ALERT pin to
assert low. The pin will remain asserted low until the
CLEAR_FAULTS command is issued, the fault bit is
written to a 1 or bias power is cycled or a MFR_RESET
command is issued, or the RUN pin is toggled OFF/ON
or the part is commanded OFF/ON via PMBus. The MFR_
GPIO_PROPAGATE_LTC3883 command determines if the
GPIO pin is pulled low when a fault is detected; however,
the ALERT pin is always pulled low if a fault or warning is
detected and the status bits are updated.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Tables 5
to 9. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition
is not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
The GPIO pin of the LTC3883 can share faults with all
ADI PMBus products including the LTC3880, LTC2974,
LTC2978, LTC4676 µModule, etc. In the event of an internal
Rev. F
For more information www.analog.com
25
LTC3883/LTC3883-1
OPERATION
fault, one or more of the LTC3883s is configured to pull
the bussed GPIO pin low. The other LTC3883s are then
configured to shut down when the GPIO pin bus is pulled
low. For autonomous group retry, the faulted LTC3883
is configured to let go of the GPIO pin bus after a retry
interval, assuming the original fault has cleared. All the
LTC3883s in the group then begin a soft-start sequence.
If the fault response is LATCH_OFF, the GPIO pin remains
asserted low until either the RUN pin is toggled OFF/ON or
the part is commanded OFF/ON. The toggling of the RUN
either by the pin or OFF/ON command will clear faults associated with the LTC3883. If it is desired to have all faults
cleared when either RUN pin is toggled, set bit 0 of MFR_
CONFIG_ALL_LTC3883 to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
Internal Memory with CRC and ECC
The LTC3883 contains internal EEPROM with Error Correction Coding (ECC) to store user configuration settings
and fault log information. EEPROM endurance and retention are specified in the Absolute Maximum Ratings and
Electrical Characteristics table.
The integrity of the NVM memory is checked with a
CRC calculation each time its data is to be read, such
as after a power-on reset. A CRC failure will prevent the
controller from leaving the inactive state. If a CRC failure
occurs, the CML bit is set in the STATUS_BYTE and
STATUS_WORD commands, the appropriate bit is set in
the STATUS_MFR_SPECIFIC command, and the ALERT and
RUN pins will be pulled low. At that point the device will
respond at special address 0x7C, which is only activated
after an invalid CRC has been detected. The chip will also
respond to global addresses 0x5A and 0x5B, but all ADI
PSM chips will respond to these addresses so users must
be careful when using global addresses. NVM repair can
be attempted by writing the desired configuration to the
controller and executing a STORE_USER_ALL command
followed by a CLEAR_FAULTS command. Contact the
factory if EEPROM repair is unsuccessful.
See the Applications Information section or contact the
factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which
the LTC3883 also supports.
SERIAL INTERFACE
The LTC3883 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor divider. In addition the LTC3883
always responds to the global broadcast address of 0x5A
(7 bit) or 0x5B (7 bit).
The serial interface supports the following protocols defined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte, 6) read word
and 7) read block. All read operations will return a valid
PEC if the PMBus master requests it. If the PEC_REQUIRED
bit is set in the MFR_CONFIG_ALL_LTC3883 command,
the PMBus write operations will not be acted upon until
a valid PEC has been received by the LTC3883.
Communication Failure
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTC3883 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master
to address all LTC3883 devices on the bus. The LTC3883
global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be disabled.
Rev. F
26
For more information www.analog.com
LTC3883/LTC3883-1
OPERATION
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTC3883. The value of the device address is set
by a combination of the ASEL configuration pin and the
MFR_ADDRESS command. Device addressing can be
disabled by writing a value of 0x80 to the MFR_ADDRESS.
Rail addressing provides a means of the PMBus master
addressing a set of LTC3883s connected to the same
output rail, simultaneously. This is similar to global addressing, however, the PMBus address can be dynamically
assigned by using the MFR_RAIL_ADDRESS command.
It is recommended that rail addressing should be limited
to command write operations.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSE command byte value. This
hardware level fault response delay is typically 2µs from
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSE command, the user can
select any of the following behaviors:
OV Pull-Down Only (OV cannot be ignored)
n
Shut Down (Stop Switching) Immediately—Latch Off
n
RESPONSES TO VOUT AND IOUT FAULTS
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
n
VOUT OV and UV conditions are monitored by comparators.
The OV and UV limits are set in three ways.
As a Percentage of the VOUT if Using the Resistor Configuration Pins
n
In NVM if Either Programmed at the Factory or Through
the GUI
n
By PMBus Command
n
The IIN and IOUT overcurrent monitors are performed by
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency of
up to 80ms. The IOUT calculation accounts for the sense
resistor and the temperature coefficient of the resistor. The
input channel current is equal to the sum of output current
times the PWM duty cycle plus the input offset current
for each channel. If this calculated input current exceed
the IN_OC_WARN_LIMIT the ALERT pin is pulled low and
the IIN_OC_WARN bit is asserted in the STATUS_INPUT
command.
The digital processor within the LTC3883 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_DELAY and can be from 120ms
to 83.88 seconds in 1ms increments. The shutdown for
Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) • 10µs. See Table 5.
Output Undervoltage Response
The response to an undervoltage comparator output can
be either:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
n
The UV responses can be deglitched. See Table 6.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle by
cycle basis. The value of the peak current limit is specified
in sense voltage in the EC table. The current limit circuit
operates by limiting the ITH maximum voltage. If DCR sensing is used, the ITH maximum voltage has a temperature
dependency directly proportional to the TC of the DCR
of the inductor. The LTC3883 automatically monitors the
Rev. F
For more information www.analog.com
27
LTC3883/LTC3883-1
OPERATION
external temperature sensors and modifies the maximum
allowed ITH to compensate for this term.
The overcurrent fault processing circuitry can execute the
following behaviors:
Current Limit Indefinitely
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
RESPONSES TO VIN OV FAULTS
VIN overvoltage is measured with the MUX’d ADC; therefore,
the response is naturally deglitched by the 80ms typical
response time of the ADC. The fault responses are:
Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
n
n
The overcurrent responses can be deglitched in increments
of (0-7) • 16ms. See Table 7
See Table 9.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT
is not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
Ignore
n Shut Down (Stop Switching) Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
n
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the user.
See Table 9.
RESPONSES TO OT/UT FAULTS
Overtemperature Fault Response—Internal
An internal temperature sensor protects against NVM
damage. Above 85°C, no writes to NVM are recommended.
Above 130°C, the part disables the NVM and does not reenable until the internal temperature has dropped to 125°C.
The LTC3883 sets bit 7 of the STATUS_TEMPERATURE
command (‘OT Warn’) above 130°C, and this bit cannot
be cleared until the internal temperature has dropped to
125°C. Above 160°C, the LTC3883 disables the PWM and
does not re-enable the PWM until the internal temperature
has dropped to 150°C. The part sets bit 6 of the STATUS_
TEMPERATURE command (‘OT Fault’) above 160°C, and
this bit cannot be cleared until the internal temperature has
dropped to 150°C. Temperature is measured by the ADC.
Internal temperature faults cannot be ignored. Internal
temperature limits cannot be adjusted by the user.
See Table 9.
Overtemperature and Undertemperature
Fault Response—Externals
An external temperature sensors can be used to sense
critical circuit elements like the inductor and power
MOSFETs. The OT_FAULT_RESPONSE and UT_FAULT_
RESPOSE commands are used to determine the appropriate response to an overtemperature and undertemperature
condition, respectively. If no external sense element is used
(not recommended) set the UT_FAULT_RESPONSE to
ignore and set the UT_FAULT_LIMIT to –275°C.
Rev. F
28
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LTC3883/LTC3883-1
OPERATION
The fault responses are:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
See Table 9.
RESPONSES TO INPUT OVERCURRENT AND OUTPUT
UNDERCURRENT FAULTS
this command re-enables the fault log feature. Before
re-enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
When the LTC3883 powers-up, it checks the NVM for a
valid fault log. If a valid fault log exists in NVM, the “Valid
Fault Log” bit in the STATUS_MFR_SPECIFIC command
will be set and an ALERT event will be generated. Also,
fault logging will be blocked until the LTC3883 has
received a MFR_FAULT_LOG_CLEAR command before
fault logging will be re-enabled.
Input overcurrent and output undercurrent are measured
with the MUX’d ADC. Both of these measurements are
naturally deglitched by the 80ms typical response time
of the ADC. The fault responses are:
The information is stored in EEPROM in the event of
any fault that disables the controller. The GPIO pin being
externally pulled low will not trigger a fault logging event.
Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
BUS TIMEOUT FAILURE
n
See Table 9.
RESPONSES TO EXTERNAL FAULTS
When the GPIO pin is pulled low, the OTHER bit is set in
the STATUS_WORD command, the appropriate bit is set
in the STATUS_MFR_SPECIFC command, and the ALERT
pin is pulled low. Responses are not deglitched. The
LTC3883 can be configured to ignore or shut down then
retry in response to its GPIO pin going low by modifying
the MFR_GPIO_RESPONSE command. To avoid the ALERT
pin asserting low when GPIO is pulled low, assert bit 1 of
MFR_CHAN_CONFIG_LTC3883.
FAULT LOGGING
The LTC3883 has fault logging capability. Data is logged
into memory in the order shown in Table 11. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not
guaranteed. When the die temperature exceeds 130°C,
the fault logging is delayed until the die temperature drops
below 120°C. The fault log data remains in NVM until a
MFR_FAULT_LOG_CLEAR command is issued. Issuing
The LTC3883 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the
first START event before the device address write byte.
Data packet information must be completed within 20ms or
the LTC3883 will three-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
The LTC3883 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command. In
no circumstances will the timeout period be less than the
tTIMEOUT_SMB specification of 32ms (typical).
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3883
supports the full PMBus frequency range from 10kHz to
400kHz.
SIMILARITY BETWEEN PMBUS, SMBUS AND I2C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
For more information www.analog.com
Rev. F
29
LTC3883/LTC3883-1
OPERATION
I2C byte commands because PMBus/SMBus provide
time-outs to prevent bus hangs and optional packet error checking (PEC) to ensure data integrity. In general, a
master device that can be configured for I2C communication can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
is not supported by all I2C controllers but is required for
SMBus/PMBus reads. If a general purpose I2C controller
is used, check that repeat start is supported.
The LTC3883 is a slave device. The master can communicate with the LTC3883 using the following formats:
Master transmitter, slave receiver
n
Master receiver, slave transmitter
n
The following PMBus protocols are supported:
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
n
The LTC3883 supports the maximum SMBus clock
speed of 100kHz and is compatible with the higher speed
PMBus specification (between 100kHz and 400kHz) if
clock stretching is enabled. For robust communication and
operation refer to the Note section in the PMBus command
summary. Clock stretching is enabled by asserting bit 1
of MFR_CONFIG_ALL_LTC3883.
Alert Response Address
n
Figures 7-16 illustrate the aforementioned PMBus protocols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the PMBus
timeout may be extended when reading the fault log.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
1
1
7
1
S
SLAVE ADDRESS Wr A
S
START CONDITION
8
1
1
DATA BYTE
A
P
x
For a description of the differences between SMBus and
I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between
SMBus and I2C.
PMBUS SERIAL DIGITAL INTERFACE
The LTC3883 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 5, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
x
Sr
REPEATED START CONDITION
Rd
READ (BIT VALUE OF 1)
Wr
WRITE (BIT VALUE OF 0)
x
SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
3883 F06
Figure 6. PMBus Packet Protocol Diagram Element Key
SDA
tf
tLOW
tr
tSU(DAT)
tHD(SDA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
START
CONDITION
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
3883 F05
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 5. Timing Diagram
Rev. F
30
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LTC3883/LTC3883-1
OPERATION
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
A value shown below a field in the following figures is a
mandatory value for that field.
Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
n
The data formats implemented by PMBus are:
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
n
Examples of these formats are shown in Figures 7-16.
Table 1. Data Format Terminology
PMBus
TERMINOLOGY
MEANING
Linear
Linear
Linear_5s_11s
L11
Page 35
Linear (for Voltage
Related Commands)
Linear
Linear_16u
L16
Page 35
Direct-Manufacturer
Customized
DirectMfr
CF
Page 35
Hex
I16
ASCII
ASC
Reg
Reg
Direct
Hex
ASCII
Register Fields
1
S
7
1
1
8
ABBREVIATIONS FOR
SUMMARY COMMAND TABLE
FOR MORE DETAIL REFER TO
THE DATA FORMAT SECTION
OF TABLE 2
TERMINOLOGY FOR: SPECS,
GUI, APPLICATION NOTES
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
DATA BYTE
A
P
3883 F07
Figure 7. Write Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3883 F08
Figure 8. Write Word Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
DATA BYTE
A
PEC
A
1
P
3883 F09
Figure 9. Write Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3883 F10
Figure 10. Write Word Protocol with PEC
Rev. F
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31
LTC3883/LTC3883-1
OPERATION
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
P
3883 F11
Figure 11. Send Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
PEC
A
P
3883 F12
Figure 12. Send Byte Protocol with PEC
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
S
7
1
1
SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
1
1
DATA BYTE HIGH A
8
P
3883 F13
Figure 13. Read Word Protocol
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
S
7
1
1
SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
8
1
DATA BYTE HIGH A
8
1
1
PEC
A
P
3883 F14
Figure 14. Read Word Protocol with PEC
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
S
7
1
1
SLAVE ADDRESS Rd A
8
1
1
DATA BYTE
A
P
3883 F15
Figure 15. Read Byte Protocol
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
S
7
1
1
SLAVE ADDRESS Rd A
8
1
DATA BYTE
A
PEC
1
1
A
P
3883 F16
Figure 16. Read Byte Protocol with PEC
Refer to Figure 6 for a legend.
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus Communication and Command Processing subsection of the
Applications Information section for further details.
Rev. F
32
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LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
PMBUS COMMANDS
The following tables list supported PMBus commands and
manufacturer specific commands. A complete description
of these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.1”. Users are encouraged to reference this specification.
Exceptions or manufacturer specific implementations
are listed below in Table 2. Floating point values listed
in the “DEFAULT VALUE” column are either Linear 16-bit
Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus
Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed
in this table are implicitly reserved by the manufacturer.
Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in this table are
implicitly not supported by the manufacturer. Attempting to
access non-supported or reserved commands may result
in a CML command fault event. All output voltage settings
and measurements are based on the VOUT_MODE setting
of 0x14. This translates to an exponent of 2–12.
If PMBus commands are received faster than they are being
processed, the part may become too busy to handle new
commands. In these circumstances the part follows the
protocols defined in the PMBus Specification v1.1, Part II,
Section 10.8.7, to communicate that it is busy. The part
includes handshaking features to eliminate busy errors
and simplify error handling software while ensuring robust
communication and system behavior. Please refer to the
subsection titled PMBus Communication and Command
Processing in the Applications Information section for
further details.
Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.)
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
PAGE
0x00
64
PAGE
0x00 Provides integration with multi-page PMBus
devices.
R/W Byte
Reg
OPERATION
0x01 Operating mode control. On/off, margin high and
margin low.
R/W Byte
Reg
Y
0x80
67
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
R/W Byte
Reg
Y
0x1E
66
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
NA
92
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
0x00
64
STORE_USER_ALL
0x15 Store user operating memory to EEPROM.
Send Byte
NA
100
RESTORE_USER_ALL
0x16 Restore user operating memory from EEPROM.
Send Byte
NA
101
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
Reg
0xB0
91
VOUT_MODE
0x20 Output voltage format and exponent (2–12).
R Byte
Reg
2–12
0x14
71
VOUT_COMMAND
0x21 Nominal output voltage set point.
R/W Word
L16
V
Y
1.0
0x1000
73
VOUT_MAX
0x24 Upper limit on the commanded output voltage
including VOUT_MARIN_HIGH.
R/W Word
L16
V
Y
5.5
0x5800
72
VOUT_MARGIN_HIGH
0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word
L16
V
Y
1.05
0x10CD
72
VOUT_MARGIN_LOW
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word
L16
V
Y
0.95
0x0F33
73
VOUT_TRANSITION_RATE 0X27 Rate the output changes when VOUT
commanded to a new value.
R/W Word
L11
V/ms
Y
0.25
AA00
80
FREQUENCY_SWITCH
R/W Word
L11
kHz
Y
350
0xFABC
70
0x33 Switching frequency of the controller.
Reg
Y
Rev. F
For more information www.analog.com
33
LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
PAGE
VIN_ON
0x35 Input voltage at which the unit should start
power conversion.
R/W Word
L11
V
Y
6.5
0xCB40
71
VIN_OFF
0x36 Input voltage at which the unit should stop
power conversion.
R/W Word
L11
V
Y
6.0
0xCB00
71
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense pins
to the sensed current. For devices using a fixed
current sense resistor, it is the resistance value
in mΩ.
R/W Word
L11
mΩ
Y
1.8
0xBB9A
74
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
L16
V
Y
1.1
0x119A
72
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an output
overvoltage fault is detected.
R/W Byte
Reg
Y
0xB8
83
VOUT_OV_WARN_LIMIT
0x42 Output overvoltage warning limit.
R/W Word
L16
V
Y
1.075
0x1133
72
VOUT_UV_WARN_LIMIT
0x43 Output undervoltage warning limit.
R/W Word
L16
V
Y
0.925
0x0ECD
73
VOUT_UV_FAULT_LIMIT
0x44 Output undervoltage fault limit.
R/W Word
L16
V
Y
0.9
0x0E66
73
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an output
undervoltage fault is detected.
R/W Byte
Reg
Y
0xB8
84
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
L11
Y
29.75
0xDBB8
77
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an output
overcurrent fault is detected.
R/W Byte
Reg
Y
0x00
86
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
L11
A
Y
20.0
0xDA80
77
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
L11
C
Y
100.0
0xEB20
79
OT_FAULT_RESPONSE
0x50 Action to be taken by the device when an external
overtemperature fault is detected,
R/W Byte
Reg
Y
0xB8
87
OT_WARN_LIMIT
0x51 External overtemperature warning limit.
R/W Word
L11
C
Y
85.0
0xEAA8
79
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
R/W Word
L11
C
Y
–40.0
0xE580
79
UT_FAULT_RESPONSE
0x54 Action to be taken by the device when an external
undertemperature fault is detected.
R/W Byte
Reg
Y
0xB8
88
VIN_OV_FAULT_LIMIT
0x55 Input supply overvoltage fault limit.
R/W Word
L11
Y
15.5
0xD3E0
70
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input
overvoltage fault is detected.
R/W Byte
Reg
Y
0x80
82
VIN_UV_WARN_LIMIT
0x58 Input supply undervoltage warning limit.
R/W Word
L11
V
Y
6.3
0xCB26
70
IIN_OC_WARN_LIMIT
0x5D Input supply overcurrent warning limit.
R/W Word
L11
A
Y
10.0
0xD280
78
POWER_GOOD_ON
0x5E Output voltage at or above which a power good
should be asserted.
R/W Word
L16
V
Y
0.93
0x0EE1
73
POWER_GOOD_OFF
0x5F Output voltage at or below which a power good
should be de-asserted.
R/W Word
L16
V
Y
0.92
0x0EB8
74
TON_DELAY
0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word
L11
ms
Y
0.0
0x8000
80
A
V
Rev. F
34
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
PAGE
TON_RISE
0x61 Time from when the output starts to rise until the R/W Word
output voltage reaches the VOUT commanded
value.
L11
ms
Y
8.0
0xD200
80
TON_MAX_FAULT_LIMIT
0x62 Maximum time from VOUT_EN on for VOUT to
cross the VOUT_UV_FAULT_LIMIT.
R/W Word
L11
ms
Y
10.00
0xD280
80
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a TON_
MAX_FAULT event is detected.
R/W Byte
Reg
Y
0xB8
85
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the start
of TOFF_FALL ramp.
R/W Word
L11
ms
Y
0.0
0x8000
81
TOFF_FALL
0x65 Time from when the output starts to fall until the
output reaches zero volts.
R/W Word
L11
ms
Y
8.00
0xD200
81
TOFF_MAX_WARN_LIMIT
0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word
L11
ms
Y
150
0xF258
81
STATUS_BYTE
0x78 One byte summary of the unit’s fault condition.
R/W Byte
Reg
NA
92
STATUS_WORD
0x79 Two byte summary of the unit’s fault condition.
R/W Word
Reg
NA
92
STATUS_VOUT
0x7A Output voltage fault and warning status.
R/W Byte
Reg
NA
93
STATUS_IOUT
0x7B Output current fault and warning status.
R/W Byte
Reg
NA
93
STATUS_INPUT
0x7C Input supply fault and warning status.
R/W Byte
Reg
NA
93
STATUS_TEMPERATURE
0x7D External temperature fault and warning status for
READ_TEMERATURE_1.
R/W Byte
Reg
NA
94
STATUS_CML
0x7E Communication and memory fault and warning
status.
R/W Byte
Reg
NA
94
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state information.
R/W Byte
Reg
READ_VIN
0x88 Measured input supply voltage.
R Word
L11
V
READ_IIN
0x89 Measured input supply current.
R Word
L11
READ_VOUT
0x8B Measured output voltage.
R Word
L16
READ_IOUT
0x8C Measured output current.
R Word
READ_TEMPERATURE_1
0x8D External diode junction temperature. This is the
value used for all temperature related processing,
including IOUT_CAL_GAIN.
R Word
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect
any other commands.
READ_DUTY_CYCLE
NA
94
NA
98
A
NA
98
V
NA
98
L11
A
NA
98
L11
C
NA
98
R Word
L11
C
NA
98
0x94 Duty cycle of the top gate control signal.
R Word
L11
%
NA
98
READ_POUT
0x96 Calculated output power.
R Word
L11
W
NA
99
READ_PIN
0x97 Calculated input power
R Word
L11
W
NA
99
PMBus_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.1.
R Byte
Reg
0x11
91
FS
MFR_ID
0x99 The manufacturer ID of the LTC3883 in ASCII.
R String
ASC
LTC
91
MFR_MODEL
0x9A Manufacturer part number in ASCII.
R String
ASC
LTC3883
91
MFR_VOUT_MAX
0xA5 Maximum allowed voltage command including
VOUT_OV_FAULT_LIMIT.
R Word
L16
5.5
0x5800
74
USER_DATA_00
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
Reg
Y
NA
90
USER_DATA_01
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
Reg
Y
NA
90
USER_DATA_02
0xB2 OEM RESERVED. Typically used for part
serialization
R/W Word
Reg
Y
NA
90
USER_DATA_03
0xB3 An NVM word available for the user.
R/W Word
Reg
Y
0x0000
90
V
Rev. F
For more information www.analog.com
35
LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
FORMAT
USER_DATA_04
0xB4 An NVM word available for the user.
R/W Word
Reg
MFR_INFO
MFR_T_SELF_HEAT
0xB6 Manufacturing Specific Information
R Word
Reg
0xB8 Reports the calculated self heat value attributed
to the inductor.
R Word
L11
C
MFR_IOUT_CAL_GAIN_
TAU_INV
0xB9 Coefficient used to emulate thermal time
constant.
R/W Word
L11
s–1
MFR_IOUT_CAL_GAIN_
THETA
0xBA Used to calculate the instance inductor self
heating effect.
R/W Word
L11
C/Watt
MFR_EE_UNLOCK
0xBD Unlock user EEPROM for access by MFR_EE_
ERASE and MFR_EE_DATA commands.
R/W Byte
MFR_EE_ERASE
0xBE Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
MFR_EE_DATA
UNITS
NVM
DEFAULT
VALUE
PAGE
Y
0x0000
92
NA
96
NA
75
Y
0.0
0x8000
75
Y
0.0
0x8000
75
Reg
NA
105
R/W Byte
Reg
NA
106
0xBF Data transferred to and from EEPROM using
sequential PMBus word reads or writes.
Supports bulk programming.
R/W Word
Reg
NA
106
MFR_CHAN_CONFIG_
LTC3883
0xD0 Configuration bits that are channel specific.
R/W Byte
Reg
Y
0x1F
65
MFR_CONFIG_ALL_
LTC3883
0xD1 General configuration bit.
R/W Byte
Reg
Y
0x09
66
MFR_GPIO_PROPAGATE_ 0xD2 Configuration that determines which faults are
LTC3883
propagated to the GPIO pin.
R/W Word
Reg
Y
0x2993
89
MFR_PWM_MODE_
LTC3883
0xD4 Configuration for the PWM engine.
R/W Byte
Reg
Y
0xD2
68
MFR_GPIO_RESPONSE
0xD5 Action to be taken by the device when the GPIO
pin is externally asserted low.
R/W Byte
Reg
Y
0xC0
90
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an internal
overtemperature fault is detected.
R Byte
Reg
0xC0
87
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of READ_
IOUT since last MFR_CLEAR_PEAKS.
R Word
L11
A
NA
99
MFR_RETRY_DELAY
0xDB Retry interval during FAULT retry mode.
R/W Word
L11
ms
Y
350
0xFABC
82
MFR_RESTART_DELAY
0xDC Minimum time the RUN pin is held low by the
LTC3883.
R/W Word
L11
ms
Y
500
0xFBE8
82
MFR_VOUT_PEAK
0xDD Maximum measured value of READ_VOUT since
last MFR_CLEAR_PEAKS.
R Word
L16
V
NA
99
MFR_VIN_PEAK
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
L11
V
NA
99
MFR_TEMPERATURE_1_
PEAK
0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
R Word
L11
C
NA
99
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
L11
A
NA
99
MFR_CLEAR_PEAKS
0xE3 Clears all peak values.
NA
92
MFR_READ_ICHIP
0xE4 Measured supply current of the LTC3883
R Word
L11
A
NA
100
MFR_PADS
0xE5 Digital status of the I/O pads.
MFR_ADDRESS
0xE6 Sets the 7-bit I2C address byte.
MFR_SPECIAL_ID
MFR_IIN_CAL_GAIN
Send Byte
R Word
Reg
R/W Byte
Reg
0xE7 Manufacturer code representing the LTC3883
R Word
Reg
0xE8 The resistance value of the input current sense
element in mΩ.
R/W Word
L11
Y
mΩ
Y
NA
95
0x4F
65
0x430X
91
5
0xCA80
78
Rev. F
36
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
PAGE
MFR_FAULT_LOG_STORE
0xEA Command a transfer of the fault log from RAM to
EEPROM. This causes the part to behave as if a
channel has faulted off.
Send Byte
NA
102
MFR_FAULT_LOG_CLEAR
0xEC Initialize the EEPROM block reserved for fault
logging and clear any previous fault logging
locks.
Send Byte
NA
105
MFR_READ_IIN_CHAN
0xED Calculated input current based upon READ_IOUT
and DUTY_CYCLE.
R Word
L11
NA
100
MFR_FAULT_LOG
0xEE Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
R Block
Reg
NA
102
MFR_COMMON
0xEF Manufacturer status bits that are common across
multiple ADI chips.
R Byte
Reg
NA
95
MFR_COMPARE_USER_
ALL
0xF0 Compares current command contents with NVM.
Send Byte
NA
101
MFR_TEMPERATURE_2_
PEAK
0xF4 Peak internal die temperature since last MFR_
CLEAR_PEAKS.
NA
100
MFR_PWM_CONFIG_
LTC3883
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
Y
0x10
69
A
Y
R Word
L11
R/W Byte
Reg
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing
element.
R/W Word
CF
ppm/°C
Y
3900
0x0F3C
74
MFR_RVIN
0xF7 The resistance value of the VIN pin filter element
in mΩ.
R/W Word
L11
mΩ
Y
3000
0x12EE
71
MFR_TEMP_1_GAIN
0xF8 Sets the slope of the external temperature sensor. R/W Word
CF
Y
1.0
0x4000
78
MFR_TEMP_1_OFFSET
0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
R/W Word
L11
Y
0.0
0x8000
79
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to
adjust common parameters.
R/W Byte
Reg
Y
0x80
65
MFR_RESET
0xFD Commanded reset without requiring a power
down.
Send Byte
NA
68
Note 1: Commands indicated with Y indicate that these commands are
stored and restored using the STORE_USER_ALL and RESTORE_USER_
ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC3883 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
C
C
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
ADI has made every reasonable attempt to keep command functionality
compatible between parts; however, differences may occur to address
product requirements.
Rev. F
For more information www.analog.com
37
LTC3883/LTC3883-1
PMBus COMMAND SUMMARY
*DATA FORMAT
L11
Linear_5s_11s
PMBus data field b[15:0]
Value = Y • 2N
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
Value = 7 • 2–13 = 854 • 10–6
From “PMBus Spec Part II: Paragraph 7.1”
L16
Linear_16u
PMBus data field b[15:0]
Value = Y • 2N
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x4C00 = ‘b0100_1100_0000_0000
Value = 19456 • 2–12 = 4.75
From “PMBus Spec Part II: Paragraph 8.2”
Reg
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
I16
Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF
ASC
Custom Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
ASCII Format
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
Rev. F
38
For more information www.analog.com
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
The Typical Application on the back page is a basic LTC3883
application circuit. The LTC3883 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. The LTC3883 can nominally
account for the temperature dependency of the DCR sensing
element. The accuracy of the current reading and current
limit are typically limited by the accuracy of the DCR resistor (accounted for in the IOUT_CAL_GAIN parameter of
the LTC3883). Thus current sensing resistors provide the
most accurate current sense and limiting for the application. Other external component selection is driven by the
load requirement, and begins with the selection of RSENSE
(if RSENSE is used) and inductor value. Next, the power
MOSFETs are selected. Then the input and output capacitors are selected. Finally the current limit is selected. All of
these components and ranges are required to be determined
prior to calculating the external compensation components.
The current limit range is required because the two ranges
(25mV to 50mV vs 37.5mV to 75mV) have different EA
gains set with bit 7 of the MFR_PWM_MODE_LTC3883
command. The voltage RANGE bit also modifies the loop
gain and impacts the compensation network set with bits
5, 6 of MFR_PWM_CONFIG_LTC3883. All other programmable parameters do not affect the loop gain, allowing
parameters to be modified without impact to the transient
response to load.
CURRENT LIMIT PROGRAMMING
The LTC3883 has two ranges of current limit programming
and a total of eight levels within each range. Refer to the
IOUT_OC_FAULT_LIMIT section of the PMBus commands.
Within each range the error amp gain is fixed, resulting in
constant loop gain. The LTC3883 will account for the DCR
of the inductor and automatically update the current limit as
the inductor temperature changes. The temperature coefficient of the DCR is stored in the MFR_IOUT_TC command.
For the best current limit accuracy, use the 75mV setting.
The 25mV setting will allow for the use of very low DCR
inductors or sense resistors, but at the expense of current limit accuracy. Keep in mind this operation is on a
cycle-by-cycle basis and is only a function of the peak
inductor current. The average inductor current is monitored
by the ADC converter and can provide a warning if too
much average output current is detected. The overcurrent
fault is detected when the ITH voltage hits the maximum
value. The digital processor within the LTC3883 provides
the ability to either ignore the fault, shut down and latch off
or shut down and retry indefinitely (hiccup). Refer to the
overcurrent portion of the Operation section for more detail.
ISENSE+ AND ISENSE– PINS
The ISENSE+ and ISENSE– pins are the inputs to the current
comparator and the A/D. The common mode input voltage
range of the current comparators is 0V to 5.5V. Both the
SENSE pins are high impedance inputs with small base
currents typically less than 1µA. When the ISENSE pin voltages are between 0V and 1.4V, the small base currents flow
out of the SENSE pins. When the ISENSE pin voltages are
greater than 1.4V, the base currents flow into the ISENSE
pins. The high impedance inputs to the current comparators allow accurate DCR sensing. Do not float these pins
during normal operation.
Filter components mutual to the ISENSE lines should be
placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to
the current sense element, see Figure 17. A non-Kelvin
connection elsewhere can add parasitic inductance and
capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. In a PolyPhase
system, poor placement of the sensing element will result in
sub-optimal current sharing between power stages. If DCR
sensing is used (Figure 18a), sense resistor R1 should be
placed close to the switching node to prevent noise from
coupling into sensitive small-signal nodes. The capacitor
TO SENSE FILTER,
NEXT TO THE CONTROLLER
COUT
INDUCTOR OR RSENSE
3883 F17
Figure 17. Optimal Sense Line Placement
Rev. F
For more information www.analog.com
39
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
C1 should be placed close to the IC pins. This impedance
difference can result in loss of accuracy in the current
reading of the ADC. The current reading accuracy can be
improved by matching the impedance of the two pins. To
accomplish this add a series resistor between VOUT and
ISENSE– equal to R1. A capacitor of 1µF or greater should
be placed in parallel with this resistor. If the peak voltage
is 1µF
PGND
R1
ISENSE+
C1*
R2
ISENSE–
SGND
[(R1+ R3)||R2] • C1 =
R3
OPTIONAL
2 •L
DCR
IOUT_CAL_GAIN = DCR •
3883 F18a
R2
; R3 = R1
R1 + R2 + R3
*PLACE C1 NEAR SENSE+, SENSE– PINS
Figure 18a. Inductor DCR Current Sense Circuit
VIN
INTVCC
VIN
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
TG
RS
SW
ESL
VOUT
LTC3883
BG
PGND
ISENSE+
ISENSE–
SGND
RF
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
CF
RF
FILTER COMPONENTS
PLACED NEAR SENSE PINS
3883 F018b
Figure 18b. Resistor Current Sense Circuit
40
VSENSE(MAX)
IMAX +
∆IL
2
Due to possible PCB noise in the current sensing loop, the
AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also
needs to be checked in the design to get a good signal-tonoise ratio. In general, for a reasonably good PCB layout,
a 15mV minimum ∆VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications.
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628/LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. In the new highest current density
solutions; however, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be less than
20mV. In addition, inductor ripple currents greater than 50%
with operation up to 1MHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. A
typical sensing circuit using a discrete resistor is shown in
Figure 18b. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of the capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 100Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 200ns.
This same RC filter with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance. For
example, Figure 19 illustrates the voltage waveform across
a 2mΩ resistor with a 2010 footprint. The waveform is
the superposition of a purely resistive component and a
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time, tON, and off-time,
tOFF, of the top switch, the value of the parasitic inductance
was determined to be 0.5nH using the equation:
ESL =
VESL(STEP)
∆IL
t •t
• ON OFF
tON + tOFF
(1)
If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the
resultant waveform looks resistive, as shown in Figure 20.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
Equation 1 to determine the ESL. However, do not overfilter
the signal. Keep the RC time constant less than or equal to
the inductor time constant to maintain a sufficient ripple
voltage on VRSENSE for optimal operation of the current
loop controller.
VSENSE
20mV/DIV
VESL(STEP)
500ns/DIV
3883 F19
Figure 19. Voltage Measured Directly Across RSENSE
INDUCTOR DCR CURRENT SENSING
For applications requiring the highest possible efficiency
at high load currents, the LTC3883 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 18a. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost a few points of efficiency compared to DCR sensing.
If the external (R1 + R3)||R2 • C1 time constant is chosen
to be exactly equal to the L/DCR time constant, assuming
R1 = R3, the voltage drop across the external capacitor,C1,
is equal to the drop across the inductor DCR multiplied by
R2/(R1+R2+R3). R2 scales the voltage across the sense
terminals for applications where the DCR is greater than
the target sense resistor value. The DCR value is entered
as the IOUT_CAL_GAIN in mΩ unless R2 is required. If
R2 is used:
IOUT _ CAL _ GAIN = DCR •
R2
R1+ R2 + R3
If there is no need to attenuate the signal, R2 can be
removed. To properly dimension the external filter components, the DCR of the inductor must be known. It
can be measured using an accurate RLC meter, but the
DCR tolerance is not always the same and varies with
temperature. Consult the manufacturers’ data sheets
for detailed information. The LTC3883 will account for
temperature variation if the correct parameter is entered
into the MFR_IOUT_CAL_GAIN_TC command. Typically
the resistance has a 3900ppm/°C coefficient.
C2 can be optimized for a flat frequency response, assuming R1 = R3 by the following equation:
C2 = [2R1 • R2 • C1-L/DCR • (2R1+R2)]/R12
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
VSENSE
20mV/DIV
R SENSE(EQUIV) =
500ns/DIV
3883 F20
VSENSE(MAX)
IMAX +
∆IL
2
Figure 20. Voltage Measured After the RSENSE Filter
Rev. F
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41
LTC3883/LTC3883-1
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To ensure that the application will deliver full load current
over the full operating temperature range, be sure to pick
the optimum ILIMIT value accounting for errors in the DCR
versus the MFR_IOUT_CAL_GAIN parameter entered.
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for errors in the
temperature sensing element of 3°C to 5°C and any
additional errors associated with the proximity of the
temperature sensor element to the inductor.
C1 is usually selected to be in the range of 0.047µF to
4.7µF. This forces (R1 + R3)||R2 to be approximately 2k.
Adding optional elements R3 and C2 shown in Figure 18a
will minimize offset errors associated with the ISNS leakage currents. Set R3 equal to the value of R1. Set C2 to a
value of 1µF or greater to ensure adequate noise filtering.
The equivalent resistance (R1 + R3)||R2 is scaled to the
room temperature inductance and maximum DCR:
(R1+ R3 ) || R2 =
2•L
(DCR
at 20°C ) • C1
The sense resistor values are:
R1 = R3; R1 =
R1 R2
RD
; R2 =
PLOSS
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆VSENSE of 10mV to 15mV.
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
∆VSENSE =
VIN – VOUT
R1• C1
•
VOUT
VIN • fOSC
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
Slope compensation provides stability in constant
frequency current mode architectures by preventing
sub-harmonic oscillations at high duty cycles. This is
accomplished internally by adding a compensation ramp
to the inductor current signal at duty cycles in excess of
35%. The LTC3883 uses a patented current limit technique
that counteracts the compensating ramp. This allows the
maximum inductor peak current to remain unaffected
throughout all duty cycles.
INDUCTOR VALUE CALCULATION
R1• RD
1– RD
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
mode will improve the converter efficiency at light loads
regardless of the current sensing method.
( VIN(MAX) – VOUT ) • VOUT
R1=
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reducing conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method. Selecting Burst Mode operation or discontinuous
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor peak-to-peak ripple current:
V
( V – VOUT )
IRIPPLE = OUT IN
VIN • fOSC • L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at the
lowest frequency with a small ripple current. Achieving
this, however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maximum, the inductor should be chosen according to:
V
( V – VOUT )
L ≥ OUT IN
VIN • fOSC • IRIPPLE
Rev. F
42
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INDUCTOR CORE SELECTION
Once the inductor value is determined, the type of inductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the inductance collapse abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
POWER MOSFET AND SCHOTTKY DIODE (OPTIONAL)
SELECTION
Two external power MOSFETs must be selected for each
controller in the LTC3883: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V. Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logiclevel MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the onresistance, RDS(ON) , Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
Main Switch Duty Cycle = OUT
VIN
V – VOUT
Synchronous Switch Duty Cycle = IN
VIN
The MOSFET power dissipations at maximum output
current are given by:
V
2
PMAIN = OUT (IMAX ) (1+ d ) RDS(ON) +
VIN
( VIN )
2 ⎛ IMAX
⎞
⎜
⎟ (RDR ) (CMILLER ) •
⎝ 2 ⎠
⎡
⎤
1
1
⎢
⎥ • fOSC
+
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
V – VOUT
2
PSYNC = IN
(IMAX ) (1+ d ) RDS(ON)
VIN
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Rev. F
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43
LTC3883/LTC3883-1
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The optional Schottky diodes conduct during the dead time
between the conduction of the two power MOSFETs. These
prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTC3883 must enter the run state prior to soft-start.
The RUN pin is released after the part initializes and VIN is
greater than the VIN_ON threshold. If multiple LTC3883s
are used in an application, they should be configured to
share the same RUN pins. They all hold their respective
RUN pins low until all devices initialize and VIN exceeds
the VIN_ON threshold for all devices. The SHARE_CLK
pin assures all the devices connected to the signal use
the same time base.
After the RUN pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAY) prior to initiating an output voltage ramp. Multiple LTC3883s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUN pin. This allows the relative delay of all parts to
be synchronized. The actual variation in the delay will be
dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Linear Technology ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be ±10% in frequency, thus the actual time delays will
have proportional variance.
Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0.0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISE
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISE to any value less than 0.250ms.
The LTC3883 will perform the necessary math internally
to assure the voltage ramp is controlled to the desired
slope. However, the voltage slope can not be any faster
than the fundamental limits of the power stage. The shorter
TON_RISE time is set, the more jagged the TON_RISE ramp
will appear. The number of steps in the ramp is equal to
TON_RISE/0.1ms.
The LTC3883 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
There is no tracking feature in the LTC3883; however, two outputs can be given the same TON_RISE and
TON_DELAY times to effectively ramp up at the same
time. If the RUN pin is released at the same time and both
LTC3883s use the same time base, the outputs will track
very closely. If the circuit is in a PolyPhase configuration,
all timing parameters must be the same.
The described method of start-up sequencing is time based.
For concatenated events it is possible to control the RUN
pin based on the GPIO pin of a different controller. The GPIO
pin can be configured to release when the output voltage of
the converter is greater than the VOUT_UV_FAULT_LIMIT.
It is recommended to use the deglitched VOUT UV fault
limit because there is little appreciable time delay between
the converter crossing the UV threshold and the GPIO pin
releasing. The deglitched output can be enabled by setting the MFR_GPIO_PROPAGATE_VOUT_UVUF bit in the
MFR_GPIO_PROPAGATE_LTC3883 command. (Refer to
the MFR section of the PMBus commands in this document). The deglitched signal may have some glitching
as the VOUT signal transitions through the comparator
threshold. A small internal digital filter of 70µs has been
added to minimize this problem. To minimize the risk of
GPIO pin glitching, make the TON_RISE times less than
100ms. If unwanted transitions still occur on GPIO, place a
capacitor to ground on the GPIO pin to filter the waveform.
The RC time-constant of the filter should be set sufficiently
fast to assure no appreciable delay is incurred. A value
of 300µs to 500µs will provide some additional filtering
without significantly delaying the trigger event.
Rev. F
44
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APPLICATIONS INFORMATION
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE_LTC3883 command. In digital servo
mode, the LTC3883 will adjust the regulated output voltage
based on the ADC voltage reading. Every 80ms the digital
servo loop will step the LSB of the DAC (nominally 1.375mV
or 0.6875mV depending on the voltage range bit) until the
output is at the correct ADC reading. At power-up this mode
engages after TON_MAX_FAULT_LIMIT unless the limit is
set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to
0 (infinite), the servo begins after TON_RISE is complete
and VOUT has exceeded the VOUT_UV_FAULT_LIMIT.
This same point in time is when the output changes from
discontinuous to the programmed mode as indicated
in MFR_PWM_MODE_LTC3883 bits 0 and 1. Refer to
Figure 21 for details on the VOUT waveform under time
based sequencing.
TON_MAX_FAULT_LIMIT
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
DAC VOLTAGE
ERROR (NOT
TO SCALE)
VOUT
TON_DELAY
TON_RISE
TIME DELAY OF
200-400ms
TIME
3883 F21
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTC3883 also supports controlled turn-off. The TOFF_DELAY and TOFF_FALL
functions are shown in Figure 22. TOFF_FALL is processed
when the RUN pin goes low or if the part is commanded
off. If the part faults off or GPIO is pulled low externally
and the part is programmed to respond to this, the output
will three-state rather than exhibiting a controlled ramp.
The output will decay as a function of the load.
The output voltage will operate as shown in Figure 22 so
long as the part is in forced continuous mode and the
TOFF_FALL time is sufficiently slow that the power stage
can achieve the desired slope. The TOFF_FALL time can
only be met if the power stage and controller can sink
Figure 21. Timing Controlled VOUT Rise
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is set to
ignore 0x00, the servo begins:
VOUT
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached; and
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is not longer active.
TOFF_DELAY
TOFF_FALL
TIME
3883 F22
Figure 22. TOFF_DELAY and TOFF_FALL
Rev. F
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LTC3883/LTC3883-1
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sufficient current to assure the output is a zero volts by
the end of the fall time interval. If the TOFF_FALL time is
set shorter than the time required to discharge the load
capacitance, the output will not reach the desired zero volt
state. At the end of TOFF_FALL, the controller will cease
to sink current and VOUT will decay at the natural rate
determined by the load impedance. If the controller is in
discontinuous mode, the controller will not pull negative
current and the output will be pulled low by the load, not
the power stage. The maximum fall time is limited to 1.3
seconds. The shorter TOFF_FALL time is set, the more
jagged the TOFF_FALL ramp will appear. The number of
steps in the ramp is equal to TOFF_FALL/0.1ms.
INTVCC REGULATOR
The LTC3883 features an NPN linear regulator that supplies power to INTVCC from the VIN supply. INTVCC powers
the gate drivers, VDD33 and much of the LTC3883 internal
circuitry. The linear regulator produces 5V at the INTVCC
pin when VIN is greater than 6.5V. The regulator can supply a peak current of 100mA and must be bypassed to
ground with a minimum of 1µF ceramic capacitor or low
ESR electrolytic capacitor. No matter what type of bulk
capacitor is used, an additional 0.1µF ceramic capacitor
placed directly adjacent to the INTVCC and PGND pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers. The NPN linear regulator on the LTC3883-1 is not
present and an external 5V supply is needed.
High input voltage application in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3883 to be
exceeded. The INTVCC current, of which a large percentage is due to the gate charge current, may be supplied by
either the internal 5V linear regulator or from an external
5V regulator on the LTC3883-1. If the LTC3883 is used
with the internal regulator activated, the power through
the IC is equal to VIN • IINTVCC. The gate charge current is
dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature
can be estimated by using the equations in Note 2 of the
Electrical Characteristics. For example, at 70°C ambient,
the LTC3883 INTVCC current is limited to less than 52mA
from a 24V supply:
TJ = 70°C + 52mA • 24V • 44°C/W = 125°C
To prevent the maximum junction temperature from being
exceeded, a LTC3883-1 can be used. In the LTC3883-1,
the INTVCC linear regulator is disabled and approximately
2mA of current is supplied internally from VIN. Significant
system efficiency and thermal gains can be realized by
powering the EXTVCC pin from a switching 5V regulator.
The VIN current resulting from the gate driver and control
circuitry will be scaled by a factor of:
⎛V
⎞⎛
⎞
1
⎜ EXTVCC ⎟ ⎜
⎟
⎝ VIN ⎠ ⎝ Efficiency ⎠
Tying the EXTVCC pin to a 5V supply (LTC3883-1 only)
reduces the junction temperature in the previous example
from 125°C to:
TJ = 70°C + 52mA • 5V • 44°C/W + 2mA • 24V • 44°C/W
= 103°C
Do not tie INTVCC on the LTC3883 to an external supply
because INTVCC will attempt to pull the external supply
high and hit current limit, significantly increasing the die
temperature.
For applications where VIN is 5V, tie the VIN and INTVCC
pins together and tie the combined pins to the 5V input
with a 1Ω or 2.2Ω resistor as shown in Figure 23. To minimize the voltage drop caused by the gate charge current a
low ESR capacitor must be connected to the VIN/INTVCC
(EXTVCC) pins. This configuration will override the INTVCC
(EXTVCC) linear regulator and will prevent INTVCC (EXTVCC)
from dropping too low. Make sure the INTVCC (EXTVCC)
LTC3883
LTC3883-1
VIN
INTVCC/EXTVCC
RVIN
1Ω
CINTVCC
4.7µF
5V
+
CIN
3883 F23
Figure 23. Setup for a 5V Input
Rev. F
46
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voltage exceeds the RDS(ON) test voltage for the MOSFETs
which is typically 4.5V for logic level devices. The UVLO
on INTVCC (EXTVCC) is set to approximately 4V. Both the
LTC3883 and LTC3883-1 are valid for this configuration.
TOPSIDE MOSFET DRIVER SUPPLY (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pin supplies the gate drive voltages for the topside MOSFETs. Capacitor CB in the Block Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on,
the driver places the CB voltage across the gate source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC. The value of the boost capacitor
CB needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
PWM jitter has been observed in some designs operating
at higher VIN/VOUT ratios. This jitter does not substantially
affect the circuit accuracy. Referring to Figure 24, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOST pin. A resistor case size of 0603 or larger is
recommended to reduce ESL and achieve the best results.
VIN
1Ω TO 5Ω
BOOST
TGATE
LTC3883/
LTC3883-1
SW
INTVCC/EXTVCC
BGATE
VIN
CB
0.2µF
DB
UNDERVOLTAGE LOCKOUT
The LTC3883 is initialized by an internal threshold-based
UVLO where VIN must be approximately 4V and INTVCC/
EXTVCC, VDD33, VDD25 must be within approximately 20%
of the regulated values. In addition, VDD33 must be within
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
comparator monitors VIN. The VIN_ON threshold must be
exceeded before the power sequencing can begin. When
VIN drops below the VIN_OFF threshold, the SHARE_CLK
pin will be pulled low and VIN must increase above the
VIN_ON threshold before the controller will restart.
The normal start-up sequence will be allowed after the
VIN_ON threshold is crossed. If GPIO is held low when
VIN is applied, ALERT will be asserted low even if the part
is programmed to not assert ALERT when GPIO is held
low. If I2C communication occurs before the LTC3883 is
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
It is possible to program the contents of the NVM in the
application if the VDD33 supply is externally driven. This
will activate the digital portion of the LTC3883 without
engaging the high voltage sections. PMBus communications are valid in this supply configuration. If VIN has not
been applied to the LTC3883, bit 3 (NVM Not Initialized)
in MFR_COMMON will be asserted low. If this condition is
detected, the part will only respond to addresses 5A and 5B.
To initialize the part issue the following set of commands:
global address 0x5B command 0xBD data 0x2B followed
by global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
the part as desired then issue a STORE_USER_ALL. When
VIN is applied a MFR_RESET command must be issued to
allow the PWM to be enabled and valid ADC conversions
to be read.
CIN AND COUT SELECTION
CINTVCC
10µF
PGND
3883 F24
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
Figure 24. Boost Circuit to Minimize PWM Jitter
Rev. F
For more information www.analog.com
47
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
1/2
I
CIN Required IRMS ≈ MAX ⎡⎣( VOUT ) ( VIN – VOUT )⎤⎦
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3883, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of using two LTC3883 2-phase operation can
be calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3883, is also
suggested. A 2.2Ω – 10Ω resistor placed between CIN
(C1) and the VIN pin provides further isolation between
the two LTC3883s.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
⎛
1 ⎞
∆VOUT ≈ IRIPPLE ⎜ESR +
⎟
8fCOUT ⎠
⎝
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the
inductor. The output ripple is highest at maximum input
voltage since IRIPPLE increases with input voltage.
FAULT CONDITIONS
The LTC3883 GPIO pin is configurable to indicate a variety of faults including OV, UV, OC, OT, timing faults, peak
overcurrent faults. In addition the GPIO pin can be pulled
low by external sources indicating a fault in some other
portion of the system. The fault response is configurable
and allows the following options:
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY
n
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The OV response is automatic. If an OV condition is detected, TG goes low and BG is asserted.
Fault logging is available on the LTC3883. The fault logging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTC3883 internal temperature is in excess of 85°C,
the write into the NVM is not recommended. The data will
still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all
NVM communication is disabled until the die temperature
drops below 120°C.
Rev. F
48
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
OPEN-DRAIN PINS
The LTC3883 has the following open-drain pins:
3.3V Pins
1. GPIO
2. SYNC
3. SHARE_CLK
4. PGOOD
5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUN
2. ALERT
3. SCL
4. SDA
All the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low threshold on the pins
is 1.4V; thus, plenty of margin on the digital signals with
3mA of current. For 3.3V pins, 3mA of current is a 1.1k
resistor. Unless there are transient speed issues associated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
RPULLUP =
tRISE
3 • 100pF
= 1k
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capacitance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is one time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
RPULLUP =
2µs – 500ns
3 • 100pF
= 5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTC3883 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by the
lower 3 bits of the MFR_PWM_CONFIG_LTC3883 command. For PolyPhase applications, it is recommended all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
250kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
The PLL has a lock detection circuit. If the PLL should lose
lock during operation, bit 4 of the STATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low.
The fault can be cleared by writing a 1 to the bit. If the
user does not wish to see the PLL_FAULT, even if a
synchronization clock is not available at power up, bit 3
of the MFR_CONFIG_ALL_LTC3883 command must be
asserted.
Rev. F
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49
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
If the SYNC signal is not clocking in the application, the
PLL will run at the lowest free running frequency of the
VCO. This will be well below the intended PWM frequency
of the application and may cause undesirable operation
of the converter.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem. Multiple LTC3883s are required to
share the SYNC pin in PolyPhase configurations, for other
configurations it is optional. If the SYNC pin is shared between LTC3883s, only one LTC3883 can be programmed
with a frequency output. All the other LTC3883s must be
programmed to external clock.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3883 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn off the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3883 is approximately
45ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current loop. As the peak current sense voltage decreases,
the minimum on-time gradually increases to 130ns. This
is of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.
INPUT CURRENT SENSE AMPLIFIER
The LTC3883 input current sense amplifier can sense the
supply current into the VIN pin using an internal sense resistor as well as the power stage current using an external
sense resistor. High frequency noise caused by the discontinuous input current can cause input current measurement errors. The noise will be the greatest in high current
applications and at large step-down ratios. Care must be
taken to mitigate the noise seen at the input current sense
amplifier inputs and supply. This can be accomplished by
careful layout as well as filtering at the VIN, VIN_SNS and
IINSNS pins. The VIN pin should be filtered with a resistor
and a ceramic capacitor located as close to the VIN pin as
possible. The supply side of the VIN pin filter should be
Kelvin connected to the supply side of the RIINSNS resistor.
A 3Ω resistor should be sufficient for most applications.
The resistor will cause an IR voltage drop from the supply to the VIN pin due to the current flowing into the VIN
pin. To compensate for this voltage drop, the MFR_RVIN
command value should be set to the nominal resistor
value. The LTC3883 will multiply the MFR_READ_ICHIP
measurement value by the user defined MFR_RVIN value
and add this voltage to the measured voltage at the VIN
pin. Therefore READ_VIN = VVIN_PIN + (MFR_READ_ICHIP
• MFR_RVIN), so that this command will return the value
of the voltage at the supply side of the VIN pin filter. If no
VIN filter element is used, set MFR_RVIN = 0.
RIINSNS
VIN
10µF
100Ω
100Ω
1µF
LTC3883
TG
M1
IIN_SNS
3Ω
10nF
10nF
10µF
VIN_SNS
SW
VIN
BG
M2
3883 F25
Figure 25. Low Noise Input Current Sense Circuit
Rev. F
50
For more information www.analog.com
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
Both the VIN_SNS and IIN_SNS pins need to be filtered with
a 1% tolerance 100Ω resistor to RIINSNS and a 10nF ceramic capacitor to GND. A larger value capacitor to GND
may be used for additional filtering. Because the input
current sense amplifier gain is calibrated for 100Ω filter
resistors, any other filter resistance value will cause an
input current measurement error. The amplifier input filter
networks should be located as close to the VIN_SNS and
IIN_SNS pins as possible.
The capacitor from the intermediate bus to ground should
be a low ESR ceramic capacitor. It should be placed as
close as possible to the drain of the top gate MOSFET to
supply high frequency transient input current. This will
help prevent noise from the top gate MOSFET current
from feeding into the input current sense amplifier inputs
and supply.
If the input current sense amplifier is not used, short the
VIN, VIN_SNS, and IIN_SNS pins together.
RCONFIG (EXTERNAL RESISTOR
CONFIGURATION PINS)
The LTC3883 default NVM is programmed to respect the
RCONFIG pins. If a user wishes the output voltage, PWM
frequency and phasing to be set without programming
the part or purchasing specially programmed parts, the
FREQ_CFG, VOUT_CFG, and VTRIM_CFG pins can be used
to establish these parameters. To save external components, the user may float the FREQ_CFG, VOUT_CFG, and
VTRIM_CFG pins which will cause the LTC3883 to default
to the respective parameters stored in NVM. The ASEL pin
should always be programmed with a resistor divider to
safeguard against a lost device address by the host.
To externally program the RCONFIG pins connect a resistor
divider between the VDD25 and GND of the LTC3883. The
RCONFIG pins are only monitored at initial power up and
during a reset so modifying their values perhaps using an
A/D after the part is powered will have no effect. 1% resistors or better must be used to assure proper operation.
Noisy clock signals should not be routed near these pins.
Voltage Selection
When an output voltage is set using the RCONFIG pins
on VOUT_CFG and VTRIM_CFG, the following parameters
are set as a percentage of the output voltage:
• VOUT_OV_FAULT_LIMIT
+10%
• VOUT_OV_WARN_LIMIT +7.5%
• VOUT_MAX +7.5%
• VOUT_MARGIN_HIGH +5%
• POWER_GOOD_ON
–7%
• POWER_GOOD_OFF
–8%
• VOUT_MARGIN_LOW
–5%
• VOUT_UV_WARN_LIMIT –6.5%
• VOUT_UV_FAULT_LIMIT –7%
Refer to Tables 12 and 13 to set the output voltage using RCONFIG pins VOUT_CFG and VTRIM_CFG. RTOP is
connected between VDD25 and the pin and RBOTTOM is
connected between the pin and SGND. 1% resistors must
be used to assure proper operation.
The output voltage set point is equal to:
VSETPOINT = VOUT_CFG + VTRIM_CFG
For example, if the VOUT_CFG pin has RTOP equal to 24.9k
and RBOTTOM equal to 4.32k, and VTRIM_CFG is set with
RTOP not inserted and RBOTTOM equal to 0Ω:
VSETPOINT = 1.1V – 0.099V or 1.001V
If odd values of output voltage are required from 0.5V to
3.3V, use only the VOUT_CFG resistor divider, the VTRIM
pin can be open or shorted to VDD25. If the output set
point is 5V, the VOUT_CFG must have RTOP equal to 10k
and RBOTTOM equal to 23.2k and VTRIM_CFG must have
RTOP equal to 20k and RBOTTOM equal to 11k.
Programming the output voltage with the RCONFIG pins
will automatically set the part to low or high range. Any
VOUT voltage at 2.5V or below will be set to low range. All
voltages above 2.5V will be set to high range.
Rev. F
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51
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
Table 12. VOUT_CFG
Table 13. VTRIM_CFG
RTOP (kΩ)
RBOTTOM (kΩ)
VOUT (V)
0 or Open
Open
NVM
10
23.2
See VTRIM
10
15.8
3.3
16.2
20.5
3.1
16.2
17.4
2.9
20
17.8
2.7
20
15
2.5
20
12.7
2.3
20
11
2.1
24.9
11.3
1.9
24.9
9.09
1.7
24.9
7.32
1.5
24.9
5.76
1.3
24.9
4.32
1.1
30.1
3.57
0.9
30.1
1.96
0.7
Open
0
0.5
VTRIM (mV)
CHANGE TO
VSET VOLTAGE
RTOP (kΩ)
RBOTTOM (kΩ)
0 or Open
Open
0
10
23.2
99
10
15.8
86.625
16.2
20.5
74.25
16.2
17.4
61.875
VOUT (V)
IF VOUT HAS
10kΩ/23.3kΩ
20
17.8
49.5
20
15
37.125
5.5
20
12.7
24.75
5.25
20
11
12.375
5
24.9
11.3
–12.375
4.75
24.9
9.09
–24.75
4.5
24.9
7.32
–37.125
4.25
24.9
5.76
–49.5
4
24.9
4.32
–61.875
3.75
30.1
3.57
–74.25
3.63
30.1
1.96
–86.625
3.5
Open
0
–99
3.46
Table 14. FREQ_CFG (Phase Based on Falling Edge of SYNC)
RTOP (kΩ)
0 or Open
10
10
16.2
16.2
20
20
20
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
RBOTTOM (kΩ)
Open
23.2
15.8
20.5
17.4
17.8
15
12.7
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
FREQUENCY (kHz)
NVM
250
250
250
425
425
425
500
500
575
575
575
650
650
650
External Clock
θSYNC TO θ0
NVM
0
120
180
0
120
180
0
180
0
120
180
0
120
180
0
DESCRIPTION
NVM
2-Phase
3-Phase
2-Phase
2-Phase
3-Phase
2-Phase
2-Phase
2-Phase
2-Phase
3-Phase
2-Phase
2-Phase
3-Phase
2-Phase
2-Phase
Rev. F
52
For more information www.analog.com
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
Frequency and Phase Selection Using RCONFIG
The frequency and phase commands are linked if they
are set using the RCONFIG pins. If PMBus commands
are used the two parameters are independent. The SYNC
pins must be shared in poly-phase configurations where
multiple LTC3883s are used to produce the output. If
the configuration is not PolyPhase the SYNC pins do not
have to be shared. If the SYNC pins are shared between
LTC3883s only one SYNC pin can be set as a frequency
output, all other SYNC pins must be set to External Clock.
For example in a 2-phase configuration clocked at 425kHz,
one of the LTC3883s must be set to the desired frequency
and phase and the other LTC3883 must be set to External
Clock. All phasing is with respect to the falling edge of SYNC.
LTC3883 Chip 1 set the frequency to 425kHz with 180°
phase shift:
RTOP = 20kΩ and RBOTTOM = 15kΩ
LTC3883 Chip 2 set the frequency to External Clock with
0° phase shift:
RTOP = open and RBOTTOM = 0Ω
Frequencies of 350kHz, 750kHz and 1000kHz can only be
set using NVM programming. If a 6-phase configuration
is desired, NVM programming will give optimal phasing.
All other configurations in frequency and phasing can be
achieved using the FREQ_CFG pin.
Address Selection Using RCONFIG
The LTC3883 address may be selected using a combination
of the address stored in NVM and the ASEL pin. The three
MSBs of the device address are set by the three MSBs
stored in NVM, and four LSBs of the device address are
set by the ASEL pin. This allows 16 different LTC3883s
on a single board with one programmed address in NVM.
If the address stored in NVM is 0x4F, then the part address
can be set from 0x40 to 0x4F using ASEL. (The standard
default address is 0x4F). Do not set any part address to
0x5A or 0x5B because these are global addresses and all
parts will respond to them.
To choose address 0x40 RTOP is open and
RBOTTOM = 0Ω
To choose address 0x45 RTOP = 24.9k and
RBOTTOM = 7.32k
To choose address 0x4E RTOP = 10.0k and
RBOTTOM = 15.8k
Table 15A1. LTC3883 MFR_ADDRESS Command Examples
Expressing Both 7- or 8-Bit Addressing
HEX DEVICE
ADDRESS BIT BIT BIT BIT BIT BIT BIT BIT
DESCRIPTION 7 BIT 8 BIT 7 6 5 4 3 2 1 0 R/W
Rail4
0x5A 0xB4
0
1
0
1
1
0
1
0
0
Global4
0x5B 0xB6
0
1
0
1
1
0
1
1
0
Default
0x4F 0x9E
0
1
0
0
1
1
1
1
0
Example 1
0x60 0xC0
0
1
1
0
0
0
0
0
0
Example 2
0x61 0xC2
Disabled2,3,5
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
Note 1: This table can be applied to the MFR_RAIL_ADDRESS command
as well as the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), or
0x5A or 0x5B (7 bit) to the MFR_ADDRESS or the MFR_RAIL_ADDRESS
commands.
Note 5: To disable the address enter 0x80 in the MFR_ADDRESS
command. The 0x80 is greater than the 7-bit address field, disabling the
address.
Table 15. ASEL
RTOP (kΩ)
RBOTTOM (kΩ)
SLAVE ADDRESS
0 or Open
Open
NVM
LSB HEX
10
23.2
NVM (3MSBs)_1111
F
10
15.8
NVM (3MSBs)_1110
E
16.2
20.5
NVM (3MSBs)_1101
D
16.2
17.4
NVM (3MSBs)_1100
C
20
17.8
NVM (3MSBs)_1011
B
20
15
NVM (3MSBs)_1010
A
20
12.7
NVM (3MSBs)_1001
9
20
11
NVM (3MSBs)_1000
8
24.9
11.3
NVM (3MSBs)_0111
7
24.9
9.09
NVM (3MSBs)_0110
6
24.9
7.32
NVM (3MSBs)_0101
5
24.9
5.76
NVM (3MSBs)_0100
4
24.9
4.32
NVM (3MSBs)_0011
3
30.1
3.57
NVM (3MSBs)_0010
2
30.1
1.96
NVM (3MSBs)_0001
1
Open
0
NVM (3MSBs)_0000
0
Rev. F
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53
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
EFFICIENCY CONSIDERATIONS
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3883 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typically results in a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD . Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PolyPhase Configuration
When configuring a PolyPhase rail with multiple LTC3883s/
LTC3880s, the user must share the SYNC, ITH, SHARE_
CLK, GPIO, and ALERT pins of both parts. Be sure to use
pull-up resistors on GPIO, SHARE_CLK and ALERT. One of
the part's SYNC pin must be set to the desired switching
frequency, and all other FREQUENCY_SWITCH commands
must be set to External Clock. If an external oscillator is
provided, set the FREQUENCY_SWITCH command to
External Clock for all parts. The relative phasing of all
the channels should be spaced equally. The MFR_RAIL_
ADDRESS of all the devices should be set to the same value.
When connecting a PolyPhase rail with LTC3883s, connect the VIN pins of the 3883s directly back to the supply
voltage through the VIN pin filter networks. Refer to the
Typical Application circuit: High Efficiency 500kHz 2-Phase
1.8V Step-Down Converter with Sense Resistors.
Rev. F
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55
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
When connecting a 3-phase LTC3883/LTC3880, the VIN
pin and power stage of the LTC3880 should be connected
to the downstream side of the LTC3883 input current
sense resistor. This allows the user to measure the total
input current of the rail. Refer to the Typical Application
circuit: High Efficiency 3-Phase 350kHz 1.8V Step-Down
Converter with Input Current Sense. The inductor DCR for
all three inductors of LTC3883/LTC3880 application can
be calculated. The DCR auto calibration routine can be
performed on the LTC3883 phase by shutting down the
other two phases. The DCR of the inductors of the LTC3880
phases can be calculated using the READ_IIN value of
the LTC3883, and the MFR_READ_IIN of the LTC3880
phases. The user can shut down the other two phases
and adjust the IOUT_CAL_GAIN value of the respective
LTC3880 phase so that the active phase’s MFR_READ_IIN
= READ_IIN of the LTC3883.
The user may also calibrate the DCR of all three inductors
by only shutting down one phase at a time and leaving the
other two phases active, however the DCR auto calibration routine cannot be used for the LTC3883 phase. The
IOUT_CAL_GAIN value of all the inductors should be set
to the nominal DRC value, DCR_NOM prior to beginning
the procedure.
During the procedure, the circuit must be in a steady-state
load condition, with the converter in CCM and sufficient
load current to create a 6mV average signal across the
RIINSNS sense resistor, as well as 6mV across the output
current sense network. First, the user needs to record
the values of READ_IIN of the LTC3883 as well as the
READ_IOUT for all three phases. These values are referred
to as READ_IIN_A, READ_IOUT_1A, READ_IOUT_2A, and
READ_IOUT_3A.
Next, phase 1 should be shut off and the values for READ_
IIN of the LTC3883 and the READ_IOUT for the two active
phases need to be recorded. These values are referred to
as READ_IIN_B, READ_IOUT_2B, and READ_IOUT_3B.
To calculate the DCR of phase 1:
Verify that READ_IIN_A = READ_IIN_B
The actual current of phase 1, IOUT_1A is calculated by:
IOUT_1A = READ_IIN_A – READ_IIN_A •
{(READ_IOUT_2A + READ_IOUT_3A)/(READ_
IOUT_2B + READ_IOUT_3B)
The actual DCR of the phase 1 inductor is calibrated to
the correct value by:
DCR_CAL = DCR_NOM • (IOUT_1A/READ_IOUT_A)
The user then needs to update the IOUT_CAL_GAIN command value with the calibrated value of inductor DCR,
DCR_CAL.
The above procedure can then be repeated to determine
the inductor DCR for phases 2 and 3.
Reference the subsection titled Inductor DCR Auto Calibration in the Applications Information section for further
detail regarding the operating conditions that must be met
to accurately calculate the inductor DCR.
When configuring a PolyPhase rail with a LTC3883 and
multiple LTC3870s, the user must share the ITH and
GPIO/FAULT pins of all parts. Bit 12 VOUT_UVUF of the
MFR_GPIO_PROPAGATE_LTC3883 command must be
set to 0. If the GPIO pin of the LTC3883 must be used for
sequencing, and bit 12 of MFR_GPIO_PROPAGATE is set
to a 1, tie the FAULT pins of the LTC3870 high with a 10k
pull-up resistor to either VDD33 or INTVCC of the LTC3870.
If the LTC3870 phases require discontinuous mode during startup and continuous mode thereafter, connect the
MODE pins of the LTC3870 to the LTC3883 PGOOD pin.
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 26. Figure 27 illustrates the current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET, M1, located within 1cm
of CIN?
Rev. F
56
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
RIINSNS
VIN
RIIN
RIIN
IIN_SNS
TSNS
VIN_SNS
Q1
LTC3883
C1
RVIN
ISENSE+
ISENSE–
VIN
CVIN
L
TG
SW
CB
BOOST
SYNC
RUN
VSENSE+
VSENSE–
1µF
CERAMIC
INTVCC
ITH
GND
GND
+
CINTVCC
CIN
VOUT
M2
D1
COUT
+
+
VDD33
VDD25
M1
BG
RSENSE
3883 F26
Figure 26. Recommended Printed Circuit Layout Diagram
RIN
SW
RSENSEIN
VIN
CIN
L
D
RSENSE
VOUT
COUT
RL
3883 F27
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
CURRENT WAVFORM
AT NODE
Figure 27. Branch Current Waveforms
2. Are ground and power ground kept separate? The
combined IC ground pin and the ground return of CINTVCC
must return to the combined COUT (–) terminals. The ITH
trace should be as short as possible. The path formed by
the top N-channel MOSFET, Schottky diode and the CIN
capacitor should have short leads and PC trace lengths.
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor by placing the capacitors next to each other
and away from the Schottky loop described above.
3. Are the ISENSE+ and ISENSE– leads routed together with
minimum PC trace spacing? The filter capacitor between
ISENSE+ and ISENSE– should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
Rev. F
For more information www.analog.com
57
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
4. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET driver current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance substantially.
5. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feed-back pins. All of these nodes have very large and
fast moving signals and therefore should be kept on the
“output side” of the LTC3883 and occupy minimum PC
trace area. If DCR sensing is used, place the top resistor
(Figure 18a, R1) close to the switching node.
6. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the GND pin of the IC.
7. Are the VIN_SNS and IIN_SNS filters Kelvin connected
to the RSENSEIN sense resistor? This will prevent the
PCB trace resistance from causing errors in the input
current measurement. These traces should be as short
as possible and routed away from any noisy nodes such
as the switching or boost nodes.
8. Is the VIN filter Kelvin connected to the input side of
the RSENSEIN resistor? This can help improve the noise
performance of the input current sense amplifier by
reducing the voltage transients between the amplifier
inputs and amplifier supply caused by the discontinuous
power stage current.
PC BOARD LAYOUT DEBUGGING
It is helpful to use a DC-50MHz current probe to monitor the
current in the inductor while testing the circuit. Monitor the
output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the operating voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
DESIGN EXAMPLE
As a design example for a medium current regulator, assume VIN = 12V nominal, VIN = 20V maximum, VOUT =
3.3V, IMAX = 15A and f = 500kHz (see Figure 28).
The regulated output is established by the VOUT_
COMMAND stored in NVM or placing the following resistor divider between VDD25 the RCONFIG pin and SGND:
1. VOUT_CFG, RTOP = 10k, RBOTTOM = 15.8 k
2. VTRIM_CFG, Open
Rev. F
58
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
5mΩ
VIN
6V TO 20V
10µF
D4
INTVCC
100Ω
1µF
10nF
TG
100Ω
LTC3883
BOOST
IIN_SNS
VIN_SNS
10nF
0.1µF
22µF
50V
1µF
M1
1.0µH
SW
M2
BG
PGND
3Ω
10k
10µF
10k
PMBus
INTERFACE
10k
10k
10k
10k
10k
5k
VDD33
VIN
2.2k
0.2µF
FREQ_CFG
PGOOD VOUT_CFG
SDA
VTRIM_CFG
SCL
ASEL
WP
ALERT
RUN
SHARE_CLK
GPIO
SYNC
ISENSE+
ISENSE–
VDD25
VSENSE–
VDD33
TSNS
ITH
GND
1.0µF
VOUT
3.3V
15A
COUT
530µF
6V
VSENSE+
1.0µF
+
2200pF
6.04k
MMBT3906
10nF
3883 F28
COUT: 330μH SANYO 4TPF330ML, 2× 100µF AVX 12106D107KAT2A
L: COILCRAFT XPL7070 1µH
M1: INFINEON BSC050NE2LS
M2: INFINEON BSC010NE2LSI
Figure 28. High Efficiency 500kHz 3.3V Step-Down Converter
The frequency and phase are set by NVM or by setting
the resistor divider between VDD25 FREQ_CFG and GND
with RTOP = 20k and RBOTTOM = 12.7k. The address is set
to XF where X is the MSB stored in NVM.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
n
n
n
n
n
n
n
n
n
VOUT_OV_FAULT_LIMIT..................................... +10%
VOUT_OV_WARN_LIMIT................................... +7.5%
VOUT_MAX....................................................... +7.5%
VOUT_MARGIN_HIGH..........................................+5%
POWER_GOOD_ON..............................................–7%
POWER_GOOD_OFF.............................................–8%
VOUT_MARGIN_LOW...........................................–5%
VOUT_UV_WARN_LIMIT...................................–6.5%
VOUT_UV_FAULT_LIMIT.......................................–7%
All other user defined parameters must be programmed
into the NVM. The GUI can be utilized to quickly set up
the part with the desired operating parameters.
The inductance values are based on a 35% maximum ripple
current assumption (5.25A). The highest value of ripple
current occurs at the maximum input voltage:
L=
⎡
VOUT ⎤
⎢1–
⎥
f • ∆IL(MAX) ⎢⎣ VIN(MAX) ⎥⎦
VOUT
The controller will require 1.05µH. The nearest standard
value is 1µH. At the nominal input the ripple will be:
⎡
V
VOUT ⎤
⎥
∆IL(NOM) = OUT ⎢1–
f • L ⎢⎣ VIN(NOM) ⎥⎦
Rev. F
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59
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
The ripple will be 4.79A (32%). The peak inductor current
will be the maximum DC value plus one-half the ripple
current or 17.39A. The minimum on time occurs at the
maximum VIN, and should not be less than 45ns:
tON(MIN) =
VOUT
VIN(MAX) • f
=
1.8V
20V ( 500kHz )
PMAIN =
The loss in the bottom side MOSFET is:
PSYNC =
Assuming the temperature measurement of the inductor
temperature is accurate and C1 is set to 0.2µF, RD is infinite
and removed from the equations.
R1=
L
(DCR
at 25°C ) • C1
=
1µH
2.5mΩ • 0.2µF
= 1.37k
The maximum power loss in R0 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
( VIN(MAX) – VOUT ) • VOUT
R1=
PLOSS
=
R1
( 20 – 1.8 ) • 1.8
1.37k
( 20V – 1.8V )
The current limit will be set 20% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
VILIMIT = IPEAK • RDCR(MAX) = 17.39A • 2.5mΩ = 43mV
The closest VILIMIT setting is 42.9mV or 46.4mV. The values
are entered with the IOUT_OC_FAULT_LIMIT command.
Based on expected variation and measurement in the lab
across the sense capacitor the user can determine the
optimal setting.
The power dissipation on the topside MOSFET can be
easily estimated. Choose a M1: INFINEON BSC050NE2LS
topside MOSFET. RDS(ON) = 5.7mΩ, CMILLER = 35pF. At
maximum input voltage with T estimated = 50°C and a
bottom side MOSFET a M2: INFINEON BSC010NE2LSI,
RDS(ON) = 1.1mΩ:
20V
2
• ( 17.25A ) •
⎡⎣ 1+ ( 0.005 ) ( 50°C – 25°C ) ⎤⎦ • 1.1mΩ
= 0.335W
Both MOSFETS have I2R losses while the PMAIN equation
includes an additional term for transition losses, which
are highest at high input voltages.
CIN is chosen for an RMS current rating of:
CIN Required IRMS =
= 23.91mW
2
• ( 17.25 ) • ⎡⎣ 1+ ( 0.005 ) ( 50°C – 25°C ) ⎤⎦
20V
1 ⎞
⎛ 1
2
+
• 5.7mΩ + ( 20V ) ( 8.695A ) • ⎜
⎝ 5 – 2.3 2.3 ⎟⎠
( 35pF ) ( 500kHz ) = 0.221W
= 180ns
The Vishay IHLP4040DZ-11 1µH (2.3mΩ DCRTYP at 25°C)
is the chosen inductor.
1.8V
17.25
20
= 4.9A
1/2
⎡⎣(1.8 ) • ( 20 – 1.8 )⎤⎦
at temperature. COUT is chosen with an ESR of 0.006Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is
VORIPPLE = R(∆IL) = 0.006Ω • 5.5A = 33mV.
CONNECTING THE USB TO I2C/SMBus/PMBus
CONTROLLER TO THE LTC3883 IN SYSTEM
The ADI USB to I2C/SMBus/PMBus controller can be
interfaced to the LTC3883 on the user’s board for programming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay, provides a
powerful way to debug an entire power system. Faults are
quickly diagnosed using telemetry, fault status commands
and the fault log. The final configuration can be quickly
developed and stored to the LTC3883 EEPROM.
Figure 29 illustrates the application schematic for powering, programming and communication with one or more
LTC3883s via the ADI I2C/SMBus/PMBus controller
regardless of whether or not system power is present.
Rev. F
60
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
VIN
LTC
CONTROLLER
HEADER
ISOLATED
3.3V
SDA
100k
100k
VIN
VDD33
TP0101K
SCL
1µF
10k
VDD25
LTC3883
1µF
SDA
10k
SCL
WP SGND
TO LTC DC1613
USB TO I2C/SMBus/PMBus
CONTROLLER
VIN
TP0101K
VDD33
1µF
VDD25
LTC3883
1µF
SDA
VGS MAX ON THE TP0101K IS 8V IF VIN > 16V
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
SCL
WP SGND
3883 F29
Figure 29. ADI Controller Connection
If system power is not present the dongle will power the
LTC3883 through the VDD33 supply pin. To initialize the
part when VIN is not applied and the VDD33 pin is powered
use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4. The
part can now be communicated with, and the project file
updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied,
a MFR_RESET must be issued to allow the PWM to be
enabled and valid ADCs to be read.
Because of the controllers limited current sourcing capability, only the LTC3883s, their associated pull-up resistors
and the I2C pull-up resistors should be powered from the
ORed 3.3V supply. In addition any device sharing the I2C
bus connections with the LTC3883 should not have body
diodes between the SDA/SCL pins and their respective
VDD node because this will interfere with bus communication in the absence of system power. If VIN is applied the
dongle will not supply the LTC3883s on the board. It is
recommended the RUN pins be held low to avoid providing
power to the load until the part is fully configured.
The ADI controller I2C connections are opto-isolated from
the PC USB. The 3.3V from the controller and the LTC3883
VDD33 pin must be driven to each LTC3883 with a separate
PFET. If VIN is not applied, the VDD33 pins can be in parallel
because the on-chip LDO is off. The controller 3.3V current limit is 100mA but typical VDD33 currents are under
15mA. The VDD33 does back drive the INTVCC/EXTVCC pin.
Normally this is not an issue if VIN is open.
INDUCTOR DCR AUTO CALIBRATION
Using the DC resistance of the inductor as a current shunt
element has several advantages—no additional power
loss, lower circuit complexity and cost. However any
error between the specified nominal inductor DCR value
and the actual DCR value will cause a proportional error
in the peak current limit, as well as the output current
read-back value. The LTC3883 can calibrate the inductor
DCR value to compensate for the tolerance from its typical
value. Setting bit 3 of the MFR_PWM_MODE_3883 command will start the calibration procedure. To successfully
complete the calibration procedure, the PWM must be
enabled, the DUTY_CYCLE value must be at least 3%, the
READ_IIN value must be at least 10mA, and the calibrated
IOUT_CAL_GAIN must be with ±30% of the uncalibrated
IOUT_CAL_GAIN value. If any of the above conditions are
not met, bit 0 of the STATUS_CML command will be set,
and the value of IOUT_CAL_GAIN will not be changed.
Rev. F
For more information www.analog.com
61
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
During the inductor DCR calibration the supply voltage,
output voltage, and load current must be in a steady state
condition for 160ms during the command execution to
ensure accurate calibration. The load current should be
sufficiently large to create at least a 6mV average signal
across the RIINSNS sense resistor as well as 6mV across
the output current sense network in order to ensure that
the READ_IIN and READ_IOUT values used in the DCR
calibration calculation are within 1% TUE. The inductor
DCR is calibrated by multiplying the measured READ_IIN
value by the measured READ_DUTY_CYCLE value to obtain
a calculated output current. The LTC3883 then updates the
IOUT_CAL_GAIN value so that the measured READ_IOUT
value matches the calculated output current value that is
based on power stage input current and duty cycle, so
that READ_IOUT • DUTY_CYCLE = READ_IIN.
ACCURATE DCR TEMPERATURE COMPENSATION
Using the DC resistance of the inductor as a current shunt
element has several advantages—no additional power loss,
lower circuit complexity and cost. However, the strong
temperature dependence of the inductor resistance and
the difficulty in measuring the exact inductor core temperature introduce errors in the current measurement.
For copper, a change of inductor temperature of only 1°C
corresponds to approximately 0.39% current gain change.
Figure 30 shows a DC/DC converter sample layout (right)
and its corresponding thermal image (left). The converter
is providing 1.8V, 1.5A to the output load.
Heat dissipation in the inductor under high load conditions creates transient and steady state thermal gradients
between the inductor and the temperature sensor, and the
sensed temperature does not accurately represent the
inductor core temperature. This temperature gradient is
clearly visible in the thermal image of Figure 30. In addition,
transient heating/cooling effects have to be accounted for
in order to reduce the transient errors introduced when
load current changes are faster than heat transfer time
constants of the inductor. Both of these problems are
addressed by introducing two additional parameters: the
thermal resistance θIS from the inductor core to the onboard temperature sensor, and the inductor thermal time
constant τ. The thermal resistance θIS [°C/W], is used to
calculate the steady-state difference between the sensed
temperature TS and the internal inductor temperature TI
for a given power dissipated in the inductor PI:
TI – TS = θIS PI = θIS VDCR IOUT
The additional temperature rise is used for a more accurate
estimate of the inductor DC resistance RI:
RI = R0 (1 + a [TS – TREF + θIS VDCR IOUT])
In the equations above, VDCR is the inductor DC voltage
drop, IOUT is the RMS value of the output current, R0 is
DC/DC
CONVERTER
INDUCTOR
TEMPERATURE
SENSOR
3883 F30
Figure 30. Thermal Image and Layout Photo
Rev. F
62
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LTC3883/LTC3883-1
APPLICATIONS INFORMATION
the inductor DC resistance at the reference temperature
TREF and α is the temperature coefficient of the resistance.
Since most inductors are made of copper, we can expect
a temperature coefficient close to αCU = 3900ppm/°C.
For a given α, the remaining parameters θIS and R0 can
be calibrated at a single temperature using only two load
currents:
RO =
θIS =
(R2 – R1) (P2 + P1) – (R2 + R1) (P2 – P1)
a ( T2 – T1) (P2 + P1) – (P2 – P1) ( 2 + a [ T1+ T2 – 2TREF ] )
1
aRO
•
a (R1+ R2 ) ( T2 – T1) – (R2 – R1) ( 2 + a [ T1+ T2 – 2TREF ] )
a ( T2 – T1) (P2 + P1) – (P2 – P1) ( 2 + a [ T1+ T2 – 2TREF ] )
The inductor resistance, RK = VDCR(K)/IOUT(K), power dissipation PK = VDCR(K) IOUT(K) and the sensed temperature
TK, (K = 1, 2) are recorded for each load current. To increase
the accuracy in calculating θIS, the two load currents should
be chosen around I1 = 10% and I2 = 90% of the current
range of the system.
The inductor thermal time constant τ models the first order
thermal response of the inductor and allows accurate DCR
compensation during load transients. During a transition
from low-to-high load current, the inductor resistance
increases due to the self-heating. If we apply a single load
step from the low current I1 to the higher current I2, the
voltage across the inductor will change instantaneously
from I1R1 to I2R1 and then slowly approach I2R2. Here R1
is the steady-state resistance at the given temperature and
load current I1, and R2 is the slightly higher DC resistance
at I2, due to the inductor self-heating. Note that the electrical time constant τEL = L/R is several orders of magnitude
shorter than the thermal one, and “instantaneous” is relative to the thermal time constant. The two settled regions
give us the data sets (I1, T1, R1, P1) and (I2, T2, R2, P2)
and the 2-point calibration technique (1.3-1.4) is used to
extract the steady-state parameters θIS and R0 (given a
previously characterized average α). The relative current
error calculated using the steady-state expression (1.2)
will peak immediately after the load step, and then decay
to zero with the inductor thermal time constant τ.
∆I
I
( t ) = a θIS ( V2 I 2 – V1I 1) e – t/ τ
The time constant τ is calculated from the slope of the
best-fit line y = ln(∆I/I) = a1 + a2t:
τ=–
1
a2
In summary, a single load current step is all that is needed
to calibrate the DCR current measurement. The stable portions of the response give us the thermal resistance θIS and
nominal DC resistance R0, and the settling characteristic
is used to measure the inductor thermal time constant τ.
To get the best performance, the temperature sensor has
to be as close as possible to the inductor and away from
other significant heat sources. For example in Figure 30,
the bipolar sense transistor is close to the inductor and
away from the switcher. Connecting the collector of the
PNP to the local power ground plane assures good thermal
contact to the inductor, while the base and emitter should
be routed to the LTC3883 separately, and the base connected to the signal ground close to LTC3883.
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay is a powerful Windows-based development
environment that supports Linear Technology digital
power ICs including the LTC3883. The software supports
a variety of different tasks. LTpowerPlay can be used to
evaluate Linear Technology ICs by connecting to a demo
board or the user application. LTpowerPlay can also be
used in an offline mode (with no hardware present) in
order to build multiple IC configuration files that can be
saved and re-loaded at a later time. LTpowerPlay provides
unprecedented diagnostic and debug features. It becomes
a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power
issues when bring up rails. LTpowerPlay utilizes Linear
Technology’s USB-to-I2C/SMBus/PMBus controller to
communication with one of the many potential targets
including the DC1778A demo board, the DC1890A socketed programming board, or a customer target system.
The software also provides an automatic update feature
to keep the revisions current with the latest set of device
Rev. F
For more information www.analog.com
63
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
Figure 31. LTpowerPlay Screen Shot
drivers and documentation. A great deal of context sensitive help is available with LTpowerPlay along with several tutorial demos. Complete information is available at
http://www.linear.com/ltpowerplay.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC3883/LTC3883-1 have a one deep buffer to hold
the last data written for each supported command prior
to processing as shown in Figure 32; Write Command
Data Processing. When the part receives a new command
from the bus, it copies the data into the Write Command
Data Buffer, indicates to the internal processor that this
command data needs to be fetched, and converts the
command to its internal format so that it can be executed.
Two distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute) to
CMD
PMBus
WRITE
WRITE COMMAND
DATA BUFFER
DECODER
CMDS
DATA
MUX
CALCULATIONS
PENDING
S
R
PAGE
•
•
•
VOUT_COMMAND
0x00
0x21
•
•
•
MFR_RESET
INTERNAL
PROCESSOR
FETCH,
CONVERT
DATA
AND
EXECUTE
0xFD
x1
3883 F32
Figure 32. Write Command Data Processing
ensure the last data written to any command is never lost.
Command data buffering handles incoming PMBus writes
by storing the command data to the Write Command Data
Buffer and marking these commands for future processing. The internal processor runs in parallel and handles
the sometimes slower task of fetching, converting and
executing commands marked for processing.
Rev. F
64
For more information www.analog.com
LTC3883/LTC3883-1
APPLICATIONS INFORMATION
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x70) == 0x70;
}while(!partReady)
Figure 33. Example of a Command Write of VOUT_COMMAND
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long relative
to PMBus timing. If the part is busy processing a command,
and new command(s) arrive, execution may be delayed
or processed in a different order than received. The part
indicates when internal calculations are in process via bit 5
of MFR_COMMON (‘calculations not pending’). When the
part is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 33 which ensures that
commands are processed in order while simplifying error
handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7 and
SMBus v2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3883. Clock
stretching will only occur if enabled and the bus communication speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat complex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON command. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON (‘chip
not busy’). When the part is busy specifically because it
is in a transitional VOUT state (margining hi/lo, power off/
on, moving to a new output voltage set point, etc.) it will
clear bit 4 of MFR_COMMON (‘output not in transition’).
When internal calculations are in process, the part will clear
bit 5 of MFR_COMMON (‘calculations not pending’). These
three status bits can be polled with a PMBus read byte of
the MFR_COMMON command until all three bits are set. A
command immediately following the status bits being set
will be accepted without NACKing or generating a BUSY
fault/ALERT notification. The part can NACK commands
for other reasons, however, as required by the PMBus spec
(for instance, an invalid command or data). An example
of a robust command write algorithm for the VOUT_
COMMAND register is provided in Figure 31.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to
the application note TBD “Implementing Robust PMBus
System Software” located at www.linear.com/designtools/
app_notes.
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Part II, Section 10.8.7 is required to communicate above
100kHz without clock stretching. Clock stretching will not
enable the LTC3883 to communicate properly when the bus
speed exceeds the specified 400kHz maximum frequency.
The LTC3883 is not recommended in applications where
the PMBus speed exceeds 400kHz.
Rev. F
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65
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
COMMAND NAME
PAGE
WRITE_PROTECT
MFR_ADDRESS
MFR_RAIL_ADDRESS
CMD
CODE DESCRIPTION
0x00 Provides integration with multi-page PMBus devices.
0x10 Level of protection provided by the device against
accidental changes.
0xE6 Sets the 7-bit I2C address byte.
0xFA Common address for PolyPhase outputs to adjust
common parameters.
DATA
TYPE
FORMAT
R/W Byte
Reg
R/W Byte
Reg
R/W Byte
R/W Byte
Reg
Reg
UNITS
Y
DEFAULT
VALUE
0x00
0x00
Y
Y
0x4F
0x80
NVM
PAGE
The LTC3883 only supports a PAGE value of 0x00 or 0xFF. Any other value will generate a CML fault. The page command
is included to provide integration with multi-page PMBus devices. There are no restrictions as to what commands can
be written or read when PAGE is set to 0xFF.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC3883 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command unless the WRITE_PROTECT command is more stringent.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL command.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_FAULTS
commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS
commands.
Rev. F
66
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTC3883 will use the address value stored in NVM.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC3883 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT UNITS
NVM
DEFAULT
VALUE
MFR_CHAN_CONFIG_LTC3883
0xD0
Configuration bits that are channel specific.
R/W Byte
Reg
Y
0x1F
MFR_CONFIG_ALL_LTC3883
0xD1
General configuration bits.
R/W Byte
Reg
Y
0x09
MFR_CHAN_CONFIG_LTC3883
General purpose configuration command common to multiple ADI products.
BIT
MEANING
7
Reserved
6
Reserved
5
Reserved
4
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF
3
Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120mS
is honored then the part will command ON.
2
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled
1
No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally.
0
Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than
12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low
to high.
This command has one data byte.
Rev. F
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67
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_CONFIG_ALL_LTC3883
General purpose configuration command common to multiple ADI products
BIT
MEANING
7
Enable Fault Logging
6
Ignore Resistor Configuration Pins
5
Reserved
4
Fast (35ms) TINIT
3
Mask PLL Unlock Fault
2
PMBus command writes require a valid Packet Error Checking, or PEC,
byte to be accepted.*
1
Enable the use of PMBus clock stretching
0
Reserved
*PMBus command writes that have a valid PEC byte are always processed.
PMBus command writes that have an invalid PEC byte are not processed and set
a CML status fault.
This command has one data byte.
ON/OFF/MARGIN
COMMAND NAME
CMD
CODE
DESCRIPTION
ON_OFF_CONFIG
0x02
RUN pin and PMBus bus on/off command configuration.
OPERATION
0x01
MFR_RESET
0xFD
TYPE
DATA
FORMAT UNITS
NVM
DEFAULT
VALUE
R/W Byte
Reg
Y
0x1E
Operating mode control. On/off, margin high and margin low.
R/W Byte
Reg
Y
0x80
Commanded reset without requiring a power-down.
Send Byte
NA
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of RUN pin input and serial bus commands needed to
turn the unit on and off. This includes how the unit responds when power is applied.
Table 3. Supported Values
VALUE
MEANING
0x1F
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
0x1E
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_command values when commanded off.
0x17
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
0x16
RUNn pin control using TOFF_command values when commanded off. OPERATION on/off control ignored.
Note: A high on the RUN pin is always required to start power conversion. Power conversion will always stop with a low on RUN.
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
Rev. F
68
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUN pin. It is also
used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUN pin instructs the
device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON
cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW,
the output will move at a fixed slope set by the VOUT_TRANSITION_RATE.
Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTC3883.
The part defaults to the ON state.
This command has one data byte.
Table 4. OPERATION Command Detail Command
OPERATION Data Contents When On_Off_Config_Use_PMBus Enables
Operation_Control
SYMBOL
ACTION
VALUE
BITS
Turn off immediately
0x00
Turn on
0x80
FUNCTION Margin Low
0x98
Margin High
0xA8
Sequence off
0x40
OPERATION Data Contents When On_Off_Config is Configured Such That
OPERATION Command is Not Used to Command Channel On or Off
SYMBOL
ACTION
VALUE
BITS
Output at Nominal
0x80
FUNCTION Margin Low
0x98
Margin High
0xA8
Note: Attempts to write a reserved value will cause a CML fault.
Rev. F
For more information www.analog.com
69
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_RESET
This command provides a means by which the user can perform a reset of the LTC3883.
This write-only command has no data bytes.
PWM CONFIGURATION
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
DEFAULT
FORMAT UNITS NVM VALUE
MFR_PWM_MODE_
LTC3883
0xD4
Configuration for the PWM engine.
R/W Byte
Reg
Y
0xD2
MFR_PWM_CONFIG_
LTC3883
0xF5
Set numerous parameters for the DC/DC controller including
phasing.
R/W Byte
Reg
Y
0x10
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
R/W Word
L11
Y
350
0xFABC
kHz
MFR_PWM_MODE_LTC3883
The MFR_PWM_MODE_LTC3883 command allows the user to program the PWM controller to use Burst Mode operation,
discontinuous (pulse-skipping mode), or forced continuous conduction mode.
BIT
MEANING
7
0b
1b
Use High Range of ILIMIT
Low Current Range
High Current Range
6
Enable Servo Mode
[5:4]
00b
01b
10b
READ_IIN Gain Setting
2x Gain, 50mV Max Input
4x Gain, 20mV Max Input
8x, Gain, 8mV Max Input
3
Start DCR Auto Calibration
2
Reserved
Bit[1:0]
00b
01b
10b
Mode
Discontinuous
Burst Mode Operation
Forced Continuous
Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this
command.
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is
active may have detrimental system results.
Bit [6] The LTC3883 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
Bit[5:4] set the READ_IIN gain and range setting of the input current sense amplifier.
Rev. F
70
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Bit[3] Setting this bit to a 1 starts the patent pending inductor DCR auto calibration to determine the DCR of the inductor. This will update the value of IOUT_CAL_GAIN using the READ_IIN, READ_IOUT, and DUTY_CYCLE values.
IOUT_CAL_GAIN is adjusted so that READ_IOUT • DUTY_CYCLE = READ_IIN. The auto calibration procedure will only
complete successfully if the following conditions are met.
1) The PWM is enabled
2) DUTY_CYCLE is at least 3%
3) READ_IIN is at least 10mA
4) The calibrated IOUT_CAL_GAIN is within ±30% of the uncalibrated IOUT_CAL_GAIN
If any of the above conditions are not met, bit 0 of the STATUS_CML command will be set, and the value of IOUT_
CAL_GAIN will not be changed. Bit[3] must then be reset to a 0 by the user. A STORE_USER_ALL command must be
issued to store the updated IOUT_CAL_GAIN value into NVM.
Bit[1:0] determine the PWM mode of operation.
This command has one data byte.
MFR_PWM_CONFIG_LTC3883
The MFR_PWM_CONFIG_LTC3883 command sets the switching frequency and phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. The RUN pin must be low
or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be
ignored and a BUSY fault will be asserted. Bit 6 of this command affects the loop gain of the PWM output which may
require modifications to the external compensation network.
BIT
MEANING
7
Reserved, set to 0.
6
If VOUT RANGE = 1, the maximum output voltage is 2.75V.
If RANGE = 0, the maximum output voltage is 5.5V.
5
Reserved
4
Share Clock Enable : If this bit is 1, the SHARE_CLK pin
will not be released until VIN > VIN_ON. The SHARE_CLK
pin will be pulled low when VIN < VIN_OFF. If this bit is
0, the SHARE_CLK pin will not be pulled low when VIN <
VIN_OFF except for the initial application of VIN.
3
Reserved, set to 0
BIT [2:0]
Phase Offset
000b
0
001b
90
010b
180
011b
270
100b
60
101b
120
110b
240
111b
300
This command has one data byte.
Rev. F
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71
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device.
Supported Frequencies:
VALUE [15:0]
0x0000
0xF3E8
0xFABC
0xFB52
0xFBE8
0x023F
0x028A
0x02EE
0x03E8
RESULTING FREQUENCY (TYP)
External Oscillator
250kHz
350kHz
425kHz
500kHz
575kHz
650kHz
750kHz
1000kHz
The part must be in the OFF state to process this command. The RUN pin must be low or the part must be commanded
off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be
asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as
the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage and Limits
COMMAND NAME
TYPE
DATA FORMAT
UNITS
NVM
DEFAULT VALUE
VIN_OV_FAULT_ LIMIT
CMD CODE DESCRIPTION
0x55
Input supply overvoltage fault limit.
R/W
Word
L11
V
Y
15.5
0xD3E0
VIN_UV_WARN_LIMIT
0x58
Input supply undervoltage warning limit.
R/W
Word
L11
V
Y
6.3
0xCB26
VIN_ON
0x35
Input voltage at which the unit should start
power conversion.
R/W
Word
L11
V
Y
6.5
0xCB40
VIN_OFF
0x36
Input voltage at which the unit should stop
power conversion.
R/W
Word
L11
V
Y
6.0
0xCB00
MFR_RVIN
0xF7
The resistance value of the VIN pin filter
element in milliohms
R/W
Word
L11
mΩ
Y
3000
0x12EE
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the measured input voltage, in volts, that causes an input
overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of the input voltage that causes an input undervoltage warning.
The warning is detected with the A/D converter resulting in latency up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. F
72
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
VIN_ON
The VIN_ON command sets the input voltage, in volts, at which the unit should start power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in volts, at which the unit should stop power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_RVIN
The MFR_RVIN command is used to set the resistance value of the VIN pin filter element in milliohms. (See also
READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
COMMAND NAME
VOUT_MODE
CMD CODE DESCRIPTION
0x20
Output voltage format and exponent (2–12).
TYPE
R Byte
DATA
FORMAT
Reg
UNITS
NVM
L16
V
Y
L16
V
Y
VOUT_MAX
0x24
VOUT_OV_FAULT_ LIMIT
0x40
Upper limit on the commanded output voltage R/W Word
including VOUT_MARGIN_HIGH
Output overvoltage fault limit.
R/W Word
VOUT_OV_WARN_ LIMIT
0x42
Output overvoltage warning limit.
R/W Word
L16
V
Y
VOUT_MARGIN_HIGH
0x25
R/W Word
L16
V
Y
VOUT_COMMAND
0x21
Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
Nominal output voltage set point.
R/W Word
L16
V
Y
VOUT_MARGIN_LOW
0x26
R/W Word
L16
V
Y
VOUT_UV_WARN_ LIMIT
0x43
Margin low output voltage set point. Must be
less than VOUT_COMMAND.
Output undervoltage warning limit.
R/W Word
L16
V
Y
VOUT_UV_FAULT_ LIMIT
0x44
Output undervoltage fault limit.
R/W Word
L16
V
Y
POWER_GOOD_ON
0x5E
R/W Word
L16
V
Y
POWER_GOOD_OFF
0x5F
R/W Word
L16
V
Y
MFR_VOUT_MAX
0xA5
Output voltage at or above which a power
good should be asserted.
Output voltage at or below which a power
good should be de-asserted.
Maximum allowed voltage command
including VOUT_OV_FAULT_LIMIT.
R Word
L16
V
DEFAULT
VALUE
2–12
0x14
5.5
0x5800
1.1
0x119A
1.075
0x1133
1.05
0x10CD
1.0
0x1000
0.95
0x0F33
0.925
0x0ECD
0.9
0x0E66
0.93
0x0EE1
0.92
0x0EB8
5.5
0x5800
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
Rev. F
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73
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
VOUT_MAX
The VOUT_MAX command sets an upper limit on the output voltage, including VOUT_MARGIN_HIGH, the unit can
command regardless of any other commands or combinations.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified
to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of
MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified
above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and
possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the GPIO pin will not assert if VOUT_OV_FAULT is
propagated. The LTC3883 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts,
which causes an output voltage high warning. The MFR_VOUT_PEAK value will be used to determine if this limit has
been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
Rev. F
74
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
POWER_GOOD_ON
The PGOOD pin and PGOOD status bit only reflect the OV/UV comparator status, the POWER_GOOD_ON command
does not impact part operation or status.
This command has two data bytes and is formatted in Linear_16u format.
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
POWER_GOOD_OFF
The PGOOD pin and PGOOD status bit only reflect the OV/UV comparator status, the POWER_GOOD_OFF command
does not impact part operation or status.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts the part can produce including
VOUT_OV_FAULT_LIMIT. If the output voltage is set to high range (Bit 6 of MFR_PWM_CONFIG_LTC3883 set to a 0)
MFR_VOUT_MAX is 5.5V. If the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG_LTC3883 set to a 1)
the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the
output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the
STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
CURRENT
Output Current Calibration
COMMAND NAME
IOUT_CAL_GAIN
MFR_IOUT_CAL_GAIN_
TC
MFR_T_SELF_HEAT
MFR_IOUT_CAL_GAIN_
TAU_INV
MFR_IOUT_CAL_GAIN_
THETA
CMD
CODE DESCRIPTION
TYPE
0x38 The ratio of the voltage at the current sense pins to the sensed
R/W Word
current. For devices using a fixed current sense resistor, it is the
resistance value in mΩ.
0xF6 Temperature coefficient of the current sensing element.
R/W Word
DATA
FORMAT UNITS NVM
L11
mΩ
Y
CF
Y
0xB8
0xB9
Reports the calculated self heat value attributed to the inductor.
Coefficient used to emulate thermal time constant.
R Word
R/W Word
L11
L11
C
s–1
Y
0xBA
Used to calculate the instance inductor self heating effect.
R/W Word
L11
C/W
Y
DEFAULT
VALUE
1.8
0xBB9A
3900
0x0F3C
NA
0.0
0x8000
0.0
0x8000
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see
also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_GAIN
sense resistor or inductor DCR in ppm/°C.
Rev. F
76
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
10–6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1‑27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_
READ_IIN_CHAN, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV AND MFR_IOUT_CAL_GAIN_THETA
The LTC3883 uses an innovative (patent pending) algorithm to dynamically model the temperature rise from the
external temperature sensor to the inductor core. This temperature rise is called MFR_T_SELF_HEAT and is used to
calculate the final temperature correction required by IOUT_CAL_GAIN. The temperature rise is a function of the power
dissipated in the inductor DCR, the thermal resistance from the inductor core to the remote temperature sensor and
the thermal time constant of the inductor to board system. The algorithm simplifies the placement requirements for
the external temperature sensor and compensates for the significant steady state and transient temperature error from
the inductor core to the primary inductor heat sink.
The best way to understand the self heating effect inside the inductor is to model the system using the circuit analogy
of Figure 21. The 1st order differential equation for the above model may be approximated by the following difference
equation:
PI – TI/θIS = Cτ ∆TI/∆t (Eq1) (when TS = 0)
from which:
∆TI = ∆t (PI θIS – TI)/(θIS Cτ) (Eq2) or
∆TI = (PI θIS – TI) • τINV (Eq3)
where
τINV = ∆t/(θIS Cτ) (Eq4)
and ∆t is the sample period of the external temperature ADC.
The LTC3883 implements the self heating algorithm using Eq3 and Eq4 where:
∆TI = ∆MFR_T_SELF_HEAT
PI = READ_IOUT • (VISENSEP – VISENSEM)
TS = READ_TEMPERATURE_1
TI = MFR_T_SELF_HEAT + TS
∆t = 1s
τINV = MFR_IOUT_CAL_GAIN_TAU_INV
θIS = MFR_IOUT_CAL_GAIN_THETA
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PMBus COMMAND DETAILS
Initially self heat is set to zero. After each temperature measurement self heat is updated to be the previous value of
self heat incremented or decremented by ∆MFR_T_SELF_HEAT.
The actual value of Cτ is not required. The important quantity is the thermal time constant τINV = (θIS Cτ). For example,
if an inductor has a thermal time constant τTHERMAL = 5 seconds then:
MFR_IOUT_CAL_GAIN_TAU_INV = ∆t / τTHERMAL = 1/5 = 0.2
Refer to the application section for more information on calibrating θIS and τINV.
If the external temperature sense network fails to detect a READ_TEMPERATURE_1 reading of –50°C to 150°C, the
variable TS in the self-heating algorithm will be set to a fixed value of –50°C. See READ_TEMPERATURE_1 for more
information.
MFR_T_SELF_HEAT is a read-only command that has two data bytes and is formatted in Linear_5_11s format.
MFR_IOUT_CAL_GAIN_TAU_INV has two data bytes and is formatted in Linear_5_11 format.
MFR_IOUT_CAL_GAIN_THETA has two data bytes and is formatted in Linear_5_11 format.
MFR_T_SELF_HEAT Data Content
Bit(s)
Symbol
Operation
b[15:0] Mfr_t_self_heat
Values are limited to the range 0°C to 50°C.
MFR_IOUT_CAL_GAIN_THETA Data Content
Bit(s)
Symbol
Operation
b[15:0] Mfr_iout_cal_gain_theta
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
MFR_IOUT_CAL_GAIN_TAU_INV Data Content
Bit(s)
Symbol
Operation
b[15:0] Mfr_iout_cal_gain_tau_inv
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
Values ≥ 1 set MFR_T_SELF_HEAT to MFR_IOUT_CAL_GAIN_THETA • READ_IOUT • (VISENSEP – VISENSEM).
Output Current
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
IOUT_OC_FAULT_LIMIT
0x46
Output overcurrent fault limit.
R/W Word
L11
A
Y
29.75
0xDBB8
IOUT_OC_WARN_LIMIT
0x4A
Output overcurrent warning limit.
R/W Word
L11
A
Y
20.0
0xDA80
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller
is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent
fault limit value is rounded up to the nearest one of the following set of discrete values:
25mV/IOUT_CAL_GAIN
28.6mV/IOUT_CAL_GAIN
32.1mV/IOUT_CAL_GAIN
35.7mV/IOUT_CAL_GAIN
39.3mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
46.4mV/IOUT_CAL_GAIN
50mV/IOUT_CAL_GAIN
37.5mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
48.2mV/IOUT_CAL_GAIN
53.6mV/IOUT_CAL_GAIN
58.9mV/IOUT_CAL_GAIN
64.3mV/IOUT_CAL_GAIN
69.6mV/IOUT_CAL_GAIN
75mV/IOUT_CAL_GAIN
Low Range (1.5x Nominal Loop Gain)
MFR_PWM_MODE_LTC3883 [7]=0
High Range (Nominal Loop Gain)
MFR_PWM_MODE_LTC3883 [7]=1
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The IOUT range is set with bit 7 of the MFR_PWM_MODE_LTC3883 command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
This command sets the value of the output current that causes an output overcurrent warning in amperes. The
READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 80ms.
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
Input Current Calibration
COMMAND NAME
MFR_IIN_CAL_GAIN
CMD CODE DESCRIPTION
0xE8
The resistance value of the input current
sense element in mΩ.
TYPE
R/W Word
DATA FORMAT
L11
UNITS
mΩ
NVM
Y
DEFAULT VALUE
5.000 0xCA80
MFR_IIN_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.
(see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
Input Current
COMMAND NAME
CMD CODE DESCRIPTION
IIN_OC_WARN_LIMIT
0x5D
Input overcurrent warning limit.
TYPE
DATA FORMAT
UNITS
NVM
DEFAULT VALUE
R/W Word
L11
A
Y
10.0 0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating
the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TEMPERATURE
External Temperature Calibration
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA FORMAT UNITS
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
CF
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature
sensor with respect to –273.1°C.
R/W Word
L11
C
NVM
DEFAULT VALUE
Y
1.0
0x4000
Y
0.0
0x8000
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities
in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. N = 8192 to 32767. The effective
adjustment is N • 2–14. The nominal value is 1.
Rev. F
80
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for nonidealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a
value of –273.15 so the default adjustment value is zero.
External Temperature Limits
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA FORMAT
UNITS
NVM
DEFAULT VALUE
OT_FAULT_LIMIT
0x4F
External overtemperature fault limit.
R/W Word
L11
C
Y
100.0 0xEB20
OT_WARN_LIMIT
0x51
External overtemperature warning limit.
R/W Word
L11
C
Y
85.0 0xEAA8
UT_FAULT_LIMIT
0x53
External undertemperature fault limit.
R/W Word
L11
C
Y
–40.0 0xE580
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes an
overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin.
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of the external sense temperature, in degrees Celsius, which causes
an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This condition is detected by the ADC so the response time may be up to 80ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
TIMING
Timing—On Sequence/Ramp
COMMAND NAME
TON_DELAY
CMD CODE DESCRIPTION
0x60
Time from RUN and/or Operation on to output
rail turn-on.
TON_RISE
0x61
Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
TON_MAX_FAULT_LIMIT
0x62
Maximum time from VOUT_EN on for VOUT to
cross the VOUT_UV_FAULT_LIMIT.
VOUT_TRANSITION_RATE
0x27
Rate the output changes when VOUT
commanded to a new value.
TYPE
R/W Word
DATA
FORMAT
L11
UNITS
ms
NVM
Y
R/W Word
L11
ms
Y
R/W Word
L11
ms
Y
R/W Word
L11
V/ms
Y
DEFAULT
VALUE
0.0
0x8000
8.0
0xD200
10.0
0xD280
0.25
0xAA00
TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid. The TON_DELAY will have a typical delay of 270µs
with an uncertainty of ±50µs.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3883 digital slope will be bypassed. The output voltage
transition will be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE is
equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded
rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
Values of greater than 0.1V/ms and less than or equal to 1V/ms are recommended. If a transition rate out of this range
is desired, contact the factory for more information.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. F
82
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Timing—Off Sequence/Ramp
COMMAND NAME
TOFF_DELAY
TOFF_FALL
TOFF_MAX_WARN_LIMIT
CMD CODE DESCRIPTION
TYPE
0x64
Time from RUN and/or Operation off to the start R/W Word
of TOFF_FALL ramp.
Time from when the output starts to fall until the R/W Word
0x65
output reaches zero volts.
Maximum allowed time, after TOFF_FALL
R/W Word
0x66
completed, for the unit to decay below 12.5%.
DATA
FORMAT
L11
UNITS
ms
NVM
Y
L11
ms
Y
L11
ms
Y
DEFAULT
VALUE
0.0
0x8000
8.0
0xD200
150
0xF258
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid. The TON_DELAY will have a typical delay of 270µs with
an uncertainty of ±50µs.
This command is excluded from fault events.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the part will three-state.
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum
fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty
of ±0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off
the output until a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the
programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN_LIMIT
is not enabled if VOUT_DECAY is disabled.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely.
Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
COMMAND NAME
MFR_RESTART_ DELAY
CMD CODE DESCRIPTION
0xDC
Minimum time the RUN pin is held low by the
LTC3883.
TYPE
DATA
FORMAT
UNITS
NVM
R/W Word
L11
ms
Y
DEFAULT
VALUE
500
0xFBE8
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after
which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_
FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,
set the MFR_RESTART_DELAY 16mS longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG_LTC3883
and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
COMMAND NAME
MFR_RETRY_ DELAY
CMD CODE DESCRIPTION
0xDB
Retry interval during FAULT retry mode.
TYPE
DATA
FORMAT
UNITS
NVM
R/W Word
L11
ms
Y
DEFAULT
VALUE
350
0xFABC
MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3883.
This command has two data bytes and is formatted in Linear_5s_11s format.
Fault Responses Input Voltage
COMMAND NAME
VIN_OV_FAULT_RESPONSE
CMD CODE DESCRIPTION
0x56
Action to be taken by the device when an
input supply overvoltage fault is detected.
TYPE
DATA
FORMAT
R/W Byte
Reg
UNITS
NVM
DEFAULT
VALUE
Y
0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
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PMBus COMMAND DETAILS
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has one data byte.
Fault Responses Output Voltage
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
VOUT_OV_FAULT_RESPONSE
0x41
Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte
Reg
Y
0xB8
VOUT_UV_FAULT_RESPONSE
0x45
Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Reg
Y
0xB8
TON_MAX_FAULT_
RESPONSE
0x63
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
Reg
Y
0xB8
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 5.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
The only values recognized for this command are:
0x00–Part performs OV pull down only, or OV_PULLDOWN.
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Table 5. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS
7:6
DESCRIPTION
Response
VALUE
00
For all values of bits [7:6], the LTC3883:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
01
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
5:3
• Bias power is removed and reapplied to the LTC3883.
Retry Setting
2:0
Delay Time
10
11
MEANING
Part performs OV pull down only or OV_PULLDOWN
(i.e., turns off the top MOSFET and turns on lower MOSFET
while VOUT is > VOUT_OV_FAULT)
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
Not supported. Writing this value will generate a CML fault.
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 6.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Rev. F
86
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Table 6. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS
7:6
DESCRIPTION
VALUE
Response
MEANING
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
• The device receives a CLEAR_FAULTS command
10
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
For all values of bits [7:6], the LTC3883:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• Bias power is removed and reapplied to the LTC3883
5:3
2:0
Retry Setting
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
Fault Responses Output Current
COMMAND NAME
IOUT_OC_FAULT_RESPONSE
TYPE
DATA
FORMAT
R/W Byte
Reg
CMD CODE DESCRIPTION
0x47
Action to be taken by the device when an
output overcurrent fault is detected.
UNITS
NVM
DEFAULT
VALUE
Y
0x00
Rev. F
For more information www.analog.com
87
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 7.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin
This command has one data byte.
Table 7. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS
7:6
DESCRIPTION
VALUE
Response
00
The LTC3883 continues to operate indefinitely while maintaining
the output current at the value set by IOUT_OC_FAULT_LIMIT
without regard to the output voltage (known as constantcurrent or brick-wall limiting).
01
Not supported.
10
The LTC3883 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• Bias power is removed and reapplied to the LTC3883.
11
The LTC3883 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
Retry Setting
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUN pin or
removing bias power.
111
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
For all values of bits [7:6], the LTC3883:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
5:3
2:0
MEANING
Delay Time
000-111 The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off response.
Fault Responses IC Temperature
COMMAND NAME
MFR_OT_FAULT_
RESPONSE
CMD CODE DESCRIPTION
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected
TYPE
DATA
FORMAT
R Byte
Reg
UNITS
NVM
DEFAULT
VALUE
0xC0
Rev. F
88
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 8.
The LTC3883 also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin
This command has one data byte.
Table 8. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS
7:6
DESCRIPTION
VALUE
MEANING
Response
00
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTC3883:
01
Not supported. Writing this value will generate a CML fault
• Sets the corresponding fault bit in the status commands and
10
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
• Notifies the host by asserting ALERT pin
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC3883
5:3
Retry Setting
2:0
Delay Time
001-111 Not supported. Writing this value will generate CML fault.
XXX
Not supported. Value ignored
Fault Responses External Temperature
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an external
overtemperature fault is detected,
R/W Byte
Reg
Y
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an external
undertemperature fault is detected.
R/W Byte
Reg
Y
0xB8
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtemperature fault on the external temp sensors. The data byte is in the format given in Table 9.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin
Rev. F
For more information www.analog.com
89
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
This condition is detected by the ADC so the response time may be up to 80ms.
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external undertemperature fault on the external temp sensors. The data byte is in the format given in Table 9.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin
This condition is detected by the ADC so the response time may be up to 80ms.
This command has one data byte.
Table 9. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS
7:6
DESCRIPTION
VALUE
MEANING
Response
00
The PMBus device continues operation without interruption.
For all values of bits [7:6], the LTC3883:
01
Not supported. Writing this value will generate a CML fault.
• Sets the corresponding fault bit in the status commands, and
10
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
XXX
Not supported. Values ignored
• Notifies the host by asserting ALERT pin
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC3883
5:3
2:0
Retry Setting
Delay Time
FAULT SHARING
Fault Sharing Propagation
COMMAND NAME
MFR_GPIO_
PROPAGATE_LTC3883
CMD CODE
0xD2
TYPE
DATA
FORMAT
R/W Word
Reg
DESCRIPTION
Configuration that determines which faults are
propagated to the GPIO pin.
UNITS
NVM
DEFAULT
VALUE
Y
0x2993
Rev. F
90
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_GPIO_PROPAGATE_LTC3883
The MFR_GPIO_PROPAGATE_LTC3883 command enables the events that can cause the GPIO pin to assert low. The
command is formatted as shown in Table 10. Faults can only be propagated to the GPIO pin if they are programmed
to respond to faults.
This command has two data bytes.
Table 10: GPIO Propagate Configuration
The GPIO pin is designed to provide electrical notification of selected events to the user.
BIT(S)
B[15]
SYMBOL
VOUT disabled while not decayed.
B[14]
Mfr_gpio_propagate_short_CMD_cycle
OPERATION
This status bit is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_
LTC3883 is a zero. If the PWM is turned off, by toggling the RUN pin or commanding the part OFF,
and then the RUN is reasserted or the part is commanded back on before the output has decayed,
VOUT will not restart until the 12.5% decay is honored. The GPIO pin is asserted during this
condition if bit 15 is asserted.
0: No action
b[13]
Mfr_gpio_propagate_ton_max_fault
1: This status bit asserts low if commanded off then on before the output has sequenced off.
Re-asserts high after sequence off.
0: No action if a TON_MAX_FAULT fault is asserted
b[12]
b[11]
Reserved
Mfr_gpio_propagate_int_ot
1: GPIO will be asserted low if a TON_MAX_FAULT fault is asserted
b[10]
b[9]
b[8]
Reserved
Reserved
Mfr_gpio_propagate_ut
b[7]
Mfr_gpio_propagate_ot
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_gpio_propagate_input_ov
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
Must be set to 0
0: No action if the UT_FAULT_LIMIT fault is asserted
1: GPIO will be asserted low if the UT_FAULT_LIMIT fault is asserted
0: No action if the OT_FAULT_LIMIT fault is asserted
1: GPIO will be asserted low if the OT_FAULT_LIMIT fault is asserted
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: GPIO will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
b[1]
Reserved
Mfr_gpio_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
Mfr_gpio_propagate_vout_uv
1: GPIO will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: GPIO will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
b[0]
Mfr_gpio_propagate_vout_ov
If this fault bit is asserted, GPIO is low anytime VOUT is below the UV threshold due to a fault. A
UV fault can only occur when the part is in a steady-state ON condition.
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: GPIO will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
Rev. F
For more information www.analog.com
91
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Fault Sharing Response
COMMAND NAME
MFR_GPIO_RESPONSE
CMD CODE DESCRIPTION
TYPE
0xD5
Action to be taken by the device when the GPIO pin R/W Byte
is asserted low.
DATA
FORMAT
Reg
UNITS
NVM
Y
DEFAULT
VALUE
0xC0
MFR_GPIO_RESPONSE
This command determines the controller’s response to the GPIO pin being pulled low by an external source.
VALUE
0xC0
0x00
MEANING
GPIO_INHIBIT The LTC3883 will three-state the output in response to the GPIO pin pulled low.
GPIO_IGNORE The LTC3883 continues operation without interruption.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD
• Sets the GPIO bit in the STATUS_MFR_SPECIFIC command, and notifies the host by asserting ALERT pin. The ALERT
pin pulled low can be disabled by setting bit[1] of MFR_CHAN_CFG_LTC3883.
This command has one data byte.
SCRATCHPAD
COMMAND NAME
USER_DATA_00
USER_DATA_01
USER_DATA_02
USER_DATA_03
USER_DATA_04
CMD CODE
0xB0
0xB1
0xB2
0xB3
0xB4
DESCRIPTION
OEM reserved. Typically used for part serialization.
Manufacturer reserved for LTpowerPlay.
OEM reserved. Typically used for part serialization.
A NVM word available for the user.
A NVM word available for the user.
TYPE
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
DATA
FORMAT
Reg
Reg
Reg
Reg
Reg
UNITS
NVM
Y
Y
Y
Y
Y
DEFAULT
VALUE
NA
NA
NA
0x0000
0x0000
USER_DATA_00 THROUGH USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
IDENTIFICATION
COMMAND NAME
PMBUS_REVISION
CAPABILITY
MFR_ID
MFR_MODEL
MFR_SPECIAL_ID
CMD CODE DESCRIPTION
0x98
PMBus revision supported by this device. Current revision is 1.1.
0x19
Summary of PMBus optional communication protocols
supported by this device.
0x99
The manufacturer ID of the LTC3883 in ASCII.
0x9A
Manufacturer part number in ASCII.
0xE7
Manufacturer code representing the LTC3883.
TYPE
R Byte
R Byte
DATA
FORMAT
Reg
Reg
R String
R String
R Word
ASC
ASC
Reg
UNITS
NVM
FS
DEFAULT
VALUE
0x11
0xB0
LTC
LTC3883
0x430X
Rev. F
92
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3883
is PMBus Version 1.1 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTC3883 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTC3883 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTC3883 using ASCII characters.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x43 denotes the part is an LTC3883, X is adjustable by the
manufacturer.
This read-only command has two data bytes.
FAULT WARNING AND STATUS
COMMAND NAME
CLEAR_FAULTS
MFR_CLEAR_PEAKS
STATUS_BYTE
CMD CODE
0x03
0xE3
0x78
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_ TEMPERATURE
0x79
0x7A
0x7B
0x7C
0x7D
STATUS_CML
0x7E
STATUS_MFR_ SPECIFIC
0x80
MFR_PADS
MFR_COMMON
0xE5
0xEF
MFR_INFO
0xB6
DESCRIPTION
Clear any fault bits that have been set.
Clears all peak values.
One byte summary of the unit’s fault
condition.
Two byte summary of the unit’s fault condition.
Output voltage fault and warning status.
Output current fault and warning status.
Input supply fault and warning status.
External temperature fault and warning status
for READ_TEMERATURE_1.
Communication and memory fault and
warning status.
Manufacturer specific fault and state
information.
Digital status of the I/O pads.
Manufacturer status bits that are common
across multiple ADI chips.
Manufacturing Specific Information
TYPE
Send Byte
Send Byte
R/W Byte
FORMAT
Reg
DEFAULT
VALUE
NA
NA
NA
R/W Word
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Reg
Reg
Reg
Reg
Reg
NA
NA
NA
NA
NA
R/W Byte
Reg
NA
R/W Byte
Reg
NA
R Word
R Byte
Reg
Reg
NA
NA
R Byte
Reg
N/A
UNITS
NVM
Rev. F
For more information www.analog.com
93
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the
ALERT pin pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be
cleared before the status register is set.
This write-only command has no data bytes.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. The MFR_RESET command will initiate this
command.
This write-only command has no data bytes.
STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the
lower byte of the status word.
The following status bits can be cleared by writing a 1 to their position in the STATUS_BYTE command:
[7] BUSY
This permits the user to clear status by means other than using the CLEAR_FAULTS command. This is also the only
bit of this command that can initiate an ALERT event.
[6] Bit 6 of this command will be set whenever the PWM is turned off. Setting this bit does not assert ALERT.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. The
low byte of STATUS_WORD is typically the same as the STATUS_BYTE command. When polling STATUS_WORD, if a
fault occurs at the exact right time, the read value can have a bit set in the lower byte with no corresponding bits set in
the upper byte. An immediate second read of STATUS_WORD will have the corresponding bits in the upper byte set.
The following status bits can be cleared by writing a 1 to their position in the STATUS_WORD command:
[8] UNKNOWN
Rev. F
94
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
[7] BUSY
This permits the user to clear status by means other than using the CLEAR_FAULTS command. These are also the
only bits of this command that can initiate an ALERT event.
[6] Bit 6 of this command will be set whenever the output is turned off.
[11] Bit 11 of this command will be set whenever the output voltage is outside of the 0V/UV thresholds.
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.
[14] Bit 14 of this command will be set by an IOUT_OC Warning or IOUT_OC Fault condition.
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT commands returns one byte with status information on VOUT .
Bit 0 of this command is undefined and reserved in the LTC3883.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT commands returns one byte with status information on IOUT.
Only bits 7, 6, and 5 are supported in the LTC3883.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_INPUT
The STATUS_INPUT commands returns one byte with status information on VIN.
Only bits 7, 5 and 1 are supported in the LTC3883.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not
generate an ALERT even if it is set.
This command has one data byte.
Rev. F
For more information www.analog.com
95
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This command is
related to the respective READ_TEMPERATURE_1 value.
Only bits 7, 6 and 4 are supported in the LTC3883.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_CML
The STATUS_CML commands returns one byte with the status information on received commands and system
memory/logic.
Bit 2 of this command is not supported in the LTC3883.
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued
operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
The format for this byte is:
BIT
MEANING
7
Internal Temperature Fault Limit Exceeded.
6
Internal Temperature Warn Limit Exceeded.
5
Factory Trim Area NVM CRC Fault.
4
PLL is Unlocked
3
Fault Log Present
2
VDD33 UV or OV Fault
0
GPIO Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be
cleared by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
96
Rev. F
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ASSIGNED DIGITAL PIN
VDD33 OV Fault
VDD33 UV Fault
Reserved
Reserved
ADC Values Invalid, Occurs During Start-Up
Device Driving ALERT Low
Reserved
Power Good
Reserved
Device Driving RUN Low
Reserved
RUN
Reserved
Device Driving GPIO Low
Reserved
GPIO
A 1 indicates the condition is true.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains bits that are common to all LTC digital power and telemetry products.
BIT
MEANING
7
Chip Not Driving ALERT Low
6
Busy when Low
5
Calculations Not Pending
4
Output in Transition when Low
3
NVM Initialized
2
Reserved
1
SHARE_CLK Timeout
0
WP Pin Status
This read-only command has one data byte.
Rev. F
For more information www.analog.com
97
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_INFO
The MFR_INFO command contains additional status bits that are LTC3883 specific and may be common to multiple
LTC PSM products.
MFR_INFO Data Contents:
BIT
MEANING
15:6 Reserved
5
4:0
EEPROM ECC status
0: Corrections made in the EEPROM user space
1: No corrections made in the EEPROM user space
Reserved
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM
bulk read operation. This read-only command has two data bytes.
TELEMETRY
COMMAND NAME
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1
CMD
CODE
0x88
0x89
0x8B
0x8C
0x8D
READ_TEMPERATURE_2
0x8E
READ_DUTY_CYCLE
READ_POUT
READ_PIN
MFR_IOUT_PEAK
0x94
0x96
0x97
0xD7
MFR_VOUT_PEAK
0xDD
MFR_VIN_PEAK
0xDE
MFR_TEMPERATURE_1_PEAK
0xDF
MFR_READ_IIN_CHAN_PEAK
0xE1
MFR_READ_ICHIP
MFR_READ_IIN_CHAN
0xE4
0xED
MFR_TEMPERATURE_2_PEAK
0xF4
DESCRIPTION
Measured input supply voltage.
Measured input supply current.
Measured output voltage.
Measured output current.
External diode junction temperature. This is the value
used for all temperature related processing, including
IOUT_CAL_GAIN.
Internal junction temperature. Does not affect any
other commands.
Duty cycle of the top gate control signal.
Calculated output power.
Calculated input power
Report the maximum measured value of READ_IOUT
since last MFR_CLEAR_PEAKS.
Maximum measured value of READ_VOUT since last
MFR_CLEAR_PEAKS.
Maximum measured value of READ_VIN since last
MFR_CLEAR_PEAKS.
Maximum measured value of external Temperature
(READ_TEMPERATURE_1) since last MFR_CLEAR_
PEAKS.
Maximum measured value of READ_IIN command
since last MFR_CLEAR_PEAKS.
Measured current used by the LTC3883
Calculated input supply current based upon
READ_IOUT and DUTY_CYCLE
Peak internal die temperature since last
MFR_CLEAR_PEAKS.
NVM
DEFAULT
VALUE
NA
NA
NA
NA
NA
TYPE
R Word
R Word
R Word
R Word
R Word
FORMAT
L11
L11
L16
L11
L11
UNITS
V
A
V
A
C
R Word
L11
C
NA
R Word
R Word
R Word
R Word
L11
L11
L11
L11
%
W
W
A
NA
NA
NA
NA
R Word
L16
V
NA
R Word
L11
V
NA
R Word
L11
C
NA
R Word
L11
A
NA
R Word
R Word
L11
L11
A
A
NA
NA
R Word
L11
C
NA
Rev. F
98
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Summary of the Status Commands
STATUS_WORD
STATUS_VOUT*
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_BYTE
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
STATUS_TEMPERATURE
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
STATUS_CML
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
DESCRIPTION
General Fault or Warning Event
Dynamic
Status Derived from Other Bits
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
(reads 0)
VOUT Short Cycled
GPIO Pulled Low By External Device
(PAGED)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD33 0V
VDD33 UV
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Output Disabled Externally
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTC3883 Forcing RUN1 Low
LTC3883 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC3883 Forcing GPIO1 Low
LTC3883 Forcing GPIO0 Low
GPIO1 Pin State
GPIO0 Pin State
MFR_PADS
MFR_INFO
(PAGED)
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
IIN_OC Warning
(reads 0)
STATUS_MFR_SPECIFIC
(PAGED)
(PAGED)
7
6
5
4
3
2
1
0
STATUS_INPUT
7
6
5
4
3
2
1
0
3883 SR01
MASKABLE GENERATES ALERT BIT CLEARABLE
Yes
No
No
Yes
No
Not Directly
Yes
No
No
Rev. F
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99
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
READ_VIN
The READ_VIN command returns the measured VIN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This
compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTC3883.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE
command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor
(see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the ISENSE pins
b) the IOUT_CAL_GAIN value
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
f) The MFR_IOUT_CAL_GAIN_TAU_INV and MFR_IOUT_CAL_GAIN_THETA
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle of controller, in percent.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
Rev. F
100
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
READ_POUT
The READ_POUT command is a reading of the DC/DC converter output power in Watts. The POUT is calculated based
on the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_PIN
The READ_PIN command is a reading of the DC/DC converter input power in Watts. The PIN is calculated based on
the most recent correlated input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_PEAK
The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. F
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101
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
MFR_READ_ICHIP
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC3883.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_CHAN
The MFR_READ_IIN_CHAN command returns the calculated value of the input current, in Amperes, as a function of
READ_IOUT and DUTY_CYCLE. For accurate values at low currents, the part must be in continuous conduction mode.
If DCR sensing is used, the accuracy of the inductor DCR resistance, IOUT_CAL_GAIN, will effect the accuracy of the
MFR_READ_IIN command.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
NVM MEMORY COMMANDS
Store/Restore
COMMAND NAME
CMD
CODE
DESCRIPTION
STORE_USER_ALL
0x15
Store user operating memory to EEPROM.
Send Byte
NA
RESTORE_USER_ALL
0x16
Restore user operating memory from EEPROM.
Send Byte
NA
MFR_COMPARE_USER_ALL
0xF0
Compares current command contents with NVM.
Send Byte
NA
TYPE
FORMAT
UNITS
NVM
DEFAULT
VALUE
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data retention of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is
disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTC3883 and programming of the NVM can be initiated when VDD33 is available and VIN is
not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by
0xC4. The part can now be communicated with, and the project file updated. To write the updated project file to the
NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to
be enabled and valid ADCs to be read.
This write-only command has no data bytes.
Rev. F
102
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the PMBus device to copy the contents of the non-volatile User memory
to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
retrieved from the User commands. When a RESTORE_USER_ALL command is issued, the RUN pin and SHARE_CLK
pin are asserted low until the restore is complete. The RUN pin and SHARE_CLK pin are then released. The RUN pins
are held low for the MFR_RESTART_DELAY. The RESTORE_USER_ALL command will place the value of all commands
stored in NMV into the RAM ignoring the pin-strapped resistor configuration pins including ASEL. The MFR_RESET
command is recommended to be used instead of RESTORE_USER_ALL because the MFR_RESET command always
honors the ASEL pins and will honor the pin-strapped RCONFIG pins, if the part is programmed to respect them.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds
130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 34. The fault log provides telemetry recording capability to
the LTC3883. During normal operation the contents of the status registers, the output voltage readings, temperature
readings as well as peak values of these quantities are stored in a continuously updated buffer in RAM. This is similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM for nonvolatile storage. The
EEPROM fault log is then locked. The part can be powered down with the fault log available for reading at a later time.
As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced. When reading the fault
log from RAM all 6 events of cyclical data remain. However, when the fault log is read from EEPROM (after a reset),
the last 2 events are lost. The read length of 147 bytes remains the same, but the fifth and sixth events are a repeat
of the fourth event.
RAM 255 BYTES
EEPROM 255 BYTES
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
•
•
•
•
•
•
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
3883 F34
Figure 34. Fault Log Conceptual Diagram
Rev. F
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103
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Fault Logging
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT
R Block
CF
UNITS
NVM
DEFAULT
VALUE
Y
NA
MFR_FAULT_LOG
0xEE
Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
MFR_FAULT_LOG_ STORE
0xEA
Command a transfer of the fault log from RAM to Send Byte
EEPROM. This causes the part to behave as if the
PWM has faulted off.
NA
MFR_FAULT_LOG_CLEAR
0xEC
Initialize the EEPROM block reserved for fault
logging and clear any previous fault logging
locks.
NA
Send Byte
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was last written. The contents of this command are stored
in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table 11. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAUTL_LOG will return a block of data 147
bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may
not contain valid data. When a fault occurs and Fault Log is enabled, a header section and the last 6 ADC events are
stored in NVM. If the Fault Log is read before a reset occurs, the most recent event is in location N (the first location).
If the part resets or VIN is lost, the event may appear in any one of the 6 cyclical data locations.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event
occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the
MFR_CONFIG_ALL_LTC3883 command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
This write-only command has no data bytes.
Table 11. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
DATA
Block Length
LIN 11 = PMBus = Rev 1.1, Part 2, section 7.1
LIN 16 = PMBus Rev 1.1, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
BITS
DATA
FORMAT
BYTE
BYTE NUM BLOCK READ COMMAND
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
Rev. F
104
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LTC3883/LTC3883-1
PMBus COMMAND DETAILS
HEADER INFORMATION
Fault Position
MFR_REAL_TIME
MFR_VOUT_PEAK
Reserved
Reserved
MFR_IOUT_PEAK
MFR_READ_IIN_CHAN_PEAK
MFR_VIN_PEAK
READ_TEMPERATURE_1
Reserved
Reserved
READ_TEMPERATURE_2
MFR_TEMPERATURE_1_PEAK
[7:0]
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Reserved
Reserved
CYCLICAL DATA
EVENT n
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
LIN 16
BYTE
BYTE
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
BYTE
LIN 11
LIN 11
BYTE
BYTE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Reserved
Reserved
READ_IOUT
MFR_READ_IIN_CHAN
READ_VIN
READ_IIN
STATUS_VOUT
Reserved
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Peak READ_VOUT since last MFR_CLEAR_PEAKS command.
Peak READ_IOUT since last MFR_CLEAR_PEAKS command.
Peak READ_IIN since last MFR_CLEAR_PEAKS command.
Peak READ_VIN since last MFR_CLEAR_PEAKS command.
External temperature during last event.
Always returns 0x00.
Always returns 0x00.
Internal temperature sensor during last event
Peak READ_TEMPERATURE_1 since last MFR_CLEAR_PEAKS
command.
Always returns 0x00.
Always returns 0x00.
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT
Indicates the fault that caused the fault log to be activated.
48 bit binary counter. The value is the time since the last reset in 200µs
increments.
LIN 16
BYTE
BYTE
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
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105
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
STATUS_WORD
MFR_READ_ICHIP
MFR_READ_ICHIP
STATUS_MFR_SPECIFIC
Reserved
EVENT n-1
[15:8]
[7:0]
[15:8]
[7:0]
Reserved
Reserved
READ_IOUT
MFR_READ_IIN_CHAN
READ_VIN
READ_IIN
STATUS_VOUT
Reserved
WORD
BYTE
BYTE
(data measured before fault was detected)
READ_VOUT
[15:8]
[7:0]
Reserved
Reserved
READ_IOUT
[15:8]
[7:0]
MFR_READ_IIN_CHAN
[15:8]
[7:0]
READ_VIN
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT
Reserved
STATUS_WORD
[15:8]
[7:0]
Reserved
Reserved
STATUS_MFR_SPECIFIC
Reserved
*
*
*
EVENT n-5
(Oldest Recorded Data)
READ_VOUT
WORD
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
BYTE
BYTE
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
BYTE
WORD
BYTE
BYTE
BYTE
BYTE
LIN 16
BYTE
BYTE
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
BYTE
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Rev. F
106
For more information www.analog.com
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
STATUS_WORD
[15:8]
[7:0]
Reserved
Reserved
STATUS_MFR_SPECIFIC
Reserved
WORD
BYTE
BYTE
BYTE
BYTE
141
142
143
144
145
146
Always returns 0x00.
Always returns 0x00.
Always returns 0x00.
Table 11a: Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
0xFF
MFR_FAULT_LOG_STORE
0x00
TON_MAX_FAULT
0x01
VOUT_OV_FAULT
0x02
VOUT_UV_FAULT
0x03
IOUT_OC_FAULT
0x05
TEMP_OT_FAULT
0x06
TEMP_UT_FAULT
0x07
VIN_OV_FAULT
0x0A
MFR_TEMP_2_OT_FAULT
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
DATA
FORMAT
UNITS
NVM
DEFAULT
VALUE
MFR_EE_UNLOCK
0xBD
Unlock user EEPROM for access by MFR_EE_ERASE and
MFR_EE_DATA commands.
R/W Byte
Reg
NA
MFR_EE_ERASE
0xBE
Initialize user EEPROM for bulk programming by MFR_EE_ R/W Byte
DATA.
Reg
NA
MFR_EE_DATA
0xBF
Data transferred to and from EEPROM using sequential
PMBus word reads or writes. Supports bulk programming.
Reg
NA
R/W
Word
All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the
die temperature drops below 125°C.
MFR_EE_UNLOCK
Multiple writes to MFR_EE_UNLOCK with the appropriate unlock keys are used to enable MFR_EE_ERASE and MFR_
EE_DATA access and configure PEC.
Communication with the LTC3883 and programming of the NVM can be initiated when VDD33 is applied and VIN is
not. To enable the part in this state, use global address 0x5B command MFR_EE_UNLOCK data 0x2B followed by address 0x5B command MFR_EE_UNLOCK data 0xC4. When VIN is applied, a MFR_RESET must be issued to allow the
PWM to be enabled and valid ADCs to be read.
Rev. F
For more information www.analog.com
107
LTC3883/LTC3883-1
PMBus COMMAND DETAILS
Writing 0x2B followed by 0xD4 clears PEC, resets the EEPROM address pointer and unlocks the part for EEPROM
erase and data command writes.
Writing 0x2B followed by 0xD5 sets the PEC, resets the EEPROM address pointer and unlocks the part for EEPROM
erase and data command writes.
Writing 0x2B followed by 0x91 and 0xE4 clears PEC, resets the EEPROM address pointer and unlocks the part for
EEPROM data reads of all locations.
Writing 0x2B followed by 0x91 and 0xE5 sets PEC, resets the EEPROM address pointer and unlocks the part for
EEPROM data reads of all locations.
MFR_EE_ERASE
A single write after the appropriate unlock key erases the EEPROM allowing subsequent data writes. This command
may be read to indicate if an EEPROM access is in progress.
A value of 0x2B will erase the EEPROM. If the part is busy writing or erasing the EEPROM a non-zero value will be
returned.
MFR_EE_DATA
Sequential writes or reads perform block loads or restores from the EEPROM. Successive MFR_EE_DATA word writes
will enter the EEPROM until it is full. Extra writes will lock the part. The first write is to the lowest address. The first
read returns the 16 bit EEPROM packing revision ID. The second read returns the number of 16 bit words available.
Subsequent reads return EEPROM data starting with the lowest address.
Rev. F
108
For more information www.analog.com
LTC3883/LTC3883-1
TYPICAL APPLICATIONS
High Efficiency 500kHz 1.2V Step-Down Converter with External VCC
5mΩ
VIN
6V TO 14V
5VIN
10µF
D1
EXTVCC
100Ω
1µF
100Ω
TG
LTC3883-1
BOOST
IIN_SNS
VIN_SNS
10nF
0.1µF
22µF
50V
1µF
M1
0.32µH
SW
10nF
M2 V
DD25
BG
3Ω
PGND
VIN
10k
10µF
10k
PMBus
INTERFACE
10k
10k
10k
10k
10k
5k
VDD33
PGOOD
20k
12.7k
SDA
SCL
20k
1k
4.32k
23.2k
1µF
17.8k
VOUT_CFG
RUN
ASEL
1k
0.22µF
SHARE_CLK
GPIO
SYNC
ISENSE+
ISENSE–
VSENSE+
VSENSE–
VDD33
+
TSNS
VDD25
1.0µF
10k
ALERT VTRIM_CFG
WP
1.0µF
24.9k
FREQ_CFG
GND
ITH
6800pF
10k
MMBT3906
10nF
COUT: 330μH SANYO 4TPF330ML,
2× 100µF AVX 12106D107KAT2A
D1: CENTRAL CMDSH-3TR
L: PULSE PA 0515.321NLT 0.32µH
M1: INFINEON BSC032NE2LS
M2: INFINEON BSC009NE2LS
VOUT
1.2V
20A
COUT
530µF
3883 TA06
Rev. F
For more information www.analog.com
109
LTC3883/LTC3883-1
TYPICAL APPLICATIONS
High Efficiency 500kHz 2.5V Step-Down Converter with Sense Resistor, No Input Current Sense
VIN
6V TO 24V
10µF
INTVCC
TG
LTC3883
BOOST
IIN_SNS
VIN_SNS
10k
PMBus
INTERFACE
10k
10k
10k
10k
10k
5k
VDD33
SDA
FREQ_CFG
SCL
VOUT_CFG
VDD25
20k
20k
20k
12.7k
15k
17.8k
ALERT V
TRIM_CFG
RUN
ASEL
SHARE_CLK
GPIO
ISENSE+
SYNC
ISENSE–
VDD25
VDD33
1.0µF
0.002Ω
M2
PGOOD
WP
1.0µF
M1
0.56µH
BG
PGND
10k
0.1µF
SW
VIN
10µF
22µF
50V
1µF
D1
30Ω
1000pF
30Ω
VSENSE+
VSENSE–
+
TSNS
GND
ITH
4700pF
6.81k
VOUT
2.5V
15A
COUT
530µF
MMBT3906
10nF
3883 TA04
COUT: 330μH SANYO 4TPF330ML,
L: VISHAY IHLP4040DZ01 0.56μH
2× 100µF AVX 12106D107KAT2A M1: INFINEON BSC050N03LSG
D1: CENTRAL CMDSH-3TR
M2: INFINEON BSC011N03LSI
Rev. F
110
For more information www.analog.com
LTC3883/LTC3883-1
TYPICAL APPLICATIONS
High Efficiency 425kHz 1V Step-Down Converter with Power Block
5mΩ
VIN
7V TO 14V
10µF
22µF
50V
1µF
7V
GATE DRIVE
INTVCC
100Ω
1µF
BOOST
100Ω
IIN_SNS
3Ω
10nF
VIN_SNS
10nF
LTC3883
BG
SW
VIN
10µF
10k
10k
PMBus
INTERFACE
10k
SDA
PGND
SCL
WP
VDD25
SHARE_CLK
10k
ALERT
10k
RUN
10k
GPIO
5k
24.9k
20k
16.2k
4.32k
17.8k
17.4k
VOUT_CFG
VTRIM_CFG
PGOOD
10k
VDD33
VIN
PWMH VOUT
P1
CS–
VGATE
CS+
TEMP+
PWML TEMP–
GND
TG
ASEL
FREQ_CFG
SYNC
TSNS
ISENSE+
1µF
0.22µF
1.2k
ISENSE–
VDD25
VDD33
VSENSE+
VSENSE–
GND
1.0µF
1.0µF
ITH
+
1000pF
5.62k
VOUT
1V
35A
COUT
530µF
100pF
COUT: 330μH SANYO 4TPF330ML, 2× 100µF AVX 12106D107KAT2A
P1: VRA001-4C3G ACBEL POWER BLOCK
3883 TA05
Rev. F
For more information www.analog.com
111
LTC3883/LTC3883-1
TYPICAL APPLICATIONS
High Efficiency 500kHz 2-Phase 1.8V Step-Down Converter with Sense Resistors
5mΩ
VIN
6V TO 18V
10µF
INTVCC
100Ω
1µF
TG
LTC3883
BOOST
IIN_SNS
100Ω
VIN_SNS
10nF
3Ω
0.002Ω
M2
BG
10k
FREQ_CFG
PGOOD VOUT_CFG
10k
10k
SDA
VTRIM_CFG
SCL
ASEL
ALERT
10k
VDD25
WP
20k
24.9k
17.8k
11.3k
RUN
10k
SHARE_CLK
10k
VDD33
0.4µH
PGND
10k
PMBus
INTERFACE
M1
0.1µF
SW
10nF
VIN
10µF
22µF
50V
1µF
D1
5k
GPIO
ISENSE+
SYNC
ISENSE–
30Ω
1000pF
30Ω
VSENSE+
VSENSE–
VDD25
TSNS
VDD33
ITH
GND
1.0µF
1.0µF
+
2200pF
4.99k
COUT1
530µF
MMBT3906
10nF
5mΩ
10µF
INTVCC
100Ω
10nF
1µF
TG
LTC3883
BOOST
IIN_SNS
100Ω
VIN_SNS
22µF
50V
1µF
D2
0.1µF
M3
0.4µH
SW
10nF
0.002Ω
M4
BG
PGND
3Ω
VIN
10µF
FREQ_CFG
PGOOD VOUT_CFG
SDA
VTRIM_CFG
SCL
ASEL
ALERT
WP
VDD25
20k
15k
RUN
SHARE_CLK
GPIO
ISENSE+
SYNC
ISENSE–
30Ω
1000pF
30Ω
VSENSE
VSENSE–
COUT1, COUT2: 330μH SANYO 4TPF330ML,
2× 100µF AVX 12106D107KAT2A
D1, D2: CENTRAL CMDSH-3TR
L: VITEC 59PR9875 0.4µH
M1, M3: INFINEON BSC050NE2LS
M2, M4: INFINEON BSC010NE2LSI
VDD25
TSNS
VDD33
ITH
1.0µF
1.0µF
VOUT
1.8V
40A
+
GND
+
100pF
COUT2
530µF
MMBT3906
10nF
3883 TA07
Rev. F
112
For more information www.analog.com
LTC3883/LTC3883-1
TYPICAL APPLICATIONS
High Efficiency 3-Phase 425kHz 1.8V Step-Down Converter with Input Current Sense
5mΩ
VIN
6V TO 14V
10µF
100Ω
1µF
TG
LTC3883
BOOST
IIN_SNS
100Ω
VIN_SNS
10nF
L0
0.56µH
M2
BG
PGND
10k
10k
SDA
VOUT_CFG
SCL
VTRIM_CFG
ALERT
10k
20k
11.3k
17.8k
1.4k
FREQ_CFG
0.22µF
SHARE_CLK
10k
ISENSE+
GPIO
5k
ISENSE–
SYNC
VSENSE+
WP
1.0µF
+
VSENSE–
VDD25
VDD33
TSNS
GND
ITH
1.0µF
10µF
1µF
24.9k
ASEL
RUN
10k
NOTE: BIT[12] VOUT_UVUF
OF COMMAND
MFR_GPIO_PROPAGATE_LTC3883
MUST BE SET TO 0.
1.4k
PGOOD
10k
PMBus
INTERFACE
VDD25
VIN
10k
10µF
M3
M1
0.1µF
SW
10nF
3Ω
L1
0.56µH
22µF
50V
1µF
D1
INTVCC
VIN
10nF
TG0
0.1µF
D3
INTVCC
TG1
LTC3870
BOOST0
0.1µF
M4
L2
0.56µH
SW1
BG0
M6
BG1
1.4k
SYNC
1µF
22µF
1µF
BOOST1
SW0
M5
COUT1
530µF
MMBT3906
2200pF
4.99k
D2
VOUT
1.8V
50A
PGND
1.4k
EXTVCC
1µF
PHASMD
MODE0
FREQ
MODE1
100k
FAULT0
ILIM
FAULT1
RUN0
RUN1
1.4k
+
0.22µF
ISENSE0+
ISENSE1+
ISENSE0–
ISENSE1–
ITH0
COUT2
530µF
D1-D3: CENTRAL CMDSH-3TR
L0-L2: VISHAY IHLP-4040DZ-11 0.56µH
ITH1
SGND
M1, M3, M4: INFINEON BSC050NE2LS
M2, M5, M6: INFINEON BSC010NE2LSI
0.22µF 1.4k
100pF
COUT1, COUT2, COUT3: 330μH SANYO 4TPF330ML,
2× 100µF AVX 12106D107KAT2A
+
COUT3
530µF
3883 TA08
Rev. F
For more information www.analog.com
113
LTC3883/LTC3883-1
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
Rev. F
114
For more information www.analog.com
LTC3883/LTC3883-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/13
Changed VOUT range to 5.4V. Added patent number.
1
Added SYNC to the Absolute Maximum Ratings.
4
Fixed conditions on the LSB step size.
6
Deleted "and," and added "The BG, TG and RUN pins are held low. The GPIO pin is in high impedance mode."
17
Deleted "ARA command..."
23, 24
Deleted five instances of "MFR_REGISTERS”
33, 35
Changed RUN to SHARE_CLK. Added text.
45
Deleted NVM.
50
Changed "IOUT_OC_FAULT_LIMIT” to "Peak Current Limit”
Deleted MFR registers. Added text to the CLEAR_FAULTS and STATUS_WORD sections.
Revised patent note.
B
7/14
Change Electrical Characteristics condition from TA = 25°C to TJ = 25°C
Reduced minimum time to react to command
C
12/15
D
05/16
E
F
01/18
09/19
PAGE NUMBER
77
91-93
112
5, 6, 7, 8
24, 65, 81, 82
Updated PSYNC equation
58
Revised schematic
109
Updated Related Parts
112
Clarified PGOOD pin description.
12
Clarified PolyPhase operation.
54
Added ECC
1, 15, 16
Reduced initialization time
5
Reduced minimum on-time
5
Added AEC-Q100 Qualified for Automotive Applications and orderable part numbers
1, 5
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
115
LTC3883/LTC3883-1
TYPICAL APPLICATION
High Efficiency 500kHz 1.8V Step-Down Converter with DCR Sense
5mΩ
VIN
6V TO 24V
10µF
D1
INTVCC
100Ω
1µF
100Ω
TG
LTC3883
BOOST
IIN_SNS
VIN_SNS
10nF
3Ω
VIN
10k
PMBus
INTERFACE
10k
10k
10k
*PGOOD PIN HAS VARIABLE LATENCY.
DO NOT USE FOR SEQUENCING
10k
10k
5k
VDD33
0.56µH
M2
BG
PGND
10k
PGOOD
SDA
RUN
1.4k
1µF
VDD25
20k
24.9k
10k
20k
12.7k
9.09k
23.2k
17.8k
FREQ_CFG
SCL
ALERT
M1
SW
10nF
10µF
0.1µF
22µF
50V
1µF
VOUT_CFG
1.4k
VTRIM_CFG
0.22µF
SHARE_CLK ASEL
GPIO
SYNC
WP
VDD25
VDD33
1.0µF
1.0µF
ISENSE+
ISENSE–
VSENSE+
VSENSE
–
+
TSNS
GND
ITH
2200pF
100pF
4.99k
VOUT
1.8V
20A
COUT
530µF
MMBT3906
3883 TA02
M1: INFINEON BSC050N03LSG COUT: 330μH SANYO 4TPF330ML,
D1: CENTRAL CMDSH-3TR
2× 100µF AVX 12106D107KAT2A
L: VISHAY IHLP-4040DZ-11 0.56µH M2: INFINEON BSC011N03LSI
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COMMENTS
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LTC3887/ Dual Output Multiphase Step-Down DC/DC Controller
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with Digital Power System Management
This product has a license from PowerOne, Inc. related to digital power technology as set forth in U.S. Patent 7000125 and other related patents owned
by PowerOne, Inc. This license does not extend to standalone power supply products.
Rev. F
116
09/19
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