LTC6810-1/LTC6810-2
6 Channel Battery Stack Monitors
FEATURES
DESCRIPTION
AEC-Q100 Qualified for Automotive Applications
n Measures Up to 6 Battery Cells in Series
n 1.8mV Maximum Total Measurement Error
n Stackable Architecture for High Voltage Systems
n 290µs to Measure All Cells in a System.
n Built-in isoSPI™ Interface
n 1Mb Isolated Serial Communications
n Uses Single Twisted Pair, Up to 100 Meters
n Low EMI Susceptibility and Emissions
n Bidirectional for Broken Wire Protection
n Guaranteed Performance Down to 5V
n Performs Redundant Cell Measurements.
n Engineered for ISO 26262 Compliant Systems
n Passive Cell Balancing with Programmable PWM
n 4 General Purpose Digital I/O or Analog Inputs
n Temperature or Other Sensor Inputs
n Configurable as an I2C or SPI master
n 4μA Sleep Mode Supply Current
n 44-Lead SSOP Package
The LTC®6810 is a multicell battery stack monitor. The
LTC6810 measures up to 6 series-connected battery cells
with a total measurement error of less than 1.8mV. The
cell measurement range of 0V to 5V makes the LTC6810
suitable for most battery chemistries. All 6 cells can be
measured in 290µs, and lower data acquisition rates can
be selected for high noise reduction.
n
Multiple LTC6810-1 devices can be connected in series,
permitting simultaneous cell monitoring of long, high
voltage battery strings. Each LTC6810 has an isoSPI
interface for high speed, RF-immune, long distance communications. Using the LTC6810-1, multiple devices are
connected in a daisy chain with one host processor connection for all devices. The LTC6810-1 supports bidirectional operation, allowing communication even with
a broken wire. Using the LTC6810-2, multiple devices
are connected in parallel to the host processor, with each
device individually addressed.
The LTC6810 can be powered directly from the battery
stack or from an isolated supply. The LTC6810 includes
passive balancing for each cell, with PWM duty cycle
control for each cell and the ability to perform redundant
cell measurements. Other features include an onboard 5V
regulator, 4 general purpose I/O lines and a sleep mode in
which current consumption is reduced to 4µA.
APPLICATIONS
Electric and Hybrid Electric Vehicles
Backup Battery Systems
n Grid Energy Storage
n High Power Portable Equipment
n
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Measurement Error vs V+
REVERSIBLE
16-BIT ∆ WITH
PROGRAMMABLE
NOISE FILTER
SERIAL
PORT B
isoSPI
SERIAL
PORT A
MUX
DIE TEMP
SECOND
REFERENCE
MEASUREMENT ERROR OF
CELL1 WITH 3.3V INPUT,
VREG INTERNALLY GENERATED,
FIGURE 2
1.5
LOGIC
4-WIRE
SPI
UNIQUE ID
MUX
2.0
isoSPI
4 GENERAL PURPOSE
ANALOG IN AND
DIGITAL IN/OUT
OPTIONAL
EEPROM
CURRENT
SENSOR
1.0
0.5
0
–0.5
–1.0
125°C
25°C
–40°C
–1.5
–2.0
10k
NTC
FIRST
REFERENCE
MEASUREMENT ERROR (mV)
LTC6810
+
5
10
15
20
V+ (V)
25
30
6810 TA01b
–
68101 TA01a
Rev. A
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1
LTC6810-1/LTC6810-2
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Pin Configuration.................................................................................................................. 3
Order Information.................................................................................................................. 4
Electrical Characteristics......................................................................................................... 4
Typical Performance Characteristics..........................................................................................10
Pin Functions......................................................................................................................17
Block Diagram.....................................................................................................................18
Operation..........................................................................................................................20
State Diagram........................................................................................................................................................ 20
Core LTC6810 State Descriptions.......................................................................................................................... 20
isoSPI State Descriptions...................................................................................................................................... 21
Power Consumption.............................................................................................................................................. 22
VREG Configurations.............................................................................................................................................. 23
ADC Operation....................................................................................................................................................... 24
Data Acquisition System Diagnostics.................................................................................................................... 29
Watchdog and Discharge Timer............................................................................................................................. 37
Reset Behaviors..................................................................................................................................................... 39
S Pin Pulse Width Modulation for Cell Balancing................................................................................................... 40
Discharge Timer Monitor....................................................................................................................................... 40
I2C/SPI Master on LTC6810 Using GPIOs............................................................................................................. 40
S Pin Muting.......................................................................................................................................................... 44
Serial ID and Authentication.................................................................................................................................. 45
Serial Interface Overview....................................................................................................................................... 45
4-Wire Serial Peripheral Interface (SPI) Physical Layer......................................................................................... 45
Data Link Layer...................................................................................................................................................... 55
Network Layer........................................................................................................................................................ 55
Applications Information........................................................................................................70
Providing DC Power............................................................................................................................................... 70
Internal Protection and Filtering............................................................................................................................. 71
Cell Balancing........................................................................................................................................................ 72
Discharge Control During Cell Measurements....................................................................................................... 74
Digital Communications......................................................................................................................................... 76
Enhanced Applications........................................................................................................................................... 86
Reading External Temperature Probes................................................................................................................... 86
Package Description.............................................................................................................88
Revision History..................................................................................................................89
Typical Application...............................................................................................................90
Related Parts......................................................................................................................90
Rev. A
2
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LTC6810-1/LTC6810-2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage, V+ to V–................................. 37.5V
Input Voltage (Relative to V–)
C0............................................................. –0.3V to 5V
S0........................................................... –0.3V to 21V
C(n), S(n) n = 1 TO 3............................... –0.3V to 21V
C(n), S(n) n = 4 TO 5.............................–0.3V to 37.5V
C(6), S(6)....................–0.3V to min(V+ + 5.5V, 37.5V)
IPA, IMA, IPB, IMB............. –0.3V to VREG + 0.3V, ≤6V
DRIVE....................................................... –0.3V to 7V
All Other Pins............................................ –0.3V to 6V
Voltage Between Inputs
C(n) to C(n – 1)....................................... –0.3V to 21V
S(n) to C(n – 1)....................................... –0.3V to 21V
C6 to C3.................................................. –0.3V to 21V
C3 to C0.................................................. –0.3V to 21V
S6 to S4.................................................. –0.3V to 21V
S4 to S2.................................................. –0.3V to 21V
S2 to S0.................................................. –0.3V to 21V
S6 to C3.................................................. –0.3V to 21V
Current In/Out of Pins
All Pins Except VREG, IPA, IMA, IPB, IMB, S(n)...10mA
IPA, IMA, IPB, IMB..............................................30mA
Operating Temperature Range
LTC6810I..............................................–40°C to 85°C
LTC6810H........................................... –40°C to 125°C
Specified Temperature Range
LTC6810I..............................................–40°C to 85°C
LTC6810H........................................... –40°C to 125°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
LTC6810-1
LTC6810-2
TOP VIEW
V –*
NC
1
2
TOP VIEW
44
V–*
V–*
1
44 V–*
43
V–*
NC
2
43 V–*
V+
3
42 WDT
V+
3
42 WDT
C6
4
41 SDI (NC)**
C6
4
41 SDI (ICMP)**
S6
5
40 SDO (NC)**
S6
5
40 SDO (IBIAS)**
C5
6
39 IPB
C5
6
39 A3
S5
7
38 IMB
S5
7
38 A2
C4
8
37 SCK (IPA)**
C4
8
37 SCK (IPA)**
S4
9
36 CSB (IMA)**
S4
9
36 CSB (IMA)**
C3 10
35 ICMP
C3 10
35 A1
S3 11
34 IBIAS
S3 11
34 A0
C2 12
33 DRIVE
C2 12
33 DRIVE
S2 13
32 VREG
S2 13
32 VREG
C1 14
31 VREF2
C1 14
31 VREF2
S1 15
30 VREF1
S1 15
30 VREF1
C0 16
29 V–
C0 16
29 V–
S0 17
V–
S0 17
28 V–
28
GPIO1 18
27 ISOMD
GPIO1 18
27 ISOMD
GPIO2 19
26 DTEN
GPIO2 19
26 DTEN
GPIO3 20
25 GPIO4
GPIO3 20
25 GPIO4
V–* 21
24 V–*
V–* 21
24 V–*
V–* 22
23 V–*
V–* 22
23 V–*
G PACKAGE
44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 50°C/W
**PINS 1, 21–24, 43 AND 44 ARE FUSED TO THE LEADFRAME.
THEY SHOULD BE CONNECTED TO V– PIN 29
**THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, NC, NC
G PACKAGE
44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 50°C/W
**PINS 1, 21–24, 43 AND 44 ARE FUSED TO THE LEADFRAME.
THEY SHOULD BE CONNECTED TO V– PIN 29
**THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, ICMP, IBIAS
Rev. A
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3
LTC6810-1/LTC6810-2
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
MSL RATING
SPECIFIED
TEMPERATURE RANGE
TUBE (37PC)
TAPE AND REEL (2000PC)
PART MARKING
PACKAGE DESCRIPTION
LTC6810IG-1#3ZZPBF
LTC6810IG-1#3ZZTRPBF
LTC6810G-1
44-Lead Plastic SSOP
1
–40°C to 85°C
LTC6810HG-1#3ZZPBF
LTC6810HG-1#3ZZTRPBF
LTC6810G-1
44-Lead Plastic SSOP
1
–40°C to 125°C
LTC6810IG-2#3ZZPBF
LTC6810IG-2#3ZZTRPBF
LTC6810G-2
44-Lead Plastic SSOP
1
–40°C to 85°C
LTC6810HG-2#3ZZPBF
LTC6810HG-2#3ZZTRPBF
LTC6810G-2
44-Lead Plastic SSOP
1
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC Specifications
Measurement Resolution
0.1
mV/bit
ADC Offset Voltage
(Note 2)
0.1
mV
ADC Gain Error
(Note 2)
0.03
0.06
%
%
l
Total Measurement Error (TME) in
Normal Mode (Note 3)
C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V– = 0
±0.2
C(n) to C(n–1) = 2.0, GPIO(n) to V– = 2.0
S(n) to S(n–1) = 2.0
±0.1
C(n) to C(n–1), GPIO(n) to V– = 2.0
S(n) to S(n–1) = 2.0
l
l
C(n) to C(n–1), GPIO(n) to V– = 3.3
S(n) to S(n–1) = 3.3
C(n) to C(n–1), GPIO(n) to V– = 3.3
S(n) to S(n–1) = 3.3
±0.2
l
l
C(n) to C(n–1) = 4.2
S(n) to S(n–1) = 4.2
C(n) to C(n–1), GPIO(n) to V– = 4.2
S(n) to S(n–1) = 4.2
±0.3
l
l
C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V– = 5.0
Sum of Cells
mV
±1.2
±1.7
mV
mV
±1.6
±2.2
mV
mV
±1.8
±2.5
mV
mV
±2.4
±3.2
mV
mV
±2.3
±3.2
mV
mV
±3.1
±4.1
mV
mV
±1
l
Internal Temperature, T = Maximum Specified
Temperature
±0.1
mV
±0.6
±5
%
°C
VREG Pin
l
±0.1
±0.25
%
VREF2 Pin
l
±0.02
±0.1
%
Digital Supply Voltage, VREGD
l
±0.1
±1
%
Rev. A
4
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LTC6810-1/LTC6810-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Total Measurement Error (TME) in
Filtered Mode (Note 3)
C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V– = 0
MIN
±0.1
C(n) to C(n–1) = 2.0, GPIO(n) to V– = 2.0
±0.1
S(n) to S(n–1) = 2.0
C(n) to C(n–1), GPIO(n) to V– = 2.0
S(n) to S(n–1) = 2.0
l
l
C(n) to C(n–1) = 3.3
S(n) to S(n–1) = 3.3
C(n) to C(n–1), GPIO(n) to V– = 3.3
S(n) to S(n–1) = 3.3
±0.2
l
l
C(n) to C(n–1) = 4.2
S(n) to S(n–1) = 4.2
C(n) to C(n–1), GPIO(n) to V– = 4.2
S(n) to S(n–1) = 4.2
±0.3
l
l
C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V– = 5.0
Sum of Cells
±1.2
±1.7
mV
mV
±1.6
±2.2
mV
mV
±1.8
±2.5
mV
mV
±2.4
±3.2
mV
mV
±2.3
±3.2
mV
mV
±3.1
±4.1
mV
mV
mV
±0.6
%
°C
VREG Pin
l
±0.1
±0.25
VREF2 Pin
l
±0.02
±0.1
%
Digital Supply Voltage, VREGD
l
±0.1
±1
%
C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V– = 0
±2
%
mV
C(n) to C(n–1), GPIO(n) to V– = 2.0
S(n) to S(n–1) = 2.0
l
l
4
5
mV
mV
C(n) to C(n–1), GPIO(n) to V– = 3.3
S(n) to S(n–1) = 3.3
l
l
5.5
6.5
mV
mV
C(n) to C(n–1), GPIO(n) to V– = 4.2
S(n) to S(n–1) = 4.2
l
l
8
9
mV
mV
Sum of Cells
±10
±0.15
l
Internal Temperature, T = Maximum Specified
Temperature
IL
UNITS
mV
±5
C(n) to C(n–1), GPIO(n) to V– = 5.0, S(n) to S(n–1) = 5.0
Input Range
MAX
±1
±0.1
l
Internal Temperature, T = Maximum Specified
Temperature
Total Measurement Error (TME) in
Fast Mode (Note 3)
TYP
mV
±1
±5
%
°C
VREG Pin
l
±0.3
±1
%
VREF2 Pin
l
±0.1
±0.25
%
Digital Supply Voltage, VREGD
l
±0.2
±2
%
C(n) n = 1 to 6
l
C(n–1)
C(n–1) + 5
V
S(n) n = 1 to 6
l
C(n–1)
C(n+1)
V
C0/S0
l
0
5
V
0
GPIO(n) n = 1 to 4
l
Input Leakage Current When Inputs
Are Not Being Measured (State:
Core = STANDBY)
C(n), S(n), n = 0 to 6
GPIO(n) n = 1 to 4
l
l
Input Current When Inputs Are Being
Measured
C(n)/S(n) n = 0 to 6
GPIO(n) n = 1 to 4
Input Current During Open Wire
Detection
10
10
5
V
±250
±250
nA
nA
±1
±1
l
70
110
µA
µA
140
µA
Rev. A
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5
LTC6810-1/LTC6810-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
3.1
3.2
3.3
UNITS
Voltage Reference Specifications
VREF1
VREF2
1st Reference Voltage
VREF1 Pin, No Load
1st Reference Voltage TC
VREF1 Pin, No Load
3
ppm/°C
1st Reference Voltage Hysteresis
VREF1 Pin, No Load
20
ppm
1st Reference V. Long Term Drift
VREF1 Pin, No Load
2nd Reference Voltage
VREF2 Pin, No Load
VREF2
l
25
Pin, 5k Load to V–
V
ppm/√khr
l
2.995
3
3.005
V
l
2.994
3
3.006
V
2nd Reference Voltage TC
VREF2 Pin, No Load
10
ppm/°C
2nd Reference Voltage Hysteresis
VREF2 Pin, No Load
100
ppm
2nd Reference V. Long Term Drift
VREF2 Pin, No Load
60
ppm/√khr
General DC Specifications
IVP
V+ Supply Current
(See Figure 1: Operation State
Diagram)
State: Core = SLEEP, isoSPI = IDLE
VREG = 0V
VREG = 0V
5.7
l
VREG = 5V
VREG = 5V
State: Core = STANDBY
Internal REG Disabled
IREG(CORE) VREG Supply Current
(See Figure 1: Operation State
Diagram)
State: Core = SLEEP, isoSPI = IDLE
µA
9
µA
l
µA
µA
25
20
35
l
50
60
µA
µA
l
30
25
50
50
70
80
µA
µA
70
60
130
l
175
200
µA
µA
3.5
6.5
µA
3.5
9
µA
48
l
20
18
75
85
µA
µA
1.2
1.1
1.7
l
2.2
2.3
mA
mA
l
5.7
5.5
6.2
6.2
6.6
6.8
mA
mA
l
State: Core = STANDBY
State: Core = MEASURE
µA
5.5
35
45
State: Core = REFUP
IREG(isoSPI) Additional VREG Supply Current
If isoSPI in READY/ACTIVE States
Note: ACTIVE State Current
Assumes tCLK = 1µs, (Note 3)
15
3.5
22
VREG = 5V
VREG = 5V
5.7
3.5
State: Core = MEASURE
State: Core = STANDBY
Internal REG Enabled
µA
14
10
l
State: Core = REFUP
IVP_INTREG Total V+ Current when Internal REG
Enabled = IVP +IREG
10
LTC6810-2: ISOMD = 1,
RB1 + RB2 = 2k
READY
l
3.6
4.5
5.4
mA
ACTIVE
l
4.6
5.8
7.0
mA
LTC6810-1: ISOMD = 0,
RB1 + RB2 = 2k
READY
l
3.6
4.5
5.2
mA
ACTIVE
l
5.6
6.8
8.1
mA
LTC6810-1: ISOMD = 1,
RB1 + RB2 = 2k
READY
l
4.0
5.2
6.5
mA
ACTIVE
l
7.0
8.5
10.5
mA
LTC6810-2: ISOMD = 1,
RB1 + RB2 = 20k
READY
l
1.0
1.8
2.6
mA
ACTIVE
l
1.2
2.2
3.2
mA
LTC6810-1: ISOMD = 0,
RB1 + RB2 = 20k
READY
l
1.0
1.8
2.6
mA
ACTIVE
l
1.3
2.3
3.3
mA
LTC6810-1: ISOMD = 1,
RB1 + RB2 = 20k
READY
l
1.6
2.5
3.5
mA
ACTIVE
l
1.8
3.1
4.8
mA
Rev. A
6
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LTC6810-1/LTC6810-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
VREG
VDRIVE
VREGD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V+ Supply Voltage
TME Specifications Met
l
5.0
20
27.5
V
V+ to C6 Voltage
TME Specifications Met
l
–0.3
VREG Supply Voltage
TME Supply Rejection < 1mV/V
l
4.5
5
5.5
V
Internal Regulator Voltage
DRIVE Pin Current > 25µA
l
4.5
4.6
4.8
V
Allowed VREG Range When Externally
Driven
DRIVE Pin Is High Z
l
4.7
5
5.3
V
DRIVE Output Voltage
V+ > 12V, Sourcing 1µA
l
5.5
5.7
6.2
V
V+ > 12V, Sourcing 1mA
l
5.3
5.5
6
V
Drive Pin Current to Enable Internal
VREGA
l
25
Maximum DRIVE Pin Current that
Does Not Power Up Internal VREGA
l
Digital Supply Voltage
l
Discharge Switch ON Resistance
VCELL = 3.3V
l
2.7
Thermal Shutdown Temperature
V
µA
1
µA
3
3.6
V
5
10
Ω
150
°C
VOL(WDT)
Watch Dog Timer (WDT) Pin Voltage
WDT Pin Sinking 4mA
l
0.4
V
VOL(GPIO)
General Purpose I/O Pin Low
GPIO Pin Sinking 4mA (Used as Digital Output)
l
0.4
V
1281
µs
ADC Timing Specifications
tCYCLE
(Figure 6)
Measurement + Calibration Cycle Time Measure 6 Cells
When Starting from the REFUP State in Measure 1 Cells
Normal Mode, SCONV = 0, MCAL = 0
Measure 6 Cells and 2 GPIO Inputs
l
1098
1165
l
381
404
444
µs
l
1411
1497
1647
µs
Measurement + Calibration Cycle Time Measure 6 Cells
When Starting from the REFUP State in Measure 1 Cells
Filtered Mode, SCONV = 0, MCAL = 0
Measure 6 Cells and 2 GPIO Inputs
l
172
183
201
ms
l
31
34
37
ms
l
228
242
267
ms
Measurement + Calibration Cycle Time Measure 6 Cells
When Starting from the REFUP State Measure 1 Cells
in Fast Mode, SCONV = 0, MCAL = 0
Measure 6 Cells and 2 GPIO Inputs
l
495
524
577
µs
l
189
200
220
µs
l
643
682
750
µs
tSKEW1
(Figure 9)
Skew Time. The Time Difference
Fast Mode
Between C6 and GPIO1 Measurements, Normal Mode
Command = ADCVAX
l
182
194
214
µs
l
511
543
598
µs
tSKEW2
(Figure 6)
Skew Time. The Time Difference
Between C6 and C1 Measurements,
Command = ADCV
Fast Mode
l
220
233
257
µs
Normal Mode
l
631
670
737
µs
tWAKE
Drive Start-Up Time (Note 5)
VREG Generated from Drive Pin, See Figure 3
l
150
300
µs
VREG Generated Internally, See Figure 2
l
Watchdog or Discharge Timer
tSLEEP
(Figure 17)
DTEN Pin = 0 or DCTO[3:0] = 0000
l
Reference Wake-up Time. Added to
tREFUP
(Figure 6, tCYCLE Time When Starting from the
Figure 30) STANDBY State. tREFUP = 0 When
Starting from Other States.
tREFUP Is Independent of the Number of Channels
Measured and the ADC Mode
Internal Regulator Start-Up Time
DTEN Pin = 1 and DCTO[3:0] = 0001
DTEN Pin = 1 and DCTO[3:0] = 1111
fS
ADC Clock Frequency
l
200
400
µs
1.8
2
2.2
sec
28
30
32
sec
112
120
128
min
2.7
3.5
4.4
ms
3.0
3.3
3.5
MHz
Rev. A
For more information www.analog.com
7
LTC6810-1/LTC6810-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Interface DC Specifications
VIH(SPI)
SPI Pin Digital Input Voltage High
Pins CSB, SCK, SDI
l
VIL(SPI)
SPI Pin Digital Input Voltage Low
Pins CSB, SCK, SDI
l
2.3
V
VIH(ADDR)
Address Pin Digital Input Voltage High Pins ISOMD, DTEN, GPIO1 to GPIO4, A0–A3
l
VIL(ADDR)
Address Pin Digital Input Voltage Low Pins ISOMD, DTEN, GPIO1 to GPIO4, A0–A3
l
1.2
V
ILEAK(DIG)
Digital Input Current
Pins CSB, SCK, SDI, ISOMD, DTEN, A0 to A3
l
±1
µA
VOL(SDO)
Digital Output Low
Pins SDO sinking 1mA
l
0.3
V
2.1
V
V
0.8
2.7
V
V
isoSPI DC Specifications (see Figure 23)
VBIAS
Voltage on IBIAS Pin
READY/ACTIVE State
IDLE State
l
1.9
IB
Isolated Interface Bias Current
IB = VBIAS/(RB1 + RB2)
l
0.1
AIB
Isolated Interface Current Gain
VA ≤ 1.6V IB = 1mA
l
18
20
l
18
20
IB = 0.1mA
VA
Transmitter Pulse Amplitude
VA = |VIP – VIM|
l
VICMP
Threshold-Setting Voltage on
ICMP Pin
VTCMP = ATCMP • VICMP
l
ILEAK(ICMP) Input Leakage Current on ICMP Pin
ILEAK(IP/IM) Leakage Current on IP and IM Pins
2
0
0.2
1
mA
22
mA/mA
23
mA/mA
1.6
V
1.5
V
l
±1
µA
IDLE State, VIP or VIM, 0V to VREG
l
±1
µA
l
0.6
V/V
ATCMP
Receiver Comparator Threshold
Voltage Gain
VCM = 2.5V to VREG – 0.2
0.4
0.5
VCM
Receiver Common-Mode Bias
IP/IM Not Driving
RIN
Receiver Input Resistance
Single-Ended to IPA, IMA, IPB, IMB
l
26
VWAKE = |VIPA – VIMA|
l
250
mV
240
ns
(VREG – VICMP/3 – 167mV)
35
45
V
kΩ
isoSPI Idle/Wake-up Specifications (see Figure 30)
VWAKE
Differential Wake-up Voltage
tDWELL
Dwell Time at VWAKE Before Wake
Detection
l
tREADY
Start-Up Time After Wake Detection
l
10
µs
tIDLE
Idle Timeout Duration
l
4.3
5.5
6.7
ms
isoSPI Pulse Timing Specifications (see Figure 28)
t½PW(CS)
Chip-Select Half-Pulse Width
Transmitter
l
120
150
180
ns
tFILT(CS)
Chip-Select Signal Filter
Receiver
l
70
90
110
ns
tINV(CS)
Chip-Select Pulse Inversion Delay
Transmitter
l
120
155
190
ns
Receiver
l
220
270
330
ns
tWNDW(CS) Chip-Select Valid Pulse Window
t½PW(D)
Data Half-Pulse Width
Transmitter
l
40
50
60
ns
tFILT(D)
Data Signal Filter
Receiver
l
10
25
35
ns
tINV(D)
Data Pulse Inversion Delay
Transmitter
l
40
55
65
ns
tWNDW(D)
Data Valid Pulse Window
Receiver
l
70
90
110
ns
Rev. A
8
For more information www.analog.com
LTC6810-1/LTC6810-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. The test conditions are V+ = 19.8V, VREG = 5.0V unless otherwise noted.
The ISOMD pin is tied to the V– pin, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Timing Requirements (see Figure 22 and Figure 29)
tCLK
SCK Period
l
1
µs
t1
SDI Setup Time Before SCK Rising
Edge
(Note 6)
l
25
ns
t2
SDI Hold Time After SCK Rising Edge
l
25
ns
t3
SCK Low
tCLK = t3 + t4 ³ 1µs
l
200
ns
t4
SCK High
tCLK = t3 + t4 ³ 1µs
l
200
ns
t5
CS Rising Edge to CS Falling Edge
l
0.6
µs
t6
SCK Rising Edge to CS Rising Edge
(Note 6)
l
0.8
µs
t7
CS Falling Edge to SCK Rising Edge
(Note 6)
l
1
µs
(Note 7)
l
60
ns
50
ns
60
ns
isoSPI Timing Specifications (see Figure 29)
t8
SCK Falling Edge to SDO Valid
t9
SCK Rising Edge to Short ±1 Transmit
l
t10
CS Transition to Long ±1 Transmit
l
t11
CS Rising Edge to SDO Rising
tRTN
Data Return Delay
(Note 7)
l
tDSY(CS)
Chip-Select Daisy-Chain Delay
l
tDSY(D)
Data Daisy-Chain Delay
l
tLAG
l
t5(GOV)
Data Daisy-Chain Lag (vs. Chip-Select) = [tDSY(D) + t½PW(D)] – [tDSY(CS) + t½PW(CS)]
Chip-Select High-to-Low Pulse
Governor
l
t6(GOV)
Data to Chip-Select Pulse Governor
tBLOCK
isoSPI Port Reversal Blocking Window
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error specification.
Note 3: S pin TME may differ from C pin TME by several bits due to the
quantization noise of the ADC and the different external filtering on the
C and S pins.
Note 4: The ACTIVE state current is calculated from DC measurements.
The ACTIVE state current is the additional average supply current into
VREG when there is continuous 1MHz communications on the isoSPI ports
with 50% data 1s and 50% data 0s. Slower clock rates reduce the supply
current. See Applications Information section for additional details.
200
ns
375
425
ns
120
180
ns
200
250
300
ns
0
55
70
ns
0.6
0.82
µs
l
0.8
1.05
µs
l
2
10
µs
l
325
Note 5: VREG is generated from the Drive pin and an external NPN
transistor, see Figure 3.
Note 6: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 7: These specifications do not include rise or fall time of SDO. While
fall time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance on the SDO pin. The time constant must
be chosen such that SDO meets the setup time requirements of the MCU.
Rev. A
For more information www.analog.com
9
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
Measurement Error vs
Temperature
Measurement Error Long Term
Drift
20
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS
1.5
20
15
1.0
15
NUMBER OF PARTS
MEASUREMENT ERROR (mV)
Measurement Error Due to IR
Reflow
MEASUREMENT ERROR (ppm)
2.0
TA = 25°C, unless otherwise noted.
0.5
0
–0.5
–1.0
10
5
–1.5
5
0
–5
–10
–15
–20
–25
–2.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
0
–400
125
–300
–200
–100
0
CHANGE IN GAIN ERROR (ppm)
6810 G01
Measurement Error vs Input
Filtered Mode
2.0
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
1.0
0.5
0
–0.5
–1.0
10.0
1.0
0.5
0
–0.5
–1.0
2.0
0
–2.0
–4.0
–6.0
–8.0
–2.0
–10.0
4
5
0
1
2
3
INPUT (V)
4
6810 G04
10.0
0.9
9.0
0.8
0.8
8.0
0.7
0.7
7.0
0.4
0.3
PEAK NOISE (mV)
1.0
0.9
0.5
0.6
0.5
0.4
0.3
3.0
2.0
0.1
1.0
2
3
INPUT (V)
4
5
0
0
1
2
3
INPUT (V)
4
6810 G07
5
4.0
0.1
1
4
5.0
0.2
0
2
3
INPUT (V)
6.0
0.2
0
1
Measurement Noise vs Input
Fast Mode
1.0
0.6
0
6810 G06
Measurement Noise vs Input
Filtered Mode
PEAK NOISE (mV)
PEAK NOISE (mV)
5
6810 G05
Measurement Noise vs Input
Normal Mode
2500
4.0
–2.0
2
3
INPUT (V)
2000
6.0
–1.5
1
1000
1500
TIME (HOURS)
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
8.0
–1.5
0
500
Measurement Error vs Input
Fast Mode
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
1.5
MEASUREMENT ERROR (mV)
1.5
0
6810 G03
MEASUREMENT ERROR (mV)
2.0
–30
100
6810 G02
Measurement Error vs Input
Normal Mode
MEASUREMENT ERROR (mV)
10
5
6810 G08
0
0
1
2
3
INPUT (V)
4
5
6810 G09
Rev. A
10
For more information www.analog.com
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
Measurement Gain Error
Hysteresis, Hot
15
TA = 25°C, unless otherwise noted.
Measurement Gain Error
Hysteresis, Cold
15
TA = 25°C TO 85°C
Noise Filter Response
0
TA = 25°C TO –40°C
10
5
NOISE REJECTION (dB)
NUMBER OF PARTS
NUMBER OF PARTS
–10
10
5
–20
–30
–40
–50
–60
0
–100 –75 –50 –25 0
25 50 75
CHANGE IN GAIN ERROR (ppm)
0
–100 –75 –50 –25 0
25 50 75
CHANGE IN GAIN ERROR (ppm)
100
6810 G10
Measurement Error vs V+
Measurement Error vs VREG
0
–0.5
VIN = 2V
VIN = 3.3V
VIN = 4.2V
–1.5
V+ (V)
1.0
0
–0.5
–1.0
–2.0
6810 G13
0
–10
–20
0.5
–30
PSRR (dB)
1.0
0
–0.5
0
–0.5
–1.0
–2.0
30
17
–70
–2.0
–80
100
20
18
19
20
21
V+ (V)
6810 G14
22
6810 G15
Measurement Error Due to a V+
AC Disturbance
0
–10
–20
–30
–50
–1.5
10
15
C5 VOLTAGE (V)
25
–40
–60
5
20
0.5
–1.5
V+(DC) = 19.8V
V+(AC) = 5V
1-BIT CHANGE < –70dB
–1.0
0
15
1.0
Measurement Error Due to a VREG
AC Disturbance
C6–C5 = 3.3V
V+ = 23.3V
1.5
10
V+ (V)
Measurement Error vs Common
Mode Voltage
2.0
125°C
25°C
–40°C
5
1M
6810 G12
C6 – C5 = 3.3V
C6 = 19.8V
1.5
0.5
–1.5
–2.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR OF
CELL1 WITH 3.3V INPUT,
VREG INTERNALLY GENERATED,
FIGURE 2
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (mV)
0.5
1k
10k
100k
INPUT FREQUENCY (Hz)
26Hz
2kHz
14kHz
422Hz
3kHz
27kHz
1kHz
7kHz
2.0
1.5
1.0
100
Top Cell Measurement Error vs V+
2.0
1.5
–1.0
10
6810 G11
PSRR (dB)
2.0
–70
100
V+(DC) = 19.8V
V+(AC) = 5V
1-BIT CHANGE < –90dB
VREG GENERATED FROM
DRIVE PIN, FIGURE 3
–40
–50
–60
–70
–80
–90
1k
10k
100k
FREQUENCY (Hz)
1M
6810 G16
10M
6810 G17
–100
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
6810 G18
Rev. A
For more information www.analog.com
11
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
Measurement Error CMRR vs
Frequency
Cell Measurement Error vs Input
RC Values
5
VCM(IN) = 5VP-P
NORMAL MODE CONVERSIONS
–30
–40
–50
–60
–70
–80
1k
10k
100k
FREQUENCY (Hz)
1M
0
–5
–10
10nF
100nF
1µF
–15
–20
100
10M
GPIO MEASURMENT ERROR (mV)
REJECTION (dB)
–20
–90
100
20
1.205
9.00
1.200
8.00
SUPPLY CURRENT (µA)
MEASUREMENT TIME (mS)
10.00
1.195
1.190
1.185
1.180
1.175
1k
INPUT RESISTANCE (Ω)
–4
–8
0
25
50
75
TEMPERATURE (°C)
100
0
100nF
1µF
10µF
–12
1
10
100
1k
INPUT RESISTANCE (Ω)
10k
6810 G21
Standby Supply Current vs V+
Internal REG Enabled
160
7.00
6.00
5.00
4.00
3.00
125°C
85°C
25°C
–40°C
1.00
0
125
5
10
15
20
25
30
V+ (V)
Standby Supply Current vs V+
Internal REG Disabled
140
130
120
1.90
125°C
85°C
25°C
–40°C
110
100
35
0
5
10
15
20
25
30
V+ (V)
6810 G23
REFUP Supply Current vs V+
Internal REG Disabled
IVP + IREG
IVP_INTREG
150
6810 G22
90
0
–20
10k
IVP + IREG
2.00
VREG = 4.5V
VREG = 5V
VREG = 5.5V
–25
4
Sleep Mode Supply Current vs V+
1.210
1.160
–50
8
6810 G20
Measurement Time vs
Temperature
1.165
12
–16
6810 G19
1.170
TIME BETWEEN MEASUREMENTS > 3RC
16
CELL MEASURMENT ERROR (mV)
–10
GPIO Measurement Error vs Input
RC Values
SUPPLY CURRENT (µA)
0
TA = 25°C, unless otherwise noted.
35
6810 G24
Measure Supply Current vs V+
Internal REG Disabled
6.50
IVP + IREG
IVP + IREG
70
60
125°C
85°C
25°C
–40°C
50
40
10
15
20
25
V+ (V)
30
35
6810 G25
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (µA)
80
1.80
1.70
125°C
85°C
25°C
–40°C
1.60
10
15
20
25
30
V+ (V)
35
6810 G26
6.25
6.00
125°C
85°C
25°C
–40°C
5.75
10
15
20
25
V+ (V)
30
35
6810 G27
Rev. A
12
For more information www.analog.com
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
VREF1 vs Temperature
3.005
5 TYPICAL UNITS
3.004
3.170
200
5 TYPICAL UNITS
3.002
VREF2 (V)
3.160
3.155
3.150
3.001
3.000
2.999
2.998
3.145
2.997
3.140
–25
0
25
50
75
TEMPERATURE (°C)
100
2.995
–50
125
–25
0
25
50
75
TEMPERATURE (°C)
6810 G28
200
25
0
–25
125°C
85°C
25°C
–40°C
–50
–75
–100
2.5
7.5
12.5 17.5 22.5 27.5 32.5 37.5
V+ (V)
–50
–100
6810 G30
100
5 TYPICAL UNITS
60
–800
–1000
0.01
125°C
85°C
25°C
–40°C
40
20
0
–20
–40
–60
–80
0.1
1
IOUT (mA)
10
–100
0
500
1000
1500
TIME (HOURS)
2000
6810 G32
2500
6810 G33
Measurement Gain Error
Hysteresis, Cold
TA = 25°C TO 85°C
VREF2 Long-Term Drift
80
VREG = 5V
–600
15
125°C
85°C
25°C
–40°C
–200
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VREG (V)
V+ = 19.8V
–400
Measurement Gain Error
Hysteresis, Hot
15
125
–200
6810 G31
0
VREF2 Load Regulation
0
CHANGE IN VREF2 (ppm)
CHANGE IN VREF2 (ppm)
75
50
100
6810 G29
VREF2 V+ Line Regulation
50
CHANGE IN VREF2 (ppm)
100
100
–150
2.996
3.135
–50
VREF2 VREG Line Regulation
150
3.003
3.165
VREF1 (V)
VREF2 vs Temperature
CHANGE IN VREF2 (ppm)
3.175
TA = 25°C, unless otherwise noted.
12
TA = 25°C TO –40°C
VREF2 Change Due to IR Reflow
10
5
NUMBER OF PARTS
NUMBER OF PARTS
NUMBER OF PARTS
10
10
5
8
6
4
2
0
–75 –50 –25 0
25 50 75 100 125
CHANGE IN GAIN ERROR (ppm)
0
–100 –75 –50 –25 0
25 50 75
CHANGE IN GAIN ERROR (ppm)
6810 G34
100
6810 G35
0
–600
–400
–200
0
200
400
CHANGE IN VREF2 (ppm)
600
6810 G36
Rev. A
For more information www.analog.com
13
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
VDRIVE vs Temperature
20
3 PARTS NO LOAD, 1mA LOAD
CHANGE IN VDRIVE (mmV)
5.90
5.80
5.70
5.60
–20
10
5
0
–5
125°C
85°C
25°C
–40°C
–10
–25
0
25
50
75
TEMPERATURE (oC)
100
–20
125
5
10
6810 G37
0
15
20
25
30
V+ (V)
Internal VREG Load Regulation
5.00
0
5
10
15
20
IOUT (mA)
25
30
35
4.75
4.70
4.65
5.50
NPN CONNECTED TO VREG
5.40 VREG LOAD CURRENT = 25mA (INCLUDES IVREG)
5.0
125°C
85°C
25°C
–40°C
3.0
2.0
1
1.5
2
2.5
3
3.5
CELL VOLTAGE (V)
4
5.10
5.00
4.90
4.80
4.70
4.55
4.60
INCREASE IN TEMPERATURE (°C)
DISCHARGE SWITCH ON-RESISTANCE (Ω)
6.0
4.0
5.20
4.60
0
40
7.0
5
10
15
20
25
VREG LOAD CURRENT (mA)
30
4.50
4.5
30
25
20
15
10
5
0
50
100
150
200
INTERNAL DISCHARGE CURRENT (mA/CELL)
6810 G43
TRANSITION BETWEEN INTERNAL LDO
AND EXTERNAL NPN POWERED VREG
5
10
6810 G44
15
20
V+ PIN VOLTAGE (V)
6810 G41
1 CELL , 100%
3 CELL, 100%
6 CELL, 50%
35
0
1
6810 G39
25
30
6810 G42
Internal Die Temperature
Measurement Error vs Temperature
Internal Die Temperature
Increase vs Discharge Current
8.0
0.1
DRIVE PIN LOAD CURRENT (mA)
5.30
4.80
4.50
125°C
85°C
25°C
–40°C
VREG Pin Voltage vs
V+ Pin Voltage
V+ below 10V
V+=15V
V+ above 20V
6810 G40
ON–RESISTANCE OF INTERNAL
DISCHARGE SWITCH MEASURED
BETWEEN S(n) AND S(n–1)
9.0
–70
6810 G38
Internal VREG Load Regulation
4.85
Discharge Switch On-Resistance
vs Cell Voltage
10.0
–60
TEMPERATURE MEASUREMENT ERROR (°C)
–300
–50
–90
VREG PIN VOLTAGE (V)
VREG PIN VOLTAGE (V)
CHANGE IN VREG (mV)
V+ = 10V
INTERNAL LDO, FIGURE 2
125°C
85°C
25°C
–40°C
–40
–100
0.01
4.90
–200
–30
–80
NPN DISCONNECTED FROM VREG
4.95 LOAD CURRENT INCLUDES IVREG OF THE CHIP
–100
VDRIVE Load Regulation
–10
–15
5.50
–50
0
15
6.00
VDRIVE (V)
VDRIVE V+ Line Regulation
CHANGE IN VDRIVE (mV)
6.10
TA = 25°C, unless otherwise noted.
10
8
5 TYPICAL UNITS
6
4
2
0
–2
–4
–6
–8
–10
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6810 G46
Rev. A
14
For more information www.analog.com
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
VREF1 and VREF2 Power-Up
TA = 25°C, unless otherwise noted.
isoSPI Current (READY) vs
Temperature
VREG and VDRIVE Power-Up
6.0
VREF1
VREG
VREG
2V/DIV
VREF1
1A/DIV
CS
5V/DIV
CS
5C/DIV
6810 G46
500µs/DIV
5.0
4.5
4.0
6810 G47
50µs/DIV
VREF1: CL = 1µF
VREF2: CL = 1µF; RL = 5k
5.5
ISOSPI CURRENT (mA)
VREF2
VREF2
1V/DIV
VDRIVE
VDRIVE
2A/DIV
IB = 1mA
VREG GENERATED FROM DRIVE PIN
VREG: CL = 1µF
3.5
–50
LTC6813–1, ISOMD = V–
LTC6813–1, ISOMD = VREG
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6810 G48
isoSPI Current (ACTIVE) vs
isoSPI Clock Frequency
IBIAS Voltage vs Temperature
2.02
8
2.01
6
5
4
LTC6810-1, WRITE
LTC6810-1, READ
LTC6810-2, WRITE
LTC6810-2, READ
3
0
200
400
600
800
ISOSPI CLOCK FREQUENCY (kHz)
1000
IB = 1mA
3 PARTS
2.00
1.99
1.98
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
6810 G49
isoSPI Driver Current Gain
(Port A/Port B) vs IBIAS Current
23
22
22
21
20
18
VA = 0.5V
VA = 1V
VA = 1.6V
0
200
400
600
800
IBIAS CURRENT, IB (µA)
2.005
2.000
1.995
1.990
0
200
400
600
800
IBIAS CURRENT, IB (µA)
1000
6810 G51
isoSPI Driver Current Gain
(Port A/Port B) vs Temperature
23
19
125
6810 G50
1000
CURRENT GAIN, AIB (mA/mA)
2
IBIAS PIN VOLTAGE (V)
7
CURRENT GAIN, AIB (mA)
ISOSPI CURRENT
ISOMD = VREG
9 IB = 1mA
IBIAS Voltage Load Regulation
2.010
IBIAS PIN VOLTAGE (V)
10
21
20
19
18
–50
6810 G52
IB = 1mA
IB = 100µA
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6810 G53
Rev. A
For more information www.analog.com
15
LTC6810-1/LTC6810-2
TYPICAL PERFORMANCE CHARACTERISTICS
isoSPI Driver Common Mode
Voltage (Port A/Port B) vs Pulse
Amplitude
isoSPI Comparator Threshold
Gain (Port A/Port B) vs Receiver
Common Mode
5.0
4.5
4.0
3.5
2.5
Ib=100uA
Ib=1mA
0
0.5
1
1.5
PULSE AMPLITUDE, VA (V)
2
0.56
0.54
0.52
0.50
0.48
0.46
VICMP=0.2V
VICMP=1V
0.44
2.5
3
3.5
4
4.5
5
RECEIVER COMMON MODE, VCM (V)
6810 G54
3 PARTS
0.54
0.52
0.50
0.48
0.46
0.44
0
0.2
0.4
0.6 0.8 1 1.2
ICMP VOLTAGE (V)
1.4
1.6
6810 G56
Typical Wake-Up Pulse Amplitude
(Port A/Port B) vs Dwell Time
0.56
300
WAKE–UP PULSE AMPLITUDE, VWAKE (mV)
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
5.5
0.56
6810 G55
isoSPI Comparator Threshold Gain
(Port A/Port B) vs Temperature
0.54
0.52
0.50
0.48
0.46
0.44
–50
isoSPI Comparator Threshold
Gain (Port A/Port B) vs ICMP
Voltage
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
COMPARATOR THRESHOLD GAIN, ATCMP (V/V)
DRIVER COMMON MODE (V)
5.5
3.0
TA = 25°C, unless otherwise noted.
VICMP=1V
VICMP=0.2V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
GUARANTEED
WAKE–UP REGION
250
200
150
100
50
0
0
6810 G57
100
200
300
400
500
WAKE–UP DWELL TIME, TDWELL (ns)
600
6810 G58
Rev. A
16
For more information www.analog.com
LTC6810-1/LTC6810-2
PIN FUNCTIONS
C0 – C6: Cell Inputs.
Serial Port Pins
S0 – S6: Balance Inputs/Outputs Redundant Cell
Measurement. 6 NMOSFETs are connected between S(n)
and S(n–1) for discharging cells. Additionally S pins can
be used for redundant cell measurement.
V+: Positive Supply Pin.
V–:
Negative Supply Pins. The
together, external to the IC.
V–
pins must be shorted
V–*: These pins are fused to the leadframe, connect to V–.
VREF2: Buffered 2nd reference voltage for driving thermistors. Bypass with an external 1µF capacitor.
VREF1: ADC Reference Voltage. Bypass with an external
1µF capacitor. No DC loads allowed.
GPIO[1:4]: General Purpose I/O. Can be used as digital
inputs or digital outputs, or as analog inputs with a measurement range from V– to 5V. GPIO[2:4] can be used as
an I2C or SPI port.
DTEN: Discharge Timer Enable. Connect this pin to VREG
to enable the Discharge Timer.
DRIVE: Connect the base of an NPN to this pin. Connect
the collector to V+ and the emitter to VREG.
VREG: 5V Regulator Input. Bypass with an external 1μF
capacitor.
ISOMD: Serial Interface Mode. Connecting ISOMD to
VREG configures the LTC6810 for 2-wire isolated interface
(isoSPI) mode. Connecting ISOMD to V– configures the
LTC6810 for 4-wire SPI mode.
WDT: Watchdog Timer Output Pin. This is an open drain
NMOS digital output. It can be left unconnected, or connected with a 1M resistor to VREG. If the LTC6810 does
not receive a valid command within 2 seconds, the watchdog timer circuit will reset the LTC6810 and the WDT pin
will go high impedance.
LTC6810-1
(DAISY-CHAINABLE)
LTC6810-2
(ADDRESSABLE)
ISOMD = VREG ISOMD = V– ISOMD = VREG ISOMD = V–
PORT B
(Pins 39,
38, 35
and 34)
PORT A
(Pins 40,
41, 37
and 36)
IPB
IPB
A3
A3
IMB
IMB
A2
A2
ICMP
ICMP
A1
A1
IBIAS
IBIAS
A0
A0
(NC)
SDO
IBIAS
SDO
(NC)
SDI
ICMP
SDI
IPA
SCK
IPA
SCK
IMA
CSB
IMA
CSB
CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Interface
(SPI). Active low chip select (CSB), serial clock (SCK),
serial data in (SDI), are digital inputs. Serial data out
(SDO) is an open drain NMOS output. SDO requires a 5K
pull-up resistor
A0–A3: Address Pins. These digital inputs are connected
to VREG or V– to set the chip address for addressable
serial commands.
IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA
(plus) and IMA (minus) are a differential input/output pair.
IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB
(plus) and IMB (minus) are a differential input/output pair.
IBIAS: Isolated Interface Current Bias. Tie IBIAS to V–
through a resistor divider to set the interface output current level. When the isoSPI interface is enabled, the IBIAS
pin voltage is 2V. The IPA/IMA or IPB/IMB output current
drive is set to 20 times the current, IB, sourced from the
IBIAS pin.
ICMP: Isolated Interface Comparator Voltage Threshold
Set. Tie this pin to the resistor divider between IBIAS
and V– to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to ½ the
voltage on the ICMP pin.
Rev. A
For more information www.analog.com
17
LTC6810-1/LTC6810-2
BLOCK DIAGRAM
LTC6810-1
1
V–
V–
V–
2 NC
44
43
6 BALANCE FETs
3 V+
S(n)
4 C6
S(n–1)
WDT 42
SDI(NC)
DIGITAL
FILTER
5 S6
LOGIC
AND
MEMORY
6 C5
7 S5
8 C4
C6
C5
C4
C3
C2
C1
C0
SDO(NC)
P
C PIN
MUX
+
IMB
DIGITAL
FILTER
ADC
M
IPB
SERIAL I/O
SCK(IPA)
–
CSB(IMA)
9 S4
10 C3
11 S3
12 C2
S6
S5
S4
S3
S2
S1
S0
SERIAL[1:9]
S PIN
MUX
IBIAS
M
1ST
REFERENCE
V+
LDO (DRIVE)
DIE
TEMPERATURE
13 S2
LDO (VREG)
3V
POR
2ND
REFERENCE
14 C1
LDO1
16 C0
P
17 S0
19
20
21
22
DRIVE
VREG
VREF2
VREF1
15 S1
18
ICMP
P
GPIO1
M
GPIO2
AUX
MUX
I8
I7
I6
I5
I4
I3
I2
I1
I0
V–
V+
VREG
3V
V–
SC
ISOMD
V–
DISCHARGE
TIMER
DTEN
GPIO4
GPIO3
GPIO[4:1]
V–
V–
V–
V–
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
68101 BD1
Rev. A
18
For more information www.analog.com
LTC6810-1/LTC6810-2
BLOCK DIAGRAM
LTC6810-2
1
V–
V–
V–
2 NC
44
43
6 BALANCE FETs
3 V+
S(n)
4 C6
S(n–1)
WDT 42
SDI(IBIAS)
DIGITAL
FILTER
5 S6
LOGIC
AND
MEMORY
6 C5
7 S5
8 C4
C6
C5
C4
C3
C2
C1
C0
SDO(ICMP)
P
C PIN
MUX
+
A2
DIGITAL
FILTER
ADC
M
A3
SERIAL I/O
SCK(IPA)
–
CSB(IMA)
9 S4
10 C3
11 S3
12 C2
S6
S5
S4
S3
S2
S1
S0
SERIAL[1:9]
S PIN
MUX
A0
M
1ST
REFERENCE
V+
LDO (DRIVE)
DIE
TEMPERATURE
13 S2
LDO (VREG)
3V
POR
2ND
REFERENCE
14 C1
LDO1
16 C0
P
17 S0
19
20
21
22
DRIVE
VREG
VREF2
VREF1
15 S1
18
A1
P
GPIO1
M
GPIO2
AUX
MUX
I8
I7
I6
I5
I4
I3
I2
I1
I0
V–
V+
VREG
3V
V–
SC
ISOMD
V–
DISCHARGE
TIMER
DTEN
GPIO4
GPIO3
GPIO[4:1]
V–
V–
V–
V–
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
68101 BD2
Rev. A
For more information www.analog.com
19
LTC6810-1/LTC6810-2
OPERATION
STATE DIAGRAM
The operation of the LTC6810 is divided into two separate
sections: the Core circuit and the isoSPI circuit. Both sections have an independent set of operating states, as well
as a shutdown timeout.
CORE LTC6810 STATE DESCRIPTIONS
SLEEP State
The references and ADC modulator are powered down.
The watchdog timer (see Watchdog and Discharge Timer)
has timed out. The discharge timer is either disabled or
timed out. The supply currents are reduced to minimum
levels. The isoSPI ports will be in the IDLE state. The Drive
pin is 0V. All state machines are reset to their default state
If a WAKEUP signal is received (see Waking Up the Serial
Interface), the LTC6810 will enter the STANDBY state.
STANDBY State
The references and the ADC are off. The watchdog timer
and/or the discharge timer is running. VREG pin is powered to 5.2V through an external transistor controlled by
the DRIVE pin. Alternatively, when V+ is less than 12V,
VREG can be powered through the internal LDO to 4.7V.
VREG can also be powered through an external source. In
this case, the internal regulator must be disabled to avoid
contention by floating the DRIVE pin. For more details see
VREG Configurations.
When a valid ADC command is received or the REFON
bit is set to 1 in the Configuration Register Group, the
IC pauses for tREFUP to allow for the references to power
up and then enters either the REFUP or MEASURE state.
Otherwise, if no valid commands are received for tSLEEP,
the IC returns to the SLEEP state if DTEN = 0 or enters
the EXTENDED BALANCING state if DTEN = 1.
REFUP State
To reach this state the REFON bit in the Configuration
Register Group must be set to 1 (using the WRCFG command, see Table 40). The ADCs are off. The references
are powered up so that the LTC6810 can initiate ADC
conversions more quickly than from the STANDBY state.
When a valid ADC command is received, the IC goes to
the MEASURE state to begin the conversion. Otherwise,
the LTC6810 will return to the STANDBY state when the
REFON bit is set to 0, (using WRCFGA command). If no
valid commands are received for tSLEEP, the IC returns
to the SLEEP state if DTEN = 0 or enters the EXTENDED
BALANCING state if DTEN = 1
CORE LTC6810
isoSPI PORT
SLEEP
IDLE
WD TIMEOUT
AND DTEN = 0
(tSLEEP)
WAKE-UP
SIGNAL
(tWAKE)
DCTO REACHES 0
WD TIMEOUT
WD TIMEOUT
AND DTEN = 1
AND DTEN = 0
EXTENDED
STANDBY
(tSLEEP)
BALANCING
WAKE-UP
REFON = 0
SIGNAL (tWAKE)
REFON = 1
(tREFUP) ADC
EVERY 30s
COMM
AND DTMEN=1
REFUP
(tREFUP)
ADC
WAKE-UP
COMMAND
SIGNAL
CONV
CONV DONE (tWAKE)
DONE
(REFON = 0)
WD TIMEOUT
AND DTEN = 1
CONV DONE
(REFON = 1)
MEASURE
IDLE TIMEOUT
(tIDLE)
WAKE-UP SIGNAL
(CORE = SLEEP)
(tWAKE)
WAKE-UP SIGNAL
(CORE = STANDBY)
(tREADY)
READY
NO ACTIVITY ON
isoSPI PORT
DTM
MEASURE
TRANSMIT/RECEIVE
ACTIVE
NOTE: STATE TRANSITION
DELAYS DENOTED BY (tX)
68101 F01
Figure 1. LTC6810 Operation State Diagram
Rev. A
20
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
MEASURE State
isoSPI STATE DESCRIPTIONS
The LTC6810 performs ADC conversions in this state. The
references and ADCs are powered up.
Note: The LTC6810-1 has two isoSPI ports (A and B), for
daisy-chain communication. The LTC6810-2 has only one
isoSPI port (A), for parallel-addressable communication.
After ADC conversions are complete the LTC6810 will
transition to either the REFUP or STANDBY states,
depending on the REFON bit. Additional ADC conversions
can be initiated more quickly by setting REFON = 1 to take
advantage of the REFUP state.
Note: Non-ADC commands do not cause a Core state transition. Only an ADC Conversion or DIAGN command will
place the Core in the MEASURE state.
EXTENDED BALANCING State
The watchdog timer has timed out, but the discharge timer
has not yet timed out (DTEN = 1). Discharge by PWM may
be in progress. If the Discharge Timer Monitor is enabled
then the LTC6810 will transition to the DTM MEASURE
state every 30 seconds to measure the cell voltages. If a
WAKEUP signal is received, the LTC6810 will transition
from EXTENDED BALANCING state to STANDBY state.
Discharge Timer Monitor MEASURE State
The watchdog timer has timed out but background monitoring has been enabled (DTMEN = 1 in the Configuration
Register). The LTC6810 enters this state from the
EXTENDED BALANCING state once every 30 seconds to
measure the cell voltages. The LTC6810 is in the highest
core power state and an A/D conversion is in progress. If
a WAKEUP signal is received, the LTC6810 will transition
from DTM MEASURE state to STANDBY state.
IDLE State
The isoSPI ports are powered down.
When isoSPI port A or port B (LTC6810-1 only) receives a
WAKEUP signal (see Waking up the Serial Interface), the
isoSPI enters the READY state. This transition happens
quickly (within tREADY) if the Core is in the STANDBY state.
If the Core is in the SLEEP state when the isoSPI receives
a WAKEUP signal, the it transitions to the READY state
within tWAKE.
READY State
The isoSPI port(s) are ready for communication. Port
B is enabled only for LTC6810-1, and is not present on
the LTC6810-2. The serial interface current in this state
depends on if the part is LTC6810-1 or LTC6810-2, the
status of the ISOMD pin, and RBIAS = RB1 + RB2 (the
external resistors tied to the IBIAS pin).
If there is no activity (i.e. no WAKEUP signal) for greater
than tIDLE = 5.5ms, the LTC6810 goes to the IDLE state.
When the serial interface is transmitting or receiving data
the LTC6810 goes to the ACTIVE state.
ACTIVE State
The LTC6810 is transmitting/receiving data using one
or both of the isoSPI ports. The serial interface consumes maximum power in this state. The supply current
increases with clock frequency as the density of isoSPI
pulses increases.
Rev. A
For more information www.analog.com
21
LTC6810-1/LTC6810-2
OPERATION
POWER CONSUMPTION
The LTC6810 is powered via two pins: V+ and VREG. The
V+ input requires voltage greater than or equal to the top
cell voltage minus 0.3V, and it provides power to the high
voltage elements of the core circuitry. The VREG input
requires 5V and provides power to the remaining core
circuitry and the isoSPI circuitry.
The power consumption varies according to the operational states. The VREG input can be powered through an
external transistor that is driven by the regulated DRIVE
output pin, through the internal LDO, or through an external supply. The internal LDO is powered from V+, so in
this configuration VREG current also comes from V+. Total
V+ current when using the internal LDO to power VREG is
given by,
IVP_INTREG = IVP + IREG
IVP current depends only on the Core state. However, IREG
current depends on both the Core state and isoSPI state,
and can therefore be divided into two components. The
isoSPI interface draws current only from the VREG pin.
Table 1 provides typical values for IVP and IREG(Core) supply currents in each of the Core states. Table 2 provides
equations to approximate IREG(isoSPI) supply pin currents
in each of the isoSPI states.
Table 1. Core Supply Current
STATE
IVP
IREG(CORE)
VREG = 0V
5.7µA
0µA
VREG = 5V
3.5µA
3.3µA
STANDBY, Int Regulator Enabled
75µA
55µA
STANDBY, Int Regulator Disabled
20µA
55µA
REFUP
30µA
1.7mA
MEASURE
50µA
6.1mA
SLEEP
Table 2. isoSPI Supply Current Equations
isoSPI
STATE
IDLE
READY
ACTIVE
ISOMD
CONNECTION
N/A
VREG
V–
VREG
IREG = IREG(Core) + IREG(isoSPI)
IREG(isoSPI)
0mA
2.2mA + 3 • IB
1.5mA + 3 • IB
⎛
100n s ⎞
Write: 2.5mA + ⎜ 3 + 20 •
⎟ • IB
tCLK ⎠
⎝
⎛
100n s • 1.5 ⎞
Read: 2.5mA + ⎜ 3 + 20 •
⎟ • IB
tCLK
⎠
⎝
V–
⎛
100n s ⎞
1.8mA + ⎜ 3 + 20 •
⎟ • IB
tCLK ⎠
⎝
Rev. A
22
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
VREG CONFIGURATIONS
This section describes the different configurations that
can be used to power VREG on the LTC6810. When V+
pin voltage is less than 12V, the DRIVE pin voltage drops
below its nominal value as the regulator on the DRIVE pin
does not have sufficient headroom. Under these conditions VREG pin cannot be powered through an external
transistor. To overcome this problem, LTC6810 has an
internal LDO that powers the VREG pin to 4.7V typically.
The internal LDO can operate for V+ pin voltage as low as
5V. The internal LDO is enabled by applying a load current
greater than 15µA on the DRIVE pin. Figure 2 shows a
typical configuration for LTC6810 using the internal LDO
when V+ is less than 12V. The suggested 100K resistor on
the DRIVE pin draws a minimum of 30µA from the DRIVE
pin. This keeps the internal regulator enabled.
LTC6810
V+ 5V TO 12V
DRIVE
VREG
V–
3V TO 5.8V
4.7V
1µF
100k
Figure 3 shows a typical configuration for LTC6810 that
uses an external transistor to power VREG. Note that this
configuration can still be used if V+ drops below 12V,
but when VREG pin voltage set by the external transistor
drops below the internal LDO level, the internal LDO will
take over and power VREG.
LTC6810
DRIVE
VREG
>12V
5.8V
5.2V
100k
1µF
V–
68101 F03
Figure 3. VREG Powered by External Transistor
Alternatively, VREG pin can also be powered from an external source. In this configuration, it is important to ensure
that the internal LDO is always shutdown so there is no
contention problem. This can be achieved by floating the
DRIVE pin. Figure 4 shows a typical configuration for
LTC6810 when VREG is powered from an external source.
LTC6810
68101 F02
Figure 2. VREG Powered by Internal LDO
The power dissipation across the pass transistor in the
internal LDO is (V+ – VREG ) • IREG. To limit the power
dissipation inside the part it is recommended to power
VREG using an external transistor when V+ pin voltage is
greater than 12V. The external transistor is driven by the
regulated DRIVE pin voltage that sets VREG pin voltage to
5.2V typically. The internal LDO is designed to only source
current, so when VREG pin is driven to 5.2V by the external
transistor the internal regulator is gracefully shutdown.
V+
V+
DRIVE
VREG
5V
ISOLATED
POWER SUPPLY
V–
68101 F04
Figure 4. VREG Powered by an Independent Supply
Rev. A
For more information www.analog.com
23
LTC6810-1/LTC6810-2
OPERATION
There is one ADC inside the LTC6810. The ADC is used to
measure the cell voltages via the C or S pins and general
purpose inputs.
ADC Modes
The ADCOPT bit (CFGR0[0]) in the Configuration Register
Group and the mode selection bits MD[1:0] in the conversion command together provide eight modes of operation
for the ADC which correspond to different oversampling
ratios (OSR). The accuracy and timing of these modes
are summarized in Table 3. In each mode, the ADC first
measures the inputs, and then performs a calibration. The
names of the modes are based on the –3dB bandwidth of
the ADC measurement.
Mode 7kHz (Normal Mode): In this mode, the ADC has
high resolution and low TME (total measurement error).
This is considered the normal operating mode because of
the optimum combination of speed and accuracy.
Mode 27kHz (Fast Mode): In this mode, the ADC has
maximum throughput but has some increase in TME (total
measurement error). So this mode is also referred to as
the fast mode. The increase in speed comes from a reduction in the oversampling ratio. This results in an increase
in noise and average measurement error.
in STANDBY state, an additional tREFUP time is required to
power up the reference before beginning the ADC conversions. The reference can remain powered up between ADC
conversions if the REFON bit in Configuration Register
Group is set to 1 so the Core is in REFUP state after a
delay tREFUP. If REFON is set to 1 the Core will go from
STANDBY to the REFUP state after a delay tREFUP. Then,
the subsequent ADC commands will not have the tREFUP
delay before beginning ADC conversions.
ADC Range and Resolution
The cell inputs and GPIO inputs have the same range and
resolution. The ADC inside the LTC6810 has an approximate range from –0.82V to +5.73V. Negative readings are
rounded to 0V. The format of the data is a 16-bit unsigned
integer where the LSB represents 100µV. Therefore, a
reading of 0x80E8 (33,000 decimal) indicates a measurement of 3.3V.
1
0.8
Mode 26Hz (Filtered Mode): In this mode, the ADC digital
filter –3dB frequency is lowered to 26Hz by increasing the
OSR. This mode is also referred to as the filtered mode
due to its low –3dB frequency. The accuracy is similar to
the 7kHz (normal) mode with lower noise.
Modes 14kHz, 3kHz, 2kHz, 1kHz and 422Hz: Modes
14kHz, 3kHz, 2kHz, 1kHz and 422Hz provide additional
options to set the ADC digital filter –3dB at 13.5kHz,
3.4kHz, 1.7kHz, 845Hz and 422Hz respectively. The accuracy of the 14kHz mode is similar to the 27kHz (fast)
mode. The accuracy of 3kHz, 2kHz, 1kHz and 422Hz
modes is similar to the 7kHz (normal) mode.
The filter bandwidths and the conversion times for these
modes are provided in Table 3 and Table 5. If the Core is
NORMAL MODE
FILTERED MODE
0.9
PEAK NOISE (mV)
ADC OPERATION
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5 2 2.5 3 3.5 4
ADC INPUT VOLTAGE (V)
4.5
5
68101 F05
Figure 5.
Delta-Sigma ADCs have quantization noise which depends
on the input voltage, especially at low Over Sampling
Ratios (OSR), such as in fast mode. In some of the ADC
modes, the quantization noise increases as the input voltage approaches the upper and lower limits of the ADC
range. For example, the total measurement noise versus
input voltage in normal and filtered modes is shown in
Figure 5.
Rev. A
24
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
Table 3. ADC Filter Bandwidth, Accuracy and Speed
MODE
–3dB FILTER BW
–40dB FILTER BW
TME SPEC AT 3.3V, 25°C
TME SPEC AT 3.3V, –40°C, 125°C
27kHz (Fast Mode)
27kHz
84kHz
±5.5mV
±5.5mV
14kHz
13.5kHz
42kHz
±5.5mV
±5.5mV
7kHz (Normal Mode)
6.8kHz
21kHz
±1.8mV
±2.4mV
3kHz
3.4kHz
10.5kHz
±1.8mV
±2.4mV
2kHz
1.7kHz
5.3kHz
±1.8mV
±2.4mV
1kHz
845Hz
2.6kHz
±1.8mV
±2.4mV
422Hz
422Hz
1.3kHz
±1.8mV
±2.4mV
26Hz (Filtered Mode)
26Hz
82Hz
±1.8mV
±2.4mV
Note: TME is the total measurement error.
Table 4. ADC Range and Resolution
SPECIFIED
RANGE
PRECISION
RANGE2
MAX NOISE
NOISE FREE
RESOLUTION3
27kHz (fast)
±4mVP-P
10 Bits
14kHz
±1mVP-P
12 Bits
7kHz (normal)
±250µVP-P
14 Bits
3kHz
±150µVP-P
14 Bits
MODE
FULL RANGE1
–0.8192V to
5.7344V
0V to 5V
LSB
0.5V to 4.5V
100µV
FORMAT
Unsigned 16 Bits
±100µVP-P
15 Bits
1kHz
±100µVP-P
15 Bits
422Hz
±100µVP-P
15 Bits
26Hz (filtered)
±50µVP-P
16 Bits
2kHz
1. Negative readings are rounded to 0V.
2. PRECISION RANGE is the range over which the noise is less than MAX NOISE.
3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE.
The specified range of the ADC is 0V to 5V. In Table 4, the
precision range of the ADC is arbitrarily defined as 0.5V
to 4.5V. This is the range where the quantization noise is
relatively constant even in the lower OSR modes (see
Figure 5). Table 4 summarizes the total noise in this range
for all eight ADC operating modes. Also shown is the
noise free resolution. For example, 14-bit noise free resolution in normal mode implies that the top 14 bits will be
noise free with a DC input, but that the 15th and 16th least
significant bits (LSB) will flicker.
Rev. A
For more information www.analog.com
25
LTC6810-1/LTC6810-2
OPERATION
tREFUP
SERIAL
INTERFACE
tCYCLE
tSKEW2
ADCV + PEC
MEASURE
C1 TO C0
ADC1
MEASURE
C2 TO C1
t1M
t0
MEASURE
C3 TO C2
t2M
MEASURE
C4 TO C3
t3M
MEASURE
C5 TO C4
t4M
MEASURE
C6 TO C5
t5M
CALIBRATE
t6M
tC
68101 F06
Figure 6. Timing for ADCV Command Measuring All 6 Cells, SCONV = 0
Table 5. Conversion and Synchronization Times for ADCV Command Measuring All Six Cells, SCONV = 0
CONVERSION TIMES (in µs)
SYNCHRONIZATION TIME
(IN µs)
MODE
t0
t1M
t2M
t5M
t6M
tC,MCAL = 0
tC,MCAL = 1
tSKEW2
27kHz
0
57
104
244
291
524
1,106
233
14kHz
0
87
162
390
465
699
1,281
379
7kHz
0
145
279
681
815
1,165
2,328
670
3kHz
0
261
511
1,262
1,513
1,863
3,026
1,252
2kHz
0
494
977
2,426
2,909
3,259
4,423
2,415
1kHz
0
959
1,908
4,753
5,702
6,052
7,215
4,742
422Hz
0
1,890
3,770
9,408
11,287
11,637
12,801
9,397
26Hz
0
29,818
59,624
149,044
178,851
182,692
201,310
149,033
Table 5 shows the conversion times for the ADCV command measuring all six cells. The total conversion time is
given by tC which indicates the end of the calibration step.
Table 6 shows the conversion time for ADCV command
measuring only 1 cell. tC indicates the total conversion
time for this command.
Figure 7 illustrates the timing of the ADCV command that
measures only one cell.
Table 6. Conversion Times for ADCV Command Measuring Only
One Cell, SCONV = 0
tREFUP
SERIAL
INTERFACE
MODE
tCYCLE
ADCV + PEC
MEASURE
C2 TO C1
ADC1
t0
CALIBRATE
t1M
CONVERSION TIMES (in μs)
tC
68101 F07
Figure 7. Timing for ADCV command measuring 1 cell,
SCONV = 0
t0
t1M
tC
27kHz
0
57
200
14kHz
0
87
229
7kHz
0
145
404
3kHz
0
261
520
2kHz
0
494
753
1kHz
0
959
1,218
422Hz
0
1,890
2,149
26Hz
0
29,817
33,567
Rev. A
26
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
Under/Over Voltage Monitoring
Whenever the C inputs are measured, the results are
compared to under voltage and over voltage thresholds
stored in memory. If the reading of a cell is above the over
voltage limit, a bit in memory is set as a flag. Similarly,
measurement results below the under voltage limit cause
a flag to be set. The over voltage and under voltage thresholds are stored in the Configuration Register Group. The
flags are stored in Status Register Group B.
Auxiliary (GPIO) Measurements (ADAX Command)
The ADAX command initiates the measurement of the
GPIO inputs. This command has options to select which
GPIO input to measure (GPIO1–4) and which ADC mode
to use. The ADAX command also measures the S0 pin and
the 2nd reference relative to the V– pin voltage. There are
options in the ADAX command to measure subsets of S0,
the GPIOs and the 2nd reference separately or to measure S0, all four GPIOs and the 2nd reference in a single
command. See the section on Commands for the ADAX
command format. All auxiliary measurements are relative
to the V– pin voltage. This command can be used to read
external temperature by connecting the temperature sensors to the GPIOs. These sensors can be powered from
the 2nd reference which is also measured by the ADAX
command, resulting in precise ratiometric measurements.
Figure 8 illustrates the timing of the ADAX command measuring S0, all GPIOs and the 2nd reference. The 2nd reference is measured after GPIO4.
Table 7 shows the conversion time for the ADAX command measuring S0, all the GPIOs and the 2nd reference.
tC indicates the total conversion time.
The timing for ADAX measuring a single auxiliary is the
same as ADCV measuring a single cell.
tREFUP
SERIAL
INTERFACE
tCYCLE
tSKEW
ADCV + PEC
MEASURE
S0
ADC1
MEASURE
GPIO1
t1M
t0
MEASURE
GPIO2
t2M
MEASURE
GPIO3
t3M
MEASURE
GPIO4
t4M
MEASURE
2ND REF
t5M
CALIBRATE
tC
t6M
68101 F08
Figure 8. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
Table 7. Conversion and Synchronization Times for ADAX Command Measuring S0, All GPIOs and 2nd Reference
CONVERSION TIMES (in µs)
MODE
t0
t1M
t2M
t3M
t4M
t5M
t6M
tC,MCAL = 0
tC,MCAL = 1
27kHz
0
57
104
151
197
244
291
521
1,103
14kHz
0
87
162
238
314
390
465
695
1,277
7kHz
0
145
279
413
547
681
815
1,161
2,324
3kHz
0
261
511
762
1,012
1,262
1,513
1,859
3,023
2kHz
0
494
977
1,460
1,943
2,426
2,909
3,255
4,419
1kHz
0
959
1,908
2,856
3,805
4,753
5,702
6,048
7,212
422Hz
0
1,890
3,770
5,649
7,529
9,408
11,287
11,634
12,797
26Hz
0
29,818
59,624
89,431
119,238
149,044
178,851
182,688
201,306
Rev. A
For more information www.analog.com
27
LTC6810-1/LTC6810-2
OPERATION
Auxiliary (GPIO) Measurements with Digital
Redundancy (ADAXD Command)
The ADAXD command operates similarly to the ADAX
command except that an additional diagnostic is performed using digital redundancy. See A/D Conversion
with Digital Redundancy.
The execution time of ADAX and ADAXD is the same.
Measuring Cell Voltages and GPIOs (ADCVAX
Command)
The ADCVAX command combines six cell measurements
with measurements of S0 and GPIO1. This command
tREFUP
SERIAL
INTERFACE
simplifies the synchronization of battery cell voltage and
current measurements when a current sensor is connected to the GPIO1 input. Figure 9 illustrates the timing
of ADCVAX command with SCONV set to 0. See the section on Commands for the ADCVAX command format. The
time values in Figure 9 assume the ADC is operating in
the 27kHz (fast) mode. The synchronization of the current
and voltage measurements, tSKEW1, in fast mode is
within 196µs.
Table 8 shows the conversion and synchronization
time for the ADCVAX command in different modes with
SCONV = 0. The total conversion time for the command
is given by tC.
tCYCLE
tSKEW1
ADCV + PEC
MEASURE
C1 TO C0
ADC
MEASURE
C2 TO C1
t1M
t0
MEASURE
C3 TO C2
t2M
MEASURE
S0
t3M
MEASURE
GPIO1
t4M
MEASURE
C4 TO C3
t5M
MEASURE
C5 TO C4
t6M
MEASURE
C6 TO C5
t7M
CALIBRATE
t8M
tC
68101 F09
Figure 9. Timing of ADCVAX command, SCONV = 0
Table 8. Conversion and Synchronization Times for ADCVAX Command, SCONV = 0
SYNCHRONIZATION
TIME (IN µs)
CONVERSION TIMES (in µs)
MODE
t0
t1M
t2M
t3M
t4M
t5M
t6M
t7M
t8M
27kHz
0
57
104
151
205
251
305
352
399
tC,MCAL = 0 tC,MCAL = 1
682
1,497
tSKEW1
194
14kHz
0
87
162
238
321
397
480
556
631
915
1,730
310
7kHz
0
145
279
413
554
688
829
963
1,097
1,497
3,126
543
3kHz
0
261
511
762
1,019
1,270
1,527
1,777
2,028
2,427
4,057
1,008
2kHz
0
494
977
1,460
1,950
2,433
2,923
3,407
3,890
4,289
5,918
1,939
1kHz
0
959
1,908
2,856
3,812
4,760
5,716
6,665
7,613
8,013
9,642
3,801
422Hz
0
1,890
3,770
5,649
7,536
9,415
11,302
13,181
15,060
15,460
17,089
7,525
26Hz
0
29,817
59,624
89,431
119,245 149,051 178,865 208,672 238,479
242,369
268,435
119,234
Rev. A
28
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
DATA ACQUISITION SYSTEM DIAGNOSTICS
The battery monitoring data acquisition system is comprised of a multiplexer, an ADC, 1st reference, digital
filters, and memory. To ensure long term reliable performance there are several diagnostic commands which can
be used to verify the proper operation of these circuits.
Measuring Internal Device Parameters (ADSTAT
Command)
The ADSTAT command is a diagnostic command that
measures the following internal device parameters: Sum
of All Cells (SC), Internal Die Temperature (ITMP), Analog
Power Supply (VA) and Digital Power Supply (VD). These
parameters are described in the section below. All the 8
ADC modes described earlier are available for these conversions. See the section on Commands for the ADSTAT
command format.
Figure 10 illustrates the timing of the ADSTAT command
measuring all the 4 internal device parameters.
Table 9 shows the conversion time of the ADSTAT command measuring all the 4 internal parameters. tC indicates
the total conversion time for the ADSTAT command. When
ADSTAT is performed measuring all 4 internal parameters,
the LTC6810 will always perform four calibration cycles,
regardless of MCAL.
The timing for ADSTAT measuring a single status parameter is the same as ADCV measuring a single cell.
Sum of All Cells Measurement: The Sum of All Cells measurement is the voltage between V+ and V– with a 10:1
attenuation. The V+ to V– voltage is the same as the total
battery voltage when the IC is powered by the battery cells.
The 16-bit ADC value of Sum of All Cells measurement (SC)
is stored in Status Register Group A. From the SC value, the
sum of all cell voltage measurements is given by,
Sum of All Cells = SC • 10 • 100µV
Internal Die Temperature: The ADSTAT command can
measure the internal die temperature. The 16 bit ADC
value of the die temperature measurement (ITMP) is
stored in Status Register Group A. From ITMP, the actual
die temperature is calculated using the expression,
Internal Die Temperature (°C) = ITMP • 100µV °C – 273°C
7.5mV
tCYCLE
tSKEW
tREFUP
SERIAL
INTERFACE
ADCV + PEC
MEASURE
SC
ADC
MEASURE
ITMP
t1M
t0
MEASURE
VA
t2M
MEASURE
VD
t3M
CALIBRATE
t4M
tC
68101 F10
Figure 10. Timing for ADSTAT command measuring SC, ITMP, VA, VD
Table 9. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, VD
SYNCHRONIZATION TIME
(in µs)
CONVERSION TIMES (in µs)
MODE
t0
t1M
t2M
t3M
t4M
tC,MCAL = 1 OR 0
27kHz
0
57
104
151
197
741
0
tSKEW
140
14kHz
0
87
162
238
314
858
0
227
7kHz
0
145
279
413
547
1,556
0
402
3kHz
0
261
511
762
1,012
2,021
0
751
2kHz
0
494
977
1,460
1,943
2,952
0
1,449
1kHz
0
959
1,908
2,856
3,805
4,814
0
2,845
422Hz
0
1,890
3,770
5,649
7,528
8,538
0
5,638
26Hz
0
29,817
59,624
89,431
119,237
134,210
0
89,420
Rev. A
For more information www.analog.com
29
LTC6810-1/LTC6810-2
OPERATION
Power Supply Measurements: The ADSTAT command is
also used to measure the Analog Power Supply (VREG)
and Digital Power Supply (VREGD).
using digital redundancy. See the A/D Conversion with
Digital Redundancy section.
The execution time of ADSTAT and ADSTATD is the same.
The 16 bit ADC value of the analog power supply measurement (VA) is stored in Status Register Group A. The 16 bit
ADC value of the digital power supply measurement (VD)
is stored in Status Register Group B. From VA and VD, the
power supply measurements are given by:
Measuring Cell Voltages and V+ to V– (ADCVSC
Command)
The ADCVSC command combines six cell measurements
and the measurement of Sum of All Cells. This command
simplifies the synchronization of the individual battery
cell voltage and the total Sum of All Cells measurement.
Figure 11 illustrates the timing of ADCVSC command.
See the section on Commands for the ADCVSC command format. The synchronization of the cell voltage and
Sum of All Cells measurements, tSKEW, in fast mode is
within 147µs.
Analog Power Supply Measurement (VREG) = VA • 100µV
Digital Power Supply Measurement (VREGD) = VD • 100µV
The value of VREG is determined by external components.
VREG should be between 4.5V and 5.5V to maintain accuracy. The value of VREGD is determined by internal components. The normal range of VREGD is 2.7V to 3.6V.
Table 10 shows the conversion and synchronization time
for the ADCVSC command in different modes (with
SCONV = 0). The total conversion time for the command
is given by tC. When ADCVSC is performed, the LTC6810
will always perform seven calibration cycles, regardless
of MCAL.
Measuring Internal Device Parameters with Digital
Redundancy (ADSTATD Command)
The ADSTATD command operates similarly to the ADSTAT
command except that an additional diagnostic is performed
tCYCLE
tREFUP
SERIAL
INTERFACE
tSKEW
ADCV + PEC
MEASURE
C1 TO C0
ADC
MEASURE
C2 TO C1
t1M
t0
MEASURE
C3 TO C2
t2M
MEASURE
SC
t3M
MEASURE
C4 TO C3
t4M
MEASURE
C5 TO C4
t5M
MEASURE
C6 TO C5
t6M
CALIBRATE
t7M
tC
68101 F11
Figure 11. Timing for ADCVSC Command, SCONV = 0
Table 10. Conversion and Synchronization Times for ADCVSC Command, SCONV = 0
SYNCHRONIZATION TIME
(in µs)
CONVERSION TIMES (in µs)
MODE
t0
t1M
t2M
t3M
t4M
t5M
t6M
t7M
tC,MCAL = 1 OR 0
tSKEW
27kHz
0
57
104
151
205
259
305
352
1,316
147
14kHz
0
87
162
238
321
404
480
556
1,520
235
7kHz
0
145
279
413
554
695
829
963
2,742
409
3kHz
0
261
511
762
1,019
1,277
1,527
1,777
3,556
758
2kHz
0
494
977
1,460
1,950
2,440
2,923
3,407
5,185
1,456
1kHz
0
959
1,908
2,856
3,812
4,768
5,716
6,665
8,443
2,853
422Hz
0
1,890
3,770
5,649
7,536
9,422
11,302
13,181
14,960
5,645
26Hz
0
29,817
59,624
89,431
119,245
149,059
178,865
208,672
234,887
89,427
Rev. A
30
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
A/D Conversion with Digital Redundancy
The internal ADC contains its own digital filter. The
LTC6810 also contains a second digital filter that is used
for redundancy and error checking.
All of the ADC and self test commands except ADAX and
ADSTAT can operate with digital redundancy. This includes
ADCV, ADOW, CVST, ADAXD, AXOW, AXST, ADSTATD,
STATST, ADCVAX and ADCVSC. DIS_RED and SCONV
must be set to 0 to enable digital redundancy during cell
measurements (see Redundant Cell Measurement Using
the S pins). When performing an ADC conversion with
redundancy, the analog modulator sends its bit stream
to both the primary digital filter and the redundant digital
filter. At the end of the conversion the results from the
two filters are compared. If any result bit mismatch is
detected then a digital redundancy fault code is stored
in place of the ADC result. The digital redundancy fault
code is a value of 0xFF0X. This is detectable because it
falls outside the normal result range of 0x0000 to 0xDFFF.
The last 4 bits are used to indicate which nibble(s) of the
result values did not match.
Indication of Digital Redundancy Fault Codes
DIS_RED bit in the Configuration Register Group is written to 1 it will disable the digital redundancy comparison
and subsequent ADC commands will store the normal
ADC result.
Redundant Cell Measurement Using the S pins
The LTC6810 has the ability to perform redundant measurements of the cells by measuring across the S pins.
Redundant measurements using an independent pair of
pins can be used to detect if leakage is present at the
pins of the IC, in the external filter components or in the
internal MUX. The Block Diagram (LTC6810-1) shows that
both the C pins and the S pins can be connected to the
ADC. If a cell is measured twice using two different measurement paths and the measurements agree, than the
two paths can be considered to be functioning correctly.
The host can enable this feature by writing the SCONV
bit in the Configuration Register Group to 1. Then any
subsequent ADC command that measures a cell voltage
will measure first using the C pins and then measure again
using the S pins. The results of the C pin measurements
are stored in the C voltage register groups. The results
from the S pin measurements are stored in S voltage
register groups (Redundant S Voltage Register Group A,
Redundant S Voltage Register Group B). It is up to the
host controller to compare the 2 measurements. The measurements may differ by several LSBs due to the quantization noise of the ADC and different external filtering on
the C pins and S pins.
DIGITAL REDUNDANCY FAULT
CODE 4 LSBs
Indication
0b0XXX
No fault detected in bits 15–12.
0b1XXX
Fault detected in bits 15–12.
0bX0XX
No fault detected in bits 11–8.
0bX1XX
Fault detected in bits 11–8.
0bXX0X
No fault detected in bits 7–4.
0bXX1X
Fault detected in bits 7–4.
0bXXX0
No fault detected in bits 3–0.
0bXXX1
Fault detected in bits 3–0.
S pin measurements utilize the redundant digital filter to
provide additional redundancy and error checking. So the
digital redundancy feature is not available when performing cell measurements with S pins.
0b0000
The digital redundancy feature will
not write this value of all zeros in
the last 4 bits.
Figure 12 shows the ADCV sequence measuring 6 cells
with redundant measurements enabled.
When the FDRF bit in the Configuration Register Group is
written to 1 it will force the digital redundancy comparison to fail during subsequent A/D conversions. When the
Table 11 shows the conversion times for the ADCV command measuring all six cells with redundant measurements enabled. The total conversion time is given by tC
which indicates the end of the calibration step.
Rev. A
For more information www.analog.com
31
LTC6810-1/LTC6810-2
OPERATION
tCYCLE
tREFUP
SERIAL
INTERFACE
ADCV + PEC
MEASURE
C1 TO C0
ADC
t0
MEASURE
S1 TO S0
t1M
MEASURE
C2 TO C21
t2M
MEASURE
S2 TO S1
MEASURE
C6 TO C5
t4M t10M
t3M
MEASURE
S6 TO S5
t11M
CALIBRATE
t12M
tC
68101 F12
Figure 12. Timing for ADCV Command Measuring All 6 Cells, SCONV = 1
Table 11. Conversion Times for ADCV Command Measuring All Six Cells, SCONV = 1
CONVERSION TIMES (in µs)
MODE t0
t1M
t2M
t3M
t4M
t5M
t6M
t7M
t8M
t9M
t10M
t11M
t12M
27kHz
0
57
104
151
197
244
291
337
384
431
477
524
571
14kHz
0
87
163
238
314
390
466
541
617
693
769
844
920
1,263
2,543
7kHz
0
145
279
413
547
680
814
948
1,082
1,216
1,350
1,484
1,618
2,077
4,637
3kHz
0
261
511
762
1,012
1,262
1,513
1,763
2,013
2,263
2,514
2,764
3,014
3,473
6,033
2kHz
0
494
977
1,460
1,943
2,426
2,909
3,392
3,875
4,358
4,841
5,324
5,807
6,266
8,827
1kHz
0
959
1,908
2,856
3,805
4,753
5,702
6,650
7,599
8,547
9,496
10,444
11,393
11,852
14,412
1,890
3,770
5,649
7,528
9,408
11,287
13,167
15,046
16,925
18,805
20,684
22,563
23,023
25,583
0 29,818 59,624 89,431 119,238 149,044 178,851 208,658 238,464 268,271 298,078 327,884 357,691
361,641
402,601
422Hz 0
26Hz
tREFUP
SERIAL
INTERFACE
tCYCLE
Figure 13 illustrates the timing of the ADCV command that
measures one cell with redundant measurement.
ADCV + PEC
MEASURE
C2 TO C1
ADC2
t0
MEASURE
S2 TO S1
t1M
tC,MCAL = 0 tC,MCAL = 1
913
2,194
CALIBRATE
t2M
tC
68101 F13
Figure 13. Timing for ADCV Command Measuring
One Cell, SCONV = 1
Table 12. Conversion Times for ADCV Command Measuring Only
One Cell, SCONV = 1
CONVERSION TIMES (in µs)
MODE
t0
t1M
t2M
tC,MCAL = 0 tC,MCAL = 1
265
381
27kHz
0
57
104
14kHz
0
87
162
323
440
7kHz
0
145
279
556
789
3kHz
0
261
512
789
1,021
2kHz
0
494
977
1,254
1,487
1kHz
0
959
1,908
2,185
2,418
422Hz
0
1,890
3,770
4,047
4,280
26Hz
0
29,817
59,624
63,392
67,116
Table 12 shows the conversion time for ADCV command
measuring only 1 cell. tC indicates the total conversion
time for this command.
Figure 14 illustrates the timing of the ADCVAX command
with SCONV set to 1.
Table 13 shows the conversion and synchronization time
for the ADCVAX command in different modes with SCONV
set to 1. The total conversion time for the command is
given by tC.
Figure 15 illustrates the timing of the ADCVSC command
with SCONV set to 1.
Table 14 shows the conversion and synchronization time
for the ADCVSC command in different modes with SCONV
set to 1. The total conversion time for the command is
given by tC.
Rev. A
32
For more information www.analog.com
ADCV +
PEC
t0
MEASURE
C1 TO C0
t1M
t2M t5M
t0
0
0
0
0
0
0
0
0
MODE
27kHz
14kHz
7kHz
3kHz
2kHz
1kHz
For more information www.analog.com
422Hz
26Hz
29,817
1,890
960
494
261
145
87
58
t1M
t2M
59,624
3,770
1,908
977
511
279
162
104
t3M
89,431
5,649
2,857
1,460
762
413
238
151
t4M
t6M
MEASURE
SO
t7M
MEASURE
GPIO1
t8M
MEASURE
C4 TO C3
t5M
9,408
4,753
2,426
1,262
681
390
244
t6M
11,287
5,702
2,909
1,513
815
465
291
13,174
6,658
3,399
1,770
956
548
345
t7M
15,053
7,606
3,882
2,020
1,090
624
392
t8M
16,940
8,562
4,373
2,278
1,231
707
446
t9M
790
500
t10M
18,827
9,518
4,863
2,536
1,372
CONVERSION TIMES (in µs)
20,706
10,466
5,346
2,786
1,506
866
546
t11M
t9M t12M
22,585
11,415
5,829
3,036
1,640
942
593
t12M
MEASURE
C6 TO C5
24,465
12,363
6,312
3,287
1,774
1,017
640
t13M
t13M
t14M
26,344
13,312
6,795
3,537
1,908
1,093
686
tC
421,333
26,860
13,828
7,311
4,053
2,424
1,493
1,086
469,740
29,886
16,853
10,337
7,078
5,449
3,006
2,599
tC,MCAL = 0 tC,MCAL = 1
68101 F14
CALIBRATE
t14M
MEASURE
S6 TO S5
119,237 149,044 178,851 208,665 238,471 268,285 298,099 327,906 357,713 387,519 417,326
7,528
3,805
1,943
1,012
547
314
198
MEASURE
S3 TO S2
tCYCLE
Figure 14. Timing of ADCVAX command, SCONV = 1
MEASURE
S1 TO S0
Table 13. Conversion Times for ADCVAX Command, SCONV = 1
ADC1
SERIAL
INTERFACE
tREFUP
LTC6810-1/LTC6810-2
OPERATION
Rev. A
33
34
ADCV +
PEC
t0
MEASURE
C1 TO C0
t1M
t2M t5M
t0
0
0
0
0
0
0
0
0
MODE
27kHz
14kHz
7kHz
3kHz
2kHz
For more information www.analog.com
1kHz
422Hz
26Hz
29,817
1,890
960
494
261
145
87
58
t1M
59,624
3,770
1,908
977
511
279
162
104
t2M
89,431
5,649
2,857
1,460
762
413
238
151
t3M
119,237
7,528
3,805
1,943
1,012
547
314
198
t4M
MEASURE
S3 TO S2
t6M
MEASURE
SC
t7M
MEASURE
C4 TO C3
tCYCLE
t8M
MEASURE
S4 TO S3
149,044
9,408
4,753
2,426
1,262
681
390
244
t5M
178,851
11,287
5,702
2,909
1,513
815
465
291
t6M
208,665
13,174
6,658
3,399
1,770
956
548
345
t7M
238,479
15,060
7,613
3,890
2,028
1,097
631
399
t8M
268,293
16,947
8,569
4,380
2,285
1,238
714
453
t9M
CONVERSION TIMES (in µs)
298,099
18,827
9,518
4,863
2,536
327,906
20,706
10,466
5,346
2,786
1,506
866
546
t11M
22,585
11,415
5,829
3,036
1,640
942
593
t12M
t12M
t13M
387,519
24,465
12,363
6,312
3,287
1,774
1,017
640
tC
436,192
27,756
15,654
9,603
6,578
5,065
2,796
2,418
436,192
27,756
15,654
9,603
6,578
5,065
2,796
2,418
tC,MCAL = 0 tC,MCAL = 1
68101 F15
CALIBRATE
t13M
MEASURE
S6 TO S5
357,713
MEASURE
C6 TO C5
t9M t11M
1,372
790
500
t10M
Figure 15. Timing of ADCVSC command, SCONV = 1
MEASURE
S1 TO S0
Table 14. Conversion Times for ADCVSC Command, SCONV = 1
ADC1
SERIAL
INTERFACE
tREFUP
LTC6810-1/LTC6810-2
OPERATION
Rev. A
LTC6810-1/LTC6810-2
OPERATION
Accuracy Check
Digital Filter Check
Measuring an independent voltage reference is the best
means to verify the accuracy of a data acquisition system.
The LTC6810 contains a 2nd reference for this purpose.
The ADAX command will initiate the measurement of the
2nd reference. The results are placed in Auxiliary Register
Group B. The range of the result depends on the accuracy
of the 2nd reference, including thermal hysteresis and
long term drift. Readings outside the range 2.99V to 3.01V
(final data sheet limits plus 2mV for Hys and 3mV for LTD)
indicate the system is out of its specified tolerance.
The delta-sigma ADC is composed of a 1-bit pulse density modulator followed by a digital filter. A pulse density
modulated bit stream has a higher percentage of 1s for
higher analog input voltages. The digital filter converts
this high frequency 1-bit stream into a single 16-bit word.
This is why a delta-sigma ADC is often referred to as an
over-sampling converter.
The self test commands verify the operation of the digital
filters and memory. Figure 16 illustrates the operation
of the ADC during self test. The output of the 1-bit pulse
density modulator is replaced by a 1-bit test signal. The
test signal passes through the digital filter and is converted to a 16-bit value. The 1-bit test signal undergoes
the same digital conversion as the regular 1-bit pulse
from the modulator, so the conversion time for any self
test command is exactly the same as the corresponding
regular ADC conversion command. The 16-bit ADC value
is stored in the same register groups as the regular ADC
conversion command. The total conversion time for the
self test commands is the same as the regular ADC conversion commands. The test signals are designed to place
alternating one-zero patterns in the registers.
MUX Decoder Check
The diagnostic command DIAGN ensures the proper operation of each multiplexer channel. The command cycles
through all channels and sets the MUXFAIL bit to 1 in
Status Register Group B if any channel decoder fails. The
MUXFAIL bit is set to 0 if the channel decoder passes the
test. The MUXFAIL bit is also set to 1 on power-up (POR)
or after a CLRSTAT command.
The DIAGN command takes about 300µs to complete if
the Core is in REFUP state and about 3.8ms to complete
if the Core is in STANDBY state. The polling methods
described in the section Polling Methods can be used to
determine the completion of the DIAGN command.
Table 15 provides a list of the self test commands. If the
digital filters and memory are working properly, then the
registers will contain the values shown in Table 15. For
more details see the Commands section.
PULSE DENSITY
MODULATED
BIT STREAM
MUX
ANALOG
INPUT
1-BIT
MODULATOR
DIGITAL
FILTER
1
SELF TEST
PATTERN
GENERATOR
16
RESULTS
REGISTER
TEST SIGNAL
68111 F10
Figure 16. Operation of LT6810 ADC Self Test
Rev. A
For more information www.analog.com
35
LTC6810-1/LTC6810-2
OPERATION
Table 15. Self Test Command Summary
OUTPUT PATTERN IN DIFFERENT ADC MODES
27kHz
7kHz, 3kHz, 2kHz,
1kHz, 422Hz, 26Hz
RESULTS REGISTER
GROUPS
0x9553
0x9555
0x6AAC
0x6AAA
C1V to C18V
(CVA, CVB, CVC, CVD)
COMMAND
SELF TEST OPTION
CVST
ST[1:0] = 01
0x9565
ST[1:0] = 10
0x6A9A
AXST
ST[1:0] = 01
0x9565
0x9553
0x9555
ST[1:0] = 10
0x6A9A
0x6AAC
0x6AAA
STATST
ST[1:0] = 01
0x9565
0x9553
0x9555
ST[1:0] = 10
0x6A9A
0x6AAC
0x6AAA
ADC Clear Commands
LTC6810 has 3 clear ADC commands: CLRCELL, CLRAUX
and CLRSTAT. These commands clear the registers that
store all ADC conversion results.
The CLRCELL command clears Cell Voltage Register
Group A, B, C and D. All bytes in these registers are set
to 0xFF by CLRCELL command.
The CLRAUX command clears Auxiliary Register Group
A and B. All bytes in these registers are set to 0xFF by
CLRAUX command.
The CLRSTAT command clears Status Register Group
A and B except the REVCODE and RSVD bits in Status
Register Group B. A read back of REVCODE will return the
revision code of the part. RSVD bits always read back 0s.
All OV and UV flags, MUXFAIL bit, and THSD bit in Status
Register Group B are set to 1 by CLRSTAT command.
The THSD bit is set to 0 after RDSTATB command. The
registers storing SC, ITMP, VA and VD are all set to 0xFF
by CLRSTAT command.
Open Wire Check (ADOW Command)
The ADOW command is used to check for any open wires
between the ADCs of the LTC6810 and the external cells.
This command performs ADC conversions on the C pin
inputs identically to the ADCV command, except two internal current sources sink or source current into the two C
pins while they are being measured. The pull-up (PUP) bit
of the ADOW command determines whether the current
sources are sinking or sourcing 100µA.
14kHz
S0, G1V to G4V, REF
(AUXA, AUXB)
SC, ITMP, VA, VD
(STATA, STATB)
The following simple algorithm can be used to check for
an open wire on any of the 7 C pins:
1. Run the 6-cell command ADOW with PUP = 1 at least
twice. Read the cell voltages for cells 1 through 6
once at the end and store them in array CELLPU(n).
2. Run the 6-cell command ADOW with PUP = 0 at least
twice. Read the cell voltages for cells 1 through 6
once at the end and store them in array CELLPD(n).
3. Take the difference between the pull-up and pull-down
measurements made in above steps for cells 2 to 6:
CELL∆(n) = CELLPU(n) – CELLPD(n).
4. For all values of n from 1 to 5: If CELLΔ(n+1) <
–400mV, then C(n) is open. If CELLPU(1) = 0.0000,
then C(0) is open. If CELLPD(6) = 0.0000, then C(6)
is open.
The above algorithm detects open wires using normal
mode conversions with as much as 10nF of capacitance
on the LTC6810 side of the open wire. However, if more
external capacitance is on the open C pin, then the length
of time that the open wire conversions are run in steps 1
and 2 must be increased to give the 100µA current sources
time to create a large enough difference for the algorithm
to detect an open connection. This can be accomplished
by running more than two ADOW commands in steps 1
and 2, or by using filtered mode conversions instead of
normal mode conversions. Use Table 16 to determine how
many conversions are necessary.
Rev. A
36
For more information www.analog.com
LTC6810-1/LTC6810-2
OPERATION
Revision Code and Reserved Bits
Table 16.
NUMBER OF ADOW COMMANDS REQUIRED IN
STEPS 1 AND 2
EXTERNAL C PIN
CAPACITANCE
NORMAL MODE
FILTERED MODE
≤10nF
2
2
100nF
10
2
1µF
100
2
C
1 + ROUNDUP(C/10nF)
2
The Status Register Group B contains a 4-bit revision
code. If software detection of device revision is necessary, then contact the factory for details. Otherwise the
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the Packet Error
Code (PEC) on data reads.
WATCHDOG AND DISCHARGE TIMER
Thermal Shutdown
To protect the LTC6810 from over-heating, there is a thermal shutdown circuit included inside the IC. If the temperature detected on the die goes above approximately
150°C, the thermal shutdown circuit trips and resets the
Configuration Register Group and PWM Register Group
to their default state. This turns off all discharge switches.
When a thermal shutdown event has occurred, the THSD
bit in Status Register Group B will go high. The CLRSTAT
command can also set the THSD bit high for diagnostic
purposes. This bit is cleared when a read operation is
performed on the Status Register Group B (RDSTATB
command).
When there is no valid command for more than 2 seconds,
the watchdog timer expires. This resets Configuration
Register bytes CFGR0, CFGR1-3 (if DTMEN=0). CFGR4,
CFGR5, and the PWM configuration bits in the PWM
Register Group are reset by the watchdog timer when the
Discharge Timer is disabled. The WDT pin is pulled high
by the external pull-up when the watchdog time elapses.
The watchdog timer is always enabled and it resets after
every valid command with matching command PEC.
The discharge timer is used to enable cell discharge using
pulse width modulation, for programmable time duration
after the watchdog time elapses. To enable the Discharge
Timer, tie the DTEN pin high to VREGA (Figure 17) and
write the DCTO value in the Configuration Register Group
LTC6810
DCTEN
EN
OSC 16Hz
VREGA
TIMEOUT
1
DCTO ≠ 0 SWTEN
S/W
TIMER
CLK
RST
2
(POR OR WRCFGA DONE OR TIMEOUT)
RST2
(RESETS DCTO, DCC)
WDTRST && ~DCTEN
RST01
(RESETS REFUP, GPIO, VUV, VOV)
OSC 16Hz
WDT0
WDTPD
WATCHDOG
TIMER
CLK
RST
WDTRST
(POR OR VALID COMMAND)
68101 F17
Figure 17. Watchdog and Discharge Timer
Rev. A
For more information www.analog.com
37
LTC6810-1/LTC6810-2
OPERATION
Table 17. DCTO Settings
DCTO
Time (min)
0
Disabled
1
0.5
2
1
3
2
4
3
5
4
to a non-zero value. Once the watchdog time elapses,
the discharge switches are now allowed to discharge at
a duty cycle specified by the PWM configuration bits in
the PWM Register Group for a time duration that is determined by the DCTO value. Table 17 shows the various
time settings and the corresponding DCTO value. Table
18 summarizes the status of the Configuration Register
Group after a watchdog timer or discharge timer event.
The status of the discharge timer can be determined by
reading the configuration register using the RDCFG command. The DCTO value indicates the time left before the
Discharge Timer expires as shown in Table 19.
Unlike the watchdog timer, the discharge timer does not
reset when there is a valid command. The discharge timer
is only reset after a valid WRCFG (Write Configuration
Register Group) command. There is a possibility that
the Discharge Timer will expire in the middle of some
commands.
If Discharge Timer expires in the middle of WRCFG
command, the Configuration Register Group and PWM
Register Group reset as per Table 18. However, at the end
of the valid WRCFG command, the new data is copied to
the configuration register. The new data is not lost when
the Discharge Timer fired.
If Discharge Timer fires in the middle of RDCFG command, the Configuration Register Group resets as per
Table 18. As a result, the read back data from bytes CRFG4
and CRFG5 could be corrupted. If Discharge Timer fires in
the middle of WRPWM or RDPWM command, the PWM
Register Group resets as per Table 18. As a result, the
data could be corrupted.
6
5
7
10
8
15
9
20
A
30
B
40
C
60
D
75
E
90
F
120
Table 18
WATCHDOG TIMER
DISCHARGE TIMER
DTEN = 0,
DCTO = XXXX
Resets CFGR0-5 and PWM Disabled
bits when it fires.
DTEN = 1,
DCTO = 0000
Resets CFGR0-5 and PWM Disabled
bits when it fires.
DTEN = 1,
DCTO != 0000
Resets CFGR0, CFGR1-3 (if Resets CFGR1-3 (if DTMEN
DTMEN=0) when it fires.
=1), and PWM bits when
it fires.
Table 19.
DCTO (READ VALUE)
TIME LEFT (MIN)
0
Disabled (or) Discharge Timer Has Timed Out
1
0 < Timer ≤ 0.5
2
0.5 < Timer ≤ 1
3
1 < Timer ≤ 2
4
2 < Timer ≤ 3
5
3 < Timer ≤ 4
6
4 < Timer ≤ 5
7
5 < Timer ≤ 10
8
10 < Timer ≤ 15
9
15 < Timer ≤ 20
A
20 < Timer ≤ 30
B
30 < Timer ≤ 40
C
40 < Timer ≤ 60
D
60 < Timer ≤ 75
E
75 < Timer ≤ 90
F
90 < Timer ≤ 120
Rev. A
38
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LTC6810-1/LTC6810-2
OPERATION
RESET BEHAVIORS
Power cycling, thermal shutdown, watchdog timeout
and discharge timeout can cause various registers and
circuitry to reset when they occur. The following summarizes the behaviors when these events occur:
RESET EVENT
Power Cycle
(V+ and VREG both
power cycled)
Thermal Shutdown
Watchdog Timeout
(while Discharge Timer
is Running)
Watchdog Timeout
(no Discharge Timer
Running)
DEVICE BEHAVIOR
Transition to STANDBY state.
All registers and state machines are reset to default values.
Cell discharge is disabled.
Cell discharge is disabled.
All of Configuration Register Group is reset.
The COMM Register Group is reset.
Transition to EXTENDED BALANCING state.
CFGR0 of Configuration Register is reset.
If DTMEN (in Configuration Register Group) = 0
then CFGR1, CFGR2 and CFGR3 of Configuration Register Group are reset.
The COMM Register Group is reset.
Transition to SLEEP state.
Cell discharge is disabled.
All state machines are reset.
All of Configuration Register Group is reset.
The PWM Register Group is reset.
The COMM Register Group is reset.
Transition to SLEEP state.
Same behavior as the previous case above.
Discharge Timeout
(while Watchdog
Timeout has Elapsed)
Discharge Timeout
Cell discharge is disabled.
(while Watchdog
The PWM Register Group is reset.
Timeout is not Elapsed) If DTMEN (in Configuration Register) = 1
then CFGAR1, CFGAR2 and CFGAR3 of Configuration Register Group are reset.
CFGAR4 and CFGAR5 of Configuration Register Group are reset.
Rev. A
For more information www.analog.com
39
LTC6810-1/LTC6810-2
OPERATION
S PIN PULSE WIDTH MODULATION FOR CELL
BALANCING
While the watchdog timer is not expired, the DCC bits
in the Configuration Register Group control the S pins
directly. After the watchdog timer expires, PWM operation
begins and continues for the remainder of the selected
software discharge time or until a wake-up event occurs
(and the watchdog timer is reset).
Once PWM operation begins, the configurations in the
PWM Register Group control the S pins to achieve the
desired duty cycle as shown in Table 20. Each PWM signal
operates on a 30 second period. For each cell, the dutycycle can be programmed from 0% to 50% duty cycle in
increments of 1/30 = 3.33% (1 second). S pins for adjacent cells are never activated at the same time, hence the
maximum 50% duty cycle. There is a non-overlap of at
least 1ms between activation of any two adjacent S pins.
Table 20. PWM Configurations
DTEN
SETTING
PWMC
SETTING
ON TIME
[SECONDS]
OFF TIME
[SECONDS]
DUTY CYCLE
[%]
1’b0
4’bXXXX
0
Continuously Off
0
1’b1
4’b1111
15
15
50
1’b1
4’b1110
14
16
46.7
1’b1
4’b1101
13
17
43.3
1’b1
4’b1100
12
18
40
1’b1
4’b1011
11
19
36.7
1’b1
4’b1010
10
20
33.3
1’b1
4’b1001
9
21
30
1’b1
4’b1000
8
22
26.7
1’b1
4’b0111
7
23
23.3
1’b1
4’b0110
6
24
20
1’b1
4’b0101
5
25
16.7
1’b1
4’b0100
4
26
13.3
1’b1
4’b0011
3
27
10
1’b1
4’b0010
2
28
6.7
1’b1
4’b0001
1
29
3.3
1’b1
4’b0000
0
Continuously Off
0
The PWM turn on/off times for the S pins are sequenced
at different intervals so that no two pins switch on or off
at the same time. The switching interval between channels is 62.5ms, and 375ms are required for all 6 pins to
switch (6 • 62.5ms).
The default value of the PWMC settings in the PWM
Register Group is all 0s. Upon entry to sleep mode, the
PWMC settings will be reset to their default value.
DISCHARGE TIMER MONITOR
The LTC6810 has the ability to periodically monitor cell
voltages while the discharge timer is active. The host
should write the DTMEN bit in the Configuration Register
Group to 1 to enable this feature.
When the discharge timer monitor is enabled and the
watchdog timer has expired, the LTC6810 will perform
a conversion of all cell voltages in 7kHz (Normal) Mode
every 30 seconds. The overvoltage and undervoltage
comparisons will be performed and flags will be set if
cells have crossed a threshold. For any undervoltage cells
the discharge timer monitor will automatically clear the
associated PWMC bits in the PWM Register Group so
that the cell will no longer be discharged. Clearing the
Discharge Control bit will also disable PWM discharge.
With this feature, the host can write the undervoltage
threshold to the desired discharge level and use the discharge timer monitor to discharge all, or selected, cells
down to that level.
During discharge timer monitoring, digital redundancy
checking will be performed on the cell voltage measurements. If a digital redundancy failure occurs, all PWMC
bits will be cleared and discharge will be terminated.
I2C/SPI MASTER ON LTC6810 USING GPIOS
The I/O ports GPIO2, GPIO3 and GPIO4 on LTC6810 can
be used as an I2C or SPI master port to communicate
to an I2C or SPI slave. In case of I2C master, GPIO3 and
GPIO4 form the SDA and SCL ports of the I2C interface
respectively. In case of SPI master, GPIO2, GPIO3 and
GPIO4 become the CSB, SDIO and SCK ports of the SPI
interface respectively. The SPI master on LTC6810 supports SPI mode 3 (CHPA = 1, CPOL = 1).
Rev. A
40
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LTC6810-1/LTC6810-2
OPERATION
The GPIOs are open drain outputs, so an external pull
up is required on these ports to operate as an I2C or SPI
master. It is also important to write the GPIO bits to 1 in
the CFG register group so these ports are not pulled low
internally by the device.
COMM Register
LTC6810 has a 6 byte COMM register as shown in Table
21. This register stores all data and control bits required
for I2C or SPI communication to a slave. The COMM register contains 3 bytes of data Dn[7:0] to be transmitted
to or received from the slave device. ICOMn[3:0] specify
control actions before transmitting/receiving the data
byte. FCOMn[3:0] specify control actions after transmitting/receiving the data byte.
If the bit ICOMn[3] in the COMM register is set to 1 the
part becomes an SPI master and if the bit is set to 0 the
part becomes a I2C master.
Table 22 describes the valid write codes for ICOMn[3:0]
and FCOMn[3:0] and their behavior when using the part
as an I2C master.
Table 23 describes the valid codes for ICOMn[3:0] and
FCOMn[3:0] and their behavior when using the part as
an SPI master.
Note that only the codes listed in Table 22 and Table 23
are valid for ICOMn[3:0] and FCOMn[3:0]. Writing any
other code that is not listed above to ICOMn[3:0] and
FCOMn[3:0] may result in unexpected behavior on the
I2C and SPI ports.
Table 21. COMM Register Memory Map
REGISTER
COMM0
RD/WR
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
ICOM0[3]
ICOM0[2]
ICOM0[1]
ICOM0[0]
BIT 3
D0[7]
BIT 2
D0[6]
BIT 1
D0[5]
BIT 0
D0[4]
COMM1
RD/WR
D0[3]
D0[2]
D0[1]
D0[0]
FCOM0[3]
FCOM0[2]
FCOM0[1]
FCOM0[0]
COMM2
RD/WR
ICOM1[3]
ICOM1[2]
ICOM1[1]
ICOM1[0]
D1[7]
D1[6]
D1[5]
D1[4]
COMM3
RD/WR
D1[3]
D1[2]
D1[1]
D1[0]
FCOM1[3]
FCOM1[2]
FCOM1[1]
FCOM1[0]
COMM4
RD/WR
ICOM2[3]
ICOM2[2]
ICOM2[1]
ICOM2[0]
D2[7]
D2[6]
D2[5]
D2[4]
COMM5
RD/WR
D2[3]
D2[2]
D2[1]
D2[0]
FCOM2[3]
FCOM2[2]
FCOM2[1]
FCOM2[0]
Table 22. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master
CONTROL BITS
CODE
ACTION
DESCRIPTION
ICOMn[3:0]
0110
START
Generate a START signal on I2C port followed by data transmission.
0001
STOP
Generate a STOP signal on I2C port.
0000
BLANK
Proceed directly to data transmission on I2C port.
0111
No Transmit
Release SDA and SCL and ignore the rest of the data.
0000
Master ACK
Master generates an ACK signal on ninth clock cycle.
1000
Master NACK
Master generates a NACK signal on ninth clock cycle.
1001
Master NACK + STOP
Master generates a NACK signal followed by STOP signal.
FCOMn[3:0]
Table 23. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master
CONTROL BITS
CODE
ACTION
DESCRIPTION
ICOMn[3:0]
1000
CSBM low
Generates a CSBM low signal on SPI port (GPIO3).
1010
CSBM falling edge
Drives CSBM (GPIO3) high, then low.
1001
CSBM high
Generates a CSBM high signal on SPI port (GPIO3).
1111
No Transmit
Releases the SPI port and ignores the rest of the data.
X000
CSBM low
Holds CSBM low at the end of byte transmission.
1001
CSBM high
Transitions CSBM high at the end of byte transmission.
FCOMn[3:0]
Rev. A
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41
LTC6810-1/LTC6810-2
OPERATION
COMM Commands
Table 24. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master
Three commands help accomplish I2C or SPI communication to the slave device: WRCOMM, STCOMM, RDCOMM
CONTROL BITS
CODE
DESCRIPTION
ICOMn[3:0]
0110
Master generated a START signal.
0001
Master generated a STOP signal.
0000
Blank, SDA was held low between bytes.
WRCOMM Command: This command is used to write
data to the COMM register. This command writes 6 bytes
of data to the COMM register. The PEC needs to be written
at the end of the data. If the PEC does not match, all data
in the COMM register is cleared to 1s when CSB goes
high. See the Bus Protocols section for more details on a
write command format.
STCOMM Command: This command initiates I2C/SPI
communication on the GPIO ports. The COMM register
contains 3 bytes of data to be transmitted to the slave.
During this command, the data bytes stored in the COMM
register are transmitted to the slave I2C or SPI device and
the data received from the I2C or SPI device is stored in
the COMM register. This command uses GPIO3 (SDA)
and GPIO4 (SCL) for I2C communication or GPIO2
(CSBM), GPIO3 (SDIOM) and GPIO4 (SCKM) for SPI
communication.
The STCOMM command is to be followed by 24 clock
cycles for each byte of data to be transmitted to the slave
device while holding CSB low. For example, to transmit 3
bytes of data to the slave, send STCOMM command and
its PEC followed by 72 clock cycles. Pull CSB high at the
end of the 72 clock cycles of STCOMM command.
During I2C or SPI communication, the data received from
the slave device is updated in the COMM register.
RDCOMM Command: The data received from the slave
device can be read back from the COMM register using the
RDCOMM command. The command reads back 6 bytes of
data followed by the PEC. See the Bus Protocols section
for more details on a read command format.
Table 24 describes the possible read back codes for
ICOMn[3:0] and FCOMn[3:0] when using the part as an
I2C master. Dn[3:0] contains the data byte transmitted by
the I2C slave.
In case of the SPI master, the read back codes for
ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111
respectively. Dn[3:0] contains the data byte transmitted
by the SPI slave.
FCOMn[3:0]
0111
Blank, SDA was held high between bytes.
0000
Master generated an ACK signal.
0111
Slave generated an ACK signal.
1111
Slave generated a NACK signal.
0001
Slave generated an ACK signal, master
generated a STOP signal.
1001
Slave generated a NACK signal, master
generated a STOP signal.
Figure 18 illustrates the operation of LTC6810 as an I2C
or SPI master using the GPIOs.
LTC6810-1/LTC6810-2
I2C/SPI
SLAVE
STCOMM
RDCOMM
GPIO
PORT
COMM
REGISTER
PORT A
WRCOMM
68101 F18
Figure 18. LTC6810 I2C/SPI Master using GPIOs
Any number of bytes can be transmitted to the slave in
groups of 3 bytes using these commands. The GPIO
ports will not get reset between different STCOMM commands. However, if the wait time between the commands
is greater than 2s, the watchdog will time out and reset
the ports to their default values.
To transmit several bytes of data using an I2C master,
a START signal is only required at the beginning of the
entire data stream. A STOP signal is only required at the
end of the data stream. All intermediate data groups can
use a BLANK code before the data byte and an ACK/NACK
signal as appropriate after the data byte. SDA and SCL
will not get reset between different STCOMM commands.
To transmit several bytes of data using SPI master, a
CSBM low signal is sent at the beginning of the 1st data
byte. CSBM can be held low or taken high for intermediate
data groups using the appropriate code on FCOMn[3:0].
Rev. A
42
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LTC6810-1/LTC6810-2
OPERATION
A CSB high signal is sent at the end of the last byte of
data. CSBM, SDIOM and SCKM will not get reset between
different STCOMM commands.
tCLK
t4
Figure 19 shows the 24 clock cycles following STCOMM
command for an I2C master in different cases. Note that
if ICOMn[3:0] specified a STOP condition, after the STOP
t3
(SCK)
START
NACK + STOP
BLANK
NACK
START
ACK
SCL (GPIO4)
SDA (GPIO3)
SCL (GPIO4)
SDA (GPIO3)
SCL (GPIO4)
SDA (GPIO3)
STOP
SCL (GPIO4)
SDA (GPIO3)
NO TRANSMIT
SCL (GPIO4)
SDA (GPIO3)
68111 F13
Figure 19. STCOMM Timing Diagram for an I2C Master
tCLK
t4
t3
(SCK)
CSBM HIGH ≥ LOW
CSBM LOW
CSBM (GPIO2)
SCKM (GPIO4)
SDIOM (GPIO3)
CSBM LOW
CSBM LOW ≥ HIGH
CSBM (GPIO2)
SCKM (GPIO4)
SDIOM (GPIO3)
CSBM HIGH/NO TRANSMIT
CSBM (GPIO2)
SCKM (GPIO4)
SDIOM (GPIO3)
68111 F14
Figure 20. STCOMM Timing Diagram for a SPI Master
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Rev. A
43
LTC6810-1/LTC6810-2
OPERATION
signal is sent, the SDA and SCL lines are held high and
all data in the rest of the word is ignored. If ICOMn[3:0]
is a NO TRANSMIT, both SDA and SCL lines are released,
and rest of the data in the word is ignored. This is used
when a particular device in the stack does not have to
communicate to a slave.
Figure 20 shows the 24 clock cycles following STCOMM
command for a SPI master. Similar to the I2C master, if
ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT
condition, the CSBM, SCKM and SDIOM lines of the SPI
master are released and the rest of the data in the word
is ignored.
Timing Specifications of I2C and SPI master
The timing of the LTC6810 I2C or SPI master will be
controlled by the timing of the communication at the
LTC6810’s primary SPI interface. Table 25 shows the
I2C master timing relationship to the primary SPI clock.
Table 26 shows the SPI master timing specifications.
Table 25. I2C MASTER TIMING
I2C MASTER
PARAMETER
TIMING RELATIONSHIP
TO PRIMARY SPI
INTERFACE
TIMING
SPECIFICATIONS AT
tCLK = 1μs
SCL Clock Frequency
1/(2 • tCLK)
Max 500kHz
tHD;STA
t3
Min 200ns
tLOW
tCLK
Min 1μs
tHIGH
tCLK
Min 1μs
tSU;STA
tCLK + t4*
Min 1.03μs
tHD;DAT
t4*
Min 30ns
tSU;DAT
t3
Min 200ns
tSU;STO
tCLK + t4*
Min 1.03μs
tBUF
3 • tCLK
Min 3μs
*Note: When using isoSPI, t4 is generated internally and is a minimum of
30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high
times of the SCK input, each with a specified minimum of 200ns.
Table 26. SPI Master Timing
SPI MASTER PARAMETER
TIMING RELATIONSHIP
TIMING
TO PRIMARY SPI
SPECIFICATIONS
INTERFACE
AT tCLK = 1μs
SDIOM Valid to SCKM Rising
Setup
t3
Min 200ns
SDIO Valid from SCKM Rising
Hold
tCLK + t4*
Min 1.03μs
SCKM Low
tCLK
Min 1μs
SCKM High
tCLK
Min 1μs
SCKM Period (SCKM_Low +
SCKM_High)
2 • tCLK
Min 2μs
CSBM Pulse Width
3 • tCLK
Min 3μs
SCKM Rising to CSBM Rising
5 • tCLK + t4*
Min 5.03μs
CSBM Falling to SCKM Falling
t3
Min 200ns
CSBM Falling to SCKM Rising
tCLK + t3
Min 1.2μs
SCKM Falling to SDIOM Valid Master requires < tCLK
*Note: When using isoSPI, t4 is generated internally and is a minimum of
30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high
times of the SCK input, each with a specified minimum of 200ns.
S PIN MUTING
The S pins may be disabled by sending the MUTE command and re-enabled by sending the UNMUTE command.
The MUTE and UNMUTE commands do not require any
subsequent data and thus the commands will propagate
quickly through a stack of LTC6810-1 devices. Likewise,
they can be sent as broadcast commands to a network of
LTC6810-2 devices. This allows the host to quickly disable and re-enable discharging without disturbing register
contents. This can be useful, for instance, to allow specific
settling time before taking cell measurements. The mute
status is reported in the read-only MUTE bit in Status
Register Group B.
Rev. A
44
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LTC6810-1/LTC6810-2
OPERATION
SERIAL ID AND AUTHENTICATION
Each LTC6810 is programmed at the factory with a unique
48-bit serial identification code (SID) which is stored in
the Serial ID Register Group. The host can read the unique
SID code for each device using the RDSID command.
The LTC6810 also contains a feature that can be used to
authenticate devices. Contact the factory for details about
the authentication feature.
SERIAL INTERFACE OVERVIEW
There are two types of serial ports on the LTC6810: a standard 4-wire serial peripheral interface (SPI) and a 2-wire
isolated interface (isoSPI). The state of the ISOMD pin
determines whether pins 36, 37, 40 and 41 are a 2-wire
or 4-wire serial port.
V+
C12
S12
LTC6810-1
There are two versions of the IC: the LTC6810-1 and the
LTC6810-2. The LTC6810-1 is used in a daisy chain configuration and the LTC6810-2 is used in an addressable
bus configuration. The LTC6810-1 provides a second isoSPI interface using pins 34, 35, 38, and 39. LTC6810-2
uses pins 34, 35, 38 and 39 to set the address of the
device, by tying these pins to V– or VREG.
4-WIRE SERIAL PERIPHERAL INTERFACE (SPI)
PHYSICAL LAYER
External Connections
Connecting ISOMD to V– configures serial port A for
4-wire SPI. The SDO pin is an open drain output which
requires a pull-up resistor tied to the appropriate supply
voltage (Figure 21).
V+
IPB
IMB
DAISY-CHAIN SUPPORT
ICMP
5k
C11
IBIAS
S11
SDO (NC)
MISO
C10
SDI (NC)
S10
SCK (IPA)
C9
CSB (IMA)
CS
S9
C12
LTC6810-2
A3
A2
A1
S12
ADDRESS PINS
5k
C11
A0
S11
SDO (IBIAS)
MISO
MOSI
C10
SDI (ICMP)
MOSI
CLK
S10
SCK (IPA)
CLK
C9
CSB (IMA)
CS
ISOMD
S9
ISOMD
C8
WDT
C8
WDT
S8
DRIVE
S8
DRIVE
C7
VREG
C7
VREG
S7
DTEN
S7
DTEN
C6
VREF1
C6
VREF1
S6
VREF2
S6
VREF2
C5
VDD
MPU
VDD
MPU
C5
S5
GPIO4
S5
GPIO4
C4
V–
C4
V–
S4
V–
S4
V–
C3
GPIO3
C3
GPIO3
S3
GPIO2
S3
GPIO2
C2
GPIO1
C2
GPIO1
S2
C0
S2
C0
C1
S1
C1
S1
68101 F21
Figure 21. 4-Wire SPI Configuration
Rev. A
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45
LTC6810-1/LTC6810-2
OPERATION
Timing
2-Wire Isolated Interface (isoSPI) Physical Layer
The 4-wire serial port is configured to operate in a SPI
system using CPHA = 1 and CPOL = 1. Consequently, data
on SDI must be stable during the rising edge of SCK. The
timing is depicted in Figure 22. The maximum data rate
is 1Mbps.
The 2-wire interface provides a means to interconnect
LTC6810 devices using simple twisted pair cabling. The
interface is designed for low packet error rates when the
cabling is subjected to high RF fields. Isolation is achieved
through an external transformer.
t1
t4
t2
t3
t6
t7
SCK
SDI
D3
D2
D1
D0
D7…D4
D3
t5
CSB
t8
SDO
D4
D3
D2
D1
D0
D7…D4
PREVIOUS COMMAND
CURRENT COMMAND
D3
68111 F16
Figure 22. Timing Diagram of 4-Wire Serial Peripheral Interface
LTC6810
WAKEUP
CIRCUIT
Tx • 20 • IB
Tx = +1
LOGIC
AND
MEMORY
Tx = 0
SDO
SDI
SCK
CSB
IP
IM
Tx = –1
PULSE
ENCODER/
DECODER
Rx = +1
RM
•
•
+
Rx = 0
Rx = –1
IB
–
1V • RB2
COMPARATOR THRESHOLD =
RB1 + RB2
+
–
IBIAS
2V
ICMP
RB1
0.5X
RB2
Figure 23. isoSPI Interface
68101 F17
Rev. A
46
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LTC6810-1/LTC6810-2
OPERATION
Standard SPI signals are encoded into differential pulses.
The strength of the transmission pulse and the threshold
level of the receiver are set by 2 external resistors. The
values of the resistors allow the user to trade off power
dissipation for noise immunity.
Figure 23 illustrates how the isoSPI circuit operates. A 2V
reference drives the IBIAS pin. External resistors RB1 and
RB2 create the reference current IB. This current sets the
drive strength of the transmitter. RB1 and RB2 also form
a voltage divider to supply a fraction of the 2V reference
for the ICMP pin, which sets the threshold voltage of the
receiver circuit.
External Connections
The LTC6810-1 has 2 serial ports which are called Port
B and Port A. Port B is always configured as a 2-wire
interface. Port A is either a 2-wire or 4-wire interface,
depending on the connection of the ISOMD pin.
When Port A is configured as a 4-wire interface, Port A
is always the slave port and Port B is the master port.
Communication is always initiated on Port A of the first
device in the daisy chain configuration. The final device
in the daisy chain does not use Port B, and it should
be terminated into RM. Figure 24 shows the simplest
port connections possible when the microprocessor
and the LTC6810s are located on the same PCB. In this
figure capacitors are used to couple signals between the
LTC6810s.
When Port A is configured as a 2-wire interface, communication can be initiated on either Port A or Port B. If
communication is initiated on Port A, LTC6810 configures
Port A as slave and Port B as master. Likewise, if communication is initiated on Port B, LTC6810 configures
Port B as slave and Port A as master. See the Reversible
isoSPI for LTC6810-1 section for a detailed description
of reversible isoSPI.
IPB
IMB
IPA
IMA
V–
LTC6810-1
–
DAISY-CHAIN V
MODE
ICMP
IBIAS
ISOMD
NC
NC
DEV D
VREG
GNDD
GNDD
GNDD
VREG
IPB
IMB
IPA
IMA
V–
LTC6810-1
–
DAISY-CHAIN V
MODE
ICMP
IBIAS
ISOMD
NC
NC
DEV C
VREG
GNDC
GNDC
GNDC
GNDC
VREG
IPB
IMB
IPA
IMA
V–
LTC6810-1
–
DAISY-CHAIN V
MODE
ICMP
IBIAS
ISOMD
NC
NC
DEV B
VREG
GNDB
GNDB
GNDB
GNDB
VREG
IPB
IMB
GNDA
LTC6810-1
DAISY-CHAIN
SCK
MODE
CSB
V–
V–
ICMP
IBIAS
ISOMD
DEV A
SDO
SDI
VDDA
CLK
CS
VDD
5k
MPU
GNDA
GNDA
MISO
MOSI
68101 F24
Figure 24. Capacitive-Coupled Daisy-Chain Configuration
Using LT6810-1
Rev. A
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47
LTC6810-1/LTC6810-2
OPERATION
Figure 25 is an example of a robust interconnection of
multiple identical PCBs, each containing 1 LTC6810-1.
The microprocessor is located on a separate PCB. To
achieve 2-wire isolation between the microprocessor PCB
and the 1st LTC6810 PCB, use the LTC6820 support IC.
The LTC6820 is functionally equivalent to the diagram in
Figure 16. In this example, communication is initiated on
Port A. So the LTC6810 configures Port A as slave and
Port B as master.
Reversible isoSPI for LTC6810-1
Figure 26 illustrates a daisy-chained configuration of
LTC6810-1s using reversible isoSPI. LTC6820s are connected on either side of the daisy-chain. Both LTC6820s
are configured as Master and share the same SPI interface
to connect to the MPU. The MPU uses two CS signals to
talk to one of the two LTC6820s.
IPB
IMB
LTC6810-1
DAISY-CHAIN IPA
MODE
IMA
V–
V–
ICMP
IBIAS
ISOMD
DEV C
VREG
GNDD
GNDD
VREG
IPB
IMB
LTC6810-1 IPA
DAISY-CHAIN IMA–
V
MODE
V–
ICMP
IBIAS
ISOMD
DEV B
VREG
GNDC
GNDC
VREG
VDDA
IPB
IMB
LTC6810-1 IPA
DAISY-CHAIN IMA–
V
MODE
V–
ICMP
IBIAS
ISOMD
DEV A
VREG
GNDA
GNDB
MSTR
MOSI
IBIAS
MISO
ICMP
SCK
POL LTC6820 CSB
PHA
VCC0
EN
IP
SLOW
IM
VCC
MOSI
MISO
CLK MPU
SC
VDD
68101 F25
GNDB
VREG
Figure 25. Transformer-Coupled Daisy-Chain Configuration Using LT6810-1
Rev. A
48
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LTC6810-1/LTC6810-2
OPERATION
For example, in Figure 26, if the bottom LTC6820 is
addressed, then LTC6810 DEV A becomes the first device
in the stack followed by DEV B and DEV C. Port A of
each LTC6810 is configured as the slave and Port B is
configured as the Master. On the other hand, if the top
LTC6820 is addressed, then LTC6810 DEV C becomes
the first device in the stack followed by DEV B and DEV
A. Port B of each LTC6810 is configured as slave and Port
A is configured as Master.
The reversible isoSPI provides a redundant communication path in the event of a single point failure in the 2-wire
interface.
IPB
IMB
LTC6810-1
DAISY-CHAIN IPA
MODE
IMA
V–
V–
ICMP
IBIAS
ISOMD
DEV C
VREG
GNDD
GNDD
VREG
IPB
IMB
LTC6810-1 IPA
DAISY-CHAIN IMA–
V
MODE
V–
ICMP
IBIAS
ISOMD
DEV B
VREG
GNDC
GNDA
GNDC
MSTR
MOSI
IBIAS
MISO
ICMP
SCK
POL LTC6820 CSB
PHA
VCC0
EN
IP
SLOW
IM
VCC
CS2
MPU
VREG
MOSI
MISO
CLK
IPB
IMB
LTC6810-1 IPA
DAISY-CHAIN IMA–
V
MODE
V–
ICMP
IBIAS
ISOMD
DEV A
VREG
GNDA
GNDB
MSTR
MOSI
IBIAS
MISO
ICMP
SCK
POL LTC6820 CSB
PHA
VCC0
EN
IP
SLOW
IM
VCC
CS1
VDD
VDDA
68101 F26
GNDB
VREG
Figure 26. Reversible isoSPI Daisy Chain using the LTC6810-1
Rev. A
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49
LTC6810-1/LTC6810-2
OPERATION
The LTC6810-2 has a single serial port (Port A) which can
be 2-wire or 4-wire, depending on the state of the ISOMD
pin. When configured for 2-wire communications, several
A3
A2
IPA
IMA
LTC6810-2
V–
PARALLEL
V–
MODE
A1
A0
ISOMD
ICMP
IBIAS
DEV C
VREG
devices can be connected in a multi-drop configuration,
as shown in Figure 27. The LTC6820 IC is used to interface the MPU (master) to the LTC6810-2s (slaves).
GNDD
GNDD
VREG
A3
A2
IPA
IMA
V–
V–
LTC6810-2
A1
PARALLEL
A0
MODE
ISOMD
ICMP
IBIAS
DEV B
VREG
GNDC
GNDC
VREG
A3
A2
IPA
IMA
V–
V–
LTC6810-2
A1
PARALLEL
A0
MODE
ISOMD
ICMP
IBIAS
DEV A
VREG
GNDB
VDDA
GNDA
GNDB
MOSI
MSTR
MISO
IBIAS
SCK
ICMP
LTC6820 CSB
POL
VCC0
PHA
EN
IP
SLOW
IM
VCC
MOSI
MISO
CLK MPU
SC
VDD
VREG
68101 F27
Figure 27. Transformer-Coupled Multi-Drop Configuration Using LT6810-2
Rev. A
50
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LTC6810-1/LTC6810-2
OPERATION
Selecting Bias Resistors
isoSPI Pulse Detail
The isoSPI transmitter drive current and comparator voltage threshold are set by a resistor divider (RBIAS = RB1 +
RB2) between the IBIAS and V– pins. The divided voltage
is connected to the ICMP pin, which sets the comparator
threshold to ½ of this voltage (VICMP). When either isoSPI
interface is enabled (not IDLE) IBIAS is held at 2V, causing
a current IB to flow out of the IBIAS pin. The IP and IM
pin drive currents are 20 • IB.
Two LTC6810 devices can communicate by transmitting
and receiving differential pulses back and forth through an
isolation barrier. The transmitter can output three voltage
levels: +VA, 0V, and –VA. A positive output results from
IP sourcing current and IM sinking current across load
resistor RM. A negative voltage is developed by IP sinking and IM sourcing. When both outputs are off, the load
resistance forces the differential output to 0V.
As an example, if divider resistor RB1 is 1.78kΩ and resistor RB2 is 200Ω (so that RBIAS = 2kΩ), then:
To eliminate the DC signal component and enhance reliability, isoSPI pulses are defined as symmetric pulse pairs.
A +1 pulse will be transmitted as a positive pulse followed
by a negative pulse. A –1 pulse will be transmitted as a
negative pulse followed by a positive pulse. The duration
of each pulse is defined as t½PW, since each is half of the
required symmetric pair (the total isoSPI pulse duration
is 2 • t½PW).
IB =
2V
RB1 + RB2
= 1mA
IDRV = IIP = IIM = 20 • IB = 20mA
VICMP = 2V •
RB2
RB1 + RB2
= IB • RB2 = 422mV
VTCMP = 0.5 • VICMP = 211mV
In this example, the pulse drive current IDRV will be 20mA,
and the receiver comparators will detect pulses with IP–IM
amplitudes greater than ±211mV.
If the isolation barrier uses 1:1 transformers connected
by a twisted pair and terminated with 100Ω resistors on
each end, then the transmitted differential signal amplitude
(±) will be:
R
VA = IDRV • M = 1V
2
(This result ignores transformer and cable losses, which
may reduce the amplitude.)
The adjustable signal amplitude allows the system to trade
power consumption for communication robustness, and
the adjustable comparator threshold allows the system to
account for signal losses.
Table 27. isoSPI Pulse Types
PULSE TYPE
FIRST LEVEL
(t½PW)
SECOND LEVEL
(t½PW)
ENDING LEVEL
Long +1
+VA (150ns)
–VA (150ns)
0V
Long –1
–VA (150ns)
+VA (150ns)
0V
Short +1
+VA (50ns)
–VA (50ns)
0V
Short –1
–VA (50ns)
+VA (50ns)
0V
A host microcontroller does not have to generate isoSPI
pulses to use this 2-wire interface. The first LTC6810 in
the system can communicate to the microcontroller using
the 4-wire SPI interface on its Port A, then daisy-chain to
other LTC6810s using the 2-wire isoSPI interface on its
Port B. Alternatively, the LTC6820 can be used to translate
the SPI signals into isoSPI pulses.
Operation with Port A Configured for SPI
When the LTC6810-1 is operation with Port A as a SPI
(ISOMD = V–), the SPI detects one of four communication
events: CSB falling, CSB rising, SCK rising with SDI = 0,
and SCK rising with SDI = 1. Each event is converted
into one of four pulse types for transmission to another
daisy-chained LTC6810. Long pulses are used to transmit
CSB changes and short pulses transmit data as explained
in Table 28.
Rev. A
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51
LTC6810-1/LTC6810-2
OPERATION
Table 28. Port B (Master) isoSPI Port Function
Table 29. Port A (Slave) isoSPI Port Function
COMMUNICATION EVENT
(Port A SPI)
TRANSMITTED PULSE
(Port B isoSPI)
CS Rising
Long +1
RECEIVED PULSE INTERNAL SPI PORT
(Port A isoSPI)
ACTION
Long +1
Drive CS High
None
Short –1 Pulse if Reading a
0 bit
CS Falling
Long –1
Long –1
Drive CS Low
SCK Rising Edge, SDI = 1
Short +1
Short +1
SCK Rising Edge, SDI = 0
Short –1
1. Set SDI = 1
2. Pulse SCK
Short –1
1. Set SDI = 0
2. Pulse SCK
Operation with Port A Configured for isoSPI
On the other side of the isolation barrier (i.e. at the other
end of the cable), the 2nd LTC6810 will have ISOMD = VREG.
Its Port A operates as a slave isoSPI interface. It receives
each transmitted pulse and reconstructs the SPI signals
internally, as shown in Table 29. In addition, during a READ
command this port may transmit return data pulses.
RETURN PULSE
(No Return Pulse if Not in READ
Mode or if Reading a 1 bit)
The slave isoSPI port (slave) never transmits long (CSB)
pulses. Furthermore, a slave isoSPI port will only transmit short –1 pulses, never a +1 pulse. The master port
recognizes a null response as a logic 1. This allows for
multiple slave devices on a single cable without risk of
collisions (Multi-drop).
+1 PULSE
+VA
+VTCMP
t1/2PW
VIP – VIM
–VTCMP
tINV
t1/2PW
–VA
–1 PULSE
+VA
+VTCMP
tINV
t1/2PW
VIP – VIM
–VTCMP
t1/2PW
–VA
68101 F28
Figure 28. isoSPI Pulse Detail
Rev. A
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LTC6810-1/LTC6810-2
OPERATION
Timing Diagrams
Bits WN–W0 refers to the 16 bit command code and the
16 bit PEC of a READ command. At the end of bit W0 the
3 parts decode the READ command and begin shifting out
data which is valid on the next rising edge of clock SCK. Bits
XN–X0 refer to the data shifted out by Part 1. Bits YN–Y0
refer to the data shifted out by Part 2 and bits ZN–Z0 refer
to the data shifted out by Part 3. All this data is read back
from the SDO port on Part 1 in a daisy-chained fashion.
Figure 29 shows the isoSPI timing diagram for a READ
command to daisy chained LTC6810-1 parts. The ISOMD
pin is tied to V– on the bottom part so its Port A is configured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI
signals of three stacked devices are shown labeled with
the port (A or B) and part number. Note that ISO B1 and
ISO A2 is actually the same signal, but shown on each
end of the transmission cable that connects Parts 1 and 2.
Likewise, ISO B2 and ISO A3 is the same signal, but with
the cable delay shown between Parts 2 and 3.
COMMAND
CSB
READ DATA
t7
t6
t1
SDI
t5
t2
tCLK
t4
SCK
t3
t8
tRISE
SDO
t11
Xn
t10
Xn-1
Z0
t9
t10
Wn
ISO B1
W0
Wn
ISO A2
Yn
W0
Yn-1
Yn
Yn-1
tRTN
tDSY(CS)
Wn
ISO B2
tDSY(D)
Wn
ISO A3
0
1000
tDSY(CS)
W0
W0
2000
Zn
Zn
Zn-1
Zn-1
3000
4000
5000
6000
68101 F29
Figure 29. isoSPI Timing Diagram
Rev. A
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53
LTC6810-1/LTC6810-2
OPERATION
Waking up the Serial Interface
Waking a Daisy Chain — Method 1
The serial ports (SPI or isoSPI) will enter the low power
IDLE state if there is no activity on Port A or Port B for
a time of tIDLE. The WAKEUP circuit monitors activity on
pins 36 and 37, which are CSB and SCK if ISOMD is low,
or IPA and IMA if ISOMD is high, and activity on pins 38
and 39, which are IMB and IPB for LTC6810-1 and A2 and
A3 for LTC6810-2.
The LTC6810-1 sends a long +1 pulse on Port B after it is
ready to communicate. In a daisy-chained configuration,
this pulse wakes up the next device in the stack which will,
in turn, wake up the next device. If there are ‘N’ devices in
the stack, all the devices are powered up within the time
N • tWAKE or N • tREADY, depending on the Core state. For
large stacks, the time N • tWAKE may be equal to or larger
than tIDLE. In this case, after waiting longer than the time
of N • tWAKE, the host may send another dummy byte and
wait for the time N • tREADY, in order to ensure that all
devices are in the READY state.
If ISOMD = V–, Port A is in SPI mode. Activity on the CSB
or SCK pin will wake up the SPI interface. If ISOMD = VREG,
Port A is in isoSPI mode. Differential activity on IPA–IMA or
IPB–IMB wakes up the isoSPI interface. The LTC6810 will
be ready to communicate when the isoSPI state changes
to READY within tWAKE or tREADY, depending on the Core
state (see Figure 1 and state descriptions for details).
Figure 30 illustrates the timing and the functionally
equivalent circuit. The wake-up circuit responds to the
difference between SCK(IPA) and CS(IMA). Common
mode signals will not wake up the serial interface. The
interface is designed to wake up after receiving a large
signal single-ended pulse, or a low-amplitude symmetric
pulse. The differential signal | SCK(IPA) – CS(IMA)|, must
be at least VWAKE = 200mV for a minimum duration of
tDWELL = 240ns to qualify as a wake up signal that powers
up the serial interface.
Method 1 can be used when all devices on the daisy chain
are in the IDLE state. This guarantees that they propagate
the wake-up signal up the daisy chain. However, this
method will fail to wake up all devices when a device in
the middle of the chain is in the READY state instead of
IDLE. When this happens, the device in READY state will
not propagate the wake-up pulse, so the devices above it
will remain IDLE. This situation can occur when attempting to wake up the daisy chain after only tIDLE of idle time
(some devices may be IDLE, some may not).
REJECTS COMMON
MODE NOISE
CSB OR IMA
SCK OR IPA
VWAKE > 250mV
|SCK(IPA) - CSB(IMA)|
tDWELL > 240ns
WAKE-UP
STATE
LOW POWER MODE
OK TO COMMUNICATE
> tREADY (10µs)
CSB
SCK
200ns
DELAY
LOW POWER MODE
> tIDLE (5.5ms)
RETRIGGERABLE
tIDLE = 5.5ms
ONE-SHOT
WAKE-UP
68101 F30
Figure 30. Wake-up Detection and IDLE Timer
Rev. A
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LTC6810-1/LTC6810-2
OPERATION
Waking a Daisy Chain — Method 2
To calculate the 15-bit PEC value, a simple procedure can
be established:
A more robust wake-up method does not rely on the built-in
wake-up pulse, but manually sends isoSPI traffic for enough
time to wake the entire daisy chain. At minimum, a pair of
long isoSPI pulses (–1 and +1) is needed for each device,
separated by more than tREADY or tWAKE (if the Core state
is STANDBY or SLEEP, respectively), but less than tIDLE.
This allows each device to wake up and propagate the next
pulse to the following device. This method works even if
some devices in the chain are not in the IDLE state. In
practice, implementing method 2 requires toggling the CSB
pin (of the LTC6820, or bottom LTC6810 with ISOMD = 0)
to generate the long isoSPI pulses. Alternatively, dummy
commands (such as RDCFG) can be executed to generate
the long isoSPI pulses.
1. Initialize the PEC to 000000000010000 (PEC is a 15 bit
register group)
2. For each bit DIN coming into the PEC register group,
set
IN0 = DIN XOR PEC [14]
IN3 = IN0 XOR PEC [2]
IN4 = IN0 XOR PEC [3]
IN7 = IN0 XOR PEC [6]
IN8 = IN0 XOR PEC [7]
IN10 = IN0 XOR PEC [9]
IN14 = IN0 XOR PEC [13]
3. Update the 15-bit PEC as follows
PEC [14] = IN14,
PEC [13] = PEC [12],
PEC [12] = PEC [11],
PEC [11] = PEC [10],
PEC [10] = IN10,
PEC [9] = PEC [8],
PEC [8] = IN8,
PEC [7] = IN7,
PEC [6] = PEC [5],
PEC [5] = PEC [4],
PEC [4] = IN4,
PEC [3] = IN3,
PEC [2] = PEC [1],
PEC [1] = PEC [0],
PEC [0] = IN0
DATA LINK LAYER
All Data transfers on LTC6810 occur in byte groups.
Every byte consists of 8 bits. Bytes are transferred with
the most significant bit (MSB) first. CSB must remain low
for the entire duration of a command sequence, including
between a command byte and subsequent data. On a write
command, data is latched in on the rising edge of CSB.
NETWORK LAYER
Packet Error Code
The packet error code (PEC) is a 15-bit cyclic redundancy
check (CRC) value calculated for all of the bits in a register
group in the order they are passed, using the initial PEC
value of 000000000010000 and the following characteristic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1.
4. Go back to step 2 until all the data is shifted. The final
PEC (16 bits) is the 15 bit value in the PEC register with
a 0 bit appended to its LSB
O/P
I/P XOR GATE
I/P
X
PEC REGISTER BIT X
DIN
14
13 12 11 10
9 8
7
6 5 4
3
2 1 0
68101 F31
Figure 31.
Rev. A
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55
LTC6810-1/LTC6810-2
OPERATION
Figure 31 illustrates the algorithm described above. An
example to calculate the PEC for a 16 bit word (0x0001)
is listed in Table 30. The PEC for 0x0001 is computed as
0x3D6E after stuffing a 0 bit at the LSB. For longer data
streams, the PEC is valid at the end of the last bit of data
sent to the PEC register.
LTC6810 calculates PEC for any command or data received
and compares it with the PEC following the command or
data. The command or data is regarded as valid only if
the PEC matches. LTC6810 also attaches the calculated
PEC at the end of the data it shifts out. Table 31 shows the
format of PEC while writing to or reading from LTC6810.
Table 30. PEC Calculation for 0x0001
PEC[14]
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
PEC[13]
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
PEC[12]
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
PEC[11]
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
PEC[10]
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
PEC[9]
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
PEC[8]
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
PEC[7]
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
PEC[6]
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
PEC[5]
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
PEC[4]
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
PEC[3]
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
PEC[2]
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
PEC[1]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
PEC[0]
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
IN14
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
IN10
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
PEC word
IN8
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
IN7
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
IN4
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
IN3
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
IN0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
DIN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Clock Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 31. Write/Read PEC format
Name
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEC0
RD/WR
PEC[14]
PEC[13]
PEC[12]
PEC[11]
PEC[10]
PEC[9]
PEC[8]
PEC[7]
PEC1
RD/WR
PEC[6]
PEC[5]
PEC[4]
PEC[3]
PEC[2]
PEC[1]
PEC[0]
0
Rev. A
56
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LTC6810-1/LTC6810-2
OPERATION
While writing any command to LTC6810, the command
bytes CMD0 and CMD1 (see Table 38 and Table 39) and
the PEC bytes PEC0 and PEC1 are sent on Port A in the
following order:
CMD0, CMD1, PEC0, PEC1
After a broadcast write command to daisy chained
LTC6810-1 devices, data is sent to each device followed
by the PEC. For example, when writing the Configuration
Register Group to two daisy-chained devices (primary
device P, stacked device S), the data will be sent to the
primary device on its slave port in the following order:
CFGR0(S), …, CFGR5(S), PEC0(S), PEC1(S),
CFGR0(P), …, CFGR5(P), PEC0(P), PEC1(P)
After a read command for daisy chained devices, each
device shifts out its data and the PEC that it computed for
its data on its slave port followed by the data received on
its master port. For example, when reading Status Register
Group B from two daisy-chained devices (primary device
P, stacked device S), the primary device sends out data on
its slave port in the following order:
STBR0(P), …, STBR5(P), PEC0(P), PEC1(P),
STBR0(S), …, STBR5(S), PEC0(S), PEC1(S)
Address Commands (LTC6810-2 Only)
An address command is one in which only the addressed
device on the bus responds. Address commands are used
only with LTC6810-2 parts. All commands are compatible
with addressing. See the Bus Protocols section for Address
command format.
Broadcast Commands (LTC6810-1 or LTC6810-2)
A broadcast command is one to which all devices on
the bus will respond, regardless of device address. This
command can be used with LTC6810-1 and LTC6810-2
parts. See the Bus Protocols section for Broadcast command format. With broadcast commands all devices can
be sent commands simultaneously.
In parallel (LTC6810-2) configurations, broadcast commands are useful for initiating ADC conversions or for
sending write commands when all parts are being written
with the same data. The polling function (automatic at the
end of ADC commands, or manual using the PLADC command) can also be used with broadcast commands, but
not with parallel isoSPI devices. Likewise, broadcast read
commands should not be used in the parallel configuration
(either SPI or isoSPI).
Daisy-chained (LTC6810-1) configurations support broadcast commands only, because they have no addressing.
All devices in the chain receive the command bytes simultaneously. For example, to initiate ADC conversions in a
stack of devices, a single ADCV command is sent, and all
devices will start conversions at the same time. For read
and write commands, a single command is sent, and then
the stacked devices effectively turn into a cascaded shift
register, in which data is shifted through each device to the
next higher (on a write) or the next lower (on a read) device
in the stack. See the Serial Interface Overview section.
Polling Methods
The simplest method to determine ADC completion is
for the controller to start an ADC conversion and wait for
the specified conversion time to pass before reading the
results. Both LTC6810-1 and LTC6810-2 also allow polling
to determine ADC completion.
In parallel configurations that communicate in SPI mode
(ISOMD pin tied low), there are two methods of polling.
The first method is to hold CSBI low after an ADC conversion command is sent. After entering a conversion
command, the SDO line is driven low when the device is
busy performing conversions. SDO is pulled high when
the device completes conversions. However, the SDO
will also go back high when CSBI goes high even if the
device has not completed the conversion (Figure 32). An
addressed device drives the SDO line based on its status
alone. A problem with this method is that the controller
is not free to do other serial communication while waiting
for ADC conversions to complete.
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LTC6810-1/LTC6810-2
OPERATION
The next method overcomes this limitation. The controller
can send an ADC start command, perform other tasks, and
then send a poll ADC converter status (PLADC) command
to determine the status of the ADC conversions (Figure 33).
After entering the PLADC command, SDO will go low if
the device is busy performing conversions. SDO is pulled
high at the end of conversions. However, the SDO will also
go high when CSBI goes high even if the device has not
completed the conversion.
In parallel configurations that communicate in isoSPI mode,
the low side port transmits a data pulse only in response
to a master isoSPI pulse received by it. So, after entering the command in either method of polling described
above, isoSPI data pulses are sent to the part to update
the conversion status. These pulses can be sent using
LTC6820 by simply clocking its SCK pin. In response to
this pulse, the device sends back a low isoSPI pulse if it
is still busy performing conversions or a high data pulse
if it has completed the conversions. If a CSB high isoSPI
pulse is sent to the device, it exits the polling command.
tCYCLE
CSB
SCK
SDI
MSB(CMD)
BIT 14(CMD)
LSB(PEC)
SDO
68101 F32
Figure 32. SDO Polling After an ADC Conversion Command (Parallel Configuration)
CSB
SCK
SDI
MSB(CMD)
BIT 14(CMD)
LSB(PEC)
SDO
CONVERSION DONE
68101 F33
Figure 33. SDO Polling Using PLADC Command (Parallel Configuration)
Rev. A
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LTC6810-1/LTC6810-2
OPERATION
In a daisy-chained configuration of N stacked devices,
the same two polling methods can be used. If the bottom
device communicates in SPI mode, the SDO of the bottom device indicates the conversion status of the entire
stack (i.e. SDO will remain low until all the devices in the
stack have completed conversions). In the first method of
polling, after an ADC conversion command is sent, clock
pulses are sent on SCK while keeping CSB low. The SDO
status becomes valid only at the end of N clock pulses on
SCK and gets updated for every clock pulse that follows
(Figure 34). In the second method, the PLADC command
is sent followed by clock pulses on SCK while keeping
If the bottom device communicates in isoSPI mode, isoSPI
data pulses are sent to the device to update the conversion
status. Using LTC6820, this can be achieved by just clocking its SCK pin. The conversion status is valid only after
the bottom LTC6810 device receives N isoSPI data pulses
and the status gets updated for every isoSPI data pulse
that follows. The device returns a low data pulse if any of
the devices in the stack is busy performing conversions
and returns a high data pulse if all the devices are free.
tCYCLE (ALL DEVICES)
CSB
1
SCK
SDI
CSBI low. Similar to the first method, the SDO status is
valid only after N clock cycles on SCKI and gets updated
after every clock cycle that follows (Figure 35).
MSB(CMD)
2
N
LSB(PEC)
SDO
68101 F34
Figure 34.
CSB
1
SCK
SDI
MSB(CMD)
2
N
LSB(PEC)
SDO
68101 F35
CONVERSION DONE
Figure 35.
Rev. A
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59
LTC6810-1/LTC6810-2
OPERATION
Bus Protocols
Protocol Format: The protocol formats for both broadcast
and address commands are depicted in Table 33 through
Table 37. Table 32 is the key for reading the protocol diagrams.
Table 32. Protocol Key
CMD0
Command Byte 0 (See Table 38 and Table 39)
CMD1
Command Byte 1 (See Table 38 and Table 39)
PEC0
Packet Error Code Byte 0 (See Table 31)
PEC1
Packet Error Code Byte 1 (See Table 31)
N
Number of Bytes
…
Continuation of Protocol
Master to Slave
Slave to Master
Command Format: The formats for the broadcast and
address commands are shown in Table 38 and Table 39
respectively. The 11 bit command code CC[10:0] is the
same for a broadcast or an address command. A list of
all the command codes is shown in Table 40. A broadcast
command has a value 0 for CMD0[7] through CMD0[3].
An address command has a value 1 for CMD0[7] followed by the 4 bit address of the device (a3, a2, a1, a0)
in bits CMD0[6:3]. An addressed device will respond
to an address command only if the physical address of
the device on pins A3 to A0 match the address specified
in the address command. The PEC for broadcast and
address commands must be computed on the entire 16
bit command (CMD0 and CMD1).
Table 33. Broadcast/Address Poll Command
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Poll Data
Table 34. Broadcast Write Command
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data Byte Low
…
8
8
8
8
8
Data Byte High
PEC0
PEC1
Shift Byte 1
8
8
8
Data Byte High
PEC0
PEC1
8
8
8
8
Data Byte High
PEC0
PEC1
Shift Byte 1
8
8
8
Data Byte High
PEC0
PEC1
…
Shift Byte n
Table 35. Address Write Command
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data Byte Low
…
Table 36. Broadcast Read Command
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data Byte Low
…
8
…
Shift Byte n
Table 37. Address Read Command
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data Byte Low
…
Table 38. Broadcast Command Format
NAME
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CMD0
WR
0
0
0
0
0
CC[10]
CC[9]
CC[8]
CMD1
WR
CC[7]
CC[6]
CC[5]
CC[4]
CC[3]
CC[2]
CC[1]
CC[0]
Table 39. Address Command Format
NAME
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CMD0
WR
1
a3*
a2*
a1*
a0*
CC[10]
CC[9]
CC[8]
CMD1
WR
CC[7]
CC[6]
CC[5]
CC[4]
CC[3]
CC[2]
CC[1]
CC[0]
*ax is Address Bit x
Rev. A
60
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LTC6810-1/LTC6810-2
OPERATION
Commands
Table 40 lists all the commands and its options for both
LTC6810-1 and LTC6810-2.
Table 40. Command Codes
COMMAND DESCRIPTION
NAME
CC[10:0] — COMMAND CODE
10
9
8
7
6
5
4
3
2
1
0
Write Configuration
Register Group
WRCFG
0
0
0
0
0
0
0
0
0
0
1
Read Configuration
Register Group
RDCFG
0
0
0
0
0
0
0
0
0
1
0
Write Control Register Group WRSCTRL*
(PWM and S)
0
0
0
0
0
0
1
0
1
0
0
Read Control Register Group RDSCTRL*
(PWM and S)
0
0
0
0
0
0
1
0
1
1
0
Write PWM Register Group
(PWM and S)
WRPWM*
0
0
0
0
0
1
0
0
0
0
0
Read PWM Register Group
(PWM and S)
RDPWM*
0
0
0
0
0
1
0
0
0
1
0
Read Cell Voltage
Register Group A
RDCVA
0
0
0
0
0
0
0
0
1
0
0
Read Cell Voltage
Register Group B
RDCVB
0
0
0
0
0
0
0
0
1
1
0
Read S Voltage
Register Group A
RDSA
0
0
0
0
0
0
0
1
0
0
0
Read S Voltage
Register Group B
RDSB
0
0
0
0
0
0
0
1
0
1
0
Read Auxiliary
Register Group A
RDAUXA
0
0
0
0
0
0
0
1
1
0
0
Read Auxiliary
Register Group B
RDAUXB
0
0
0
0
0
0
0
1
1
1
0
Read Status
Register Group A
RDSTATA
0
0
0
0
0
0
1
0
0
0
0
Read Status
Register Group B
RDSTATB
0
0
0
0
0
0
1
0
0
1
0
Read Serial ID
Register Group
RDSID
0
0
0
0
0
1
0
1
1
0
0
Start Cell Voltage ADC
Conversion and Poll Status
ADCV
0
1
MD[1]
MD[0]
1
1
DCP
0
CH[2]
CH[1]
CH[0]
Start Open Wire ADC
Conversion and Poll Status
ADOW
0
1
MD[1]
MD[0]
PUP
1
DCP
1
CH[2]
CH[1]
CH[0]
Start Self-Test Cell Voltage
Conversion and Poll Status
CVST
0
1
MD[1]
MD[0]
ST[1]
ST[0]
0
0
1
1
1
Start GPIOs/Cell 0/REF2 ADC
Conversion and Poll Status
ADAX
1
0
MD[1]
MD[0]
1
1
0
0
CHG[2] CHG[1] CHG[0]
Start GPIOs/Cell 0/REF2
ADC Conversion with Digital
Redundancy and Poll Status
ADAXD
1
0
MD[1]
MD[0]
0
0
0
0
CHG[2] CHG[1] CHG[0]
Rev. A
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61
LTC6810-1/LTC6810-2
OPERATION
COMMAND DESCRIPTION
NAME
CC[10:0] — COMMAND CODE
10
9
8
7
6
5
4
3
2
1
0
Start GPIOs/Cell 0/REF2 ADC
Open Wire Conversion
AXOW
1
0
MD[1]
MD[0]
PUP
0
1
0
Start Self-Test GPIOs/Cell 0/
REF2 Conversion and Poll
Status
AXST
1
0
MD[1]
MD[0]
ST[1]
ST[0]
0
0
Start Status Group ADC
Conversion and Poll Status
ADSTAT
1
0
MD[1]
MD[0]
1
1
0
1
CHST[2] CHST[1] CHST[0]
Start Status Group ADC
Conversion with Digital
Redundancy and Poll Status
ADSTATD
1
0
MD[1]
MD[0]
0
0
0
1
CHST[2] CHST[1] CHST[0]
Start Self-Test Status Group
Conversion and Poll Status
STATST
1
0
MD[1]
MD[0]
ST[1]
ST[0]
0
1
1
1
1
Start Combined Cell Voltage
and Cell 0, GPIO1 Conversion
and Poll Status
ADCVAX
1
0
MD[1]
MD[0]
1
1
DCP
1
1
1
1
Start Combined Cell Voltage
and SC Conversion and Poll
Status
ADCVSC
1
0
MD[1]
MD[0]
1
1
DCP
0
1
1
1
Clear Cell Voltage
Register Group
CLRCELL
1
1
1
0
0
0
1
0
0
0
1
Clear Auxiliary
Register Group
CLRAUX
1
1
1
0
0
0
1
0
0
1
0
Clear Status Register Group
CLRSTAT
1
1
1
0
0
0
1
0
0
1
1
Poll ADC Conversion Status
PLADC
1
1
1
0
0
0
1
0
1
0
0
Diagnose MUX and Poll
Status
DIAGN
1
1
1
0
0
0
1
0
1
0
1
Write COMM
Register Group
WRCOMM
1
1
1
0
0
1
0
0
0
0
1
Read COMM
Register Group
RDCOMM
1
1
1
0
0
1
0
0
0
1
0
Start I2C/SPI Communication
STCOMM
1
1
1
0
0
1
0
0
0
1
1
MUTE
0
0
0
0
0
1
0
1
0
0
0
UNMUTE
0
0
0
0
0
1
0
1
0
0
1
Mute Discharge
Unmute Discharge
CHG[2] CHG[1] CHG[0]
1
1
1
*The WRSCTRL and WRPWM and RDSCTRL and RDPWM commands all access the same PWM Register Group. The WRSCTRL and RDSCTRL
commands are provided for compatibility with other LTC681x devices in a daisy-chain.
Table 41. Command Bit Descriptions
NAME
MD[1:0]
DESCRIPTION
ADC Mode
VALUES
MD
ADCOPT(CFGR0[0]) = 0
ADCOPT (CFGR0[0]) = 1
00
422Hz Mode
1kHz Mode
01
27 kHz Mode (Fast)
14 kHz Mode
10
7 kHz Mode (Normal)
3 kHz Mode
11
26 Hz Mode (Filtered)
2 kHz Mode
Rev. A
62
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LTC6810-1/LTC6810-2
OPERATION
NAME
DESCRIPTION
DCP
Discharge Permitted
VALUES
DCP
0
Discharge Not Permitted
1
Discharge Permitted
Total Conversion Time in 8 ADC Modes
CH
CH[2:0]
PUP
Cell Selection for ADC
Conversion
Pull-Up/Pull-Down Current
for Open Wire Conversions
000
All Cells
001
Cell 1
010
Cell 2
011
Cell 3
100
Cell 4
101
Cell 5
110
Cell 6
27kHz
14kHz
7kHz
3kHz
2kHz
1kHz
422Hz
26Hz
524µs
699µs
1.2ms
1.9ms
3.3ms
6.1ms
12ms
201ms
200µs
229µs
404µs
520µs
753µs
1.2ms
2.1ms
34ms
PUP
0
Pull-Down Current
1
Pull-Up Current
Self Test Conversion Result
ST[1:0]
Self Test Mode Selection
ST
27kHz
14kHz
7kHz
3kHz
2kHz
1kHz
422Hz
26Hz
01
Self Test 1
0x9565
0x9553
0x9555
0x9555
0x9555
0x9555
0x9555
0x9555
10
Self test 2
0x6A9A
0x6AAC
0x6AAA
0x6AAA
0x6AAA
0x6AAA
0x6AAA
0x6AAA
Total Conversion Time in the 8 ADC Modes
CHG
CHG[2:0]
GPIO Selection for ADC
Conversion
000
S0, GPIO 1–4,
2nd Reference
001
S0
010
GPIO 1
011
GPIO 2
100
GPIO 3
101
GPIO 4
110
2nd Reference
27kHz
14kHz
7kHz
3kHz
2kHz
1kHz
422Hz
26Hz
521µs
695µs
1.2ms
1.9ms
3.3ms
6.0ms
12ms
183ms
200µs
229µs
403µs
520µs
752µs
1.2ms
2.1ms
34ms
27kHz
14kHz
7kHz
3kHz
2kHz
1kHz
422Hz
26Hz
741µs
858µs
1.6ms
2.0ms
3.0ms
4.8ms
8.5ms
134ms
200µs
229µs
403µs
520µs
752µs
1.2ms
2.1ms
34ms
Total Conversion Time in 8 ADC Modes
CHST
CHST[2:0]* Status Group Selection
000
SOC, ITMP,
VA, VD
001
SC
010
ITMP
011
VA
100
VD
*Note: Valid options for CHST in ADSTAT command are 0–4. If CHST is set to 5/6 in ADSTAT command, the LTC6810 treats it like ADAX command with
CHG =5/6.
Rev. A
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LTC6810-1/LTC6810-2
OPERATION
Memory Map
Table 42. Configuration Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CFGR0
RD/WR
RSVD
GPIO4
GPIO3
GPIO2
GPIO1
REFON
DTEN
ADCOPT
CFGR1
RD/WR
VUV[7]
VUV[6]
VUV[5]
VUV[4]
VUV[3]
VUV[2]
VUV[1]
VUV[0]
CFGR2
RD/WR
VOV[3]
VOV[2]
VOV[1]
VOV[0]
VUV[11]
VUV[10]
VUV[9]
VUV[8]
CFGR3
RD/WR
VOV[11]
VOV[10]
VOV[9]
VOV[8]
VOV[7]
VOV[6]
VOV[5]
VOV[4]
CFGR4
RD/WR
DCC0
MCAL
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
CFGR5
RD/WR
DCTO[3]
DCTO[2]
DCTO[1]
DCTO[0]
SCONV
FDRF
DIS_RED
DTMEN
Table 43. Cell Voltage Register Group A
REGISTER
CVAR0
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RD
C1V[7]
C1V[6]
C1V[5]
C1V[4]
C1V[3]
C1V[2]
C1V[1]
C1V[0]
CVAR1
RD
C1V[15]
C1V[14]
C1V[13]
C1V[12]
C1V[11]
C1V[10]
C1V[9]
C1V[8]
CVAR2
RD
C2V[7]
C2V[6]
C2V[5]
C2V[4]
C2V[3]
C2V[2]
C2V[1]
C2V[0]
CVAR3
RD
C2V[15]
C2V[14]
C2V[13]
C2V[12]
C2V[11]
C2V[10]
C2V[9]
C2V[8]
CVAR4
RD
C3V[7]
C3V[6]
C3V[5]
C3V[4]
C3V[3]
C3V[2]
C3V[1]
C3V[0]
CVAR5
RD
C3V[15]
C3V[14]
C3V[13]
C3V[12]
C3V[11]
C3V[10]
C3V[9]
C3V[8]
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Table 44. Cell Voltage Register Group B
REGISTER
RD/WR
BIT 7
CVBR0
RD
C4V[7]
C4V[6]
C4V[5]
C4V[4]
C4V[3]
C4V[2]
C4V[1]
C4V[0]
CVBR1
RD
C4V[15]
C4V[14]
C4V[13]
C4V[12]
C4V[11]
C4V[10]
C4V[9]
C4V[8]
CVBR2
RD
C5V[7]
C5V[6]
C5V[5]
C5V[4]
C5V[3]
C5V[2]
C5V[1]
C5V[0]
CVBR3
RD
C5V[15]
C5V[14]
C5V[13]
C5V[12]
C5V[11]
C5V[10]
C5V[9]
C5V[8]
CVBR4
RD
C6V[7]
C6V[6]
C6V[5]
C6V[4]
C6V[3]
C6V[2]
C6V[1]
C6V[0]
CVBR5
RD
C6V[15]
C6V[14]
C6V[13]
C6V[12]
C6V[11]
C6V[10]
C6V[9]
C6V[8]
Table 45. Auxiliary Register Group A
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AVAR0
REGISTER
RD
S0V[7]
S0V[6]
S0V[5]
S0V[4]
S0V[3]
S0V[2]
S0V[1]
S0V[0]
AVAR1
RD
S0V[15]
S0V[14]
S0V[13]
S0V[12]
S0V[11]
S0V[10]
S0V[9]
S0V[8]
AVAR2
RD
G1V[7]
G1V[6]
G1V[5]
G1V[4]
G1V[3]
G1V[2]
G1V[1]
G1V[0]
AVAR3
RD
G1V[15]
G1V[14]
G1V[13]
G1V[12]
G1V[11]
G1V[10]
G1V[9]
G1V[8]
AVAR4
RD
G2V[7]
G2V[6]
G2V[5]
G2V[4]
G2V[3]
G2V[2]
G2V[1]
G2V[0]
AVAR5
RD
G2V[15]
G2V[14]
G2V[13]
G2V[12]
G2V[11]
G2V[10]
G2V[9]
G2V[8]
Rev. A
64
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LTC6810-1/LTC6810-2
OPERATION
Table 46. Auxiliary Register Group B
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AVBR0
RD
G3V[7]
G3V[6]
G3V[5]
G3V[4]
G3V[3]
G3V[2]
G3V[1]
G3V[0]
AVBR1
RD
G3V[15]
G3V[14]
G3V[13]
G3V[12]
G3V[11]
G3V[10]
G3V[9]
G3V[8]
AVBR2
RD
G4V[7]
G4V[6]
G4V[5]
G4V[4]
G4V[3]
G4V[2]
G4V[1]
G4V[0]
AVBR3
RD
G4V[15]
G4V[14]
G4V[13]
G4V[12]
G4V[11]
G4V[10]
G4V[9]
G4V[8]
AVBR4
RD
REF[7]
REF[6]
REF[5]
REF[4]
REF[3]
REF[2]
REF[1]
REF[0]
AVBR5
RD
REF[15]
REF[14]
REF[13]
REF[12]
REF[11]
REF[10]
REF[9]
REF[8]
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Table 47. Status Register Group A
REGISTER
RD/WR
BIT 7
STAR0
RD
SC[7]
SC[6]
SC[5]
SC[4]
SC[3]
SC[2]
SC[1]
SC[0]
STAR1
RD
SC[15]
SC[14]
SC[13]
SC[12]
SC[11]
SC[10]
SC[9]
SC[8]
STAR2
RD
ITMP[7]
ITMP[6]
ITMP[5]
ITMP[4]
ITMP[3]
ITMP[2]
ITMP[1]
ITMP[0]
STAR3
RD
ITMP[15]
ITMP[14]
ITMP[13]
ITMP[12]
ITMP[11]
ITMP[10]
ITMP[9]
ITMP[8]
STAR4
RD
VA[7]
VA[6]
VA[5]
VA[4]
VA[3]
VA[2]
VA[1]
VA[0]
STAR5
RD
VA[15]
VA[14]
VA[13]
VA[12]
VA[11]
VA[10]
VA[9]
VA[8]
Table 48. Status Register Group B
REGISTER
STBR0
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RD
VD[7]
VD[6]
VD[5]
VD[4]
VD[3]
VD[2]
VD[1]
VD[0]
STBR1
RD
VD[15]
VD[14]
VD[13]
VD[12]
VD[11]
VD[10]
VD[9]
VD[8]
STBR2
RD
C4OV
C4UV
C3OV
C3UV
C2OV
C2UV
C1OV
C1UV
STBR3
RD
RSVD
RSVD
RSVD
MUTE
C6OV
C6UV
C5OV
C5UV
STBR4
RD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
STBR5
RD
REV[3]
REV[2]
REV[1]
REV[0]
RSVD
RSVD
MUXFAIL
THSD
Table 49. Redundant S Voltage Register Group A
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RD
S1V[7]
S1V[6]
S1V[5]
S1V[4]
S1V[3]
S1V[2]
S1V[1]
S1V[0]
CVCR1
RD
S1V[15]
S1V[14]
S1V[13]
S1V[12]
S1V[11]
S1V[10]
S1V[9]
S1V[8]
CVCR2
RD
S2V[7]
S2V[6]
S2V[5]
S2V[4]
S2V[3]
S2V[2]
S2V[1]
S2V[0]
CVCR0
CVCR3
RD
S2V[15]
S2V[14]
S2V[13]
S2V[12]
S2V[11]
S2V[10]
S2V[9]
S2V[8]
CVCR4
RD
S3V[7]
S3V[6]
S3V[5]
S3V[4]
S3V[3]
S3V[2]
S3V[1]
S3V[0]
CVCR5
RD
S3V[15]
S3V[14]
S3V[13]
S3V[12]
S3V[11]
S3V[10]
S3V[9]
S3V[8]
Rev. A
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OPERATION
Table 50. Redundant S Voltage Register Group B
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CVDR0
RD
S4V[7]
S4V[6]
S4V[5]
S4V[4]
S4V[3]
S4V[2]
S4V[1]
S4V[0]
CVDR1
RD
S4V[15]
S4V[14]
S4V[13]
S4V[12]
S4V[11]
S4V[10]
S4V[9]
S4V[8]
CVDR2
RD
S5V[7]
S5V[6]
S5V[5]
S5V[4]
S5V[3]
S5V[2]
S5V[1]
S5V[0]
CVDR3
RD
S5V[15]
S5V[14]
S5V[13]
S5V[12]
S5V[11]
S5V[10]
S5V[9]
S5V[8]
CVDR4
RD
S6V[7]
S6V[6]
S6V[5]
S6V[4]
S6V[3]
S6V[2]
S6V[1]
S6V[0]
CVDR5
RD
S6V[15]
S6V[14]
S6V[13]
S6V[12]
S6V[11]
S6V[10]
S6V[9]
S6V[8]
BIT 3
BIT 2
BIT 1
BIT 0
Table 51. COMM Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
COMM0
RD/WR
ICOM0[3]
ICOM0[2]
ICOM0[1]
ICOM0[0]
D0[7]
D0[6]
D0[5]
D0[4]
COMM1
RD/WR
D0[3]
D0[2]
D0[1]
D0[0]
FCOM0[3]
FCOM0[2]
FCOM0[1]
FCOM0[0]
COMM2
RD/WR
ICOM1[3]
ICOM1[2]
ICOM1[1]
ICOM1[0]
D1[7]
D1[6]
D1[5]
D1[4]
COMM3
RD/WR
D1[3]
D1[2]
D1[1]
D1[0]
FCOM1[3]
FCOM1[2]
FCOM1[1]
FCOM1[0]
COMM4
RD/WR
ICOM2[3]
ICOM2[2]
ICOM2[1]
ICOM2[0]
D2[7]
D2[6]
D2[5]
D2[4]
COMM5
RD/WR
D2[3]
D2[2]
D2[1]
D2[0]
FCOM2[3]
FCOM2[2]
FCOM2[1]
FCOM2[0]
Table 52. PWM Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SCTL0
RD/WR
PWM2[3]
PWM2[2]
PWM2 [1]
PWM2[0]
PWM1[3]
PWM1[2]
PWM1[1]
PWM1[0]
SCTL1
RD/WR
PWM4[3]
PWM4[2]
PWM4[1]
PWM4[0]
PWM3[3]
PWM3[2]
PWM3[1]
PWM3[0]
SCTL2
RD/WR
PWM6[3]
PWM6[2]
PWM6[1]
PWM6[0]
PWM5[3]
PWM5[2]
PWM5[1]
PWM5[0]
SCTL3
RD/WR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SCTL4
RD/WR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SCTL5
RD/WR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Table 53. Serial ID Register Group
REGISTER
SIDR0
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RD
SID[7]
SID[6]
SID[5]
SID[4]
SID[3]
SID[2]
SID[1]
SID[0]
SIDR1
RD
SID[15]
SID[14]
SID[13]
SID[12]
SID[11]
SID[10]
SID[9]
SID[8]
SIDR2
RD
SID[23]
SID[22]
SID[21]
SID[20]
SID[19]
SID[18]
SID[17]
SID[16]
SIDR3
RD
SID[31]
SID[30]
SID[29]
SID[28]
SID[27]
SID[26]
SID[25]
SID[24]
SIDR4
RD
SID[39]
SID[38]
SID[37]
SID[36]
SID[35]
SID[34]
SID[33]
SID[32]
SIDR5
RD
SID[47]
SID[46]
SID[45]
SID[44]
SID[43]
SID[42]
SID[41]
SID[40]
Rev. A
66
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LTC6810-1/LTC6810-2
OPERATION
Table 54. Memory Bit Descriptions
NAME
DESCRIPTION
VALUES
GPIOx
GPIOx Pin
Control
Write: 0 -> GPIOx pin pull down ON; 1-> GPIOx pin pull down OFF
Read: 0 -> GPIOx pin at logic 0; 1 -> GPIOx pin at logic 1
REFON
References
Powered Up
1 -> References remain powered up until watchdog time out
0 -> References shut down after conversions
DTEN
Discharge Timer 1 -> Enables the Discharge Timer for discharge switches
0 -> Disables Discharge Timer
Enable
ADCOPT
ADC Mode
Option Bit
ADCOPT: 0 -> Selects Modes 27kHz, 7kHz, 422Hz or 26Hz with MD[1:0] bits in ADC conversion commands.
1 -> Selects Modes 14kHz, 3kHz, 1kHz or 2kHz with MD[1:0] bits in ADC conversion commands.
VUV
Undervoltage
Comparison
Voltage*
Comparison voltage = VUV • 16 • 100µV
Default: VUV = 0x000
VOV
Overvoltage
Comparison
Voltage*
Comparison voltage = VOV • 16 • 100µV
Default: VUV = 0x000
MCAL
Enables
1 -> Enables multicalibration during ADC conversions, for backwards compatibility with 6811/6812/6810.
Multi-Calibration Defaults to 0, single calibration during ADC.
DCC[x]
Discharge
Cell x
x = 1 to 6 1 -> Turn ON shorting switch for Cell x, S[x] to S[x–1]
0 -> Turn OFF shorting switch for Cell x, S[x] to S[x–1] (default)
x = 0
DCTO
Discharge Time
Out Value
1 -> Turn ON S0 pulldown for discharging optional 7th cell
0 -> Turn OFF S0 pulldown (default)
DCTO
(Write)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Time
(min)
Disabled
0.5
1
2
3
4
5
10
15
20
30
40
60
75
90
120
DCTO
(Write)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Time
Left
(min)
Disabled
or Time
Out
0
to
0.5
0.5
to
1
1
to
2
2
to
3
3
to
4
4
to
5
5
to
10
10
to
15
15
to
20
20
to
30
30
to
40
40
to
60
60
to
75
75
to
90
90
to
120
SCONV
Enable Cell
Measurement
Redundancy
Using S Pins
1 -> Enables redundant measurements of the cell voltages using the S pins
0 -> Disables redundant measurements of the cell voltages
FDRF
Force Digital
Redundancy
Failure
1 -> Forces the digital redundancy comparison for A/D conversions to fail
0 -> Enables the normal redundancy comparison
DIS_RED
Disable Digital
Redundancy
Check
1 -> Disables the digital redundancy comparison for A/D conversions
0 -> Enables the digital redundancy comparison for A/D conversions
DTMEN
Enable
1 -> Enables the Discharge Timer Monitor function if the DTEN pin is asserted.
Discharge Timer 0 -> Disables the Discharge Timer Monitor function. The normal Discharge Timer function will be enabled if DTEN pin is
Monitor
asserted.
CxV
Cell x Voltage*
x = 1 to 6 16 bit ADC measurement value for Cell x
Cell Voltage for Cell x = CxV • 100µV
CxV is reset to 0xFFFF on power up and after Clear command
S0V
S0 Voltage*
16 bit ADC measurement value for S0 with respect to V–
S0 Voltage = S0V • 100µV
S0V is reset to 0xFFFF on power up and after Clear command
Rev. A
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67
LTC6810-1/LTC6810-2
OPERATION
NAME
DESCRIPTION
VALUES
GxV
GPIO x Voltage* x = 1 to 4 16 bit ADC measurement value for GPIOx
Voltage for GPIOx = GxV • 100µV
GxV is reset to 0xFFFF on power up and after Clear command
REF
2nd Reference
Voltage*
16 bit ADC measurement value for 2nd Reference
Voltage for 2nd Reference = REF • 100µV
Normal range is within 2.99V to 3.01V considering data sheet limits, hysteresis and long term drift
SC
Sum of All Cells
Measurement*
16 bit ADC measurement value of the Sum of All Cell Voltages
Sum of All Cells Voltage = SC • 100µV • 10
ITMP
Internal Die
Temperature*
16 bit ADC measurement value of Internal Die temperature
Temperature measurement (ºC) = ITMP • 100µV/7.5mV/ºC – 273ºC
VA
Analog Power
Supply Voltage*
16 bit ADC measurement value of Analog power supply voltage
Analog Power supply voltage = VA • 100µV
The value of VA is set by external components and should be in the range 4.5V to 5.5V for normal operation
VD
Digital Power
Supply Voltage*
16 bit ADC measurement value of Digital power supply voltage
Digital Power supply voltage = VD • 100µV
Normal range is within 2.7V to 3.6V
CxOV
Cell ‘x’
x = 1 to 6 Cell voltage compared to VOV comparison voltage
Overvoltage Flag
0 -> Cell ‘x’ not flagged for overvoltage condition.
1-> Cell ‘x’ flagged
CxUV
Cell ‘x’
Undervoltage
Flag
x = 1 to 6 Cell voltage compared to VUV comparision voltage
0 -> Cell ‘x’ not flagged for under–v
REV
Revision Code
Device Revision Code
RSVD
Reserved Bits
Read: Read back value can be 1 or 0
RSVD0
Reserved Bits
Read: Read back value is always 0
RSVD1
Reserved Bits
Read: Read back value is always 1
MUXFAIL
Multiplexer Self
Test Result
Read:
THSD
Thermal
Shutdown
Status
Read: 0 -> Thermal shutdown has not occurred 1 -> Thermal shutdown has occurred
THSD bit cleared to ‘0’ on read of Status Register Group B
SxV
Redundant Cell x x = 1 to 6 16 bit redundant ADC measurement value for Cell x
Redundant measurement of Cell Voltage for Cell x = SxV • 100µV
Voltage* via the
SxV is reset to 0xFFFF on power up and after Clear command
S pins
PWMx[x]
PWM Discharge 0000 – Selects 0% Discharge Duty Cycle if Watchdog Timer Has Expired
Control
0001 – Selects 3.3% Discharge Duty Cycle if Watchdog Timer Has Expired
0010 – Selects 6.7% Discharge Duty Cycle if Watchdog Timer Has Expired
…
1110 – Selects 46.7% Discharge Duty Cycle if Watchdog Timer Has Expired
1111 – Selects 50% Discharge Duty Cycle if Watchdog Timer Has Expired
SID[x]
Serial ID
ICOMn
Initial
Communication
Control Bits
0 -> Multiplexer passed self test
1 -> Multiplexer failed self test
Unique 48-bit serial identification code
Write
I 2C
SPI
Read
I2C
SPI
0110
0001
0000
0111
START
STOP
BLANK
NO TRANSMIT
1000
1010
1001
1111
CSB low
CSB Falling Edge
CSB high
NO TRANSMIT
0110
0001
0000
0111
START from Master
STOP from Master
SDA low between bytes SDA high between bytes
0111
Rev. A
68
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LTC6810-1/LTC6810-2
OPERATION
NAME
DESCRIPTION
VALUES
Dn
I2C/SPI
Data transmitted(received) to(from) I2C/SPI slave device
FCOMn
Final
Communication
Control Bits
Communication
Data Byte
Write
I2C
SPI
Read
I2C
SPI
0000
1000
1001
Master ACK
Master NACK
Master NACK + STOP
X000
1001
CSB low
CSB high
0001
0111
1111
0001
ACK from Master
ACK from Slave
NACK from Slave
ACK from Slave + NACK from Slave +
STOP from Master STOP from Master
1001
1111
*Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.
Rev. A
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69
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
PROVIDING DC POWER
2. Internal Regulator
The primary supply pin for the LTC6810 is the 5V ±0.5V
VREG input pin. There are three ways to generate the VREG
input as follows:
t low V+ voltages where there is not enough headroom
A
to regulate the Drive Pin, VREGA is driven by an internal
regulator. The Drive pin is designed such that when used
with an external NPN, VREGA will be set to a voltage that
is at least 400mV greater than the internal VREGA voltage.
This ensures that when the DRIVE pin regulator has sufficient headroom the internal VREGA will turn off. The internal
regulator is enabled by applying a 25µA load on the DRIVE
pin. Connecting a 100k resistor on the DRIVE pin to GND
allows the part to work across the entire V+ supply range.
When V+ is too low, the 100k resistor on the DRIVE pin
pulls enough current to enable the internal regulator that
sets VREGA to about 4.7V. When V+ is high, the DRIVE pin
sets VREGA to about 5.1V. The internal regulator is not
capable of sinking current and will shutdown in this case.
1. Simple Linear Regulator
The DRIVE pin can be used to form a discrete regulator
with the addition of a few external components, as shown
in Figure 36. The DRIVE pin provides a 5.6V output, capable of sourcing 1mA. When buffered with an NPN transistor, this provides a stable 5V over temperature. The NPN
transistor should be chosen to have a sufficient Beta over
temperature (>40) to supply the necessary supply current. The peak VREG current requirement of the LTC6810
approaches 20mA when simultaneously communicating
over isoSPI and making ADC conversions. If the VREG pin
is required to support any additional load, a transistor with
an even higher beta may be required.
The NPN collector can be powered from any voltage
source that is a minimum 6V above V–. This includes the
cells that are being monitored, or an unregulated power
supply. A 100Ω/100nF RC decoupling network is recommended for the collector power connection to protect the
NPN from transients. The emitter of the NPN should be
bypassed with a 1µF capacitor. Larger capacitance should
be avoided since this will increase the wake-up time of the
LTC6810. Some attention should be given to the thermal
characteristic of the NPN, as there can be significant heating with a high collector voltage.
100Ω
LTC6810
WDT
DRIVE
DXT5551P5
VREG
DTEN
VREF1
VREF2
GPIO4
V–
V–
GPIO3
0.1µF
3. External Regulator for Improved Efficiency
F or improved efficiency when powering the LTC6810 from
the cell stack, the VREG may be powered from a DC/DC
converter, rather than the NPN pass transistor. An ideal
circuit is based on Analog Devices’ LTC3990 step-down
regulator, as shown in Figure 37. A 50Ω resistor is recommended between the battery stack and the LTC3990
input; this will prevent in-rush current when connecting
to the stack and it will reduce conducted EMI. The EN pin
should be connected to the DRIVE pin which will put the
LTC3990 into a low power state when the LTC6810 is
in the sleep state. In this mode, to avoid any contention
with the internally generated VREGA, the load current on
the DRIVE pin should be less than 1µA to ensure that the
internal regulator is disabled.
VIN
6.5V
MINIMUM
VIN
BOOST
LT3990
1µF
DRIVE
1µF
EN/UVLO
PG
33µH
BD
22pF
RT
374k
68101 F36
Figure 36. Simple VREG Power Source Using NPN Pass Transistor
f = 400kHz
GND
VREG
5V
40mA
SW
2.2µF
1µF
0.22µF
1M
FB
22µF
316k
68101 F37
Figure 37. VREG Powered from Cell Stack with High
Efficiency Regulator
Rev. A
70
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LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
INTERNAL PROTECTION AND FILTERING
structure is the same. Zener-like suppressors are shown
with their nominal clamp voltage, and the unmarked
diodes exhibit standard PN junction behavior.
Internal Protection Features
The LTC6810 incorporates various ESD safeguards
to ensure robust performance. An equivalent circuit
showing the specific protection structures is shown in
Figure 38. While pins 34 to 39 have different functionality
for the LTC6810-1 and LTC6810-2 variants, the protection
3
LTC6810
V+
12V
12V
24V
12V
24V
4
5
6
7
8
9
10
11
12
13
14
15
16
17
28
29
12V
C6
S6
C5
24V
C1
V
12V
24V
24V
12V
24V
12V
24V
24V
12V
25Ω
12V
24V
24V
24V
12V
12V
24V
24V
S0
–
12V
24V
S1
C0
24V
24V
S2
12V
12V
24V
24V
S3
C2
24V
24V
S4
C3
12V
24V
S5
C4
12V
24V
12V
12V
12V
12V
12V
WDT
SDI
SDO
IPB/A3
IMB/A2
SCK
CSB
ICMP/A1
IBIAS/A0
DRIVE
VREG
VREF2
VREF1
ISOMD
DTEN
GPIO4
GPIO3
GPIO2
GPIO1
42
41
40
39
38
37
36
35
34
33
32
31
30
27
26
25
20
19
18
68101 F39
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 28
Figure 38. Internal ESD Protection Structures of the LTC6810
Filtering of Cell and GPIO Inputs
The LTC6810 uses a delta-sigma ADC, which has a delta
sigma modulator followed by a SINC3 finite impulse
response (FIR) digital filter. This greatly relaxes input
filtering requirements. Furthermore, the programmable
oversampling ratio allows the user to determine the best
trade-off between measurement speed and filter cutoff
frequency. Even with this high order low pass filter, fast
transient noise can still induce some residual noise in
measurements, especially in the faster conversion modes.
This can be minimized by adding an RC low pass decoupling to each ADC input, which also helps reject potentially
damaging high energy transients. Adding more than about
100Ω to the ADC inputs begins to introduce a systematic
error in the measurement, which can be improved by raising the filter capacitance or mathematically compensating
in software with a calibration procedure. For situations
that demand the highest level of battery voltage ripple
rejection, grounded capacitor filtering is recommended.
This configuration has a series resistance and capacitors
that decouple HF noise to V–. In systems where noise
is less periodic or higher oversample rates are in use, a
differential capacitor filter structure is adequate. In this
configuration there are series resistors to each input,
but the capacitors connect between the adjacent C pins.
However, the differential capacitor sections interact. As a
result, the filter response is less consistent and results
in less attenuation than predicted by the RC, by approximately a decade. Note that the capacitors only see one
cell of applied voltage (thus smaller and lower cost) and
tend to distribute transient energy uniformly across the IC
(reducing stress events on the internal protection structure). Figure 39 shows the two methods schematically.
ADC accuracy varies with R, C as shown in the Typical
Performance curves, but error is minimized if R = 100Ω
and C = 10nF. The GPIO pins will always use a grounded
capacitor configuration because the measurements are
all with respect to V–.
Rev. A
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71
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
100Ω
RDIS
100Ω
10nF
C2
RDIS
10nF
S2
100Ω
10nF
C1
LTC6810
RDIS
10nF
S1
100Ω
RDIS
RFILTER
C1
LTC6810
100Ω
10nF
RDIS
S0
V–
10nF
RFILTER
C0
C(N)
S(N)
CFILTER
C(N–1)
RDISCHARGE
S0
V–
S(N+1)
CFILTER
RDISCHARGE
S1
C0
LTC6810
C(N+1)
RDISCHARGE
S2
100Ω
RDIS
RFILTER
C2
S(N–1)
68101 F41a
68101 F39
GROUNDED CAPACITOR FILTER
DIFFERENTIAL CAPACITOR FILTER
a)
Figure 39. Input Filter Structure Configurations
LTC6810
C(N+1)
RDISCHARGE
CELL BALANCING
The LTC6810 includes signals (pins S0 through S6) that
can be used to balance cells with internal or external
discharge. Cells can be discharged using the internal
N-channel NMOS at the S pins, or the S pins can act
as digital outputs to drive external transistors. Figure 40
shows an example of internal cell balancing using
the LTC6810.
LTC6810
C(N+1)
RDISCHARGE
S(N+1)
C(N)
RDISCHARGE
C(N)
RDISCHARGE
S(N)
C(N–1)
RDISCHARGE
S(N+1)
S(N)
C(N–1)
RDISCHARGE
S(N–1)
S(N–1)
68101 F41b
Choosing a Discharge Resistor
When sizing the balancing resistor it is important to know
the typical battery imbalance and the allowable time for
cell balancing. In most small battery applications it is reasonable for the balancing circuitry to be able to correct
for a 5% SOC (State Of Charge) error with 5 hours of
balancing. For example a 5AHr battery with a 5% SOC
imbalance will have approximately 250mAHrs of imbalance. Using a 50mA balancing current this could be corrected in 5 hours. With a 100mA balancing current, the
error would be corrected in 2.5Hrs. In systems with very
large batteries it becomes difficult to use passive balancing to correct large SOC imbalances in short periods of
time. The excessive heat created during balancing generally limits the balancing current. In large capacity battery
b)
Figure 40. Internal Discharge Circuits
applications if short balancing times are required an active
balancing solution should be considered. When choosing
a balance resistor the following equations can be used to
help determine a resistor value:
Balance Current =
%SOC_Imbalance • Battery Capacity
Balance Resistor =
Number of Hours to Balance
Nominal Cell Voltage
Balance Current
Rev. A
72
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LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
With passive balancing, if one cell in a series stack
becomes overcharged, an S output can slowly discharge
this cell by connecting it to a resistor. Each S output is
connected to an internal N-channel MOSFET with a maximum on resistance of 4Ω. An external resistor should be
connected in series with these MOSFETs to allow most of
the heat to be dissipated outside of the LTC6810 package,
as illustrated in Figure 40.
Cell Balancing with Internal MOSFETs
The internal discharge switches (MOSFETs) S1 through
S6 can be used to passively balance cells as shown in
Figure 40a with balancing current of 150mA or less.
Balancing current larger than 150mA is not recommended
for the internal switches due to excessive die heating.
When discharging cells with the internal discharge
switches, the die temperature should be monitored.
100Ω
10nF
RDIS
Cell Balancing with External Transistors
For applications that require balancing currents above
150mA, the S outputs can be used to control external
transistors. The S pins can act as digital outputs suitable
for driving the gate of an external MOSFET or the base
of an external NPN as illustrated in Figure 41. Figure 41
shows external transistor circuits that include RC filtering.
100Ω
C2
LTC6810
9.1V
10nF
RDIS
NPN
S2
1k
B1
Figure 40b shows the discharge current path thru the
internal discharge switches. Asserting adjacent discharge
switches will result in a current path shown on the right
in Figure 40b. The LTC6810 does not allow adjacent
discharge switches to be asserted, so the WRFG command
will not be executed if adjacent DCC bits in the CONFIG
register are asserted. The current path shown at the right
of Figure 40b shows that if adjacent discharges switches
were permitted to be on, discharge current would flow
through the series combination of cells instead of the
individual cells.
100Ω
C1
10nF
RDIS
NPN
S1
1k
B2
C1
10nF
RDIS
9.1V
S1
1k
B2
100Ω
100Ω
C0
C0
10nF
RDIS
1k
10nF
RDIS
S0
LTC6810
S2
1k
B1
100Ω
C2
Q3
NPN
1k
S0
9.1V
V–
V–
68101 F41
Figure 41. External Discharge Circuit
Rev. A
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73
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Table 55. Discharge Control During an ADCV Command with DCP = 0
CELL MEASUREMENT PERIODS
CELL1
DISCHARGE
PIN
t0 to t1M
S1
OFF
CELL2
CELL3
CELL4
CELL CALIBRATION PERIODS
CELL5
CELL6
t1M to t2M t2M to t3M t3M to t4M t4M to t5M t5M to t6M
OFF
ON
ON
ON
CELL1
CELL2
CELL3
CELL4
CELL5
CELL6
t6M to t1C
t1C to t2C
t2C to t3C
t3C to t4C
t4C to t5C
t5C to t6C
OFF
OFF
OFF
ON
ON
ON
OFF
S2
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
S3
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
S4
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
S5
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
S6
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
DISCHARGE CONTROL DURING CELL
MEASUREMENTS
If the discharge permitted (DCP) bit is high at the time of
a cell measurement command, the S pin discharge states
do not change during cell measurements. However, if the
DCP bit is low, S pin discharge states will be disabled
while the corresponding cell or adjacent cells are being
measured. If using an external discharge transistor, the
relatively low 1kΩ impedance of the internal LTC6810
PMOS transistors should allow the discharge currents
to fully turn off before the cell measurement. Table 55
illustrates the ADCV command with DCP = 0. In this
table, OFF indicates that the S pin discharge is forced
off irrespective of the state of the corresponding DCC[x]
bit. ON indicates that the S pin discharge will remain on
during the measurement period if it was ON prior to the
measurement command.
In some cases it is not possible for the automatic discharge control to eliminate all measurement error caused
by running the discharges. This is due to the discharge
transistor not turning off fast enough for the cell voltage
to completely settle before the measurement starts. For
the best measurement accuracy when running discharge,
the MUTE and UNMUTE commands should be used. The
MUTE command can be issued to temporarily disable
all discharge transistors before the ADCV command is
issued. After issuing a MUTE command a delay of roughly
50µS should be issued before sending a ADC conversion
command. This allows the cell voltage to settle before
any measurement is taken. After the cell conversion completes an UNMUTE can be sent to re-enable all discharge
transistors that were previously ON. Using this method
maximizes the measurement accuracy with a very small
time penalty.
Method to Verify Discharge Circuits
When using the internal and external discharge feature,
the ability to verify the discharge functionality can be
verified in software. The discharge circuits are shown in
Figures 40 and 41. The functionality of the discharge circuits can be verified by implementing a redundant S pin
measurement and comparing it to a C pin measurement.
The S pins on the LTC6810 have two purposes, to provide internal discharge or turn on the external discharge
device but also to allow for a redundant cell measurement. Asserting the SCONV bit in the config register will
enable the redundant S pin cell measurements. The S pin
measurements taken when the discharge is on require
that the discharge permit bit (DCP) be set. The S pin
measurements when discharge is on will be a function of
the external discharge resistors but will generally be substantially less than C pin measurements. The resistance
of the internal discharge FET is approximately 10Ω, if the
external discharge resistor in Figure 40 is also 10Ω, the
S pin measurement when discharge is on will be 1/3 of
the C pin measurement.
Rev. A
74
For more information www.analog.com
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Seven Cell Application with Redundant Measurement
The LTC6810 has the ability to measure an additional seventh cell with redundancy and internal discharge capability. In six cell applications C0 is connected to V–. An
additional seventh cell, Cell 0, can be connected between
C0 and V– as shown in Figure 42. The primary cell measurement is done by connecting GPIO1 to C0 and using
the ADAX command to measure Cell 0. External filtering
V+
RFILTER
RFILTER
CFILTER
RDISCHARGE
CELL5
RFILTER
CFILTER
RDISCHARGE
CELL4
RFILTER
CFILTER
RDISCHARGE
CELL3
RFILTER
CFILTER
RDISCHARGE
CELL2
RFILTER
CFILTER
RDISCHARGE
CELL1
RFILTER
CFILTER
RDISCHARGE
CELL0
RFILTER
LTC6810
CFILTER
C2
RDIS
C6
RDISCHARGE
CELL6
is added to the C0 pin as shown in Figure 42. A redundant
measurement can be made by with the S0 pin. Asserting
the SCONV bit in the configuration register and using the
ADCVAX command will combine the six cell measurements with redundancy along with measurements of S0
and GPIO1. Figure 43 shows the seven cell application
where the S pins are used to drive the gates of external
MOSFETs. An external PFET is used to discharge Cell 0.
S6
CFILTER
2N7002BK
CELL2
LTC6810
S2
1k
C5
9.1V
S5
RFILTER
C1
C4
RDIS
S4
CFILTER
S1
2N7002BK
C3
CELL1
1k
S3
9.1V
C2
RFILTER
C0
S2
RDIS
C1
2N7002BK
S1
CELL0
S0
1k
GPIO1
C0
S0
CFILTER
RDIS
GPIO1
RQJ0303PGD
V–
68101 F43
Figure 42. Seven Cell with Internal Discharge
V–
68101 F44
Figure 43. Seven Cell with External Discharge
Rev. A
For more information www.analog.com
75
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
DIGITAL COMMUNICATIONS
PEC Calculation
The Packet Error Code (PEC) can be used to ensure that
the serial data read from the LTC6810 is valid and has not
been corrupted. This is a critical feature for reliable communication, particularly in environments of high noise.
The LTC6810 requires that a PEC be calculated for all
data being read from and written to the LTC6810. For
this reason it is important to have an efficient method for
calculating the PEC.
The C code below provides a simple implementation of
a lookup table derived PEC calculation method. There
are two functions. The first function init_PEC15_Table()
should only be called once when the microcontroller starts
and will initialize a PEC15 table array called pec15Table[].
This table will be used in all future PEC calculations. The
PEC15 table can also be hard coded into the microcontroller rather than running the init_PEC15_Table() function at startup. The pec15() function calculates the PEC
and will return the correct 15 bit PEC for byte arrays of
any given length.
/************************************
Copyright 2012 Analog Devices, Inc.
Permission to freely use, copy, modify, and distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies:
THIS SOFTWARE IS PROVIDED “AS IS” AND LTC DISCLAIMS ALL WARRANTIES
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
EVENT SHALL LTC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE OF SAME, INCLUDING
ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
PERFORMANCE OF THIS SOFTWARE.
***********************************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
{
remainder = i 0; --bit)
{
if (remainder & 0x4000)
{
remainder = ((remainder 7) ^ data[i]) & 0xff;//calculate PEC table address
remainder = (remainder 50m): IB = 1mA and K = 0.25
For addressable multidrop: IB = 1mA and K = 0.4
For applications with little system noise, setting IB to
0.5mA is a good compromise between power consumption and noise immunity. Using this IB setting with a
1:1 transformer and RM = 100Ω, RB1 should be set to
3.01k and RB2 set to 1k. With typical CAT5 twisted pair,
these settings will allow for communication up to 50m.
Applications in very noisy environments or with cables
longer than 50m should increase the IB to 1mA. Higher
drive current compensates for the increased insertion
loss in the cable and provides high noise immunity.
When using cables over 50m and a transformer with a
1:1 turns ratio and RM = 100Ω, RB1 would be 1.5k and
RB2 would be 499Ω.
The length of the cable determines the maximum clock
rate of an isoSPI link. For cables 10 meters or less, the
maximum 1MHz SPI clock frequency is possible. As the
length of the cable increases, the maximum possible SPI
clock rate decreases. This dependence is a result of the
increased propagation delays that can create possible timing violations. Figure 45 shows how the maximum data
rate reduces as the cable length increases when using a
CAT 5 twisted pair.
ISOLATION BARRIER
(MAY USE ONE OR TWO TRANFORMERS)
ISOMD
MASTER
SDO
SDI
SCK
CS
IPB
+
VA
MOSI
IMB –
2V
MISO IBIAS
SCK
CS
ICMP
LTC6810
RM
RB1
•
•
•
•
TWISTED-PAIR CABLE
WITH CHARACTERISTIC IMPEDANCE RM
+ IPA ISOMD
RM VA
LTC6810
– IMA
2V
IBIAS
RB1
VREG
ICMP
RB2
RB2
68101 F45
Figure 44. isoSPI Circuit
Rev. A
For more information www.analog.com
77
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
1.2
they may be preferred. In this case, the addition of a split
termination resistor and a bypass capacitor (Figure 46a)
can enhance the isoSPI performance. Large center tap
capacitors greater than 10nF should be avoided as they
may prevent the isoSPI common mode voltage from
settling. Common mode chokes similar to those used
in Ethernet or CANbus applications are recommended.
Specific examples are provided in Table 57.
CAT-5 ASSUMED
DATA RATE (Mbps)
1.0
0.8
0.6
0.4
0.2
IP
49.9Ω
100µH CMC
•
100
LTC6810
6820 TA01b
10nF
49.9Ω
XFMR
•
•
isoSPI LINK
•
10
CABLE LENGTH (METERS)
IM
V–
Figure 45. Data Rate vs Cable Length
Cable delay affects three timing specifications, tCLK, t6 and
t7. In the Electrical Characteristics table, each is derated
by 100ns to allow for 50ns of cable delay. For longer
cables, the minimum timing parameters obey the following relationship:
tCLK, t6 and t7 > 0.9μs + 2 • tCABLE(0.2m per nS)
a)
IP
51Ω
LTC6810
10nF
For high levels of electromagnetic interference (EMC),
additional filtering is recommended. The circuit example in
Figure 46 shows the use of common-mode chokes (CMC)
to add common-mode noise rejection from transients
on the battery lines. The use of a center tapped transformer will also provide additional noise performance. A
bypass capacitor connected to the center tap creates a low
impedance for common-mode noise (Figure 46b). Since
transformers without a center tap can be less expensive,
51Ω
IM
V–
Implementing a Modular isoSPI Daisy Chain
The hardware design of a daisy-chain isoSPI bus is identical for each device in the network due to the daisy-chain
point-to-point architecture. The simple design as shown in
Figure 44 is functional, but inadequate for most designs.
The use of cables between battery modules, particularly
in automotive applications, can add noise to the communication lines. Therefore, the termination resistor RM
should be split and bypassed with a capacitor as shown
in Figure 46. This change provides both a differential and
a common mode termination, which increases the system
noise immunity.
100µH CMC
•
1
CT XFMR
•
•
isoSPI LINK
•
0
10nF
68101 F46
b)
Figure 46. Daisy Chain Interface Components
An important daisy chain design consideration is the number of devices in the isoSPI network, since this determines
the serial timing and affects data latency and throughput.
The maximum number of devices in an isoSPI daisy chain
is dictated by the serial timing requirements. However, it
is important to note that the serial read back time, and the
increased current consumption, might present a practical
limitation.
For a daisy chain, there are two timing consideration
that must be made (see Figure 29) to guarantee proper
operation:
1. t6, the time between the last clock and the rising chip
select must be long enough.
2. t5, the time between commands, so the time from a
rising chip select to the next falling chip select must
be long enough.
Rev. A
78
For more information www.analog.com
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
IPB
49.9Ω
LTC6810
10nF
49.9Ω
GNDD
IMB
IBIAS
ICMP
1k
1k
GNDD
IPA
49.9Ω
10nF
49.9Ω
IMA
GNDD
CT
10nF*
GNDD
T1
•
•
V–
GNDD
CT
10nF*
GNDC
IPB
49.9Ω
LTC6810
10nF
49.9Ω
GNDC
IMB
IBIAS
ICMP
1k
1k
GNDC
IPA
49.9Ω
49.9Ω
V–
IMA
10nF
GNDC
GNDC
CT
10nF*
•
GNDC
T2
•
CT
10nF*
GNDB
IPB
49.9Ω
LTC6810
49.9Ω
IMB
IBIAS
ICMP
1k
10nF
GNDB
1k
GNDB
IPA
•
•
IP
49.9Ω
49.9Ω
49.9Ω
V–
IMA
LTC6820
CT
10nF
10nF*
GNDB GNDB
CT
10nF*
GNDA
49.9Ω
IBIAS
ICMP
10nF
GNDA
IM
1k
1k
GNDA
V–
GNDA
GNDB
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP
68101 F47
Figure 47. Daisy Chain Interface Components on Single Board
Rev. A
For more information www.analog.com
79
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Both t5 and t6 must be lengthened as the number of
LTC6810 devices in the daisy chain increase. The equations for these times are below:
t5 > (#devices • 70ns) + 900ns
t6 > (#devices • 70ns) + 950ns
Connecting Multiple LTC6810-1s on the Same PCB
When connecting multiple LTC6810-1 devices on the
same PCB, only a single transformer is required between
the LTC6810‑1 isoSPI ports. The absence of the cable also
reduces the noise levels on the communication lines and
often only a split termination is required. Figure 47 shows
an example application that has multiple LTC6810-1s
VREG
ACT45B-101-2P-TL003
49.9Ω
IPA
1k
C13
10nF
GNDB
IMB
10nF
•
49.9Ω 10nF
IBIAS
ICMP
On single board designs with lower noise requirements,
it is possible for a simplified capacitor-isolated coupling
as shown in Figure 48 to replace the transformer. In this
circuit the transformer is directly replaced with two 10nF
capacitors. An optional common mode choke (CMC)
helps provides noise rejection similar to application circuits using transformers. The circuit is designed to use
IBIAS/ICMP settings identical to the transformer circuit.
•
LTC6810
IPB
on the same PCB, communicating to the bottom MCU
through a LTC6820 isoSPI driver. If a transformer with
a center tap is used, a capacitor can be added for better
noise rejection. Additional noise filtering is provided with
discrete common mode chokes (CMC) placed to both
sides of the single transformer as shown in Figure 47.
1k
GNDB
VREG
49.9Ω 10nF
49.9Ω
V–
GNDB
IMA
VREG
ACT45B-101-2P-TL003
49.9Ω 10nF
49.9Ω
GNDA
IMB
IBIAS
ICMP
IPA
1k
10nF
•
LTC6810
IPB
•
GNDB
10nF
1k
VREG
GNDA
49.9Ω 10nF
49.9Ω
V–
GNDA
IMA
GNDA
68101 F48
Figure 48. Capacitive Isolation Coupling for LTC6810-1s on the Same PCB
Rev. A
80
For more information www.analog.com
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Connecting an MCU to an LTC6810-1 with an isoSPI
Data Link
The LTC6820 will convert standard 4-wire SPI into a
2-wire isoSPI link that can communicate directly with
the LTC6810. An example is shown in Figure 49. The
LTC6820 can be used in applications to easily provide
isolation between the microcontroller and the stack of
LTC6810s. The LTC6820 also enables system configurations that have the BMS controller at a remote location
relative to the LTC6810 devices and the battery pack.
Configuring the LTC6810-2 in a Multi-Drop isoSPI Link
The addressing feature of the LTC6810-2 allows multiple
devices to be connected to a single isoSPI master by distributing them along one twisted pair. In effect, this creates
a large parallel SPI network. A basic multi-drop system
is shown in Figure 50; the twisted pair is terminated only
at the beginning (master) and the end of the cable. In
between, the additional LTC6810-2s are connected to
short stubs on the twisted pair. These stubs should be
kept short, with as little capacitance as possible, to avoid
degrading the termination along the isoSPI wiring.
When an LTC6810-2 is not addressed, it will not transmit
data pulses. This eliminates the possibility for collisions
V+
IPB
LTC6810
•
•
•
•
since only the addressed device returns data to the master. Generally, multi-drop systems are best confined to
compact assemblies where they can avoid excessive isoSPI pulse-distortion and EMC pickup.
Basic Connection of the LTC6810-2 in a Multi-Drop
Configuration
In a multi-drop isoSPI bus, placing the termination at the
end of the transmission line provides the best performance (with 100Ω typically). Each of the LTC6810 isoSPI
ports should be connected to the bus with a resistor network, as shown in Figure 51a. Here again, a center-tapped
transformer offers the best performance and a commonmode-choke (CMC) increases the noise rejection further,
as shown in Figure 51b. An RC snubber is used at the IC
connections to suppress resonances (the IC capacitance
provides sufficient out-of-band rejection). When using a
non-center-tapped transformer, a virtual CT can be generated by connecting a CMC as a voltage-splitter. Series
resistors are recommended to decouple the LTC6810 and
board parasitic capacitance from the transmission line.
Reducing these parasitics on the transmission line will
minimize reflections.
10nF
49.9Ω
IMB
IBIAS
ICMP
1k
•
•
49.9Ω
GNDB
1k
IPA
IP
IMA
•
•
•
10nF
49.9Ω
V–
LTC6820
49.9Ω
•
49.9Ω
IBIAS
ICMP
10nF
1k
GNDA
49.9Ω
GNDB
GNDA
GNDB
IM
1k
V–
68101 F49
GNDA
Figure 49. Interfacing an LTC6810-1 with a µC Using an LTC6820 for Isolated SPI Control
Rev. A
For more information www.analog.com
81
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
LTC6810
•
•
IPA
VREGC
ISOMD
IBIAS
100Ω
1.21k
ICMP
IMA
806Ω
V–
GNDC
LTC6810
•
•
IPA
GNDC
VREGB
ISOMD
IBIAS
1.21k
ICMP
IMA
100nF
µC
SDO
SDI
SCK
CS
5V
1.21k
5V
1.21k
LTC6820
VDDS
EN
IBIAS
MOSI
ICMP
MISO
GND
SCK
SLOW
CS
MSTR
5V
IP
POL
IM
PHA
5V
VDD
806Ω
V–
806Ω
GNDB
LTC6810
•
•
•
•
IPA
GNDB
VREGA
ISOMD
IBIAS
100Ω
1.21k
100nF
ICMP
IMA
806Ω
V–
GNDA
GNDA
68101 F50
Figure 50. Connecting the LTC6810-2 in a Multi-Drop Configuration
Rev. A
82
For more information www.analog.com
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
IPA
IMA
V–
•
•
•
•
isoSPI
BUS
22Ω
•
15pF
100µH CMC HV XFMR 22Ω
100µH CMC
•
LTC6810
402Ω
10nF
a)
IPA
15pF
IMA
V–
CT HV XFMR 22Ω
•
100µH CMC
•
•
isoSPI
BUS
22Ω
•
LTC6810
402Ω
10nF
68101 F51
b)
Figure 51. Preferred isoSPI Bus Couplings For Use With LTC6810-2
Rev. A
For more information www.analog.com
83
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Table 56. Recommended Transformers
SUPPLIER
PART NUMBER
TEMP RANGE
VWORKING
VHIPOT/60S
CT
CMC
H
L
W
(W/ LEADS)
PINS
AECQ200
l
Recommended Dual Transformers
Bourns
SM91501AL
–40°C to 125°C
1000V
4.3kVdc
l
l
5.0mm
15.0mm
14.7mm
12SMT
Bourns
SM13105L (AS4562)
–40°C to 125°C
1600V
4.3kVrms
l
l
5.0mm
15.0mm
27.9mm
12SMT
–
Bourns
US4374
–40°C to 125°C
950V
4.3kVdc
l
l
4.9mm
15.6mm
24.0mm
12SMT
l
Jingweida
S12502BA
–40°C to 125°C
1000V
4.3kVdc
l
l
5.0mm
14.8mm
14.8mm
12SMT
l
TG110-AE050N5LF
–40°C to 85/125°C
60V (est)
1.5kVrms
l
l
6.4mm
12.7mm
9.5mm
16SMT
l
Sumida
CLP178-C20114
–40°C to 125°C
1000V (est)
3.75kVrms
l
l
9mm
17.5mm
15.1mm
12SMT
–
Sumida
CLP0612-C20115
600Vrms
3.75kVrms
l
–
5.7mm
12.7mm
9.4mm
16SMT
–
1000V
4.3kVdc
–
l
3.5mm
14.7mm
15.0mm
10SMT
l
Halo
Pulse
HM2100NL
–40°C to 105°C
Pulse
HM2112ZNL
–40°C to 125°C
1600V
4.3kVdc
l
l
3.5mm
14.7mm
15.5mm
12SMT
l
Pulse
HX1188FNL
–40°C to 85°C
60V (est)
1.5kVrms
l
l
6.0mm
12.7mm
9.7mm
16SMT
–
Pulse
HX0068ANL
–40°C to 85°C
60V (est)
1.5kVrms
l
l
2.1mm
12.7mm
9.7mm
16SMT
–
Wurth
7490140110
–40°C to 85°C
250Vrms
4kVrms
l
l
10.9mm 24.6mm
17.0mm
16SMT
–
Wurth
7490140111
0°C to 70°C
1000V (est)
4.5kVrms
l
–
8.4mm
17.1mm
15.2mm
12SMT
–
Wurth
749014018
0°C to 70°C
250Vrms
4kVrms
l
l
8.4mm
17.1mm
15.2mm
12SMT
–
1000V
4.3kVdc
l
l
6.5mm
8.5mm
8.9mm
6SMT
l
Recommended Single Transformers
Bourns
SM91502AL
–40°C to 125°C
Bourns
SM13102AL (US4195)
–40°C to 125°C
800V
4kVrms
l
l
3.8mm
11.6mm
21.1mm
6SMT
–
Halo
TD04-QXLTAW
–40°C to 85°C
1000V (est)
5kVrms
l
–
8.6mm
8.9mm
16.6mm
6TH
–
Halo
TGR04-6506V6LF
–40°C to 125°C
300V
3kVrms
l
–
10mm
9.5mm
12.1mm
6SMT
–
Halo
TGR04-A6506NA6NL
–40°C to 125°C
300V
3kVrms
l
–
9.4mm
8.9mm
12.1mm
6SMT
l
Halo
TDR04-A550ALLF
–40°C to 105°C
1000V
5kVrms
l
–
6.4mm
8.9mm
16.6mm
6TH
l
Jingweida
S06107BA
–40°C to 125°C
1000V (est)
4.3kVdc
l
l
6.3mm
7.6mm
9.9mm
6SMT
–
Pulse
HM2101NL
–40°C to 105°C
1000V
4.3kVdc
–
l
5.7mm
7.6mm
9.3mm
6SMT
l
Pulse
HM2113ZNL
–40°C to 125°C
1600V
4.3kVdc
l
l
3.5mm
9mm
15.5mm
6SMT
l
Sumida
CEEH96BNP-LTC6804/11
–40°C to 125°C
600V
2.5kVrms
–
–
7mm
9.2mm
12.0mm
4SMT
–
Sumida
CEP99NP-LTC6804
–40°C to 125°C
600V
2.5kVrms
l
–
10mm
9.2mm
12.0mm
8SMT
–
Sumida
ESMIT-4180/A
–40°C to 105°C
250Vrms
3kVrms
–
–
3.5mm
5.2mm
9.1mm
4SMT
l
Sumida
ESMIT-4187
–40°C to 105°C
>400Vrms (est)
2.5kVrms
–
–
3.5mm
7.5mm
12.8mm
4SMT
l
VMT40DR-201S2P4
–40°C to 125°C
600V (est)
3.4kVdc
l
–
4.0mm
8.5mm
13.8mm
6SMT
l
TDK
ALT4532V-201-T001
–40°C to 105°C
80V
~1kV
l
–
2.9mm
3.2mm
4.5mm
6SMT
l
TDK
VGT10/9EE-204S2P4
–40°C to 125°C
700V
2.8kVrms
l
–
10.6mm 10.4mm
12.6mm
8SMT
l
ALTW0806C-C03
–40°C to 125°C
300V (est)
3kVrms
l
–
8.8mm
8.9mm
6SMT
l
Wurth
750340848
–40°C to 105°C
250V
3kVrms
–
XFMRS
XFBMC29-BA09
–40°C to 85°C
1600V (est)
2.9kVrms
l
TDK
Sunlord
l
6.3mm
2.2mm
4.4mm
9.1mm
4SMT
–
5.0mm
10.0mm
19.5mm
6SMT
l
Rev. A
84
For more information www.analog.com
LTC6810-1/LTC6810-2
APPLICATIONS INFORMATION
Transformer Selection Guide
As shown in Figure 44, a transformer or pair of transformers are used to isolate the isoSPI signals between
two isoSPI ports. The isoSPI signals have programmable
pulse amplitudes up to 1.6VP-P and pulse widths of 50ns
and 150ns. To be able to transmit these pulses with the
necessary fidelity the system requires that the transformers have primary inductances above 60µH and a 1:1 turns
ratio. It is also necessary to use a transformer with less
than 2.5µH of leakage inductance. In terms of pulse shape
the primary inductance will mostly effect the pulse droop
of the 50ns and 150ns pulses. If the primary inductance is
too low the pulse amplitude will begin to droop and decay
over the pulse period, if the pulse droop is severe the
effective pulse width seen by the receiver will drop, reducing noise margin. Some droop is acceptable as long as it
is a relatively small percentage of the total pulse amplitude. The leakage inductance will primarily effect the rise
and fall times of the pulses. Slower rise and fall times will
effectively reduce the pulse width. Pulse width is determined by the receiver as the time the signal is above the
threshold set at the ICMP pin. This means that slow rise
and fall times cut into the timing margins. Generally it
is best to keep pulse edges as fast as possible. When
evaluating transformers it is also worth noting is the parallel winding capacitance. While transformers have very
good CMRR at low frequency, this rejection will degrade
at higher frequencies and this is largely due to the winding
to winding capacitance. So when choosing a transformer
it is best to pick one with less parallel winding capacitance
when possible.
When choosing a transformer it is equally important to
pick a part that has an adequate isolation rating for the
application. The working voltage rating of a transformer
is a key spec when selecting a part for an applications.
Interconnecting daisy chain links between LTC6810-1
devices will typically see
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