LTC692/LTC693
Microprocessor
Supervisory Circuits
FEATURES
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DESCRIPTION
Guaranteed Reset Assertion at VCC = 1V
1.5mA Maximum Supply Current
Fast (35ns Maximum) Onboard Gating of RAM Chip
Enable Signals
4.40V Precision Voltage Monitor
Power OK/Reset Time Delay: 200ms or Adjustable
Minimum External Component Count
1μA Maximum Standby Current
Voltage Monitor for Power-Fail or Low Battery
Warning
Thermal Limiting
Performance Specified Over Temperature
Superior Upgrade for MAX690 Family
SO8 and SO16 Packaging
APPLICATIONS
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The LTC®692/LTC693 provide complete power supply
monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
the power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
chip enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with VCC as low as 1V.
The LTC692/LTC693 power the active CMOS RAMs with a
charge-pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
For an early warning of impending power failure, the
LTC692/LTC693 provide an internal comparator with a
user-defined threshold. An internal watchdog timer is
also available, which forces the reset pins to active states
when the watchdog input is not toggled prior to a preset
timeout period.
Critical μP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners..
TYPICAL APPLICATION
RESET Output Voltage vs
Supply Voltage
VIN ≥ 7.5V
+
10μF
LT1086-5
VIN
VOUT
ADJ
5V
VCC
+
100μF
0.1μF
VOUT
0.1μF
LTC692
LTC693
POWER TO
μP
CMOS RAM POWER
μP
SYSTEM
VBATT
3V
RESET
51k
PFI
10k
MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
GND
μP RESET
PFO
μP NMI
WDI
I/O LINE
RESET OUTPUT VOLTAGE (V)
5
TA = 25°C
EXTERNAL PULL-UP = 10μA
VBATT = 0V
4
3
2
1
692_3 • TA01
0.1μF
100Ω
0
0
1
3
4
2
SUPPLY VOLTAGE (V)
5
692_3 • TA02
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LTC692/LTC693
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Terminal Voltage
VCC ...................................................... –0.3V to 6.0V
VBATT ................................................... –0.3V to 6.0V
All Other Inputs ..................... –0.3V to (VOUT + 0.3V)
Input Current
VCC ................................................................. 200mA
VBATT ................................................................ 50mA
GND ................................................................. 20mA
VOUT Output Current ................. Short-Circuit Protected
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC692C/LTC693C ................................. 0°C to 70°C
LTC692I .............................................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VOUT 1
8
VBATT
VCC 2
7
RESET
GND 3
6
WDI
PFI 4
5
PFO
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 130°C/W (N)
TJMAX = 110°C, θJA = 180°C/W (S)
VBATT
1
16 RESET
VOUT
2
15 RESET
VCC
3
14 WDO
GND
4
13 CE IN
BATT ON
5
12 CE OUT
LOW LINE
6
11 WDI
OSC IN
7
10 PFO
OSC SEL
8
9
N PACKAGE
16-LEAD PDIP
S8 PACKAGE CONDITIONS: PCB MOUNT ON FR4 MATERIAL,
STILL AIR AT 25°C, COPPER TRACE
PFI
SW PACKAGE
16-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 130°C/W
S16 PACKAGE CONDITIONS: PCB MOUNT ON FR4 MATERIAL,
STILL AIR AT 25°C, COPPER TRACE
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC692CN8#PBF
LTC692CN8#TRPBF
LTC692CN8
8-Lead Plastic DIP
0°C to 70°C
LTC692CS8#PBF
LTC692CS8#TRPBF
692
8-Lead Plastic SO
0°C to 70°C
LTC692IS8#PBF
LTC692IS8#TRPBF
692I
8-Lead Plastic SO
–40°C to 85°C
LTC693CN#PBF
LTC693CN#TRPBF
LTC693CN
16-Lead Plastic DIP
0°C to 70°C
LTC693CS#PBF
LTC693CS#TRPBF
LTC693CS
16-Lead Plastic SO
0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC692/LTC693
PRODUCT SELECTION GUIDE
PINS
RESET
THRESHOLD
(V)
WATCHDOG
TIMER
BATTERY
BACKUP
POWER-FAIL
WARNING
LTC692
8
4.40
X
X
X
LTC693
16
4.40
X
X
X
LTC690
8
4.65
X
X
X
LTC691
16
4.65
X
X
X
LTC694
8
4.65
X
X
X
LTC695
16
4.65
X
X
X
LTC699
8
4.65
X
LTC1232
8
4.37/4.62
X
LTC1235
16
4.65
X
X
X
LTC694-3.3
8
2.90
X
X
X
LTC695-3.3
16
2.90
X
X
X
RAM WRITEPROTECT
CONDITIONAL
BATTERY
BACKUP
PUSHBUTTON
RESET
X
X
X
X
X
X
X
X
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.50
4.00
V
V
Battery Backup Switching
Operating Voltage Range
VCC
VBATT
VOUT Output Voltage
4.50
2.00
IOUT = 1mA
VCC – 0.05
VCC – 0.10
VCC – 0.005
VCC – 0.005
V
V
IOUT = 50mA
VCC – 0.50
VCC – 0.250
V
VBATT – 0.1
VBATT – 0.02
VOUT in Battery Backup Mode
IOUT = 250μA, VCC < VBATT
Supply Current (Exclude IOUT)
IOUT ≤ 50mA
Supply Current in Battery Backup Mode
VCC = 0V, VBATT = 2.8V
Battery Standby Current
(+ = Discharge, – = Charge)
5.5V > VCC > VBATT + 0.2V
Battery Switchover Threshold
VCC – VBATT
Power Up
Power Down
l
V
l
0.6
0.6
1.5
2.5
mA
mA
l
0.04
0.04
1
5
μA
μA
0.02
0.10
μA
μA
l
–0.1
–1.0
70
50
Battery Switchover Hysteresis
mV
mV
20
BATT ON Output Voltage (Note 4)
ISINK = 3.2mA
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = VOUT, Sink Current
BATT ON = 0V, Source Current
mV
0.4
V
mA
μA
0.5
35
1
25
4.25
4.40
4.50
Reset and Watchdog Timer
l
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Active Time
(Note 5)
40
OSC SEL High, VCC = 5V
l
160
140
200
200
V
mV
240
280
ms
ms
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LTC692/LTC693
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Watchdog Timeout Period, Internal Oscillator
Long Period, VCC = 5V
l
1.2
1.0
1.6
1.6
2.00
2.25
sec
sec
l
80
70
100
100
120
140
ms
ms
4097
1025
Clock
Cycles
Short Period, VCC = 5V
Watchdog Timeout Period, External Clock
(Note 6)
Long Period
Short Period
4032
960
Reset Active Time PSRR
1
ms/V
Watchdog Timeout Period PSRR, Internal OSC
1
ms/V
l
Minimum WDI Input Pulse Width
VIL = 0.4V, VIH = 3.5V
RESET Output Voltage at VCC = 1V
ISINK = 10μA, VCC = 1V
RESET and LOW LINE Output Voltage
(Note 4)
ISINK = 1.6mA, VCC = 4.25V
ISOURCE = 1μA, VCC = 5V
3.5
RESET and WDO Output Voltage
(Note 4)
ISINK = 1.6mA, VCC = 5V
ISOURCE = 1μA, VCC = 4.25V
3.5
RESET, RESET, WDO, LOW LINE Output
Short-Circuit Current (Note 4)
Output Source Current
Output Sink Current
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
200
ns
4
1
3
25
200
mV
0.4
V
V
0.4
V
V
25
μA
mA
0.8
V
V
3.5
WDI = VOUT
WDI = 0V
l
l
4
–8
50
–50
μA
μA
VCC = 5V
l
1.25
1.3
1.35
V
Power-Fail Detector
PFI Input Threshold
PFI Input Threshold PSRR
0.3
PFI Input Current
PFO Output Voltage (Note 4)
PFO Short-Circuit Source Current
(Note 4)
±0.01
ISINK = 3.2mA
ISOURCE = 1μA
mV/V
±25
nA
0.4
V
V
25
μA
mA
3.5
PFI = High, PFO = 0V
PFI = Low, PFO = VOUT
1
3
25
PFI Comparator Response Time (Falling)
ΔVIN = –20mV, VOD = 15mV
2
μs
PFI Comparator Response Time (Rising)
(Note 4)
ΔVIN = 20mV, VOD = 15mV with 10kΩ
Pull-Up
40
8
μs
μs
Chip Enable Gating
CE IN Threshold
VIL
VIH
0.8
2.0
CE IN Pull-Up Current (Note 7)
CE OUT Output Voltage
CE Propagation Delay
CE OUT Output Short-Circuit Current
3
ISINK = 3.2mA
ISOURCE = 3mA
ISOURCE = 1μA, VCC = 0V
VCC = 5V, CL = 20pF
Output Source Current
Output Sink Current
μA
0.4
V
V
V
35
45
ns
ns
VOUT – 1.50
VOUT – 0.05
l
20
20
30
35
V
V
mA
mA
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LTC692/LTC693
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator
OSC IN Input Current (Note 7)
±2
OSC SEL Input Pull-Up Current (Note 7)
μA
5
OSC IN Frequency Range
OSC SEL = 0V
OSC IN Frequency with External Capacitor
OSC SEL = 0V, COSC = 47pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range, consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3μA. However, external
pull-up resistors may be used when higher speed is required.
Note 5: The LTC692/LTC693 have minimum reset active times of 140ms
(200ms typically). The reset active time of the LTC693 can be adjusted
(see Table 2 in Applications Information Section).
l
0
μA
250
4
kHz
kHz
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (see Block Diagram).
Variation in the timeout period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the timeout period is 64 clocks plus one clock of jitter.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.
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LTC692/LTC693
TYPICAL PERFORMANCE CHARACTERISTICS
5.00
2.80
VCC = 5V
VBATT = 2.8V
TA = 25°C
OUTPUT VOLTAGE (V)
4.95
OUTPUT VOLTAGE (V)
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
4.90
SLOPE = 5Ω
4.85
4.80
1.308
VCC = 0V
VBATT = 2.8V
TA = 25°C
VCC = 5V
1.306
PFI INPUT THRESHOLD (V)
VOUT vs IOUT
2.78
SLOPE = 125Ω
2.76
2.74
1.304
1.302
1.300
1.298
1.296
4.75
10
0
30
40
20
LOAD CURRENT (mA)
2.72
50
0
100
300
400
200
LOAD CURRENT (μA)
692_3 • TPC01
208
200
192
PFO OUTPUT VOLTAGE (V)
RESET VOLTAGE THRESHOLD (V)
216
4.40
4.39
4.38
6
VCC = 5V
TA = 25°C
5
4
3
VPFI
+
2
1.3V
–
100
0
1.305V
4.36
50
25
75
0
TEMPERATURE (°C)
100
692_3 • TPC04
VPFI = 20mV STEP
VCC = 5V
TA = 25°C
4
3
2
VPFI
+
1
1.3V
–
PFO
30pF
0
1.315V
0
20 40
6
5
2
3 4 5
TIME (μs)
6
7
8
692_3 • TPC06
VCC = 5V
TA = 25°C
4
3
2
5V
1
0
1.315V
VPFI = 20mV STEP
1.295V
1
Power-Fail Comparator Response
Time with Pull-Up Resistor
PFO OUTPUT VOLTAGE (V)
PFO OUTPUT VOLTAGE (V)
5
0
125
692_3 • TPC05
Power-Fail Comparator
Response Time
6
30pF
4.37
4.35
–50 –25
125
PFO
1
1.285V
50
25
75
0
TEMPERATURE (°C)
125
Power-Fail Comparator
Response Time
4.41
VCC = 5V
184
–50 –25
100
692_3 • TPC03
Reset Voltage Threshold
vs Temperature
224
RESET ACTIVE TIME
50
25
75
0
TEMPERATURE (°C)
692_3 • TPC02
Reset Active Time
vs Temperature
232
1.294
–50 –25
500
692_3 • TPC07
+
1.3V
–
10k
PFO
30pF
VPFI = 20mV STEP
1.295V
60 80 100 120 140 160 180
TIME (μs)
VPFI
0
2
4
8 10 12 14 16 18
TIME (μs)
6
692_3 • TPC08
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LTC692/LTC693
PIN FUNCTIONS
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of VOUT. BATT ON goes high
when VOUT is internally switched to VBATT .
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or VOUT
when C3 is not used.
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT , C3 is shut down and
PFO is forced low.
CE OUT : Logic Output on the Chip Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
RESET: Logic Output for μP Reset Control. Whenever VCC
falls below either the reset voltage threshold (4.40V typically) or VBATT, RESET goes active low. After VCC returns
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 140ms. When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for
a minimum of 140ms for every preset timeout period
(see Figure 11). The reset active time is adjustable on
the LTC693. An external pushbutton reset can be used in
connection with the RESET output. See Pushbutton Reset
in the Applications Information section.
GND: Ground Pin.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.40V typically),
LOW LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when VCC drops below VBATT (see
Table 1).
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 200ms typical. OSC IN selects between the 1.6
seconds and 100ms typical watchdog timeout periods. In
both cases the timeout period immediately after a reset is
1.6 seconds typical.
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low
allows OSC IN to be driven from an external clock signal
or an external capacitor to be connected between OSC
IN and GND.
RESET: RESET is an Active High Logic Output. It is the
inverse of RESET.
VBATT : Backup Battery Input. When VCC falls below VBATT ,
auxiliary power connected to VBATT is delivered to VOUT
through PMOS switch, M2. If backup battery or auxiliary
power is not used, VBATT should be connected to GND.
VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1μF capacitor.
VOUT : Voltage Output for Backed-Up Memory. Bypass with
a capacitor of 0.1μF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on-resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
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LTC692/LTC693
PIN FUNCTIONS
WDI: Watchdog Input. WDI is a three level input. Driving
WDI either high or low for longer than the watchdog timeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
BLOCK DIAGRAM
M2
VBATT
VOUT
M1
VCC
CHARGE
PUMP
–
C2
+
BATT ON
LOW LINE
+
C1
–
CE OUT
1.3V
GND
CE IN
–
C3
+
PFI
RESET
OSC IN
OSC
OSC SEL
WDI
PFO
RESET PULSE
GENERATOR
RESET
TRANSITION
DETECTOR
WATCHDOG
TIMER
WDO
LTC692/3 • BD
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LTC692/LTC693
APPLICATIONS INFORMATION
Microprocessor Reset
Battery Switchover
The LTC692/LTC693 use a bandgap voltage reference
and a precision voltage comparator C1 to monitor the
5V supply input on VCC (see Block Diagram). When VCC
falls below the reset voltage threshold, the RESET output
is forced to active low state. The reset voltage threshold
accounts for a 10% variation on VCC, so the RESET output
becomes active low when VCC falls below 4.50V (4.40V
typical). On power-up, the RESET signal is held active low
for a minimum of 140ms after reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize. The reset active time is adjustable on the LTC693.
On power down, the RESET signal remains active low
even with VCC as low as 1V. This capability helps hold the
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. When
VCC rises to 70mV above VBATT, the battery switchover
comparator, C2, connects VOUT to VCC through a charge
pumped NMOS power switch, M1. When VCC falls to 50mV
above VBATT , C2 connects VOUT to VBATT through a PMOS
switch, M2. C2 has typically 20mV of hysteresis to prevent
spurious switching when VCC remains nearly equal to VBATT.
The response time of C2 is approximately 20μs.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at the VCC pin do
not activate the RESET output. Response time is typically
10μs. To help prevent mistriggering due to transient loads,
VCC pin should be bypassed with a 0.1μF capacitor with
the leads trimmed as short as possible.
The LTC693 has two additional outputs: RESET and
LOW LINE. RESET is an active high output and is the
inverse of RESET. LOW LINE is the output of the precision voltage comparator, C1. When VCC falls below the
reset voltage threshold, LOW LINE goes low. LOW LINE
returns high as soon as VCC rises above the reset voltage threshold.
V2
V1
VCC
RESET
t1
During normal operation, the LTC692/LTC693 use a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to VOUT from VCC and has a typical on-resistance
of 5Ω. The VOUT pin should be bypassed with a capacitor of 0.1μF or greater to ensure stability. Use of a larger
bypass capacitor is advantageous for supplying current
to heavy transient loads.
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC – VOUT voltage differential) is desired, the LTC693 should be used. This
product provides BATT ON output to drive the base of the
external PNP transistor (Figure 2). If higher currents are
needed with the LTC692, a high current Schottky diode can
be connected from the VCC pin to the VOUT pin to supply
the extra current.
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
V1
t1
t1 = RESET ACTIVE TIME
LOW LINE
692_3 • F01
Figure 1. Reset Active Time
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LTC692/LTC693
APPLICATIONS INFORMATION
ANY PNP POWER TRANSISTOR
I=
VOUT – VBATT
R
5
3
5V
0.1μF
LTC693
1
3V
R
BATT ON
2
VOUT
VCC
5V
VBATT
GND
4
VOUT
VCC
LTC692
LTC693
0.1μF
0.1μF
0.1μF
VBATT
3V
GND
692_3 • F02
692_3 • F03
Figure 2. Using BATT ON to Drive External PNP Transistor
Figure 3. Charging External Battery Through VOUT
The LTC692/LTC693 are protected for safe area operation
with a short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long
periods of time, thermal shutdown turns the power switch
off until the device cools down. The threshold temperature
for thermal shutdown is approximately 155°C with about
10°C of hysteresis which prevents the device from oscillating in and out of shutdown.
memory backup instead of a battery. The charging resistor
for the rechargeable batteries should be connected to VOUT
since this eliminates the discharge path that exists when
the resistor is connected to VCC (Figure 3).
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
VBATT pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC692/LTC693 use a charge-pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by the
VBATT pin is strictly junction leakage.
A 125Ω PMOS switch connects the VBATT input to VOUT in
battery backup mode. The switch is designed for very low
dropout voltage (input-to-output differential). This feature
is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS
circuitry. The supply current in battery backup mode is
1μA maximum.
The operating voltage at the VBATT pin ranges from 2.0V to
4.0V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short-term
Replacing the Backup Battery
When changing the backup battery with system power on,
spurious resets can occur while the battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge up
the stray capacitance on the VBATT pin. The oscillation cycle
is as follows: When VBATT reaches within 50mV of VCC,
the LTC692/LTC693 switch to battery backup. VOUT pulls
VBATT low and the devices go back to normal operation.
The leakage current then charges up the VBATT pin again
and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from VBATT to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1μA maximum over temperature and the external resistor
required to hold VBATT below VCC is:
R≤
VCC – 50mV
1μA
With VCC = 4.25V, a 3.9M resistor will work. With a 3V
battery, this resistor will draw only 0.77μA from the battery, which is negligible in most cases.
0692fb
10
LTC692/LTC693
APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond VCC due
to the lead inductance (Figure 4).
Table 1. Input and Output Status in Battery Backup Mode
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC.
10Ω
VBATT
3.9M
0.1μF
STATUS
VCC
C2 monitors VCC for active switchover
VOUT
VOUT is connected to VBATT through an internal PMOS switch
VBATT
The supply current is 1μA maximum
BATT ON
Logic high. The open-circuit output voltage is equal to VOUT
PFI
Power failure input is ignored
PFO
Logic low
RESET
Logic low
RESET
Logic high. The open-circuit output voltage is equal to VOUT
LOW LINE Logic low
LTC692
LTC693
WDI
GND
692_3 • F04
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when VCC is at an invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When VCC is 5V, CE OUT
follows CE IN with a typical propagation delay of 20ns.
When VCC falls below the reset voltage threshold or VBATT,
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
WDO
Logic high. The open-circuit output voltage is equal to VOUT
CE IN
Chip Enable input is ignored
CE OUT
Logic high. The open-circuit output voltage is equal to VOUT
OSC IN
OSC IN is ignored
OSC SEL
OSC SEL is ignored
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
V2
V1
Watchdog input is ignored
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
Memory Protection
VCC
SIGNAL
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
CE OUT
VOUT = VBATT
VOUT = VBATT
692_3 • F05
Figure 5. Timing Diagram for CE IN and CE OUT
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11
LTC692/LTC693
APPLICATIONS INFORMATION
VCC
5V
0.1μF
VOUT
VCC
+
10μF
LTC693
0.1μF
CE OUT
VBATT
CE IN
RESET
3V
GND
62512
RAM
CS
20ns PROPAGATION DELAY
FROM DECODER
GND
692_3 • F06
RESET
TO μP
Figure 6. A Typical Nonvolatile CMOS RAM Application
VCC
5V
VOUT
0.1μF
VCC
+
10μF
0.1μF
LTC692
CS
RESET
GND
VBATT
3V
62128
RAM
CS1
CS2
GND
692_3 • F07
Figure 7. Write-Protect for RAM with the LTC692
Power-Fail Warning
The LTC692/LTC693 generate a power failure output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
power failure input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at
the PFI pin falls below 1.3V, several milliseconds before
the 5V supply falls below the maximum reset voltage
threshold of 4.50V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the summing junction at the PFI pin.
⎛ R1 R1⎞
VH = 1.3V ⎜ 1+
+
⎝ R2 R3 ⎟⎠
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
⎛ R1 (5V – 1.3V)R1⎞
VL = 1.3V ⎜ 1+
–
⎝ R2 1.3V(R3 + R4) ⎟⎠
Asssuming R4
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