LTC694-3.3/LTC695-3.3
3.3V Microprocessor
Supervisory Circuits
FEATURES
DESCRIPTION
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The LTC®694-3.3/LTC695-3.3 provide complete 3.3V power
supply monitoring and battery control functions. These
include power-on reset, battery back-up, RAM write protection, power failure warning and watchdog timing. The
devices are pin compatible upgrades of the LTC694/LTC695
that are optimized for 3.3V systems. Operating power
consumption has been reduced to 0.6mW (typical) and
3μW maximum in battery back-up mode. Microprocessor
reset and memory write protection are provided when the
supply falls below 2.9V. The RESET output is guaranteed
to remain logic low with VCC as low as 1V.
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Guaranteed Reset Assertion at VCC = 1V
Pin Compatible with LTC694/LTC695 for 3.3V Systems
200μA Typical Supply Current
Fast (30ns Typ) Onboard Gating of
RAM Chip Enable Signals
SO-8 and S16 Packages
2.90V Precision Voltage Monitor
Power OK/Reset Time Delay: 200ms or Adjustable
Minimum External Component Count
1μA Maximum Standby Current
Voltage Monitor for Power-Fail or
Low-Battery Warning
Thermal Limiting
Performance Specified Over Temperature
The LTC694-3.3/LTC695-3.3 power the active RAMs with
a charge pumped NMOS power switch to achieve low
dropout and low supply current. When primary power is
lost, auxiliary power, connected to the battery input pin,
powers the RAMs in standby through an efficient PMOS
switch.
APPLICATIONS
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3.3V Low Power Systems
Critical μP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
For an early warning of impending power failure, the
LTC694-3.3/LTC695-3.3 provide an internal comparator
with a user-defined threshold. An internal watchdog timer
is also available, which forces the reset pins to active states
when the watchdog input is not toggled prior to a preset
timeout period.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
+
1μF
OUT SENSE
3.3V
VCC
+
100μF
0.1μF
SHDN
GND
LTC695-3.3
VBATT
2.4V
51k
PFI
18k
MICROPROCESSOR RESET, BATTERY BACK-UP,
RAM WRITE PROTECTION, POWER WARNING AND
WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR 3.3V MICROPROCESSOR SYSTEM
VOUT
CE IN
CE OUT
RESET
PFO
GND WDI
POWER TO
μP
CMOS RAM POWER
0.1μF
μP
SYSTEM
DECODER OUTPUT
RAM CS
μP RESET
μP NMI
I/O LINE
100Ω
5
RESET OUTPUT VOLTAGE (V)
LT1129-3.3
VIN
VOUT
VIN ≥ 5V
RESET Output Voltage
vs Supply Voltage
4
3
2
1
0.1μF
694/5-3.3 TA01
0
0
1
3
4
2
SUPPLY VOLTAGE (V)
5
694/5-3.3 TA02
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LTC694-3.3/LTC695-3.3
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Terminal Voltage
VCC.......................................................... –0.3V to 6V
VBATT ...................................................... –0.3V to 6V
All Other Inputs ..................... –0.3V to (VOUT + 0.3V)
Input Current
VCC ..................................................................100mA
VBATT .................................................................25mA
GND ...................................................................10mA
VOUT Output Current ................. Short-Circuit Protected
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC694C-3.3/LTC695C-3.3 ...................... 0°C to 70°C
LTC694I-3.3/LTC695I-3.3 ....................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VBATT
1
16 RESET
VOUT
2
15 RESET
VCC
3
14 WDO
GND
4
13 CE IN
BATT ON
5
12 CE OUT
LOW LINE
6
11 WDI
7
10 PFO
OSC IN
OSC SEL
9
8
16 RESET
VBATT 1
VOUT
VCC 2
GND 3
15 RESET
14 WDO
BATT ON 4
LOW LINE 5
13 CE IN
OSC IN 6
OSC SEL 7
11 WDI
12 CE OUT
10 PFO
9 PFI
8
PFI
SW PACKAGE
16-LEAD PLASTIC WIDE SO
N PACKAGE
16-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W
TJMAX = 110°C, θJA = 130°C/W
TOP VIEW
TOP VIEW
VOUT
1
8
VBATT
VOUT
1
8
VBATT
VCC
2
7
RESET
VCC
2
7
RESET
GND
3
6
WDI
GND
3
6
WDI
PFI 4
5
PFO
PFI
4
5
PFO
N8 PACKAGE
8-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 180°C/W
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LTC694-3.3/LTC695-3.3
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC695CN-3.3#PBF
LTC695CN-3.3#TRPBF
LTC695CN-3.3
16-Lead PDIP
0°C to 70°C
LTC695IN-3.3#PBF
LTC695IN-3.3#TRPBF
LTC695IN-3.3
16-Lead PDIP
–40°C to 85°C
LTC695CSW-3.3#PBF
LTC695CSW-3.3#TRPBF
LTC695CSW-3.3
16-Lead Plastic Wide SO
0°C to 70°C
LTC695ISW-3.3#PBF
LTC695ISW-3.3#TRPBF
LTC695ISW-3.3
16-Lead Plastic Wide SO
–40°C to 85°C
LTC694CN8-3.3#PBF
LTC694CN8-3.3#TRPBF
LTC694CN8-3.3
8-Lead PDIP
0°C to 70°C
LTC694IN8-3.3#PBF
LTC694IN8-3.3#TRPBF
LTC694IN8-3.3
8-Lead PDIP
–40°C to 85°C
LTC694CS8-3.3#PBF
LTC694CS8-3.3#TRPBF
6943
8-Lead Plastic SO
0°C to 70°C
LTC694IS8-3.3#PBF
LTC694IS8-3.3#TRPBF
694I3
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
Consult LTC Marketing for military grade parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PRODUCT SELECTION GUIDE
PINS
RESET
THRESHOLD
(V)
WATCHDOG
TIMER
BATTERY
BACK-UP
POWER-FAIL
WARNING
LTC694-3.3
8
2.90
X
X
X
LTC695-3.3
16
2.90
X
X
X
LTC690
8
4.65
X
X
X
LTC691
16
4.65
X
X
X
LTC694
8
4.65
X
X
X
LTC695
16
4.65
X
X
X
LTC699
8
4.65
X
LTC1232
8
4.37/4.62
X
LTC1235
16
4.65
X
RAM WRITE
PROTECT
PUSH-BUTTON
RESET
CONDITIONAL
BATTERY
BACK-UP
X
X
X
X
X
X
X
X
X
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LTC694-3.3/LTC695-3.3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VBATT = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.50
2.75
V
V
Battery Back-Up Switching
l
l
3.0
1.5
l
VCC – 0.1
VCC – 0.2
VCC – 0.01
VCC – 0.01
V
V
IOUT = 50mA
l
VCC – 0.8
VCC – 0.4
V
VOUT in Battery Back-Up Mode
IOUT = 250μA, VCC < VBATT
l
VBATT – 0.1
VBATT – 0.02
V
Supply Current (Exclude IOUT)
IOUT ≤ 50μA, VCC = 3.6V
Supply Current in Battery Back-Up Mode
VCC = 0V, VBATT = 2V
Operating Voltage Range
VCC
VBATT
VOUT Output Voltage
IOUT = 1mA
Battery Standby Current (+ = Discharge, – = Charge) 3.6V > VCC > VBATT + 0.2V
Battery Switchover Threshold (VCC – VBATT)
l
0.2
0.2
0.6
1.0
mA
mA
l
0.04
0.04
1
5
μA
μA
0.02
0.10
μA
μA
l
–0.02
–0.10
Power-Up
Power-Down
Battery Switchover Hysteresis
BATT ON Output Voltage (Note 4)
ISINK = 800μA
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = VOUT, Sink Current
BATT ON = 0V, Source Current
70
50
mV
mV
20
mV
l
0.3
V
25
mA
μA
3.0
V
l
0.5
25
1
l
2.8
2.9
l
160
140
200
200
240
280
ms
ms
l
1.2
1.0
1.6
1.6
2.0
2.25
sec
sec
l
80
70
100
100
120
140
ms
ms
l
l
4032
960
4097
1025
Clock
Cycles
Reset and Watchdog Timer
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Active Time
Watchdog Timeout Period, Internal Oscillator
40
OSC SEL HIGH, VCC = 3V
Long Period, VCC = 3V
Short Period, VCC = 3V
Watchdog Timeout Period, External Clock (Note 5)
Long Period, VCC = 3V
Short Period, VCC = 3V
Reset Active Time PSRR
Watchdog Timeout Period PSRR, Internal OSC
Short Period
Long Period
Minimum WDI Input Pulse Width
VIL = 0.4V, VIH = 3V
l
RESET Output Voltage at VCC = 1V
_
RESET and LOW LINE Output Voltage (Note 4)
ISINK = 10μA, VCC = 1V
l
ISINK = 400μA, VCC = 2.8V
ISOURCE = 0.1μA, VCC = 3V
l
l
2.3
ISINK = 400μA, VCC = 3V
ISOURCE = 0.1μA, VCC = 2.8V
l
l
2.3
Output Source Current
Output Sink Current
l
1
Logic Low
Logic High
l
l
2.3
WDI = VOUT
WDI = 0V
l
l
–50
RESET and WDO Output Voltage (Note 4)
_
RESET, RESET, WDO, LOW LINE
Output Short-Circuit Current (Note 4)
WDI Input Threshold
WDI Input Current
mV
4
ms/V
2
32
ms/V
ms/V
200
ns
4
3
9
4
–8
200
mV
0.3
V
V
0.3
V
V
25
μA
mA
0.4
V
V
50
μA
μA
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LTC694-3.3/LTC695-3.3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VBATT = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
1.3
1.35
UNITS
Power-Fail Detector
l
PFI Input Threshold
1.25
PFI Input Threshold PSRR
0.3
V
mV/V
PFI Input Current
l
PFO Output Voltage (Note 4)
ISINK = 800μA
ISOURCE = 0.1μA
l
l
2.3
PFO Short-Circuit Source Current (Note 4)
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = VOUT
l
1
PFI Comparator Response Time (Falling)
ΔVIN = –20mV, VOD = 15mV
2
μs
PFI Comparator Response Time (Rising) (Note 4)
ΔVIN = 20mV, VOD = 15mV
with 10kΩ Pull-Up
40
8
μs
μs
±0.01
3
17
±25
nA
0.3
V
V
25
μA
μA
Chip Enable Gating
CE IN Threshold
0.45
VIL
VIH
1.9
CE IN Pull-Up Current (Note 6)
CE OUT Output Voltage
3
ISINK = 800μA
ISOURCE = 400μA
ISOURCE = 1μA, VCC = 0V
l
l
l
CE IN Propagation Delay
CL = 20pF
l
CE OUT Output Short-Circuit Current
Output Source Current
Output Sink Current
μA
0.3
V
V
V
50
ns
VOUT – 0.50
VOUT – 0.05
30
V
V
15
20
mA
mA
OSC IN Input Current (Note 6)
±2
μA
OSC SEL Input Pull-Up Current (Note 6)
5
μA
Oscillator
OSC IN Frequency Range
OSC SEL = 0V
OSC SEL = 0V, CA = 47pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts,
_ consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3μA. However, external pullup resistors may be used when higher speed is required.
l
0
125
4
kHz
kHz
Note 5: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer. Variation in the timeout
period is caused by phase errors which occur when the oscillator divides
the external clock by 64. The resulting variation in the timeout period is 64
plus one clock of jitter.
Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.
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LTC694-3.3/LTC695-3.3
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs Load Current
2.40
VCC = 3.3V
VBATT = 2.4V
TA = 25°C
2.39
OUTPUT VOLTAGE (V)
3.20
SLOPE = 4.6Ω
3.15
3.10
2.38
SLOPE = 90Ω
2.37
2.36
3.05
2.35
10
0
30
40
20
LOAD CURRENT (mA)
100
0
50
300
400
200
LOAD CURRENT (μA)
1.304
1.302
1.300
1.298
500
1.294
–50 –25
Power-Fail Comparator
Response Time
PFO OUTPUT VOLTAGE (V)
2.5
2.0
VPFI
1.5
1.3V
+
PFO
30pF
–
1.0
0.5
0
3.0
3.5
VCC = 3.3V
TA = 25°C
2.5
2.0
1.5
VPFI
+
1.0
1.3V
–
PFO
30pF
0.5
VPFI = 20mV STEP
0
1
2
3 4 5
TIME (μs)
1.315V
1.295V
6
7
8
9
2.5
2.0
3.3V
1.5
1.0
0.5
1.315V
1.295V
VPFI = 20mV STEP
0
20 40
VPFI
+
1.3V
–
0
2
4
8 10 12 14 16 18
TIME (μs)
694/5-3.3 G06
RESET Output Voltage
vs Supply Voltage
Reset Voltage Threshold
vs Temperature
5
2.90
VCC = 3.3V
PFO
30pF
6
694/5-3.3 G05
Reset Active Time
vs Temperature
10k
VPFI = 20mV STEP
60 80 100 120 140 160 180
TIME (μs)
694/5-3.3 G04
VCC = 3.3V
200
190
180
170
160
50
25
75
0
TEMPERATURE (°C)
100
125
694/5-3.3 G07
2.89
RESET OUTPUT VOLTAGE (V)
RESET VOLTAGE THRESHOLD (V)
210
150
–50 –25
VCC = 3.3V
TA = 25°C
3.0
0
0
1.305V
1.285V
125
694/5-3.3 G03
3.5
3.5
3.0
100
Power-Fail Comparator
Response Time with Pull-Up
Resistor
Power-Fail Comparator
Response Time
VCC = 3.3V
TA = 25°C
50
25
75
0
TEMPERATURE (°C)
694/5-3.3 G02
694/5-3.3 G01
PFO OUTPUT VOLTAGE (V)
1.306
1.296
3.00
RESET ACTIVE TIME (ms)
VCC = 3.3V
1.308
PFO OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.25
1.310
VCC = 0V
VBATT = 2.4V
TA = 25°C
PFI INPUT THRESHOLD (V)
3.30
220
Power Failure Input Threshold
vs Temperature
Output Voltage vs Load Current
2.88
2.87
2.86
2.85
2.84
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
694/5-3.3 G08
4
3
2
1
0
0
1
3
4
2
SUPPLY VOLTAGE (V)
5
694/5-3.3 G09
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LTC694-3.3/LTC695-3.3
PIN FUNCTIONS
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 25mA and can provide
base drive for an external PNP transistor to increase the
output current above the 50mA rating of VOUT. BATT ON
goes high when VOUT is internally switched to VBATT.
_
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See the Applications Information section
and Figure 5 for additional information.
_
CE OUT: Logic Output on the Chip Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
GND: Ground Pin.
_
_
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the VCC input. When VCC
falls below
the reset voltage threshold (2.90V typically),
_
LOW LINE goes low. As _soon as VCC rises above the reset
voltage
_ threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when VCC drops below VBATT (see
Table 1).
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced
low. In this configuration the nominal reset active time and
watchdog timeout period are determined by the number
of clocks or set by the formula (see the Applications Information section). When OSC SEL is high or floating, the
internal oscillator is enabled and the reset active time is
fixed at 200ms typical for the LTC695-3.3. OSC IN selects
between the 1.6 seconds and 100ms typical watchdog
timeout periods. In both cases, the timeout period immediately after a reset is 1.6 seconds typical.
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low,
allows OSC IN to be driven from an external clock signal
or an external capacitor can be connected between OSC
IN and GND.
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or VOUT
when C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Active High Logic Output. It is the inverse of
RESET.
RESET: Logic Output for μP Reset Control. Whenever VCC
falls below either the reset voltage threshold (2.90V, typically) or VBATT, RESET goes active low. After VCC returns
to 3.3V, the reset pulse generator forces RESET to remain
active low for a minimum of 140ms. When the watchdog
timer is enabled but not serviced prior to a preset timeout
period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for every preset timeout
period (see Figure 11). The reset active time is adjustable
on the LTC695-3.3. An external push-button reset can be
used in connection with the RESET output. See Push-Button Reset in the Applications Information section.
VBATT: Back-Up Battery Input. When VCC falls below VBATT,
auxiliary power connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
VCC : 3.3V Supply Input. The VCC pin should be bypassed
with a 0.1μF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1μF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
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LTC694-3.3/LTC695-3.3
PIN FUNCTIONS
WDI: Watchdog Input. WDI is a three-level input. Driving
WDI either high or low for longer than the watchdog timeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high_ whenever
there is a transition on the WDI pin, or LOW LINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
BLOCK DIAGRAM
M2
VBATT
VOUT
M1
VCC
CHARGE
PUMP
–
+
BATT ON
C2
LOW LINE
+
C1
–
CE OUT
1.3V
CE IN
GND
–
C3
+
PFI
RESET
OSC IN
OSC
OSC SEL
WDI
PFO
TRANSITION
DETECTOR
RESET PULSE
GENERATOR
WATCHDOG
TIMER
RESET
WDO
694/5-3.3 BD
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LTC694-3.3/LTC695-3.3
APPLICATIONS INFORMATION
Microprocessor Reset
Battery Switchover
The LTC694-3.3/LTC695-3.3 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the
3.3V supply input on VCC (see the Block Diagram). When
VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold
accounts for a 10% variation on VCC, so the RESET output
becomes active low when VCC falls below 3.0V (2.9V typical). On power-up, the RESET signal is held active low for a
minimum of 140ms after reset voltage threshold is reached
to allow the power supply and microprocessor to stabilize.
The reset active time is adjustable on the LTC695-3.3.
On power-down, the RESET signal remains active low
even with VCC as low as 1V. This capability helps hold the
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. When
VCC rises to 70mV above VBATT, the battery switchover
comparator, C2, connects VOUT to VCC through a charge
pumped NMOS power switch, M1. When VCC falls to 50mV
above VBATT, C2 connects VOUT to VBATT through a PMOS
switch, M2. C2 has typically 20mV of hysteresis to prevent
spurious switching when VCC remains nearly equal to VBATT.
The response time of C2 is approximately 20μs.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at VCC pin do
not activate the RESET output. Response time is typically
10ms. To help prevent mistriggering due to transient loads,
the VCC pin should be bypassed with a 0.1μF capacitor
with the leads trimmed as short as possible.
The LTC695-3.3
has two additional outputs: RESET and
_
LOW LINE. RESET
_ is an active high output and is the inverse
of RESET. LOW LINE is the output of the precision voltage
comparator C1._ When VCC falls below
_ the reset voltage
threshold, LOW LINE goes low. LOW LINE returns high as
soon as VCC rises above the reset voltage threshold.
V2
V1
VCC
RESET
t1
During normal operation, the LTC694-3.3/LTC695-3.3 use
a charge-pumped NMOS power switch to achieve low
dropout and low supply current. This power switch can
deliver up to 50mA to VOUT from VCC and has a typical on
resistance of 5Ω. The VOUT pin should be bypassed with
a capacitor of 0.1μF or greater to ensure stability. Use of
a larger bypass capacitor is advantageous for supplying
current to heavy transient loads.
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC – VOUT voltage differential) is desired, the LTC695-3.3 should be used. This
product provides BATT ON output to drive the base of
an external PNP transistor (Figure 2). If higher currents
are needed with the LTC694-3.3, a high current Schottky
diode can be connected from the VCC pin to the VOUT pin
to supply the extra current.
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
V1
t1
t1 = RESET ACTIVE TIME
LOW LINE
694/5-3.3 F01
Figure 1. Reset Active Time
69453fb
9
LTC694-3.3/LTC695-3.3
APPLICATIONS INFORMATION
ANY PNP POWER TRANSISTOR
I=
VOUT – VBATT
R
R
5
3
3.3V
0.1μF
1
2.4V
3.3V
BATT ON
2
VOUT
VCC
LTC695-3.3
VCC
VOUT
0.1μF
0.1μF
LTC694-3.3
LTC695-3.3
0.1μF
VBATT
GND
4
2.4V
VBATT
GND
694/5-3.3 F02
694/5-3.3 F03
Figure 2. Using BATT ON to Drive External PNP Transistor
Figure 3. Charging External Battery Through VOUT
The LTC694-3.3/LTC695-3.3 are protected for safe area
operation with short-circuit limit. Output current is limited
to approximately 200mA. If the device is overloaded for
a long period of time, thermal shutdown turns the power
switch off until the device cools down. The threshold
temperature for thermal shutdown is approximately 155°C
with about 10°C of hysteresis which prevents the device
from oscillating in and out of shutdown.
The operating voltage at the VBATT pin ranges from 1.5V
to 2.75V. The charging resistor for rechargeable batteries
should be connected to VOUT since this eliminates the
discharge path that exists when the resistor is connected
to VCC (Figure 3).
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
VBATT pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC694-3.3/LTC695-3.3 use a charge-pumped NMOS
power switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by
VBATT pin is strictly junction leakage.
A 125Ω PMOS switch connects the VBATT input to VOUT
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This
feature is advantageous for low current applications such
as battery back-up in CMOS RAM and other low power
CMOS circuitry. The supply current in battery back-up
mode is 1μA maximum.
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while the battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge
up the stray capacitance on the VBATT pin. The oscillation
cycle is as follows: When VBATT reaches within 50mV of
VCC, the LTC694-3.3/LTC695-3.3 switch to battery backup.
VOUT pulls VBATT low and the device goes back to normal
operation. The leakage current then charges up the VBATT
pin again and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from VBATT to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1μA maximum over temperature so the external resistor
required to hold VBATT below VCC is:
R≤
VCC – 50mV
1µA
With VCC = 3V, a 2.7M resistor will work. With a 2V battery,
this resistor will draw only 0.7μA from the battery, which
is negligible in most cases.
69453fb
10
LTC694-3.3/LTC695-3.3
APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond VCC due
to the lead inductance (Figure 4).
10Ω
VBATT
2.7M
0.1μF
LTC694-3.3
LTC695-3.3
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC.
GND
694/5-3.3 F04
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the VBATT Pin to Ground
While the Battery is Removed, Eliminating Spurious Resets
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
STATUS
VCC
C2 monitors VCC for active switchover.
VOUT
VOUT is connected to VBATT through an internal PMOS switch.
VBATT
The supply current is 1μA maximum.
BATT ON
Logic high. The open-circuit output voltage is equal to VOUT.
PFI
Power failure input is ignored.
PFO
Logic low.
RESET
Logic low.
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level.
_ Two
additional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT
follows CE IN with a typical propagation delay of 30ns.
When VCC falls below the reset voltage threshold or VBATT,
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
RESET
Logic high. The open-circuit output voltage is equal to VOUT.
_
LOW LINE Logic low.
WDI
Watchdog input is ignored.
WDO
CE IN
Logic high. The open-circuit output voltage is equal to VOUT.
_
Chip Enable input is ignored.
CE OUT
Logic high. The open-circuit output voltage is equal to VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
VCC
V2
V1
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
VOUT = VBATT
CE OUT
VOUT = VBATT
694/5-3.3 F05
Figure 5. Timing Diagram for CE IN and CE OUT
69453fb
11
LTC694-3.3/LTC695-3.3
APPLICATIONS INFORMATION
VOUT
VCC
3.3V
0.1μF
VCC
+
0.1μF
10μF
LTC695-3.3
62512
RAM
CE OUT
VBATT
2.4V
GND
CS
30ns PROPAGATION DELAY
FROM DECODER
CE IN
RESET
GND
Memory protection can also be achieved with the LTC6943.3 by using RESET as shown in Figure 7.
RESET
TO μP
694/5-3.3 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
VCC
3.3V
0.1μF
VOUT
VCC
+
0.1μF
10μF
62128
RAM
CS1
LTC694-3.3
CS
RESET
GND
VBATT
2.4V
CS2
GND
694/5-3.3 F07
Figure 7. Write Protect for RAM with LTC694-3.3
LT1129-3.3
VIN
VOUT
VIN ≥ 5V
+
10μF
R1
51k
3.3V
VCC
+
OUT SENSE
SHDN
ADJ
100μF
R3
200k
0.1μF
R4
10k
LTC694-3.3
LTC695-3.3
PFO
PFI
R2
16k
GND
TO μP
694/5-3.3 F08
Figure 8. Monitoring Unregulated DC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
VIN r 6.5V
+
10μF
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
LT1129-3.3
VIN
VOUT
OUT SENSE
SHDN
ADJ
10μF
+
3.3V
R4
R1
10k
27k
R3
2.7M
R2
16k
Power-Fail Warning
The LTC694-3.3/LTC695-3.3 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
power failure input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 3.3V output. The
voltage divider ratio can be chosen such that the voltage
at the PFI pin falls below 1.3V several milliseconds before
the 3.3V supply falls below the maximum reset voltage
threshold 3.0V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the summing junction at the PFI pin.
⎛ R1 R1⎞
VH =1.3V ⎜ 1+ + ⎟
⎝ R2 R3 ⎠
0.1μF
VCC
LTC694-3.3
LTC695-3.3
PFO
PFI GND
694/5-3.3 F09
TO μP
R5
5k
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
⎛ R1 (3.3V ±1.3V)R1⎞
VL =1.3V ⎜ 1+
–
⎝ R2 1.3V(R3 + R4) ⎟⎠
Assuming R4
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