LTC7817
40V, Low IQ, 3MHz,
Triple Output Buck/Buck/Boost Synchronous Controller
FEATURES
Dual Buck Plus Single Boost Synchronous Controllers
n Low Operating I :
Q
14μA (14V to 3.3V, Channel 1 On)
n Outputs Remain in Regulation Through Cold Crank
Down to 1V Input Supply Voltage
n Wide Bias Input Voltage Range: 4.5V to 40V
n Buck and Boost Output Voltages up to 40V
n R
SENSE or DCR Current Sensing
n PassThru™ Operation: 100% Duty Cycle for
Boost Synchronous MOSFET
n Programmable Fixed Frequency (100kHz to 3MHz)
n Phase-Lockable Frequency (100kHz to 3MHz)
n Selectable Continuous, Pulse-Skipping, or Low
Ripple Burst Mode Operation at Light Loads
n Very Low Buck Dropout Operation: 99% Duty Cycle
n Low Shutdown I : 1.5μA
Q
n Small 38-Lead 5mm × 7mm QFN Package
n AEC-Q100 Qualified for Automotive Applications
n
APPLICATIONS
DESCRIPTION
The LTC®7817 is a high performance triple output (buck/
buck/boost) synchronous DC/DC switching regulator controller that drives all N-channel power MOSFET stages.
Its constant frequency current mode architecture allows
a phase-lockable switching frequency of up to 3MHz.
The LTC7817 operates from a wide 4.5V to 40V input
supply range. When biased from the output of the boost
converter or another auxiliary supply, the LTC7817 can
operate from an input supply as low as 1V after start-up.
The very low no-load quiescent current extends operating
run time in battery powered systems. OPTI-LOOP® compensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC7817 features a precision 0.8V reference for the
bucks, 1.2V reference for the boost and a power good
output indicator.
The LTC7817 synchronous boost PassThru capability
minimizes losses in automotive start-stop applications.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.
Automotive and Transportation
Industrial
n Military/Avionics
n
n
TYPICAL APPLICATION
VOUT3
REGULATED TO 10V
WHEN VIN < 10V
FOLLOWS VIN
WHEN VIN > 10V
VIN
1V TO 38V
STARTUP
ABOVE 5V
VFB3
22µF
150µF
VBIAS
TG3
1.5mΩ
1.4µH
0.1µF
BOOST1
0.1µF
SW3
LTC7817
VOUT3
2mΩ
SENSE3–
SENSE3+
RUN1,2,3
22µF
BG1
TRACK/SS1,2,3
INTVCC
VOUT1
3.3V
12A
330µF
VBATT
VOUT3
VOLTAGE
2V/DIV
68.1k
VOUT2
TG2
VOUT1
BOOST2
VPRG3
0.1µF
1.8µH
3mΩ
SW2
0.1µF
VOUT3
210k
SENSE1+
SENSE1–
VFB1
ITH1,2,3
4.7µF
0.9µH
SW1
BG3
150µF
LTC7817 Response to a Cold
LTC7818 Response to a Cold Crank
Crank
Automotive Waveform
Automotive Waveform
TG1
BOOST3
10µF
BG2
VOUT2
5V
10A
330µF
0V
TIME (10ms/DIV)
7817 TA01b
BOOST1,2,3
SENSE2+
SENSE2–
VFB2
SGND EXTVCC
357k
PLLIN/MODE
FREQ
PGND
VOUT2
68.1k
7817 TA01a
Rev A
Document Feedback
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1
LTC7817
TG1
PGOOD1
TRACK/SS1
ITH1
VFB1
SENSE1+
TOP VIEW
38 37 36 35 34 33 32
31 SW1
FREQ 1
30 BOOST1
PLLIN/MODE 2
SS3 3
29 BG1
SENSE3+ 4
28 SW3
SENSE3– 5
27 TG3
VFB3 6
26 BOOST3
39
PGND
ITH3 7
25 BG3
SGND 8
24 VBIAS
RUN1 9
23 EXTVCC
RUN2 10
22 INTVCC
RUN3 11
21 BG2
SENSE2– 12
20 BOOST2
SW2
TG2
VPRG3
TRACK/SS2
ITH2
13 14 15 16 17 18 19
VFB2
Bias Input Supply Voltage (VBIAS)............... –0.3V to 40V
BOOST1, BOOST2, BOOST3........................ –0.3V to 46V
Switch Voltage (SW1, SW2, SW3)................. –5V to 40V
RUN1, RUN2, RUN3 Voltages...................... –0.3V to 40V
SENSE1+, SENSE1– Voltages....................... –0.3V to 40V
SENSE2+, SENSE2– Voltages...................... –0.3V to 40V
SENSE3+, SENSE3– Voltages...................... –0.3V to 40V
EXTVCC Voltage.......................................... –0.3V to 30V
INTVCC, (BOOST1-SW1),
(BOOST2-SW2), (BOOST3-SW3).............. –0.3V to 6V
TRACK/SS1, TRACK/SS2, SS3 Voltages....... –0.3V to 6V
ITH1, ITH2, ITH3 Voltages............................ –0.3V to 2V
VFB3 Voltage............................................... –0.3V to 40V
VFB1, VFB2, PLLIN/MODE Voltages................ –0.3V to 6V
VPRG3, FREQ, PGOOD1 Voltages................. –0.3V to 6V
BG1, BG2, BG3, TG1, TG2, TG3........................... (Note 9)
Operating Junction Temperature Range (Notes 2,8)
LTC7817E, LTC7817I........................... –40°C to 125°C
LTC7817J, LTC7817H.......................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
SENSE1–
(Note 1)
SENSE2+
ABSOLUTE MAXIMUM RATINGS
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34.7°C/W
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7817EUHF#PBF
LTC7817EUHF#TRPBF
7817
38-Lead (5mm x 7mm) Plastic QFN
–40°C to 125°C
LTC7817IUHF#WPBF
LTC7817IUHF#WTRPBF
7817
38-Lead (5mm x 7mm) Plastic QFN
–40°C to 125°C
LTC7817JUHF#WPBF
LTC7817JUHF#WTRPBF
7817
38-Lead (5mm x 7mm) Plastic QFN
–40°C to 150°C
LTC7817HUHF#WPBF
LTC7817HUHF#WTRPBF
7817
38-Lead (5mm x 7mm) Plastic QFN
–40°C to 150°C
AUTOMOTIVE PRODUCTS**
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
2
Rev A
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LTC7817
ELECTRICAL CHARACTERISTICS
The l indicates specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (VBIAS, VIN)
VBIAS
Bias Input Supply Operating Voltage Range
VIN
Boost Converter Input Supply Operating
Range
VBIAS ≥ 4.5V
4.5
40
V
1
40
V
Front Page Circuit, 14V to 3.3V, No Load,
RUN2,3 = 0V
14
µA
Controller Operation
VOUT1,2
Buck Output Voltage Operating Range
VOUT3
Boost Output Voltage Operating Range
VFB1,2
Buck Regulated Feedback Voltage
VFB3
Boost Regulated Feedback Voltage
0.8
(Note 4) VBIAS = 4.5V to 40V,
ITH1,2 Voltage = 0.6V to 1.2V
0ºC to 85ºC, All Grades
(Note 4) VBIAS = 4.5V to 40V,
ITH3 Voltage = 0.6V to 1.2V,
VPRG3 = FLOAT
VPRG3 = 0V
VPRG3 = INTVCC
l
l
l
l
0.788
0.792
1.177
7.81
9.77
Buck Feedback Current
gm1,2,3
VSENSE(MAX)
Boost Feedback Current
VPRG3 = FLOAT
RUN3 = 0V, VPRG3 = 0V or INTVCC
RUN3 = 2V, VPRG3 = 0V or INTVCC
Buck Feedback Overvoltage Protection
Threshold
Measured at VFB1,2 Relative to
Regulated VFB1,2
Transconductance Amplifier gm
(Note 4) ITH1,2,3=1.2V, Sink/Source=5μA
Maximum Current Sense Threshold
VFB1,2 = 0.7V, VSENSE1,2– = 3.3V
VFB3 = 1.1V, VSENSE3+ = 12V
VSENSE1,2– = 3.3V
VSENSE1,2+ = 3.3V
VSENSE3– = 12V
VSENSE1– ≤ 2.7V
3.2V ≤ VSENSE1– < INTVCC – 0.5V
VSENSE1– > INTVCC + 0.5V
VSENSE2– = 3.3V
VSENSE2– > INTVCC + 0.5V
VSENSE3+ = 3.3V
VSENSE3+ > INTVCC + 0.5V
Matching for Channels 1 & 2
ISENSE1,2+
ISENSE3–
SENSE1,2+ Pin Current
ISENSE1–
SENSE1– Pin Current
ISENSE2–
SENSE2 – Pin Current
ISENSE3+
SENSE3+ Pin Current
SENSE3– Pin Current
Soft-Start Charge Current
VTRACK/SS1,2 = 0V, VSS3 = 0
RUN Pin ON Threshold
VRUN1,2,3 Rising
RUN Pin Hysteresis
VRUN1,2,3 Falling
7
40
V
40
V
0.800
0.800
0.812
0.808
V
V
1.195
8.00
10.0
1.213
8.13
10.17
V
V
V
±5
±50
nA
±5
±5
1
±50
±50
nA
nA
µA
10
13
%
1.8
l
mmho
45
50
55
mV
–3.5
0
3.5
mV
±1
µA
±1
µA
2
40
660
620
660
l
µA
µA
µA
±2
µA
µA
±2
µA
µA
10
12.5
15
µA
1.15
1.20
1.25
V
100
mV
Rev A
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3
LTC7817
ELECTRICAL
CHARACTERISTICS
The
l indicates specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Supply Current (Note 5)
VBIAS Shutdown Current
RUN1, 2, 3 = 0V
VBIAS Sleep Mode Current
VSENSE1– < 3.2V, EXTVCC = 0V
1.5
µA
One Channel On
All Channels On
15
18
24
30
µA
µA
Sleep Mode Current (Note 3)
Only Channel 1 On
VSENSE1– ≥ 3.2V
VBIAS Current, EXTVCC = 0V
VBIAS Current, EXTVCC = 4.8V
EXTVCC Current, EXTVCC ≥ 4.8V
SENSE1– Current
5
1
5
10
9
4
10
18
µA
µA
µA
µA
Sleep Mode Current (Note 3)
All Channels On
VSENSE1– ≥ 3.2V, EXTVCC ≥4.8V
VBIAS Current
EXTVCC Current
SENSE1– Current
1
8
16
4
14
26
µA
µA
µA
Pulse-Skipping or Forced Continuous Mode
VBIAS or EXTVCC Current (Note 3)
One Channel On
All Channels On
1.5
3
mA
mA
TG or BG On-Resistance
Pull-up
Pull-down
2.0
1.0
Ω
Ω
TG or BG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
TG Off to BG On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
Bucks (Channels 1, 2)
Boost (Channel 3)
15
15
ns
ns
BG Off to TG On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
Bucks (Channels 1, 2)
Boost (Channel 3)
15
15
ns
ns
tON(MIN)1,2
Buck TG Minimum On-Time
(Note 7)
40
ns
tON(MIN)3
Boost BG Minimum On-Time
(Note 7)
80
ns
Maximum Duty Factor for TG
Bucks (Channels 1,2), FREQ = 0V
Boost (Channel 3) in Overvoltage
99
100
%
%
100
93
%
%
50
µA
Gate Drivers
Maximum Duty Factor for BG
Bucks (Channels 1,2) in Overvoltage
Boost (Channel 3), FREQ = 0V
BOOST3 Charge Pump Available
Output Current
VBOOST3 = 16V, VSW3 = 12V, FREQ = 0V,
Forced Continuous Mode
98
20
INTVCC Low Dropout (LDO) Linear Regulator
INTVCC Regulation Point
4.9
INTVCC Load Regulation
ICC = 0mA to 100mA, VBIAS ≥ 6V
ICC = 0mA to 100mA, VEXTVCC ≥ 6V
EXTVCC LDO Switchover Voltage
EXTVCC Rising
4.5
EXTVCC Switchover Hysteresis
UVLO
4
Undervoltage Lockout
5.1
5.3
V
1.2
1.2
2
2
%
%
4.7
4.8
V
250
INTVCC Rising
INTVCC Falling
l
l
4.10
3.75
4.20
3.90
mV
4.35
4.00
V
V
Rev A
For more information www.analog.com
LTC7817
ELECTRICAL
CHARACTERISTICS
The
l indicates specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VFREQ = 0V, PLLIN/MODE = DC Voltage
330
380
430
kHz
2.0
2.25
2.5
MHz
450
100
500
3
550
kHz
kHz
MHz
3
MHz
Oscillator and Phase-Locked Loop
fOSC
Low Fixed Frequency
High Fixed Frequency
VFREQ = INTVCC, PLLIN/MODE = DC Voltage
Programmable Frequency
RFREQ = 374kΩ, PLLIN/MODE = DC Voltage
RFREQ = 75kΩ, PLLIN/MODE = DC Voltage
RFREQ = 12kΩ, PLLIN/MODE = DC Voltage
Synchronizable Frequency Range
PLLIN/MODE = External Clock
PLLIN Input High Level
PLLIN Input Low Level
l
l
0.1
l
l
2.2
0.5
V
V
0.2
0.4
V
PGOOD1 Output
PGOOD1 Voltage Low
IPGOOD1 = 2mA
PGOOD1 Leakage Current
VPGOOD1 = 5V
±1
µA
PGOOD1 Trip Level
VFB1 Relative to Set Regulation Point
VFB1 Rising
Hysteresis
7
10
2.5
13
%
%
VFB1 Falling
Hysteresis
–13
–10
2.5
–7
%
%
PGOOD1 Delay for Reporting a Fault
25
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7817 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC7817E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7817I is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC7817J is guaranteed over the –40°C to 150°C
operating junction temperature range, and the LTC7817H is guaranteed
over the –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according
to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package
thermal impedance.
Note 3: When SENSE1– ≥ 3.2V or EXTVCC ≥ 4.8V, VBIAS supply current is
transferred to these pins to reduce the total input supply quiescent current.
SENSE1– bias current is reflected to the buck channel 1 input supply (VIN1)
by the formula IVIN1 = ISENSE1– • VOUT1/(VIN1 • η), where η is the efficiency.
EXTVCC bias current is similarly reflected to a buck channel input supply
µs
when biased by a buck channel output. To minimize input supply current,
select channel 1 to be the lowest output voltage greater than 3.2V and
connect EXTVCC to the lowest output voltage greater than 4.8V.
Note 4: The LTC7817 is tested in a feedback loop that servos VITH1,2,3
to a specified voltage and measures the resultant VFB1,2,3. The
specifications at 0°C and 85°C are not tested in production and are
assured by design, characterization and correlation to production testing
at other temperatures (125°C for the LTC7817E/LTC7817I, 150°C for the
LTC7817J/LTC7817H)
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current > 40% of IL(MAX) (See Minimum On-Time
Considerations in the Applications Information section).
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 9: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Rev A
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5
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
BURST EFFICIENCY
90
PULSE–SKIPPING
EFFICIENCY
FCM EFFICIENCY
1
60
FCM LOSS
50
40 PULSE–SKIPPING
LOSS
30
0.1
BURST
LOSS
VIN = 10V 0.01
VOUT = 5V
20
10
0
0.0001
FIGURE 10 CIRCUIT
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
0.001
Efficiency
InputVoltage
Voltage
(Buck)
Efficiency vsvsInput
(Buck)
VIN = 10V
VOUT = 5V
10
EFFICIENCY
80
1
0.1
70
POWER LOSS
0.01
60
50
40
0.0001
100
100
0.001
fSW=380kHz (FIGURE 10)
fSW=2.25MHz (FIGURE 14)
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
95
POWER LOSS (W)
70
90
10
POWER LOSS (W)
EFFICIENCY (%)
80
100
100
EFFICIENCY (%)
100
Efficiency
andPower
Power
Loss
Efficiency and
Loss
vs
OutputCurrent
Current(Buck)
(Buck)
vs Output
EFFICIENCY (%)
Efficiencyand
andPower
Power
Loss
Efficiency
Loss
vsOutput
OutputCurrent
Current
(Buck)
vs
(Buck)
10
0.0001
90
85 V = 10V
IN
VOUT = 5V
ILOAD = 4A
80
fSW = 380kHz (FIGURE 10)
fSW = 2.25MHz (FIGURE 14)
75
4
12
20
28
INPUT VOLTAGE (V)
7817 G03
7817 G02
7817 G01
Load Step (Buck)
Burst Mode Operation
Load Step (Buck)
Pulse-Skipping
Pulse–SkippingMode
Mode
LoadStep
Step(Buck)
(Buck)
Load
ForcedContinuous
ContinuousMode
Mode
Forced
VOUT
200mV/DIV
VOUT
200mV/DIV
VOUT
200mV/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
50µs/DIV
7817 G04
50µs/DIV
36
7817 G05
50µs/DIV
7817 G06
VIN = 10V
VOUT = 5V
300mA TO 6A LOAD STEP
FIGURE 10 CIRCUIT
VIN = 10V
VOUT = 5V
300mA TO 6A LOAD STEP
FIGURE 10 CIRCUIT
VIN = 10V
VOUT = 5V
300mA TO 6A LOAD STEP
FIGURE 10 CIRCUIT
Inductor Current at Light Load
(Buck)
Start-Up
Soft Start–Up
Buck Regulated Feedback Voltage
Voltage
vs Temperature
vs Temperature
FORCED
CONTINUOUS
MODE
VOLTAGE
RUN1,2
5V/DIV
BURST MODE
OPERATION
2A/DIV
PULSE
SKIPPING
MODE
VOUT2
1V/DIV
VOUT1
1V/DIV
4µs/DIV
VIN = 10V
VOUT = 5V
NO LOAD
FIGURE 10 CIRCUIT
7817 G07
1ms/DIV
VIN = 10V
FIGURE 10 CIRCUIT
7817 G08
REGULATED FEEDBACK VOLTAGE (mV)
808
806
804
802
800
798
796
794
792
–55
–25
5
35
65
95
TEMPERATURE (oC)
125
155
7817 G09
6
Rev A
For more information www.analog.com
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiencyand
andPower
Power
Loss
Efficiency
Loss
vs Output
OutputCurrent
Current(Boost)
(Boost)
vs
100
100
BURST EFFICIENCY
90
10
VIN = 8V
50
FCM LOSS
1
40
VIN = 5V 0.01
VOUT = 10V
10
0
0.0001
0.1
BURST
LOSS
30 PULSE
SKIPPING
20 LOSS
FIGURE 10 CIRCUIT
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
0.001
96
VIN = 5V
85
80
75
ILOAD = 2A
94
ILOAD = 4A
92
90
88
70
65
60
0.0001
FIGURE 10 CIRCUIT
BURST MODE OPERATION
VOUT = 10V
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
7817 G10
86
84
10
0
2
4
6
INPUT VOLTAGE (V)
8
Load Step
Step (Boost)
(Boost)
Load
Pulse-Skipping Mode
Pulse–Skipping
Load
Load Step
Step (Boost)
(Boost)
Forced Continuous Mode
VOUT3
500mV/DIV
VOUT3
500mV/DIV
VOUT3
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
LOAD
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
7817 G13
10
7817 G12
7817 G11
Load
Load Step
Step (Boost)
(Boost)
Burst Mode Operation
100µs/DIV
FIGURE 10 CIRCUIT
PULSE–SKIPPING MODE
VOUT = 10V
98
EFFICIENCY (%)
FCM EFFICIENCY
POWER LOSS (W)
60
90
EFFICIENCY (%)
PULSE–SKIPPING
EFFICIENCY
70
Efficiency
InputVoltage
Voltage
(Boost)
Efficiency vsvsInput
(Boost)
100
100
95
80
EFFICIENCY (%)
Efficiency
Efficiency
vs Output
OutputCurrent
Current
(Boost)
vs
(Boost)
LOAD
CURRENT
5A/DIV
100µs/DIV
7817 G14
100µs/DIV
VIN = 5V
VOUT = 10V
300mA TO 3.3A LOAD STEP
FIGURE 10 CIRCUIT
VIN = 5V
VOUT = 10V
300mA TO 3.3A LOAD STEP
FIGURE 10 CIRCUIT
VIN = 5V
VOUT = 10V
300mA TO 3.3A LOAD STEP
FIGURE 10 CIRCUIT
Inductor Current at Light Load
(Boost)
Start–Up (Boost)
(Boost)
Soft Start-Up
Boost Regulated Feedback
Voltage vs Temperature
7817 G15
FORCED
CONTINUOUS
MODE
RUN3
5V/DIV
BURST MODE
OPERATION
5A/DIV
VOUT3
2V/DIV
PULSE
SKIPPING
MODE
4µs/DIV
VIN = 5V
VOUT = 10V
NO LOAD
FIGURE 10 CIRCUIT
7817 G16
GND
FIGURE 10 CIRCUIT
VIN = 5V
2ms/DIV
VIN = 5V
FIGURE 10 CIRCUIT
7817 G17
REGULATED FEEDBACK VOLTAGE (V)
1.207
1.204
1.201
1.198
1.195
1.192
1.189
1.186
1.183
–55
–25
5
35
65
95
TEMPERATURE (oC)
125
155
7817 G18
Rev A
For more information www.analog.com
7
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
800
30
20
10
0
–10
600
SENSE2– OR SENSE3+ CURRENT
500
400
300
200
–20
–30
SENSE1– CURRENT
700
100
0
0.2
0.4
0.6 0.8 1.0
ITH VOLTAGE (V)
1.2
0
1.4
MODE = INTVCC
0
5
10
15 20 25 30
SENSE VOLTAGE (V)
35
7817 G19
60
40
30
20
10
400
300
200
SENSE1– = INTVCC–0.5V
100
CHARGE PUMP CURRENT (μA)
CHANGE IN FREQUENCY (%)
2
0
–2
–4
–25
5
35
65
95
TEMPERATURE (oC)
155
7817 G25
SENSE = 3.3V
125
155
SENSE = 0V
–1.0
–55
–25
125
155
7817 G24
80
BOOST3–SW3 = 4V
90 FREQ = 0V
60
50
40
30
150°C
–55°C
25°C
1000 1500 2000
FREQUENCY (kHz)
5
35
65
95
TEMPERATURE (oC)
BOOST3
BOOST3Charge
ChargePump
PumpOutput
Output
Current
Currentvs
vsSW3
SW3Voltage
Voltage
70
500
SENSE = 12V
SENSE = 1V
–0.4
80
0
40
0.0
100
0
35
MODE = INTVCC
–0.2
100
20
15 20 25 30
SENSE VOLTAGE (V)
–0.8
SENSE2–,SENSE3+ = INTVCC–0.5V
10
125
10
0.2
BOOST3 = 16V
90 SW3 = 12V
4
5
0.4
BOOST3Charge
ChargePump
PumpOutput
Output
BOOST3
Currentvs
vsFrequency
Frequency
Current
RFREQ=374k (100kHz)
RFREQ=75k (500kHz)
RFREQ=12.5k (3MHz)
FREQ=GND (380kHz)
FREQ=INTVCC (2.25MHz)
0
7817 G23
Oscillator Frequency
vs Temperature
8
0
–0.6
7817 G22
5
35
65
95
TEMPERATURE (oC)
10
0.6
500
–100
–55
100 200 300 400 500 600 700 800
FEEDBACK VOLTAGE (mV)
–25
20
0.8
600
0
–6
–55
30
1.0
SENSE CURRENT (µA)
50
6
40
+
−
SENSE1,2
SENSE1,2+ and
and SENSE3
SENSE3– Input
Input
Current
Current vs
vs Temperature
Temperature
SENSE = INTVCC+0.5V
700
8
50
7817 G21
MODE = INTVCC
800
SENSE CURRENT (μA)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
900
10
60
+ Input
SENSE1,2– and
SENSE3
SENSE1,2–,
SENSE3+
Input
Current vs Temperature
Buck Foldback Current Limit
0
70
7817 G20
70
0
40
2500
3000
7817 G26
CHARGE PUMP CURRENT (μA)
40
MAXIMUM CURRENT SENSE THRESHOLD (mV)
900
PULSE–SKIPPING
BURST MODE
FORCED CONTINUOUS
SENSE CURRENT (μA)
CURRENT SENSE THRESHOLD (mV)
50
Maximum Current Sense
Maximum vs
Current
Threshold
Threshold
SENSESense
Common
vs SENSE
Common Mode Voltage
Mode
Voltage
andSENSE3+
SENSE3+ Current
Current
SENSE1,2– and
vs Voltage
Current
Sense
Threshold
Maximum
Current
Sense vs ITH
Voltage
Threshold vs ITH Voltage
70
60
50
40
30
20
150°C
–55°C
25°C
10
0
0
5
10
15
20
25
SW3 VOLTAGE (V)
30
35
7817 G27
Rev A
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LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC = 6V
4.8
EXTVCC = 5V
4.6
4.4
4.2
4.0
0
50
100
150
200
250
INTVCC LOAD CURRENT (mA)
5.2
5.0
4.8
EXTVCC Rising
4.6
1.24
1.18
1.16
1.14
1.12
1.10
25
125
125
155
UVLO FALLING
3.9
3.7
–55
155
–25
5
35
65
95
TEMPERATURE (oC)
20
15
10
0
–55
Shutdown Current
VBIAS Voltage
Input Voltage
vs Input
6.0
125
155
7817 G32
7817 G31
5.0
150°C
4.0
3.0
25°C
2.0
–55°C
1.0
EXTVCC = 12V, SENSE1–=3.3V
5
35
65
95
TEMPERATURE (oC)
155
7.0
EXTVCC = 0V, SENSE1–=3.3V
–25
125
7817 G30
8.0
EXTVCC = 0V, SENSE1–=0V
5
1.08
5
35
65
95
TEMPERATURE (oC)
5
35
65
95
TEMPERATURE (oC)
VBIAS = 12V
35 ALL CHANNELS ON
SLEEP MODE
30
VBIAS CURRENT (μA)
RUN THRESHOLD (V)
–25
40
Rising
Falling
–25
4.0
7817 G29
1.22
1.06
–55
4.1
VBIAS
ModeCurrent
Quiescent
Quiescent
BIAS Sleep
vs Temperature
Current
vs Temperature
1.20
UVLO RISING
4.2
3.8
7817 G28
RUN Pin Thresholds
vs Temperature
1.26
EXTVCC Falling
4.4
4.2
–55
300
4.3
INTVCC Voltage
UVLO THRESHOLD (V)
EXTVCC = 0V
5.0
4.4
VBIAS CURRENT (μA)
INTVCC VOLTAGE (V)
5.2
INTVCC
Undervoltage Lockout
INTV
CC Undervoltage Lockout
Thresholds
Thresholds vs
vs Temperature
Temperature
5.4
VBIAS = 12V
INTVCC OR EXTVCC VOLTAGE (V)
5.4
EXTV
Switchover and INTV CC
EXTVCC
CC Switchover and INTVCC
Voltage
Voltage vs
vs Temperature
Temperature
INTV
Voltage vs Current
INTVCC
CC Voltage vs Current
0
0
5
10 15 20 25 30
VBIAS INPUT VOLTAGE (V)
35
40
7817 G33
Rev A
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9
LTC7817
PIN FUNCTIONS
FREQ (Pin 1): Frequency Control Pin for the Internal
Oscillator. Connect to ground to set the switching frequency to 380KHz. Connect to INTVCC to set the switching frequency to 2.25MHz. Frequencies between 100kHz
and 3MHz can be programmed using a resistor between
the FREQ pin and ground. Minimize the capacitance on
this pin.
PLLIN/MODE (Pin 2): External Synchronization Input and
Mode Select Input. When an external clock is applied to
this pin, the phase-locked loop forces the rising TG1 signal to be synchronized with the rising edge of the external
clock, and the regulators operate in forced continuous
mode. When not synchronizing to an external clock, this
input, which acts on all three channels, determines how
the LTC7817 operates at light loads. Pulling this pin to
ground selects Burst Mode operation. An internal 100k
resistor to ground also invokes Burst Mode operation
when the pin is floating. Tying this pin to INTVCC forces
continuous inductor current operation. Tying this pin to
INTVCC through a 100k resistor selects pulse-skipping
operation.
SGND (Pin 8): Small Signal Ground common to all three
controllers, must be routed separately from high current
grounds to the common (-) terminals of the CIN capacitors.
RUN1, RUN2, RUN3 (Pins 9, 10, 11): Run Control Inputs
for Each Controller. Forcing any of these pins below
1.1V disables switching of the corresponding controller.
Forcing all of these pins below 0.7V shuts down the entire
LTC7817, reducing the quiescent current to approximately
1.5µA. These pins can be tied to VIN or VBIAS for alwayson operation.
VPRG3 (Pin 17): Boost Output Voltage Programming Pin.
This pin sets the boost channel to adjustable output voltage or to a fixed output voltage. Floating this pin allows
the boost channel output to be programmed through the
VFB3 pin using external resistors, regulating VFB3 to the
1.2V reference. Connecting this pin to GND or INTVCC
programs the boost channel output to 8V or 10V (respectively), with VFB3 directly connected to the output.
10
INTVCC (Pin 22): Output of the Internal 5.1V Low Dropout
Regulator. The driver and control circuits are powered by
this supply. Must be decoupled to ground with a minimum
of 4.7μF ceramic or tantalum capacitor.
EXTVCC (Pin 23): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VBIAS whenever
EXTVCC is higher than 4.7V. See INTVCC Regulators in the
Applications Information section. Do not exceed 30V on
this pin. Connect this pin to ground if the EXTVCC LDO
is not used.
VBIAS (Pin 24): Main Bias Input Supply Pin. A bypass
capacitor should be tied between this pin and ground.
BG1, BG2, BG3 (Pins 29, 21, 25): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to INTVCC.
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26):
Bootstrapped Supplies to the Top Side Floating Drivers.
Connect capacitors between the corresponding BOOST
and SW pins for each channel. Also connect Schottky
diodes between the BOOST1 and INTVCC pins, the
BOOST2 and INTVCC pins, and the BOOST3 and INTVCC
pins. Voltage swing at the BOOST1, 2 pins is from INTVCC
to (VIN+INTVCC). Voltage swing at the BOOST3 pin is from
INTVCC to (VOUT3 + INTVCC).
SW1, SW2, SW3 (Pins 31, 19, 28): Switch Node
Connections to Inductors.
TG1, TG2, TG3 (Pins 32, 18, 27): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing of INTVCC
superimposed on the switch node voltage SW.
PGOOD1 (Pin 33): Open-Drain Power Good Output. The
VFB1 pin is monitored to ensure that VOUT1 is in regulation.
When VOUT1 is not within ±10% of its regulation point,
the PGOOD1 pin is pulled low.
Rev A
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LTC7817
PIN FUNCTIONS
TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3): External
Tracking and Soft-Start Input. For the buck channels, the
LTC7817 regulates the VFB1,2 voltage to the lesser of 0.8V
or the voltage on the TRACK/SS1,2 pin. For the boost
channel, the LTC7817 regulates VFB3 to the lesser of 1.2V
or the voltage on the SS3 pin. Internal 12.5µA pull-up
current sources are connected to these pins. A capacitor
to ground sets the startup ramp time to the final regulated output voltage. The ramp time is equal to 0.65ms
for every 10nF of capacitance for the buck channels and
1ms for every 10nF for the boost channel. Alternatively,
a resistor divider on another voltage supply connected
to the TRACK/SS pins of the buck channels allows the
LTC7817 output to track the other supply during startup.
ITH1, ITH2, ITH3 (Pins 35, 15, 7): Error Amplifier Outputs
and Regulator Compensation Points. Each associated
channel’s current comparator trip point increases with
this control voltage. Place compensation components
between the ITH pins and ground.
VFB1, VFB2 (Pins 36, 14): Buck Controller Feedback
Inputs. Connect an external resistor divider between the
output voltage and the VFB pin to set the regulated output
voltage. Tie VFB2 to INTVCC to configure the bucks for a
two-phase single output application, in which both buck
channels share VFB1, ITH1, and TRACK/SS1.
VFB3 (Pin 6): Boost Controller Feedback Input. When
VPRG3 is floating, connect an external resistor divider
between the boost output voltage and the VFB3 pin to
set the regulated voltage. When VPRG3 is connected to
ground or INTVCC, tie VFB3 directly to the boost converter
output.
SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4): The
Positive (+) Input to the Differential Current Comparators.
The ITH pin voltage and controlled offsets between the
SENSE– and SENSE+ pins in conjunction with RSENSE
set the current trip threshold. For the boost channel, the
SENSE3+ pin supplies current to the current comparator
when it is greater than INTVCC.
SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5): The
Negative (–) Input to the Differential Current Comparators.
When SENSE1– is 3.2V or greater, it supplies the majority of the sleep mode quiescent current instead of VBIAS,
further reducing the input-referred quiescent current. For
the buck channels, the SENSE– pins supply current to the
current comparators when they are greater than INTVCC.
PGND (Exposed Pad Pin 39): Driver Power Ground.
Connects to the sources of bottom N-channel MOSFETs
and the (–) terminal(s) of decoupling capacitors. The
exposed pad must be soldered to PCB ground for rated
electrical and thermal performance.
Rev A
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11
LTC7817
FUNCTIONAL DIAGRAM
INTVCC
BUCK CHANNELS 1 AND 2
DB
RUN
BOOST
ALLOFF
1.2V
FREQ
OSCILLATOR
AND PLL
CLK1
S
INTVCC
R
BG
BOT
0.425V
CIN
SW
SWITCH
LOGIC
TOP ON
Q
CB
TG
TOP
DROPOUT
DETECT
CLK2
VIN1,2
PGND
SLEEP
PLLIN/MODE
L
ICMP
100k
RSENSE
IR
VOUT1,2
COUT
VBIAS
2mV
SENSE+
EXTVCC
SENSE–
SLOPE COMP
4.7V
5.1V
INTVCC
EN
EA
VBIAS LDO
EXTVCC LDO
0.8V
RA
OV
0.88V
0.88V
CC2
12.5µA
ITH
CLAMP
1.4V
RC
ITH
SGND
PGOOD1
RB
VFB
EN
5.1V
CC1
TRACK/SS
VFB1
ALLOFF
CSS
0.72V
BOOST CHANNEL 3
INTVCC
CHARGE
PUMP
RUN3
TOP
ALLOFF
S
VOUT3
CB3
COUT3
TG3
1.2V
CLK1
DB3
BOOST3
SW3
Q
BOT ON
R
0.425V
SWITCH
LOGIC
INTVCC
BOT
BG3
PGND
SLEEP
L3
PLLIN/MODE
RSENSE3
IR
ICMP
VIN3
CIN3
2mV
SENSE3–
SENSE3+
SLOPE COMP
R1
EA
1.2V
R2
RB
VFB3
RA
VPRG3
OV
1.32V
ITH
CLAMP
VPRG3
FLOAT
GND
INTVCC
VOUT3
ADJUSTABLE
8V FIXED
10V FIXED
RC3
ITH3
12.5µA
1.4V
VOUT3
CC4
SS3
ALLOFF
CC3
CSS3
7817 FD
12
Rev A
For more information www.analog.com
LTC7817
OPERATION
(Refer to Functional Diagram)
Main Control Loop
The LTC7817 is a synchronous three-channel controller
utilizing a constant frequency, peak current mode architecture. The two step-down (buck) controllers, channels
1 and 2, operate 180° out of phase with each other. The
step-up (boost) controller, channel 3, operates in phase
with channel 1. During normal operation, the main switch
(external top MOSFET for the buck channels or the external bottom MOSFET for the boost channel) is turned on
when the clock for that channel sets the SR latch, causing
the inductor current to increase. The main switch is turned
off when the main current comparator, ICMP, resets the
SR latch. After the main switch is turned off each cycle,
the synchronous switch (the bottom MOSFET for the buck
channels or the top MOSFET for the boost channel) is
turned on which causes the inductor current to decrease
until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of
the next clock cycle.
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin, (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground)
to the internal reference voltage (0.8V for the bucks or
1.2V for the boost). When the load current increases, it
causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
Power and Bias Supplies (VBIAS, EXTVCC, and INTVCC)
The INTVCC pin supplies power for the top and bottom
MOSFET drivers and most of the internal circuitry. LDOs
(low dropout linear regulators) are available from both the
VBIAS and EXTVCC pins to provide power to INTVCC, which
has a regulation point of 5.1V. When the EXTVCC pin is left
open or tied to a voltage less than 4.7V, the VBIAS LDO
(low dropout linear regulator) supplies power to INTVCC.
If EXTVCC is taken above 4.7V, the VBIAS LDO is turned
off and an EXTVCC LDO is turned on. Once enabled, the
EXTVCC LDO supplies power to INTVCC. Using the EXTVCC
pin allows the INTVCC power to be derived from a high
efficiency external source such as one of the LTC7817
switching regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each
cycle through an external diode when the switch voltage
goes low.
For buck channels 1 and 2, if the buck’s input voltage
decreases to a voltage close to its output, the loop may
enter dropout and attempt to turn on the top MOSFET
continuously. The dropout detector detects this and forces
the top MOSFET off for a short time every tenth cycle to
allow CB to recharge, resulting in a 99% duty cycle at
380kHz operation and approximately 98% duty cycle at
2MHz operation.
Shutdown and Start-Up (RUN1, RUN2, RUN3 and
TRACK/SS1, TRACK/SS2, SS3 Pins)
The three channels of the LTC7817 can be independently
shut down using the RUN1, RUN2 and RUN3 pins. Pulling
a RUN pin below 1.1V shuts down the main control loop
for that channel. Pulling all three pins below 0.7V disables
all controllers and most internal circuits, including the
INTVCC LDOs. In this state, the LTC7817 draws only 1.5μA
of quiescent current.
The RUN pins may be externally pulled up or driven
directly by logic. Each pin can tolerate up to 40V (absolute maximum), so it can be conveniently tied to VBIAS or
to an input supply in always-on applications where one
or more controllers are enabled continuously and never
shut down. Additionally, a resistive divider from the input
supply to a RUN pin can be used to set a precise input
undervoltage lockout so that the power supply does not
operate below a user-adjustable level.
The start-up of each channel’s output voltage VOUT is controlled by the voltage on the TRACK/SS pin (TRACK/SS1
for channel 1, TRACK/SS2 for channel 2, SS3 for channel 3). When the voltage on the TRACK/SS pin is less than
the internal reference voltage (0.8V for the bucks or 1.2V
for the boost), the LTC7817 regulates the VFB voltage to
the TRACK/SS pin voltage instead of the corresponding
Rev A
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13
LTC7817
OPERATION
reference voltage. This allows the TRACK/SS pin to be
used as a soft-start which smoothly ramps the output
voltage on startup, thereby limiting the input supply
inrush current. An external capacitor from the TRACK/
SS pin to GND is charged by an internal 12.5μA pull-up
current, creating a voltage ramp on the TRACK/SS pin. As
the TRACK/SS voltage rises linearly from 0V to 0.8V/1.2V
(and beyond), the output voltage VOUT rises smoothly
from zero to its final value.
Alternatively, the TRACK/SS pins for buck channels 1 and
2 can be used to make the start-up of VOUT track that
of another supply. Typically this requires connecting to
the TRACK/SS pin through an external resistor divider
from the other supply to ground (see the Applications
Information section).
Light Load Operation: Burst Mode Operation, PulseSkipping, or Forced Continuous Mode (PLLIN/MODE Pin)
The LTC7817 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping
mode or forced continuous conduction mode at low load
currents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to ground. To select forced continuous operation, tie the
PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTVCC – 1.3V. An internal 100k
resistor to ground invokes Burst Mode operation when
the PLLIN/MODE pin is floating and pulse-skipping mode
when the PLLIN/MODE pin is tied to INTVCC through an
external 100k resistor.
When the controllers are enabled for Burst Mode operation, the minimum peak current in the inductor is set to
approximately 25% of its maximum value even though
the voltage on the ITH pin might indicate a lower value. If
the average inductor current is higher than the load current, the error amplifier EA will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.45V.
14
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7817 draws.
If one channel is in sleep mode and the other two are shut
down, the LTC7817 draws only 15μA of quiescent current.
If all three channels are in sleep mode, the LTC7817 draws
only 18µA of quiescent current. When VOUT on channel 1
is 3.2V or higher, the majority of this quiescent current is
supplied by the SENSE1– pin, which further reduces the
input-referred quiescent current by the ratio of VIN/VOUT
multiplied by the efficiency.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the main switch on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the synchronous switch
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
In forced continuous operation the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping mode, the LTC7817 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the main switch to stay off for the same
Rev A
For more information www.analog.com
LTC7817
OPERATION
number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
When synchronizing to an external clock applied to the
PLLIN/MODE pin, the LTC7817 operates in forced continuous mode.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The free running switching frequency of the LTC7817
controllers is selected using the FREQ pin. Tying FREQ to
GND selects 380kHz while tying FREQ to INTVCC selects
2.25MHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 100kHz
and 3MHz.
A phase-locked loop (PLL) is available on the LTC7817
to synchronize the internal oscillator to an external clock
source connected to the PLLIN/MODE pin. The LTC7817’s
PLL aligns the turn-on of controller 1’s external top
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external top MOSFET
is 180° out-of-phase to the rising edge of the external
clock source.
The PLL frequency is prebiased to the free running frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL only needs to make slight changes in order to
synchronize the rising edge of the external clock to the
rising edge of TG1. For more rapid lock-in to the external
clock, use the FREQ pin to set the internal oscillator to
approximately the frequency of the external clock. The
LTC7817’s PLL is guaranteed to lock to an external clock
source whose frequency is between 100kHz and 3MHz.
Boost Controller Operation When VIN > VOUT
When the input voltage to the boost channel rises above
its regulated VOUT voltage, the controller can behave differently depending on the mode, inductor current and VIN
voltage. When VIN exceeds the regulated VOUT in forced
continuous mode, the loop works to keep the top MOSFET
on continuously. An internal charge pump delivers current
to the boost capacitor from the BOOST3 pin to maintain
a sufficiently high TG3 voltage.
If VIN is between 100% and 110% of the regulated VOUT
voltage and pulse-skipping mode is selected, TG3 turns
on if the inductor current rises above approximately 4%
of the programmed current limit. Similarly, if Burst Mode
operation is selected, then TG3 turns on as long as at
least one channel is awake. If both buck channels are
asleep or shut down, TG3 remains off regardless of the
inductor current.
If VIN rises above 110% of the regulated VOUT voltage
in any mode, the controller turns on TG3 continuously
regardless of the inductor current. In Burst Mode operation, however, the internal charge pump is disabled when
none of the channels are awake. With the charge pump
off, the boost capacitor may discharge, resulting in an
insufficient TG3 voltage needed to keep the top MOSFET
completely on.
Boost Controller at Low Input Voltage
The LTC7817 features a rail-to-rail current comparator for
the boost channel which functions down to zero volts. The
minimum boost converter input voltage is therefore determined by the practical limitations of the boost converter
architecture. Since the input voltage could be lower than
the 4.5V VBIAS limit, VBIAS can be connected to the output
of the boost controller, as illustrated in the typical application circuit in Figure 10. This allows the boost controller to
handle very low input voltage transients while maintaining
output voltage regulation.
The PLLIN/MODE pin is TTL compatible with thresholds
of 1.6V (rising) and 1.1V (falling) and is guaranteed to
operate with a clock signal swing of 0.5V to 2.5V.
Rev A
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15
LTC7817
OPERATION
Buck Controller Output Overvoltage Protection
The two buck channels have an overvoltage comparator
that guards against transient overshoots as well as other
more serious conditions that may overvoltage their outputs. When the VFB1,2 pin rises more than 10% above its
regulation point of 0.8V, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Buck Foldback Current
When the buck output voltage falls to less than 50% of its
nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
16
interval (as long as the VFB voltage is keeping up with
the TRACK/SS1,2 voltage). There is no foldback current
limiting for the boost channel.
Channel 1 Power Good (PGOOD1)
Channel 1 has a PGOOD1 pin that is connected to an
open drain of an internal N-channel MOSFET. The MOSFET
turns on and pulls the PGOOD1 pin low when the VFB1
pin voltage is not within ±10% of the 0.8V reference. The
PGOOD1 pin is also pulled low when the RUN1 pin is
low (shut down). When the VFB1 pin voltage is within the
±10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source no greater than 6V, such as INTVCC.
Rev A
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LTC7817
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC7817 application circuit. External component selection
is largely driven by the load requirement and begins with
the selection of the inductor, current sense components,
operating frequency, and light load operating mode. The
remaining power stage components, consisting of the
input and output capacitors, and power MOSFETs can
then be chosen. Next, feedback resistors are selected
to set the desired output voltage. Then, the remaining
external components are selected, such as for soft-start,
biasing, and loop compensation.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addition to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also
be considered. The inductor value has a direct effect on
ripple current.
For a buck regulator, the maximum average inductor current IL(MAX) is equal to the maximum output current. The
peak current is equal to the average inductor current plus
half of the inductor ripple current, ΔIL, which for a buck
regulator decreases with higher inductance or higher frequency and increases with higher VIN:
ΔIL =
⎛ V ⎞
1
VOUT ⎜ 1− OUT ⎟
(f)(L)
VIN ⎠
⎝
For a boost regulator, the maximum average output
current in continuous conduction mode is equal to the
maximum average inductor current multiplied by a factor
of VIN/VOUT, or IOUT(MAX) = IL(MAX) • VIN/VOUT. Be aware
that the maximum output current from a boost regulator
decreases with decreasing VIN. The choice of IL(MAX) therefore depends on the maximum load current for a regulated
VOUT at the minimum normal operating VIN. If the load
current limit for a given VIN is exceeded, VOUT will decrease
until the IOUT(MAX) = IL(MAX) • VIN/VOUT equation is satisfied. Additionally, when the output is in overvoltage (VIN >
VOUT), the top switch is on continuously and the maximum
load current is equal to IL(MAX). The inductor ripple current ΔIL for a boost regulator increases with higher VOUT:
ΔIL =
⎛
1
V ⎞
VIN ⎜ 1− IN ⎟
(f)(L) ⎝ VOUT ⎠
Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting ripple current is ΔIL = 0.3 • IL(MAX). The maximum
ΔIL occurs at the maximum input voltage for a buck and
at VIN = VOUT/2 for a boost.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
lower load currents, which can cause a dip in efficiency
in the upper range of low current operation.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency regulators generally cannot afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is very dependent
on inductance value selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Rev A
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17
LTC7817
APPLICATIONS INFORMATION
Current Sense Selection
The LTC7817 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing.
The choice between the two current sensing schemes
is largely a design trade-off between cost, power consumption and accuracy. DCR sensing has become popular
because it saves expensive current sensing resistors and
is more power efficient, particularly in higher current and
lower frequency applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value.
The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode voltage range on
these pins is 0V to 40V (absolute maximum), enabling
the LTC7817 to regulate output voltages up to a maximum of 40V. The SENSE1+, SENSE2+, and SENSE3– pins
are high impedance, drawing less than ≈1μA. This high
impedance allows the current comparators to be used in
inductor DCR sensing. The impedance of the SENSE1–,
SENSE2–, and SENSE3+ pins changes depending on the
common mode voltage. When less than INTVCC – 0.5V,
these pins are relatively high impedance, drawing ≈1μA.
When above INTVCC + 0.5V, a higher current (≈600μA)
flows into each pin. Between INTVCC – 0.5V and INTVCC
+ 0.5V, the current transitions from the smaller current
to the higher current. Channel 1’s SENSE1– pin has an
additional ≈40μA current when its voltage is above 3.2V
to bias internal circuitry from VOUT1, thereby reducing the
input-referred supply current.
18
Filter components mutual to the sense lines should be
placed close to the LTC7817, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
TO SENSE FILTER
NEXT TO THE CONTROLLER
CURRENT FLOW
INDUCTOR OR RSENSE
7817 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small signal nodes.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required output current. Each controller’s current comparator has a
maximum threshold VSENSE(MAX) of 50mV. The current
comparator threshold voltage sets the peak inductor
current.
Using the maximum inductor current (IL(MAX)) and ripple
current (ΔIL) from the Inductor Value Calculation section,
the target sense resistor value is:
VSENSE(MAX)
RSENSE ≤
ΔI
IL(MAX) + L
2
Rev A
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LTC7817
APPLICATIONS INFORMATION
To ensure that the application will deliver full load current over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
To avoid potential jitter or instability due to PCB noise coupling into the current sense signal, the AC current sensing
ripple of ΔVSENSE = ΔIL • RSENSE should also be checked
to ensure a good signal-to-noise ratio. In general, for a
reasonably good PCB layout, a target ΔVSENSE voltage of
10mV to 20mV at nominal input voltage for the bucks or
at 50% duty cycle for the boost is recommended for both
RSENSE and DCR sensing applications.
The parasitic inductance (ESL) of the sense resistor
introduces significant error in the current sense signal
for lower inductor value (5A)
applications. For a buck converter, this error is proportional to the input voltage and may degrade line regulation
or cause loop instability. An RC filter into the sense pins,
as shown in Figure 2a, can be used to compensate for
this error. Set the RC filter time constant RF • CF = ESL/
RSENSE for optimal cancellation of the ESL. In general,
select CF to be in the range of 1nF to 10nF and calculate
the corresponding RF. Surface mount sense resistors in
low ESL wide footprint geometries are recommended to
minimize this error. If not specified on the manufacturer's
data sheet, the ESL can be approximated as 0.4nH for
a resistor with a 1206 footprint and 0.2nH for a 1225
footprint.
VIN1,2
(VOUT3)
INTVCC
LTC7817 TG
SENSE RESISTOR
WITH PARASITIC
INDUCTANCE
BOOST
L
SW
BG
RF
SENSE1,2+
(SENSE3–)
RSENSE
ESL
VOUT1,2
(VIN3)
RF *CF = ESL/RSENSE
POLE-ZERO
CANCELLATION
CF
SENSE1, 2–
(SENSE3+)
PLACE RF AND CF NEAR SENSE PINS
7817 F02a
2a. Using a Resistor to Sense Current
VIN1,2
(VOUT3)
INTVCC
BOOST
LTC7817
INDUCTOR
TG
L
SW
BG
SENSE1, 2+
(SENSE3–)
SENSE1, 2–
(SENSE3+)
DCR
VOUT1,2
(VIN3)
R1
C1*
R2
GND
7817 F02b
*PLACE C1 NEAR SENSE PINS
(R1||R2) • C1 = L/DCR
RSENSE(EQ) = DCR(R2/(R1+R2))
2b. Using the Inductor DCR to Sense Current
Inductor DCR Current Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC7817 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
Figure 2. Current Sensing Methods
Rev A
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19
LTC7817
APPLICATIONS INFORMATION
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1+R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the maximum inductor current (IL(MAX)) and ripple
current (ΔIL) from the Inductor Value Calculation section,
the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV) ≤
ΔI
IL(MAX)+ L
2
To ensure that the application will deliver full load current over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C. To
scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD =
R SENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1||R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ≈1μA current.
The target equivalent resistance R1||R2 is calculated from
the nominal inductance, C1 value, and DCR:
L
R1! R2 =
(DCR at 20°C) • C1
20
The sense resistor values are:
R1! R2
R1• RD
R1=
; R2 =
RD
1− RD
The maximum power loss in R1 is related to duty cycle.
For the buck controllers, the maximum power loss occurs
in continuous mode at the maximum input voltage:
(VIN(MAX) − VOUT ) • VOUT
PLOSS R1=
R1
For the boost controller, the maximum power loss occurs
in continuous mode at VIN = VOUT/2:
PLOSS R1=
(VOUT(MAX) − VIN ) • VIN
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
Setting the Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing gate charge and transition losses, but requires
larger inductance values and/or more output capacitance
to maintain low output ripple voltage.
In higher voltage applications transition losses contribute more significantly to power loss, and a good balance
between size and efficiency is generally achieved with a
switching frequency between 300kHz and 900kHz. Lower
voltage applications benefit from lower switching losses
and can therefore more readily operate at higher switching
frequencies up to 3MHz if desired.
Rev A
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LTC7817
APPLICATIONS INFORMATION
100
BOOST MAXIMUM DUTY CYCLE (%)
A further constraint on the operating frequency is due
to the maximum duty cycle of the boost channel. The
maximum duty cycle, which can be approximated as
DCMAX ≈ (1-VIN(MIN)/VOUT3)*100%, is limited as shown
in Figure 3a. At low frequencies, the output will dropout
if the required duty cycle is higher than 93%. At high
frequencies, the maximum duty cycle available to maintain constant frequency operation is reduced further. In
this region, if a higher duty cycle is required to keep the
output voltage in regulation, the controller will skip the
top MOSFET (TG3) turn-on and keep the bottom MOSFET
(BG3) on for more than one clock cycle to achieve the
higher duty cycle at an effectively lower frequency. Choose
a frequency that limits the maximum duty cycle to a value
lower than the curve shown in Figure 3a. The switching
frequency is set using the FREQ and PLLIN/MODE pins
as shown in Table 1.
95
90
85
80
75
77.5% at 2.25MHz
70
65
100k
1M
FREQUENCY (Hz)
3M
7817 F03a
3a. Relationship Between Oscillator Frequency
and Boost Channel Maximum Duty Cycle
10M
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
380kHz
INTVCC
DC Voltage
2.25MHz
Resistor to GND
DC Voltage
100kHz to 3MHz
Any of the Above
External Clock
100kHz to 3MHz
Phase-Locked to
External Clock
Tying the FREQ pin to ground selects 380kHz while
tying FREQ to INTVCC selects 2.25MHz. Placing a resistor between FREQ and ground allows the frequency to
be programmed anywhere between 100kHz and 3MHz.
Choose a FREQ pin resistor from Figure 3b or the following equation:
37MHz
RFREQ (in kΩ) =
fOSC
FREQUENCY (Hz)
Table 1.
1M
100k
10k
100k
FREQ PIN RESISTOR (Ohms)
500k
7817 F03b
3b. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
Figure 3. Setting the Operating Frequency
Rev A
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21
LTC7817
APPLICATIONS INFORMATION
A phase-locked loop (PLL) is also available on the
LTC7817 to synchronize the internal oscillator to an external clock source connected to the PLLIN/MODE pin. After
the PLL locks, TG1 is synchronized to the rising edge of
the external clock signal, and TG2 is 180° out of phase
from TG1. See the Phase-Locked Loop and Frequency
Synchronization section for details.
Selecting the Light-Load Operating Mode
The LTC7817 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode at light load currents. To select Burst Mode operation, tie the PLLIN/
MODE to ground. To select forced continuous operation,
tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to INTVCC through a
100k resistor. An internal 100k resistor from the PLLIN/
MODE pin to ground selects Burst Mode if the pin is floating. When synchronized to an external clock through the
PLLIN/MODE pin, the LTC7817 operates in forced continuous mode. Table 2 summarizes the use of the PLLIN/
MODE pin to select the light load operating mode.
Table 2.
PLLIN/MODE PIN
LIGHT-LOAD OPERATING
MODE
MODE WHEN
SYNCHRONIZED
0V or Floating
Burst Mode
Forced Continuous
100k to INTVCC
Pulse-Skipping
Forced Continuous
INTVCC
Forced Continuous
Forced Continuous
22
In general, the requirements of each application will dictate
the appropriate choice for light-load operating mode. In
Burst Mode operation, the inductor current is not allowed
to reverse. The reverse current comparator turns off the
bottom MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the regulator operates in discontinuous operation.
In addition, when the load current is very light, the inductor current will begin bursting at frequencies lower than
the switching frequency, and enter a low current sleep
mode when not switching. As a result, Burst Mode operation has the highest possible efficiency at light load.
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advantage of lower output voltage ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
light load efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
Rev A
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LTC7817
APPLICATIONS INFORMATION
In some applications, it may be desirable to change light
load operating mode based on the conditions present in
the system. For example, if a system is inactive, one might
select high efficiency Burst Mode operation by keeping
the PLLIN/MODE pin set to 0V. When the system wakes,
one might send an external clock to PLLIN/MODE, or tie
PLLIN/MODE to INTVCC to switch to low noise forced continuous mode. Such on-the-fly mode changes can allow
an individual application to benefit from the advantages
of each light load operating mode.
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7817: one N-channel MOSFET for the
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the buck).
The peak-to-peak gate drive levels are set by the INTVCC
regulation point of 5.1V. Consequently, logic level threshold MOSFETs must be used in most applications. Pay
close attention to the BVDSS specification for the MOSFETs
as well; many of the logic level MOSFETs are limited to
30V or less.
Selection criteria for the power MOSFETs include the on
resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge
curve usually provided on the MOSFET manufacturers’
data sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Buck Main Switch Duty Cycle =
VOUT
VIN
Buck Sync Switch Duty Cycle =
VIN − VOUT
VIN
Boost Main Switch Duty Cycle =
VOUT − VIN
VOUT
Boost Sync Switch Duty Cycle =
VIN
VOUT
For a buck converter, the MOSFET power dissipations at
maximum output current are given by:
PMAIN_BUCK =
(
VOUT
I
VIN OUT(MAX)
) (1+ δ )RDS(ON) +
2
⎛ IOUT(MAX) ⎞
(VIN )2 ⎜
⎟⎠ (RDR )(CMILLER ) •
2
⎝
⎡
1
1 ⎤
+
⎢
⎥ (f)
V
V
−
V
THMIN
THMIN
INTVCC
⎣
⎦
V −V
PSYNC_BUCK = IN OUT IOUT(MAX)
VIN
(
) (1+ δ )RDS(ON)
2
Similarly, for a boost converter:
PMAIN_BOOST =
( VOUT − VIN ) VOUT
VIN
2
(IOUT(MAX) )
2
•
⎛ VOUT3 ⎞ ⎛ IOUT(MAX) ⎞
⎟⎜
⎟⎠ •
2
⎝ VIN ⎠ ⎝
(1+ δ )RDS(ON) + ⎜
⎡
1
1 ⎤
+
⎥ (f)
⎣ INTVCC − VTHMIN VTHMIN ⎦
(RDR )(CMILLER ) • ⎢ V
PSYNC_BOOST =
(
VOUT
I
VIN OUT(MAX)
) (1+ δ )RDS(ON)
2
where δ is the temperature dependency of RDS(ON)
(δ ≈ 0.005/°C) and RDR is the effective driver resistance at
Rev A
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23
LTC7817
APPLICATIONS INFORMATION
the MOSFET’s Miller threshold voltage (RDR≈2Ω). VTHMIN
is the typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest
at high input voltages for the bucks and high output voltages for the boost. For VIN < 20V for the bucks (or VOUT
< 20V for the boost) the high current efficiency generally
improves with larger MOSFETs, while for VIN > 20V for the
bucks (VOUT > 20V for the boost) the transition losses rapidly increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses for the buck
controllers are greatest at high input voltage when the top
switch duty factor is low or during a short-circuit when
the synchronous switch is on close to 100% of the period.
Boost CIN and COUT Selection
The input ripple current in a boost converter is relatively
low (compared to the output ripple current) because this
current is continuous. The boost input capacitor CIN voltage rating should comfortably exceed the maximum input
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input voltage for any possible overvoltage transients that could
apply excess stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher
the required input capacitance. The required amount of
input capacitance is also greatly affected by the duty cycle.
High output current applications that also experience high
duty cycles can place great demands on the input supply,
both in terms of DC current and ripple current.
24
The output current in a boost converter is discontinuous,
so COUT should be selected to meet output voltage ripple
requirements. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when
choosing the right capacitor for a given output ripple voltage. The ripple due to charging and discharging the bulk
capacitance of COUT is given by:
Ripple =
(
IOUT(MAX) • VOUT − VIN(MIN)
COUT • VOUT • f
)V
The ripple due to the voltage drop across the ESR is given
by:
1 ⎞
⎛
ΔVESR = ⎜ IL(MAX) + ΔIL ⎟ •ESR
⎝
⎠
2
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
Buck CIN and COUT Selection
The selection of CIN for the two buck controllers is simplified by the two-phase architecture and its impact on
the worst-case RMS current drawn through the input
network (battery/fuse/capacitor). It can be shown that
the worst-case capacitor RMS current occurs when only
one controller is operating. The controller with the highest VOUT • IOUT product needs to be used in the formula
shown in Equation 1 to determine the maximum RMS
capacitor current requirement.
Rev A
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LTC7817
APPLICATIONS INFORMATION
Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current
from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by
a factor of 30% to 70% when compared to a single phase
power supply solution.
source impedance of the power supply/battery is included
in the efficiency testing.
In continuous mode, the source current of the top
MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. At maximum load current IMAX, the maximum RMS
capacitor current is given by:
IMAX
1/2
C Required I
⎡⎣( VOUT ) ( VIN − VOUT ) ⎤⎦
IN
RMS ≈
V
A small (0.1μF to 1μF) bypass capacitor between the chip
VBIAS pin and ground, placed close to the LTC7817, is
also suggested. An optional 1Ω to 10Ω resistor placed
between CIN and the VBIAS pin provides further isolation
from a noisy input supply.
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design.
Due to the high operating frequency of the LTC7817,
ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question.
The benefit of the LTC7817 two-phase operation can be
calculated by using this equation for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a two-phase system. The overall benefit
of a multiphase design will only be fully realized when the
The drains of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the drains and CIN may produce undesirable resonances
at VIN.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
⎛
1 ⎞
ΔVOUT ≈ ΔIL ⎜ ESR +
8fCOUT ⎟⎠
⎝
where f is the operating frequency, COUT is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
Setting the Buck Output Voltage
The LTC7817 output voltages for the buck channels are
each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 4 The
regulated output voltage is determined by:
⎛ R ⎞
VOUT, BUCK = 0.8V ⎜ 1+ B ⎟
⎝ RA ⎠
Place resistors RA and RB very close to the VFB pin to
minimize PCB trace length and noise on the sensitive VFB
node. Great care should be taken to route the VFB trace
away from noise sources, such as the inductor or the
SW trace. To improve frequency response, a feedforward
capacitor (CFF) may be used.
Rev A
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25
LTC7817
APPLICATIONS INFORMATION
VOUT3
VOUT
1/3 LTC7817
RB
LTC7817
CFF
(FLOAT)
VFB
RB
CFF
VPRG3 VFB3
RA
RA
7817 F05a
5a. Setting Boost Output Using External Resistors
7817 F04
Figure 4. Setting Buck Output Voltage
For applications with multiple output voltage levels, select
channel 1 to be the lowest output voltage that is greater
than 3.2V. When the SENSE1– pin (connected to VOUT1)
is above 3.2V, it biases some internal circuitry instead of
VBIAS, thereby increasing light load Burst Mode efficiency.
Similarly, connect EXTVCC to the lowest output voltage
that is greater than the 4.7V EXTVCC rising switch-over
threshold. EXTVCC then supplies the high current gate
drivers and relieves additional quiescent current from
VBIAS, further reducing the VBIAS pin current to ≈1μA in
sleep.
Setting Boost Output Voltage (VPRG3 Pin)
The VPRG3 pin selects whether the boost controller output voltage is set by an external feedback resistor divider
or programmed to a fixed 8V or 10V output. Floating
VPRG3 allows the boost output voltage to be set by an
external feedback resistor divider as shown in Figure 5a.
The regulated output voltage is then determined by:
⎛ R ⎞
VOUT, BOOST = 1.195V ⎜ 1+ B ⎟
⎝ RA ⎠
Tying the VPRG3 to GND or INTVCC configures the boost
controller for a fixed output voltage of 8V or 10V, respectively. As shown in Figure 5b, directly connect VFB3 to the
output when configured for a fixed output voltage.
LTC7817
GND/INTVCC
COUT
VOUT3
8V/10V
7817 F05b
5b. Setting Boost to Fixed 8V/10V Output
Figure 5. Setting Boost Output Voltage
RUN pins below 0.7V disables the controllers and most
internal circuits, including the INTVCC LDOs. In this state,
the LTC7817 draws only ≈1.5μA of quiescent current.
The RUN pins are high impedance and must be externally
pulled up/down or driven directly by logic. Each RUN pin
can tolerate up to 40V (absolute maximum), so it can
be conveniently tied to VBIAS in always-on applications
where the controller is enabled continuously and never
shut down. Do not float the RUN pins.
The RUN pins can also be configured as precise undervoltage lockouts (UVLOs) on a supply such as VBIAS or
VOUT3 with a resistor divider from the supply to ground.
For example, a simple resistor divider can be used as
shown in Figure 6 to satisfy a VBIAS UVLO requirement.
VBIAS
1/3 LTC7817
R1
RUN
RUN Pins and Undervoltage Lockout
R2
The three channels of the LTC7817 are enabled using the
RUN1, RUN2, and RUN3 pins. The RUN pins have a rising threshold of 1.2V with 100mV of hysteresis. Pulling
a RUN pin below 1.1V shuts down the main control loop
and resets the soft-start for that channel. Pulling all three
26
VPRG3 VFB3
7817 F06
Figure 6. Using the RUN Pins as a UVLO
Rev A
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LTC7817
APPLICATIONS INFORMATION
The VBIAS UVLO thresholds can be computed as:
⎛ R1⎞
UVLO Rising = 1.2V ⎜ 1+ ⎟
⎝ R2 ⎠
(VOUT), as shown in Figure 8. During start-up VOUT will
track VX according to the ratio set by the resistor divider:
VX
The current that flows through the R1-R2 divider directly
adds to the shutdown, sleep, and active current of the
LTC7817, and care should be taken to minimize the impact
of this current on the overall efficiency of the application
circuit. Resistor values in the MΩ range may be required
to keep the impact on quiescent shutdown and sleep currents low.
VOUT
R
+R TRACKB
• TRACKA
R TRACKA
R A +R B
RA
Set RTRACKA = RA and RTRACKB = RB for coincident tracking (VOUT = VX during start-up).
VX(MASTER)
OUTPUT (VOUT)
⎛ R1⎞
UVLO Falling = 1.1V ⎜ 1+ ⎟
⎝ R2 ⎠
=
VOUT(SLAVE)
Soft-Start and Tracking (TRACK/SS1, TRACK/SS2, SS3
Pins)
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground. An internal 12.5μA
current source charges the capacitor, providing a linear
ramping voltage at the TRACK/SS pin. The LTC7817 will
regulate its feedback voltage (and hence VOUT) according
to the voltage on the TRACK/SS pin, allowing VOUT to rise
smoothly from 0V to its final regulated value. For a desired
soft-start time, tSS, select a soft-start capacitor CSS =
tSS • 15μF/sec for the buck channels and CSS = tSS • 10μF/
sec for the boost channel.
7817 F07a
7a. Coincident Tracking
VX(MASTER)
OUTPUT (VOUT)
The start-up of each VOUT is controlled by the voltage on
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/
SS2 for channel 2, SS3 for channel 3). When the voltage
on the TRACK/SS pin is less than the internal 0.8V reference (1.2V reference for the boost channel), the LTC7817
regulates the VFB pin voltage to the voltage on the TRACK/
SS pin instead of the internal reference. The TRACK/SS
pin can be used to program an external soft-start function
or to allow VOUT to track another supply during start-up.
TIME
VOUT(SLAVE)
TIME
7b. Ratiometric Tracking
7817 F07b
Figure 7. Two Different Modes of Output Voltage Tracking
VOUT
RB
VFB
VX
Alternatively, the TRACK/SS1 and TRACK/SS2 pins can
be used to track two or more supplies during start-up,
as shown qualitatively in Figure 7a and Figure 7b. To do
this, a resistor divider should be connected from the master supply (VX) to the TRACK/SS pin of the slave supply
RA
LTC7817
RTRACKB
TRACK/SS1,2
RTRACKA
7817 F08
Figure 8. Using the TRACK/SS Pin for Tracking
Rev A
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27
LTC7817
APPLICATIONS INFORMATION
Single Output Two-Phase Operation
For high power applications, the two buck channels can
be operated in a two-phase single output configuration.
The buck channels switch 180° out-of-phase, which
reduces the required output capacitance in addition to
the required input capacitance and power supply induced
noise. To configure the LTC7817 for two-phase operation,
tie VFB2 to INTVCC, ITH2 to ground, and RUN2 to RUN1.
The RUN1, VFB1, ITH1, TRACK/SS1 pins are then used
to control both buck channels, but each channel uses its
own ICMP and IR comparators to monitor their respective inductor currents. Figure 11 is a typical application
configured for single output two-phase operation.
INTVCC Regulators
The LTC7817 features two separate internal low dropout
linear regulators (LDOs) that supply power at the INTVCC
pin from either the VBIAS pin or the EXTVCC pin depending
on the EXTVCC pin voltage. INTVCC powers the MOSFET
gate drivers and most of the internal circuitry. The VBIAS
LDO and the EXTVCC LDO each regulate INTVCC to 5.1V
and can provide a peak current of at least 100mA.
The INTVCC pin must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor, placed as close as
possible to the pin. An additional 1μF ceramic capacitor
placed directly adjacent to the INTVCC and GND pins is
also highly recommended to supply the high frequency
transient currents required by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7817 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.7V, the VBIAS LDO is enabled. Power dissipation for the IC in this case is equal to VBIAS • IINTVCC.
The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the LTC7817 INTVCC current
28
is limited to less than 44mA from a 36V supply when not
using the EXTVCC supply at a 70°C ambient temperature:
TJ = 70°C + (44mA)(36V)(34.7°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked
while operating in continuous conduction mode (PLLIN/
MODE = INTVCC) at maximum VBIAS.
When the voltage applied to EXTVCC rises above 4.7V, the
VBIAS LDO is turned off and the EXTVCC LDO is enabled.
The EXTVCC LDO remains on as long as the voltage applied
to EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.1V, so while EXTVCC
is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.1V (up to an absolute maximum of 30V),
INTVCC is regulated to 5.1V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC7817’s
switching regulator outputs (4.7V ≤ VOUT ≤ 30V) during
normal operation and from the VBIAS LDO when the output
is out of regulation (e.g., start-up, short-circuit). If more
current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. In this case, do not apply more
than 6V to the EXTVCC pin.
Significant efficiency and thermal gains can be realized by
powering INTVCC from a buck output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of VOUT/(VIN • Efficiency). For 5V to 30V
regulator outputs, this means connecting the EXTVCC pin
directly to VOUT. Tying the EXTVCC pin to an 8.5V supply
reduces the junction temperature in the previous example
from 125°C to:
TJ = 70°C + (44mA)(8.5V)(34.7°C/W) = 83°C
However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from
the output.
Rev A
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LTC7817
APPLICATIONS INFORMATION
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC grounded. This will cause INTVCC to be powered from the internal VBIAS LDO resulting in an efficiency penalty of up to 10% or more at high input
voltages.
2. EXTVCC connected directly to one of the buck regulator outputs. This is the normal connection for an
application with an output in the range of 5V to 30V
and provides the highest efficiency. If both buck outputs are in the 5V to 30V range, connect EXTVCC to
the lesser of the two outputs to maximize efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available, it may be used to power EXTVCC
provided that it is compatible with the MOSFET gate
drive requirements. This supply may be higher or
lower than VBIAS; however, a lower EXTVCC voltage
results in higher efficiency.
4. EXTVCC connected to an output-derived boost or
charge pump. For regulators where both of the buck
channel outputs are below 5V, efficiency gains can still
be realized by connecting EXTVCC to an output-derived
voltage that has been boosted to greater than 5.1V.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the
BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is
charged though external diode DB from INTVCC when the
SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns
on the topside switch. The switch node voltage, SW, rises
to VIN for the buck channels (VOUT for the boost channel)
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply: VBOOST = VIN
+ VINTVCC (or for the boost controller, VBOOST = VOUT +
VINTVCC). The value of the boost capacitor CB needs to be
100 times that of the total input capacitance of the topside
MOSFET(s). For a typical application, a value of CB = 0.1μF
is generally sufficient.
The external diode DB can be a Schottky diode or silicon diode, but in either case it should have low leakage
and fast recovery. The reverse breakdown of the diode
must be greater than VIN(MAX). Pay close attention to the
reverse leakage at high temperatures where it generally
increases substantially.
A leaky diode not only increases the quiescent current
of the buck converter, but it can create current path from
the BOOST pin to INTVCC. This will cause INTVCC to rise
if the diode leakage exceeds the current consumption on
INTVCC, which is primarily a concern in Burst Mode operation where the load on INTVCC can be very small. There
is an internal voltage clamp on INTVCC that prevents the
INTVCC voltage from running away, but this clamp should
be regarded as a failsafe only.
The topside MOSFET driver for the boost channel includes
an internal charge pump that delivers current to the bootstrap capacitor from the BOOST3 pin. This charge current maintains the bias voltage required to keep the top
MOSFET on continuously during dropout/overvoltage
conditions. Curves displaying the available charge pump
current under different operating conditions can be found
in the Typical Performance Characteristics section.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration that the LTC7817 is capable of turning on the top
MOSFET (or bottom MOSFET for the boost controller).
It is determined by internal timing delays and the gate
charge required to turn on the MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
tON(MIN)_BUCK <
VOUT
VIN • f
tON(MIN)_BOOST <
VOUT − VIN
VOUT • f
Rev A
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29
LTC7817
APPLICATIONS INFORMATION
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The minimum on-time for the LTC7817 is approximately 40ns for
the bucks and 80ns for the boost. However, as the peak
sense voltage decreases the minimum on-time for the
bucks gradually increases up to about 60ns. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If a buck output voltage rises 10% above the set regulation point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if VOUT
returns to a safe level, normal operation automatically
resumes.
Fault Conditions: Buck Current Limit and Foldback
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating (such as
a short from INTVCC to ground) internal overtemperature
shutdown circuitry will shut down the LTC7817. When
the internal die temperature exceeds 180°C, the INTVCC
LDO and gate drivers are disabled. When the die cools
to 160°C, the LTC7817 enables the INTVCC LDO and
resumes operation beginning with a soft-start startup.
Long-term overstress (TJ > 125°C) should be avoided
as it can degrade the performance or shorten the life of
the part.
The LTC7817 includes current foldback for the buck channels to reduce the load current when the output is shorted
to ground. If the output voltage falls below 50% of its
regulation point, then the maximum sense voltage is progressively lowered from 100% to 40% of its maximum
value. Under short-circuit conditions with very low duty
cycles, the LTC7817 will begin cycle skipping to limit the
short circuit current. In this situation the bottom MOSFET
dissipates most of the power but less than in normal operation. The short-circuit ripple current is determined by the
minimum on-time, tON(MIN) ≈ 40ns, the input voltage and
inductor value:
ΔIL(SC) = tON(MIN) • VIN/L
The resulting average short-circuit current is:
ISC = 40% • ILIM(MAX) − ΔIL(SC)/2
Fault Conditions: Buck Overvoltage Protection
(Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the controller is operating.
30
A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
Phase-Locked Loop and Frequency Synchronization
The LTC7817 has an internal phase-locked loop (PLL)
which allows the turn-on of the top MOSFET of controller 1 to be synchronized to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn on
of controller 2’s top MOSFET is thus 180° out of phase
with the external clock.
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. Before synchronization,
the PLL is prebiased to the frequency set by the FREQ
pin. Consequently, the PLL only needs to make minor
adjustments to achieve phase-lock and synchronization.
Although it is not required that the free-running frequency
be near the external clock frequency, doing so will prevent the oscillator from passing through a large range of
frequencies as the PLL locks.
Rev A
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APPLICATIONS INFORMATION
When synchronized to an external clock, the LTC7817
operates in forced continuous mode. The LTC7817 is
guaranteed to synchronize to an external clock applied to
the PLLIN/MODE pin that swings up to at least 2.5V and
down to 0.5V or less. Note that the LTC7817 can only be
synchronized to an external clock frequency within the
range of 100kHz to 3MHz.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7817 circuits: 1) IC VBIAS current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET transition losses.
1. The VBIAS current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Other than at
very light loads in burst mode, VBIAS current typically
results in a small (1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately CLOAD • 25μs/μF. Thus a 10μF capacitor
would require a 250μs rise time, limiting the charging
current to about 200mA.
Rev A
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LTC7817
APPLICATIONS INFORMATION
Buck Design Example
To allow for additional margin, a lower value RSENSE
may be used (for example, 1.8mΩ); however, be
sure that the inductor saturation current has sufficient margin above VSENSE(MAX)/RSENSE, where the
maximum value of 55mV is used for VSENSE(MAX).
For this low inductor value and high current application, an RC filter into the sense pins should be used
to compensate for the parasitic inductance (ESL) of
the sense resistor. Assuming an RSENSE geometry of
1225 with a parasitic inductance of 0.2nH, the RC filter
time constant should be RC = ESL/RSENSE = 0.2nH /
2mΩ = 100ns, which may be implemented with 100Ω
resistor in series with the SENSE+ pin and 1nF capacitor between SENSE+ and SENSE−.
As a design example for one of the buck channels,
assume VIN(NOMINAL) = 12V, VIN(MAX) = 22V, VOUT = 3.3V,
IOUT = 20A, and fSW = 1MHz.
1. Set the operating frequency. The frequency is not one
of the internal preset values, so a resistor from the
FREQ pin to GND is required, with a value of:
37MHz
= 37kΩ
1MHz
2. Determine the inductor value. Initially select a value
based on an inductor ripple current of 30%. The
inductor value can then be calculated from the following equation:
VOUT ⎛
VOUT ⎞
L=
⎜ 1–
⎟ = 0.4µH
fSW ( ΔIL ) ⎝ VIN(NOM) ⎠
RFREQ (in kΩ) =
The highest value of ripple current occurs at the maximum input voltage. In this case the ripple at VIN = 22V
is 35%
3. Verify that the minimum on-time of 40ns is not violated. The minimum on-time occurs at VIN(MAX):
tON(MIN) =
VOUT
VIN(MAX)(fSW )
= 150ns
This is more than sufficient to satisfy the minimum
on time requirement. If the minimum on time is violated, the LTC7817 skips pulses at high input voltage, resulting in lower frequency operation and higher
inductor current ripple than desired. If undesirable,
this behavior can be avoided by decreasing the frequency (with the inductor value accordingly adjusted)
to avoid operation near the minimum on-time.
4. Select the RSENSE resistor value. The peak inductor
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
in this case. The RSENSE resistor value can then be
calculated based on the minimum value for the maximum current sense threshold (45mV):
45mV
RSENSE ≤
≅ 2mΩ
23A
5. Select the feedback resistors. If very light load efficiency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
RA = 0.8V/50μA = 16kΩ. RB can then be calculated
as RB = RA(3.3V/0.8V – 1) = 50kΩ.
6. Select the MOSFETs. The best way to evaluate
MOSFET performance in a particular application is
to build and test the circuit on the bench, facilitated
by an LTC7817 demo board. However, an educated
guess about the application is helpful to initially select
MOSFETs. Since this is a high current, low voltage
application, I2R losses will likely dominate over transition losses for the top MOSFET. Therefore, choose
a MOSFET with lower RDS(ON) as opposed to lower
gate charge to minimize the combined loss terms.
The bottom MOSFET does not experience transition
losses, and its power loss is generally dominated by
I2R losses. For this reason, the bottom MOSFET is
typically chosen to be of lower RDS(ON) and subsequently higher gate charge than the top MOSFET.
Due to the high current in this application, two
MOSFETs may be needed in parallel to more evenly
balance the dissipated power and to lower the RDS(ON).
Be sure to select logic-level threshold MOSFETs, since
the gate drive voltage is limited to 5.1V (INTVCC).
Rev A
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33
LTC7817
APPLICATIONS INFORMATION
7. Select the input and output capacitors. CIN is chosen
for an RMS current rating of at least 10A (IOUT/2, with
margin) at temperature assuming only this channel is
on. COUT is chosen with an ESR of 3mΩ for low output ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple
due to ESR is approximately:
VORIPPLE = ESR • ∆IL = 3mΩ • 6A = 18mVP-P
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
8. Determine the bias supply components. Since the
regulated output is not greater than the EXTVCC switchover threshold (4.7V), it cannot be used to bias
INTVCC. However, if another supply is available, for
example if the other buck channel is regulating to
5V, connect that supply to EXTVCC to improve the
efficiency. For an 6.5ms soft start, select a 0.1μF
capacitor for the TRACK/SS pin. As a first pass estimate for the bias components, select CINTVCC = 4.7μF,
boost supply capacitor CB = 0.1μF and low forward
drop boost supply diode CMDSH-4E from Central
Semiconductor.
9. Determine and set application-specific parameters.
Set the PLLIN/MODE pin based on the trade-off of
light load efficiency and constant frequency operation. The RUN pin can be used to control the minimum input voltage for regulator operation or can be
tied to VIN for always-on operation. Use ITH compensation components from the typical applications as a
first guess, check the transient response for stability,
and modify as necessary.
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN?
Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET
and the CIN capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the
(–) terminals of the input capacitor by placing the
capacitors next to each other and away from the loop
described above.
3. Do the LTC7817 VFB pins’ resistive dividers connect
to the (+) terminals of COUT? The resistive divider
must be connected between the (+) terminal of COUT
and signal ground. Place the divider close to the VFB
pin to minimize noise coupling into the sensitive VFB
node. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? Route these traces
away from the high frequency switching nodes, on
an inner layer if possible. The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
PC Board Layout Checklist
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pin? This capacitor carries the MOSFET drivers’
current peaks. An additional 1μF ceramic capacitor
placed immediately next to the INTVCC and GND pins
can help improve noise performance substantially.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 9 illustrates the current waveforms present
in the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
6. Keep the switching nodes (SW1, SW2, SW3), top gate
nodes (TG1, TG2, TG3), and boost nodes (BOOST1,
BOOST2, BOOST3) away from sensitive small-signal
nodes, especially from the other channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast-moving signals and therefore
34
Rev A
For more information www.analog.com
LTC7817
APPLICATIONS INFORMATION
should be kept on the output side of the LTC7817 and
occupy minimum PC trace area. Minimize the inductance of the TG and BG gate drive traces and their
respective return paths to the controller IC (SW and
GND) by using wide traces and multiple parallel vias.
7. Use a modified star ground technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback resistive divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
threshold—typically 25% of the maximum designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its individual performance should both controllers be turned on
at the same time. A particularly difficult region of operation is when one controller channel is nearing its current
comparator trip point when the other channel is turning
on its top MOSFET. This occurs around 50% duty cycle
on either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation. Investigate
whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for inductive
coupling between CIN, the top MOSFET, and the bottom
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Rev A
For more information www.analog.com
35
LTC7817
APPLICATIONS INFORMATION
SW1
L1
RSENSE1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW2
L2
RSENSE2
VOUT2
COUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
RL2
7817 F09
Figure 9. Branch Current Waveforms for Bucks
36
Rev A
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
INTVCC
VBIAS
D3
RUN1 RUN2 RUN3
VFB3
MTOP3
VIN
1V TO 38V*
(>5V START-UP)
CIN
100µF
1.4µH
10µF
x3
MBOT3
1nF
L1
0.1µF
SW3
2mΩ
0.9µH
BG1
BG3
1nF
SENSE1+
SENSE1–
VFB1
SENSE3
210k
INTVCC
68.1k
D2 VOUT3
PGOOD1
INTVCC
TG2
BOOST2
INTVCC
VPRG3
11k
3.3nF
100pF
1.9k
VOUT2
5V/10A
BG2
MBOT2
100µF
x2
1nF
SGND
COUT2
330µF
357k
TRACK/SS1
TRACK/SS2
SS3
220pF
22nF
3.3nF
3mΩ
1.8µH
SENSE2+
SENSE2–
EXTVCC
VFB2
ITH1
ITH2
ITH3
100pF
L2
0.1µF
FREQ
PLLIN/MODE
4.5k
MTOP2
SW2
4.7µF
VOUT1
3.3V/12A
COUT1
330µF
100µF
x2
20Ω
MBOT1
LTC7817
SENSE3–
+
VOUT3
10V WHEN VIN10V
MTOP1
SW1
0.1µF
COUT3
150µF
10µF
x6
D1
TG1
BOOST1
TG3
BOOST3
L3
1.5mΩ
INTVCC
PGND
0.1µF
0.1µF
68.1k
0.1µF
7817 TA02
D1,2,3: CENTRAL SEMI CMDSH-4E
fSW = 380kHz
CIN: SUNCON 63CE100LX
COUT1,2: KEMET T520V337M006ATE015 * WHEN VIN < 4V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
COUT3: SUNCON 50HVPF150M
* OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES MAY BE LIMITED BY THE THERMAL
CHARACTERISTICS OF THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN
MTOP1,2: INFINEON BSC059N04LS6
MBOT1,2: INFINEON BSC022N04LS6
MTOP3: INFINEON BSC022N04LS6
MBOT3: INFINEON BSC059N04LS6
L1: WURTH 744355090
L2: WURTH 744313180
L3: WURTH 7443550140
(10a)
No-Load
No–LoadBurst
BurstMode
ModeInput
Input Current
Current
vs
Input
vs Input Voltage Voltage
Efficiency
vs Load
Load Current
Current
Efficiency vs
98
70
ALL THREE CHANNELS ON
VIN CURRENT (μA)
EFFICIENCY (%)
GND
94
92
90
VOUT1 = 3.3V
88
86
VOUT1
2V/DIV
Only Channel 1 On
All Channels On
60
96
Short-Circuit
Short–CircuitResponse
Response
VOUT2 = 5V
VIN=12V
VIN=24V
0
2
4
6
8
LOAD CURRENT (A)
(10b)
40
INDUCTOR
CURRENT
5A/DIV
30
20
0A
10
VIN=12V
VIN=24V
10
50
12
7817 F10b
0
5
10
15
20
25
30
VIN VOLTAGE (V)
(10c)
35
VIN = 12V
ILOAD = 12A
200µs/DIV
7817 F10d
40
7817 F10c
(10d)
Figure 10. High Efficiency Wide Input Range Dual 5V/3.3V Regulator
Rev A
For more information www.analog.com
37
LTC7817
TYPICAL APPLICATIONS
VIN
12V NOMINAL
4.5V-38V
CIN
100µF
VBIAS
10µF
x4
SENSE3+
10µF
x2
MBOT1
TG3
VFB3
VOUT1
5V/30A
INTVCC
PGOOD1
VPRG3
INTVCC
VFB2
TG2
BOOST2
ITH1
ITH3
47pF
3.65k
1nF
TRACK/SS2
ITH2
SGND
100pF
4.7nF
L2
0.1µF
PLLIN/MODE
COUT1
220µF
MTOP2
SW2
FREQ
100µF
x2
1nF
VIN
D2
27.4k
4.7µF
1nF
SENSE1+
SENSE1–
SENSE2–
SENSE2+
BG3
INTVCC
2mΩ
1µH
LTC7817
10pF
2k
L1
0.1µF
BG1
SW3
MBOT3
523k
MTOP1
SW1
BOOST3
0.1µF
MTOP3
VOUT3
24V/2A
D1
SENSE3–
INTVCC D3
L3
4.7µH
INTVCC
TG1
BOOST1
1nF
4mΩ
COUT3
47µF
RUN1 RUN2 RUN3
1µH
BG2
2mΩ
MBOT2
10pF
EXTVCC
VFB1
TRACK/SS1
SS3
PGND
357k
68.1k
0.1µF
0.22µF
7817 TA03
MTOP1,2: INFINEON BSC059N04LS6
MBOT1,2: INFINEON BSC022N04LS6
MTOP3: INFINEON BSC059N04LS6
MBOT3: INFINEON BSC059N04LS6
L1,2: COILCRAFT XAL1580-102ME
L3: COILCRAFT XAL1010-472ME
D1,2,3: CENTRAL SEMI CMDSH-4E
CIN: SUNCON 63HVPF100M
COUT1: PANASONIC 6TPF220M5L
COUT3: SUNCON 63CE47LX
fSW=380kHz
VOUT1 FOLLOWS VIN WHEN VIN < 5V
VOUT3 FOLLOWS VIN WHEN VIN > 24V
(11a)
Two-Phase
Two–PhaseBuck
BuckLoad Step
Transient
Load StepResponse
Transient Response
Efficiency
vs Load
Load Current
Current
Efficiency vs
L1 INDUCTOR
CURRENT
10A/DIV
L2 INDUCTOR
CURRENT
10A/DIV
20µs/DIV
VIN = 15V
10A TO 30A LOAD STEP
7817 F11b
100
95
98
90
96
EFFICIENCY (%)
EFFICIENCY (%)
VOUT1
500mV/DIV
Efficiency vs Input Voltage
100
85
80
Buck
75
70
0.001
VIN=10V
VIN=20V
0.01
Boost
VIN=10V
VIN=20V
0.1
1
LOAD CURRENT (A)
10
(11c)
92
Buck, ILOAD=5A
Buck, ILOAD=20A
Boost, ILOAD=2A
90
30
7817 F11c
(11b)
94
88
5
10
15
20
25
30
VIN INPUT VOLTAGE (V)
35
40
7817 F11d
(11d)
Figure 11. High Efficiency 380kHz Wide Input Range 24V/2A Boost and Two-Phase 5V/30A Buck Regulator
38
Rev A
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
VBIAS
RUN1 RUN2 RUN3
VFB3
INTVCC
2mΩ
TG3
BOOST3
L3
10µF
MBOT3
1nF
3k
11.2k
10nF
2.2nF
TG1
BOOST1
MTOP1
L1
0.1µF
SW1
FREQ
PLLIN/MODE
6mΩ
VOUT1
5V / 5A
3.3µH
BG1
MBOT1
47µF
x2
1nF
SENSE1+
SENSE1–
EXTVCC
VFB1
357k
TRACK/SS1
TRACK/SS2
SS3
SGND
10nF
26.1k
D1 VOUT2
47pF
47pF
499k
INTVCC
ITH1
ITH2
ITH3
47pF
1nF
SENSE2
VFB2
PGOOD1
VPRG3
INTVCC
4.7µF
COUT2
100µF
22µF
MBOT2
SENSE2+
–
BG3
INTVCC
VOUT2
10V TO 16V*
8A**
3mΩ
LTC7817
SENSE3–
SENSE3+
5k
L2
3.3µH
BG2
SW3
VOUT3
10V TO 38V***
MTOP2
SW2
0.1µF
1µH
CIN
33µF
D2
0.1µF
MTOP3
COUT3
150µF
6.8µF
x4
TG2
BOOST2
D3
VIN
1V TO 38V
(>5V START-UP)
INTVCC
PGND
10nF
0.1µF
10pF
68.1k
0.1µF
7817 TA04
MTOP1: INFINEON BSZ088N03MS
MBOT1: INFINEON BSZ088N03MS
MTOP2: INFINEON BSC059N04LS6
MBOT2: INFINEON BSC007N04LS6
MTOP3: INFINEON BSC007N04LS6
MBOT3: INFINEON BSC059N04LS6
D1,2,3: CENTRAL SEMI CMDSH-4E
CIN: SUNCON 50HVH33M
COUT2: KEMET T521X107M025ATE060
COUT3: SUNCON 50HVPF150M
L1: WURTH 744325330
L2: WURTH 74439369033
L3: WURTH 7443320100
fSW=380kHz
* VOUT2 = 10V WHEN VIN < 10V
VOUT2 = 16V WHEN VIN > 16V
VOUT2 FOLLOWS VIN WHEN VIN IS 10V TO 16V
** WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
*** VOUT3 = 10V WHEN VIN < 10V
VOUT3 FOLLOWS VIN WHEN VIN > 10V
(12a)
Output
Output Voltage
Voltage vs
vs Input
Input Voltage
Voltage
40
VVOUT1 Efficiency
Efficiency vs
vs Input
Input Voltage
Voltage
BURST MODE OPERATION
95 VOUT1 = 5V
VOUT3
90
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
35
30
25
20
VOUT2
15
10
ILOAD = 5A
85
ILOAD = 1A
80
75
70
VOUT1
5
0
OUT1
100
ILOAD = 100mA
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
65
35
40
60
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
7817 F12b
(12b)
35
40
7817 F12c
(12c)
Figure 12. Wide Input Range 10V-16V PassThru Cascaded Regulator and 5V Buck Regulator
Rev A
For more information www.analog.com
39
LTC7817
TYPICAL APPLICATIONS
499k
VBIAS
RUN1 RUN2 RUN3
VFB3
INTVCC
MTOP2
L2
0.1µF
MTOP3
L3
1.5mΩ
VIN(VBATT)
12V NOMINAL
1V TO 38V
(>5V START-UP)
TG3
BOOST3
0.68µH
10µF
x2
CIN
56µF
3mΩ
2.2µH
BG2
SW3
MBOT3
1nF
SW2
0.1µF
10µF
x2
MBOT2
SENSE2+
SENSE2–
EXTVCC
VFB2
SENSE3–
SENSE3+
COUT2
47µF
VOUT2
12V/8A*
1nF
LTC7817
BG3
VOUT3
16V**
COUT3
150µF
10µF
x4
D2
TG2
BOOST2
40.2k
D3
INTVCC
499k
35.7k
INTVCC
D1 VOUT3
PGOOD1
VPRG3
INTVCC
FREQ
INTVCC
4.7µF
TG1
BOOST1
75k
6.8nF
6k
47pF
3.3nF
7.6k
100µF
x2
MBOT1
47µF
215k
TRACK/SS1
TRACK/SS2
SS3
SGND
VOUT1
3.3V / 5A
1nF
SENSE1+
SENSE1–
VFB1
47pF
22nF
6mΩ
2.2µH
BG1
ITH1
ITH2
ITH3
47pF
L1
0.1µF
SW1
PLLIN/MODE
6k
MTOP1
68.1k
PGND
0.1µF
0.1µF
0.1µF
7817 TA05
MTOP1: INFINEON BSZ088N03MS
MBOT1: INFINEON BSZ088N03MS
MTOP2,3: INFINEON BSC059N04LS6
MBOT2,3: INFINEON BSC059N04LS6
D1,2,3: CENTRAL SEMI CMDSH-4E
CIN: SUNCON 50HVP56M
COUT2: KEMET T521W476M016ATE45
COUT3: SUNCON 50HVPF150M
L1: COILCRAFT XAL60300-222ME
L2: COILCRAFT XAL8080-222ME
L3: COILCRAFT XAL1010-681ME
fSW=500kHz
* WHEN VIN < 7V, MAXIMUM COMBINED LOAD CURRENT AVAILABLE IS REDUCED
** VOUT3 = 16V WHEN VIN < 16V
VOUT3 FOLLOWS VIN WHEN VIN > 16V
(13a)
18
Typical Current
Current Limit
Limit
VOUT2 Typical
V
OUT2
vs
V
Input
Voltage
IN
vs VIN Input Voltage
Cold
Cold Crank
Crank Transient
Transient Response
Respone
18V
VOUT3
95
14
10
VOLTAGE
2V/DIV
8
VBATT
6
BURST MODE OPERATION
ALL CHANNELS ON
VOUT2 = 12V
85
80
75
70
4
VOUT1
2
0
VVOUT2
Efficiency vs Load Current
OUT2 Efficiency vs Load Current
90
VOUT2
12
EFFICIENCY (%)
VOUT2 CURRENT LIMIT (A)
ALL CHANNELS ON
16 IOUT1 = NO LOAD
100
0
2
4
6
8
VIN VOLTAGE (V)
(13b)
10
12
0V
TIME (10ms/DIV)
VIN = 8V
VIN = 12V
VIN = 24V
65
7817 F13c
60
0.001
7817 F13b
0.01
0.1
1
LOAD CURRENT (A)
10
7817 F13d
(13c)
(13d)
Figure 13. High Efficiency Wide Input Range 12V Regulator
40
Rev A
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
INTVCC
VBIAS
D3
RUN1 RUN2 RUN3
VFB3
MTOP3
×2
L3
2mΩ
VIN
1V TO 38V*
(>5V START-UP)
CIN
220µF
63V
10µF
x2
SENSE1+
SENSE1–
VFB1
1nF
210k
INTVCC
PGOOD1
TG2
BOOST2
INTVCC
FREQ
12.4k
47pF
680pF
47pF
7.68k
VOUT2
5V/7A
75Ω
MBOT2
10µF
1nF
SENSE2+
SENSE2–
EXTVCC
VFB2
SGND
PGND
COUT2
100µF
6.3V
357k
TRACK/SS1
TRACK/SS2
SS3
220pF
6.8nF
2.2nF
5mΩ
0.33µH
BG2
ITH1
ITH2
ITH3
9.3k
L2
0.1µF
VPRG3
PLLIN/MODE
47pF
MTOP2
SW2
4.7µF
VOUT1
3.3V/10A
68.1k
D2 VOUT3
INTVCC
COUT1
150µF
4V
4.7µF
x4
100Ω
MBOT1
LTC7817
SENSE3–
SENSE3+
VOUT3
8V WHEN VIN8V
3mΩ
0.16µH
BG1
BG3
L1
0.1µF
SW3
MBOT3
1nF
MTOP1
SW1
0.1µF
COUT3
68µF
50V
10µF
x3
D1
TG1
BOOST1
TG3
BOOST3
0.16µH
INTVCC
0.1µF
0.1µF
68.1k
0.1µF
7817 TA06
MTOP1,2: INFINEON BSC093N04LS
MBOT1,2: INFINEON BSC093N04LS
MTOP3 (x2): INFINEON BSC027N04LS
MBOT3: INFINEON BSC059N04LS
L1,3: COILCRAFT XAL5030-161ME
L2: COILCRAFT XAL5030-331ME
D1,2,3: INFINEON BAS140WE6327HTSA1
fSW=2.25MHz
CIN: SUNCON 63CE220LX
* WHEN VIN < 4V, MAXIMUM COMBINED LOAD CURRENT AVAILABLE IS REDUCED
COUT1: KEMET T520B157M004ATE015
* OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES MAY BE LIMITED BY THE THERMAL
COUT2: KEMET T520B107M006APE070
CHARACTERISTICS OF THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN
COUT3: PANASONIC 50SVPF68M
(14a)
Efficiency
Efficiency and
and Power
Power Loss
Loss vs
Load
Current
vs Load
Current
VIN = 12V
EFFICIENCY (%)
EFFICIENCY
50
1
POWER LOSS
40
0.1
30
0.01
20
10
0
0.0001
ALL THREE CHANNELS ON
BURST MODE OPERATION
0.001
0.01
0.1
LOAD CURRENT (A)
(14b)
1
10
7817 F14b
0.001
POWER LOSS (W)
60
10
VOUT1 = 3.3V
100
VIN = 24V
35 IOUT1 = 4A
VOUT2 = 5V
80
70
40
OUT1
90
80
30
25
EFFICIENCY (%)
90
Efficiency
vs Input
Input Voltage
Voltage
Efficiency vs
V
VOUT1 Switch
Switch Node
Node Waveform
Waveform
100
SWITCH NODE VOLTAGE
100
20
15
10
70
60
50
40
5
20
0
10
–5
0
100ns/Div
7817 F14c
ALL THREE CHANNELS ON
BURST MODE OPERATION
VOUT2 = 5V
VOUT1 = 3.3V
30
IOUT1 = 100mA
IOUT1 = 5A
0
5
(14c)
Figure 14. High Efficiency Wide Input Range 2.25MHz Dual 5V/3.3V Regulator
For more information www.analog.com
10
IOUT2 = 100mA
IOUT2 = 5A
15 20 25 30
VIN VOLTAGE (V)
(14d)
35
40
7817 F14d
Rev A
41
LTC7817
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
5.15 ±0.05
4.10 ±0.05
3.00 REF
3.15 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
0.75 ±0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ±0.10
5.50 REF
7.00 ±0.10
3.15 ±0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ±0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
42
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev A
For more information www.analog.com
LTC7817
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/21
Added AEC-Q100 Qualified for Automotive Applications.
PAGE NUMBER
1
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
43
LTC7817
TYPICAL APPLICATION
INTVCC
VBIAS
D3
RUN1 RUN2 RUN3
VFB3
MTOP3
VIN
1V TO 38V*
(>5V START-UP)
CIN
220µF
63V
0.16µH
10µF
x2
SW3
MBOT3
1nF
SENSE1+
SENSE1–
VFB1
2mΩ
1nF
PGOOD1
4.7µF
INTVCC
FREQ
VPRG3
PLLIN/MODE
INTVCC
7.5k
47pF
5.5k
4.7nF
3.3nF
47pF
13.1k
TG2
BOOST2
68.1k
MTOP2
0.1µF
SW2
9mΩ
VOUT2
8.5V/3A
50Ω
MBOT2
47µF
1nF
SENSE2+
SENSE2–
EXTVCC
VFB2
200k
TRACK/SS1
TRACK/SS2
SS3
47pF
SGND
4.7nF
L2
1.2µH
BG2
ITH1
ITH2
ITH3
VOUT1
3.3V/10A
210k
D2 VOUT3
INTVCC
COUT1
100µF
x2
10µF
100Ω
MBOT1
LTC7817
SENSE3–
SENSE3+
VOUT3
10V WHEN VIN < 10V
FOLLOWS VIN WHEN VIN > 10V
0.16µH
BG1
BG3
L1
0.1µF
SW1
0.1µF
COUT3
82µF
50V
10µF
x3
MTOP1
x2
D1
TG1
BOOST1
TG3
BOOST3
L3
2mΩ
INTVCC
PGND
0.1µF
0.1µF
20.8k
0.1µF
7817 TA07
MTOP1,2: VISHAY SiR836DP
MBOT1,2: VISHAY SiR836DP
MTOP3: VISHAY SiR640DP
MBOT3: VISHAY SiR640DP
D1,2,3: CENTRAL SEMI CMDSH-4E
L1,3: COILCRAFT XAL5030-161ME
L2: COILCRAFT XAL5030-122ME
CIN: SUNCON 63CE220LX
COUT1: PANASONIC 6TPE100MPB
COUT3: PANASONIC 50SVPF82M
fSW=2.25MHz
* WHEN VIN < 4V, MAXIMUM COMBINED LOAD CURRENT AVAILABLE IS REDUCED
* OUTPUT CURRENT CAPABILITY AT HIGH INPUT VOLTAGES MAY BE LIMITED BY THE THERMAL
CHARACTERISTICS OF THE OVERALL SYSTEM AND PRINTED CIRCUIT BOARD DESIGN
Figure 15. High Efficiency Wide Input Range 2.25MHz Dual 3.3V/8.5V Regulator
RELATED PARTS
PART NUMBER DESCRIPTION
LTC7818
LTC7804
LTC7803
LTC7815
LTC3859AL
LTC3899
LTC7800
LTC3892
44
COMMENTS
40V, Low IQ, 3MHz, Triple Output Buck/Buck/Boost
Synchronous Controller with Spread Spectrum
40V Low IQ, 3MHz Synchronous Boost Controller
100% Duty Cycle Capable
40V Low IQ, 3MHz 100% Duty Cycle Synchronous
Step-Down Controller
38V Low IQ, Triple Output, Buck/Buck/Boost Synchronous
Controller PLL Fixed Operating Frequency 320kHz to 2.25MHz
38V Low IQ, Triple Output, Buck/Buck/Boost Synchronous
Controller PLL Fixed Operating Frequency 50kHz to 900kHz
60V Low IQ, Triple Output, Buck/Buck/Boost Synchronous
Controller PLL Fixed Operating Frequency 50kHz to 900kHz
60V Low IQ, High Frequency Synchronous Step-Down
Controller
60V Low IQ, Dual 2-Phase Synchronous Step-Down
Controller with Adjustable Gate Drive Voltage
4.5V ≤ VIN ≤ 40V, IQ = 14µA, 100% Duty Cycle Capable Boost
Buck and Boost VOUT Up to 40V, PLL Fixed Frequency 100kHZ to 3MHz
4.5V(Down to 1V after Start-up) ≤ VIN ≤ 40V, VOUT up to 40V, IQ = 14µA
PLL Fixed Frequency 100kHZ to 3MHHz, 3mm x 3mm QFN-16, MSOP-16E
4.4V≤ VIN ≤ 40V, 0.8V ≤ VOUT ≤ 40V, IQ = 12µA
PLL Fixed Operating Frequency 50kHz to 900kHz
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, IQ = 28μA
Buck VOUT Range: 0.8V to 24V, Boost VOUT Up to 60V
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, IQ = 28μA
Buck VOUT Range: 0.8V to 24V, Boost VOUT Up to 60V
4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, IQ = 28μA
Buck & Boost VOUT Up to 60V
4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50μA
PLL Fixed Frequency 320kHz to 2.25MHz
4.5V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, IQ = 50μA
PLL Fixed Frequency 50kHz to 900kHz
Rev A
09/21
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For more information www.analog.com
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