LTC7871
Six-Phase, Synchronous Bidirectional
Buck or Boost Controller
FEATURES
DESCRIPTION
Unique Architecture Allows Dynamic Regulation of
Input Voltage, Output Voltage or Current
n Operates with External Gate Drivers and MOSFETs
n V
HIGH Voltages Up to 100V; VLOW Voltages Up to 60V
n Synchronous Rectification: Up to 98% Efficiency
n ADI-Proprietary Advanced Current Mode Control
n ±1% Voltage Regulation Accuracy Overtemperature
n Accurate, Programmable Inductor Current
Monitoring and Bidirectional Regulation
n SPI Compliant Serial Interface
n Operation Status and Fault Report
n Programmable V
HIGH, VLOW Margining
n Phase-Lockable Frequency: 60kHz to 750kHz
n Optional Spread Spectrum Modulation
n Multiphase/Multi-ICs Operation Up to 24 Phases
n Selectable CCM/DCM/Burst Mode Operation
n Thermally Enhanced 64-Lead LQFP Package
n AEC-Q100 Qualification in Progress
The LTC®7871 is a high performance bidirectional buck or
boost switching regulator controller that operates in either
buck or boost mode on demand. It regulates in buck mode
from VHIGH-to-VLOW and boost mode from VLOW-to-VHIGH
depending on a control signal, making it ideal for 48V/12V
automotive dual battery systems. An accurate current programming loop regulates the maximum current that can
be delivered in either direction. The LTC7871 allows both
batteries to supply energy to the load simultaneously by
driving energy from either battery to the other.
APPLICATIONS
The LTC7871 is available in a 64 pin 10mm × 10mm
LWE package.
n
n
n
Its proprietary constant frequency current mode architecture enhances the signal-to-noise ratio enabling low
noise operation and provides excellent current matching between phases. Additional features include an SPIcompliant serial interface, discontinuous or continuous
mode of operation, OV/UV monitors, independent loop
compensation for buck and boost operation, accurate
inductor current monitoring and overcurrent protection.
Automotive 48V/12V Dual Battery Systems
Backup Power Systems
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
High Voltage Bidirectional Controller with Programming and Monitoring Functions
VHIGH
30V TO
70V
2.2µF
×12
+
33µF
×12
3.01M
210k
499k
12.7k
2.2Ω
48.7k
10k
47pF
1µF
OVHIGH
UVHIGH
VFBHIGH
VHIGH
VFBLOW
OVLOW
EXTVCC
PWM1
499Ω
499Ω
16.9k
LTC7060
0.33µF
ITHHIGH
45.3k
100pF
0.1µF
51k
4.7µF
4.7µF
37.4k
BUCK BOOST
NOTE: SDO REQUIRES PULL-UP
Document Feedback
6.8µH
DRIVER
1nF
LTC7871
0.1µF
10k
VHIGH
SPI
INTERFACE
ITHLOW
IMON
SS
SETCUR
DRVCC
V5
PWMEN
1.5k
0.1µF
1.69k
SNSA1+
SNSD1+
SNS1–
VHIGH
PWM6
DRIVER
6.8µH
16.9k
LTC7060
SNSA6+
SNSD6+
SNS6–
22µF
×6
+
VLOW
12V/180A
100µF
×6
BUCK
5V/DIV
VLOW
2V/DIV
IL
5A/DIV
VHIGH
2V/DIV
VSW
100V/DIV
50µs/DIV
(PHASE 2 TO PHASE 5)
FREQ
SGND
BUCK
SCLK
SDI
SDO
CSB
0.1µF
10k
90.9k
110k
1mΩ
Boost-to-Buck Transition
0.1µF
1mΩ
1.5k
7871 TA01b
PINS NOT USED
IN THIS CIRCUIT:
CLKOUT
DRVSET
MODE
ILIM
RUN
FAULT
PGOOD
0.1µF
1.69k
7871 TA01a
For more information www.analog.com
Rev. A
1
LTC7871
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application ................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Order Information.................................................................................................................. 3
Pin Configuration.................................................................................................................. 3
Electrical Characteristics......................................................................................................... 4
Typical Performance Characteristics........................................................................................... 8
Pin Functions......................................................................................................................10
Block Diagram.....................................................................................................................12
Operation..........................................................................................................................13
Applications Information........................................................................................................20
Serial Port.............................................................................................................................................................. 31
Serial Port Register Details.................................................................................................................................... 35
Typical Applications..............................................................................................................47
Package Description.............................................................................................................48
Revision History..................................................................................................................49
Typical Application...............................................................................................................50
Related Parts......................................................................................................................50
2
Rev. A
For more information www.analog.com
LTC7871
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SNSA6+
SNS6–
SNSD6+
SNSD5+
SNS5–
SNSA5+
SNSA4+
SNS4–
SNSD4+
NC
BUCK
FREQ
SYNC
MODE
CLKOUT
ILIM
TOP VIEW
SS 1
NC 2
VFBLOW 3
ITHLOW 4
SGND 5
ITHHIGH 6
VFBHIGH 7
NC 8
V5 9
IMON 10
SETCUR 11
NC 12
OVHIGH 13
UVHIGH 14
OVLOW 15
SGND 16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
SGND
VHIGH
NC
DRVCC
SGND
DRVSET
NC
EXTVCC
NC
SCLK
SDI
SDO
CSB
PWM6
FAULT
PWM5
PWM4
SNSA1+ 17
SNS1– 18
SNSD1+ 19
SNSD2+ 20
SNS2– 21
SNSA2+ 22
SNSA3+ 23
SNS3– 24
SNSD3+ 25
NC 26
RUN 27
PWMEN 28
PWM1 29
PGOOD 30
PWM2 31
PWM3 32
VHIGH ...................................................... –0.3V to 100V
Current Sense Voltages
(SNSD+, SNSA+, SNS– Phase 1 to 6) .... –0.3V to 60V
(SNSA+ – SNS–) .................................. –0.3V to 0.3V
(SNSD+ – SNS–) .................................. –0.3V to 0.3V
EXTVCC ..................................................... –0.3V to 60V
DRVCC ........................................................ –0.3V to 11V
RUN, OVHIGH, UVHIGH, OVLOW ..................... –0.3V to 6V
V5 ............................................................... –0.3V to 6V
SCLK, SDI, SDO, CSB................................... –0.3V to 6V
PWM1, PWM2, PWM3
PWM4, PWM5, PWM6, PWMEN.............. –0.3V to V5
ITHHIGH, ITHLOW, VFBHIGH, VFBLOW............. –0.3V to V5
FAULT, SETCUR, DRVSET, PGOOD............... –0.3V to V5
IMON, ILIM, SS, BUCK, MODE..................... –0.3V to V5
FREQ, SYNC, CLKOUT................................. –0.3V to V5
Operating Junction Temperature Range
(Notes 2, 3)........................................ –40°C to 150°C
Storage Temperature Range.................. –65°C to 150°C
DRVCC/EXTVCC Peak Current
(Guarantee by Design)......................................150mA
LWE PACKAGE
64-LEAD (10mm × 10mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 17°C/W
EXPOSED PAD (PIN 65) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION*
TEMPERATURE RANGE
LTC7871ELWE#PBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 125°C
LTC7871ILWE#PBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 125°C
LTC7871JLWE#PBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 150°C
LTC7871HLWE#PBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 150°C
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC7871ELWE#WPBF
LTC7871ILWE#WPBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 125°C
LTC7871JLWE#WPBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 150°C
LTC7871HLWE#WPBF
LTC7871
64-Lead (10mm × 10mm) Plastic LQFP
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
This product is available in 160-piece trays.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
For more information www.analog.com
3
LTC7871
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VHIGH = 48V, VRUN = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
100
V
Main Control Loops
VHIGH
VHIGH Supply Voltage Range
6
VLOW
VLOW Supply Voltage Range
VHIGH > 6V
60
V
VLOW Regulated Feedback Voltage
(Note 4); ITHLOW Voltage = 1.5V
l
1.188
1.200
1.212
V
VHIGH Regulated Feedback Voltage
(Note 4); ITHHIGH Voltage = 0.5V
l
1.188
1.200
1.212
V
VLOW EA Feedback Current
(Note 4)
–10
–40
nA
VHIGH EA Feedback Current
(Note 4)
–10
–40
nA
1.2
Reference Voltage Line Regulation
(Note 4); VHIGH = 7V to 80V
0.02
0.2
%
VHIGH/VLOW Voltage Load Regulation
Measured in Servo Loop, ∆ITH Voltage = 1.0V to 1.5V
Measured in Servo Loop, ∆ITH Voltage = 1.0V to 0.5V
0.01
–0.01
0.2
–0.2
%
%
gm–buck
Buck Mode Transconductance
Amplifier gm–buck
(Note 4) ITHLOW = 1.5V, Sink/Source 5µA
2
mmho
gm–boost
Boost Mode Transconductance
Amplifier gm–boost
(Note 4) ITHHIGH = 0.5V, Sink/Source 5µA
1
mmho
IQ
VHIGH DC Supply Current
(Note 5)
Shutdown Mode, VHIGH Supply Current VRUN = 0V; VHIGH = 48V
Shutdown Mode, VLOW Supply Current VRUN = 0V; VLOW = 12V
UVLO
DRVCC Undervoltage Lockout
Threshold
DRVCC Ramping Down, VDRVSET = VV5
DRVCC Ramping Down, VDRVSET = Float
DRVCC Ramping Down, VDRVSET = 0V
DRVCC Undervoltage Hysteresis
VDRVSET = Float, VV5
VDRVSET = 0V
V5 Undervoltage Lockout Threshold
V5 Ramping Down, VDRVSET = Float, VV5
V5 Ramping Down, VDRVSET = 0V
V5 Undervoltage Hysteresis
VDRVSET = Float, VV5
VDRVSET = 0V
RUN Pin On Threshold
VRUN Rising
6.9
4.8
3.9
4.2
3.9
1.1
RUN Pin Source Current
VRUN < 1.1V
RUN Pin Hysteresis Current
VRUN > 1.3V
l
Soft-Start Charging Current
VSS = 1.2V
BUCK Pin Input Threshold
VBUCK Rising
VBUCK Falling
BUCK Pin Pull-Up Resistance
BUCK Pin to V5
Buck Mode
Boost Mode
mA
µA
µA
7.2
5.0
4.1
7.5
5.2
4.3
V
V
V
4.4
4.1
V
V
4.6
4.3
0.2
0.5
l
Maximum Duty Cycle
16
0.8
0.5
RUN Pin On Hysteresis
ISS
10
30
20
1.22
V
V
V
V
1.35
V
80
mV
0.6
2
µA
2
6
µA
0.8
96
1.0
1.2
µA
2.2
1.7
V
V
200
kΩ
98
92
%
%
Current Monitoring and Regulation Functions
ISNSA+
SNSA+ Pins Input Current
±0.05
±1
µA
ISNSD+
SNSD+ Pins Input Current
±0.05
±1
µA
ISNS–
SNS– Pins Input Current
1
ILIM Pin Input Resistance
ISETCUR
SETCUR Pin Sourcing Current
100
MFR_IDAC_SETCUR = 0x00
l
15.0
16.0
IMON Current Proportional to VLOW at VILIM = Float, RSENSE = 3mΩ
Max Current
IMON Zero Current Voltage
4
mA
1.240
1.250
kΩ
17.0
µA
±10
%
1.260
V
Rev. A
For more information www.analog.com
LTC7871
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VHIGH = 48V, VRUN = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
Current Sense Pin Voltage
(VSNSD+ – VSNS–) to IMON Gain
VILIM = 0V, 1/4 VV5
VILIM = Float, 3/4 VV5, VV5
MIN
TYP
40
20
MAX
UNITS
V/V
V/V
Total DC Sense Signal Gain
DCR Configuration
5
V/V
Total DC Sense Signal Gain
RSENSE Configuration
4
V/V
VSENSE(MAX) Maximum Current Sense Threshold
(Buck and Boost Mode)
(DCR
Configuration)
VILIM = 0V
VILIM = 1/4 VV5
VILIM = Float
VILIM = 3/4 VV5
VILIM = VV5
l
l
l
l
l
6.5
17.0
27.0
36.0
44.0
10.0
20.0
30.0
40.0
50.0
13.5
23.0
33.0
44.0
56.0
mV
mV
mV
mV
mV
VSENSE(MAX) Maximum Current Sense Threshold
(Buck and Boost Mode)
(RSENSE
Configuration)
VILIM = 0V
VILIM = 1/4 VV5
VILIM = Float
VILIM = 3/4 VV5
VILIM = VV5
l
l
l
l
l
8.1
21.2
33.7
45.0
55.0
12.5
25.0
37.5
50.0
62.5
16.9
28.8
41.3
55.0
70.0
mV
mV
mV
mV
mV
VOCFT
Overcurrent Fault Threshold,
VSNSD+ – VSNS–
VILIM = 0V
VILIM = 1/4 VV5
VILIM = Float
VILIM = 3/4 VV5
VILIM = VV5
l
l
l
l
l
31.0
43.0
54.0
65.0
76.0
37.5
50.0
62.5
75.0
87.5
44.0
57.0
71.0
85.0
99.0
mV
mV
mV
mV
mV
VNOCFT
Negative Overcurrent Fault Threshold, VILIM = 0V
VSNSD+ – VSNS–
VILIM = 1/4 VV5
VILIM = Float
VILIM = 3/4 VV5
VILIM = VV5
l
l
l
l
l
–45.0
–58.0
–72.0
–86.0
–100.0
–37.5
–50.0
–62.5
–75.0
–87.5
–30.0
–42.0
–53.0
–64.0
–75.0
mV
mV
mV
mV
mV
Overcurrent Fault Threshold
Hysteresis, |VSNSD+ – VSNS–|
VILIM = 0V
VILIM = 1/4 VV5, Float, 3/4 VV5, VV5
25
31
mV
mV
DRVCC and V5 Linear Regulators
VDRVCC
DRVCC Regulation Voltage
12V < VEXTVCC < 60V, VDRVSET = VV5
12V < VEXTVCC < 60V, VDRVSET = Float
12V < VEXTVCC < 60V, VDRVSET = 0V
DRVCC Load Regulation
EXTVCC Switchover Voltage
9.5
7.6
4.8
10
8
5
10.5
8.4
5.2
V
V
V
IDRVCC = 0mA to 100mA, VEXTVCC = 14V
1.6
3.0
%
EXTVCC Ramping Positive, VDRVSET = VV5
EXTVCC Ramping Positive, VDRVSET = Float
EXTVCC Ramping Positive, VDRVSET = 0V
10.7
8.5
6.9
EXTVCC Hysteresis
V5
V
V
V
12
V5 Regulation Voltage
6V < VDRVCC < 10V
V5 Load Regulation
IV5 = 0mA to 20mA
4.8
%
5.0
5.2
V
0.5
1
%
–1
1
%
–64
63
µA
Current DACs (IDAC)
VHIGH/VLOW IDAC Accuracy
MFR_IDAC_VLOW/HIGH = 0x40 or 0x7F
VHIGH/VLOW IDAC Program Range
SETCUR IDAC Program Range
LSB
0
VHIGH/VLOW IDAC LSB
SETCUR IDAC LSB
31
1
1
µA
µA
µA
Oscillator and Phase-Locked Loop
IFREQ
FREQ Pin Output Current
19
20
21
Nominal Frequency
fLOW
Low Fixed Frequency
VSYNC = 0V, RFREQ = 51.1k
230
250
270
kHz
VSYNC = 0V, RFREQ = 27.4k
55
70
85
kHz
fHIGH
High Fixed Frequency
VSYNC = 0V, RFREQ = 105k
640
710
780
kHz
l
µA
Rev. A
For more information www.analog.com
5
LTC7871
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VHIGH = 48V, VRUN = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
Synchronizable Frequency
SYNC = External Clock
Spread Spectrum Frequency
Modulation Range
VSYNC = 5V, RFREQ = 51.1k, MFR_SSFM = 0x00
θ2 – θ1
Phase 2 Relative to Phase 1
MIN
l
MAX
UNITS
60
TYP
750
kHz
–12
12
%
180
Deg
θ3 – θ1
Phase 3 Relative to Phase 1
60
Deg
θ4 – θ1
Phase 4 Relative to Phase 1
240
Deg
θ5 – θ1
Phase 5 Relative to Phase 1
120
Deg
θ6 – θ1
Phase 6 Relative to Phase 1
300
Deg
θCLKOUT – θ1
CLKOUT Phase to Phase 1
30
Deg
V5
V
Clock Output High Voltage
ILOAD = 0.5mA
Clock Output Low Voltage
ILOAD = –0.5mA
SYNC Pin Input Threshold
SYNC Pin Rising
SYNC Pin Falling
V5 – 0.2
2
SYNC Pin Input Resistance
0.2
V
1.1
V
V
100
kΩ
Power Good and FAULT
PGOOD Voltage Low
IPGOOD = 2mA
PGOOD Leakage Current
VPGOOD = 5V
0.1
VFBHIGH/VFBLOW Ramping Negative
PGOOD Trip Level, VFBHIGH/VFBLOW
With Respect to the Regulated Voltage VFBHIGH/VFBLOW Ramping Positive
PGOOD Delay
PGOOD Pin High to Low
FAULT Voltage Low
IFAULT = 2mA
FAULT Voltage Leakage Current
VFAULT = 5V
FAULT Delay
FAULT Pin High to Low
±1
µA
%
%
40
0.1
µs
0.3
V
±1
µA
120
1.15
VOVLOW > 1.2V
1.2
µs
1.25
5
VHIGH OV Comparator Threshold
VHIGH OV Comparator Hysteresis
V
–10
10
VLOW OV Comparator Threshold
VLOW OV Comparator Hysteresis
0.3
1.15
VOVHIGH > 1.2V
1.2
µA
1.25
5
VHIGH UV Comparator Threshold
1.15
VHIGH UV Comparator Hysteresis
VUVHIGH < 1.2V
PWM Output High Voltage
ILOAD = 0.5mA
l
PWM Output Low Voltage
ILOAD = –0.5mA
l
1.2
V
V
µA
1.25
5
V
µA
PWM Outputs
V5 – 0.5
V
PWM Output Current in Hi-Z State
0.5
V
±5
µA
0.5
V
DIGITAL I/O: CSB, SCLK, SDI, SDO
VIL
Digital Input Low Voltage
Pins CSB, SCLK, SDI
VIH
Digital Input High Voltage
Pins CSB, SCLK, SDI
VOL
Digital Output Voltage Low
Pin SDO, Sinking 1mA
RCSB
CSB Pin Pull-Up Resistor
300
kΩ
RSCLK
SCLK Pin Pull-Down Resistor
300
kΩ
RSDI
SDI Pin Pull-Down Resistor
300
kΩ
6
1.8
V
0.3
V
Rev. A
For more information www.analog.com
LTC7871
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VHIGH = 48V, VRUN = 5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Interface Timing Characteristics (Refer to Timing Diagram in Figure 9 and 10)
tCKH
SCLK High Time
45
ns
tCSS
CSB Setup Time
40
ns
tCSH
CSB High Time
60
ns
tCS
SDI to SCLK Setup Time
40
ns
tCH
SDI to SCLK Hold Time
20
ns
tDO
SCLK to SDO Time
90
ns
tC%
SCLK Duty Cycle
45
fSCLK(MAX)
Maximum SCLK Frequency
5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7871 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC7871E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7871I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC7871J is guaranteed over the –40°C to 150°C
operating junction temperature range. The LTC7871H is guaranteed
over the full –40°C to 150°C operating junction temperature range. High
50
55
%
MHz
junction temperature degrades operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 17°C/W)
Note 4: The LTC7871 is tested in a feedback loop that servos VITHHIGH
and VITHLOW to a specified voltage and measures the resultant VFBHIGH,
VFBLOW, respectively.
Note 5: Dynamic supply current may be higher due to the loading current
at DRVCC linear regulator.
Rev. A
For more information www.analog.com
7
LTC7871
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency Buck Mode
Power Loss Buck Mode
100
VHIGH = 48V
VLOW = 12V
60 FIGURE
18 CIRCUIT
POWER LOSS (W)
90
85
80
75
70
VHIGH = 48V
VLOW = 12V
FIGURE 18 CIRCUIT
65
1
10
LOAD CURRENT (A)
95
90
50
EFFICIENCY (%)
95
EFFICIENCY (%)
Efficiency Boost Mode
70
100
60
TA = 25°C, unless otherwise noted.
40
30
20
0
1
10
LOAD CURRENT (A)
20
10
1.5
1.6
1.2
0.8
0.4
5
0.9
–45 –20
30 55 80 105 130 155
TEMPERATURE (°C)
1.200
1.198
30 55 80 105 130 155
TEMPERATURE (°C)
300
5.0
280
4.8
260
240
200
–45 –20
30 55 80 105 130 155
TEMPERATURE (°C)
Undervoltage Lockout
Threshold (V5) vs Temperature
RISING
4.6
4.4
4.2
220
1.196
5
7871 G06
UVLO THRESHOLD (V)
FREQUENCY (kHz)
REGULATED FEEDBACK VOLTAGE (V)
1.202
5
30 55 80 105 130 155
TEMPERATURE (°C)
7871 G07
8
1.1
Oscillator Frequency
vs Temperature
Temperature
VFBLOW
VFBHIGH
5
1.2
7871 G05
Regulated Feedback Voltage
vs Temperature
1.194
–45 –20
1.3
1.0
0
–45 –20
50
ON
OFF
1.4
7871 G04
1.204
RUN Pin Threshold
RUN PIN THRESHOLD (V)
SS PULL–UP CURRENT (µA)
POWER LOSS (W)
30
50
vs Temperature
RUN
Pin Threshold vs Temperature
2.0
40
1
10
LOAD CURRENT (A)
7871 G03
SS Pin Pull-Up Current
60
1.206
60
0.1
100 200
vs Temperature
Temperature
VHIGH = 48V
VLOW = 12V
50 FIGURE 18 CIRCUIT
VHIGH = 48V
VLOW = 12V
FIGURE 18 CIRCUIT
7871 G02
Power Loss Boost Mode
1
10
LOAD CURRENT (A)
75
65
7871 G01
0
0.1
80
70
10
100 200
85
7871 G08
4.0
–45 –20
5
30 55 80 105 130 155
TEMPERATURE (°C)
7871 G09
Rev. A
For more information www.analog.com
LTC7871
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs Temperature
13.0
TA = 25°C, unless otherwise noted.
FREQ Pin Source Current
vs Temperature
vs Temperature
Shutdown Current vs Temperature
60.0
VHIGH = 48V
21.5
VHIGH = 48V
21.0
11.0
10.0
9.0
50.0
FREQ PIN CURRENT (µA)
SHUTDOWN CURRENT (µA)
QUIESCENT CURRENT (mA)
12.0
40.0
30.0
5
20.0
–45 –20
30 55 80 105 130 155
TEMPERATURE (°C)
5
50
16.8
40
16.4
16.2
16.0
15.8
15.6
15.4
15.2
15.0
–45 –20
5
30 55 80 105 130 155
TEMPERATURE (°C)
70
GND
1/4 V5
FLOAT
3/4 V5
V5
30
20
10
0
–10
–20
–30
80
0
0.5
1
1.5
ITH VOLTAGE (V)
10
–10
–30
–50
GND
1/4 V5
FLOAT
3/4 V5
V5
60
50
40
30
20
10
0
0.5
1
1.5
ITH VOLTAGE (V)
2
30
20
0
2
0
0.2
0
0
0.2
0.4
0.6
0.8
1.0
FEEDBACK VOLTAGE (V)
1.2
7871 G17
7871 G16
0.4
0.6
0.8
1.0
FEEDBACK VOLTAGE (V)
1.2
7871 G15
Maximum Current Sense
Threshold vs Feedback Voltage—
BUCK (RSENSE)
70
MAX CURRENT SENSE (mV)
30
40
7871 G14
Current Sense Threshold
vs ITH Voltage—(R
vs ITH Voltage (RSENSE
))
SENSE
GND
1/4 V5
FLOAT
3/4 V5
V5
50
10
–40
–50
GND
1/4 V5
FLOAT
3/4 V5
V5
60
7871 G13
50
Maximum Current Sense
Threshold vs Feedback Voltage—
BUCK (DCR)
MAX CURRENT SENSE (mV)
17.0
30 55 80 105 130 155
TEMPERATURE (°C)
7871 G12
Current Sense Threshold
vs ITH Voltage (DCR)
CURRENT SENSE THRESHOLD (mV)
SETCUR PIN CURRENT (µA)
SETCUR Pin Source Current
vs Temperature
vs
Temperature
16.6
5
7871 G11
7871 G10
CURRENT SENSE THRESHOLD (mV)
19.5
18.5
–45 –20
30 55 80 105 130 155
TEMPERATURE (°C)
Overcurrent Fault Threshold
vs Temperature
Temperature
100
OVERCURRENT FAULT THRESHOLD (mV)
7.0
–45 –20
–70
20.0
19.0
8.0
70
20.5
80
60
40
GND
1/4 V5
FLOAT
3/4 V5
V5
20
0
–45 –20
5
30 55 80 105 130 155
TEMPERATURE (°C)
7871 G18
Rev. A
For more information www.analog.com
9
LTC7871
PIN FUNCTIONS
RUN (Pin 27): Enable Control Input. A voltage above
1.22V turns on the IC. There is a 2µA pull-up current on
this pin. Once the RUN pin rises above the 1.22V threshold, the pull-up current increases to 6µA.
V5 (Pin 9): Internal 5V Regulator Output. The control
circuits are powered from this voltage. Bypass this pin
to SGND with a minimum of 4.7µF low ESR tantalum or
ceramic capacitor.
VFBHIGH (Pin 7): VHIGH Voltage Sensing Error Amplifier
Noninverting Input.
DRVCC (Pin 46): Gate Driver Current Supply LDO Output.
The voltage on this pin can be set to 5V, 8V, or 10V by
the DRVSET pin. Bypass this pin to ground plane with a
minimum of 4.7μF low ESR tantalum or ceramic capacitor.
VFBLOW (Pin 3): VLOW Voltage Sensing Error Amplifier
Inverting Input.
ITHHIGH/ITHLOW (Pins 6 and 4): Current Control Threshold
and Error Amplifier Compensation Point. The current comparator’s threshold varies with the ITH control voltage.
SS (Pin 1): Soft-Start Input. The voltage ramp rate at this
pin sets the voltage ramp rate of the regulated voltage. A
capacitor to ground accomplishes soft-start. This pin has
a 1µA pull-up current.
MODE (Pin 51): Mode Set Pin. Tying this pin to SGND
enables forced continuous mode in buck or boost modes.
Floating this pin results in burst mode in buck mode and
discontinuous mode in boost mode. Tying this pin to V5
enables discontinuous mode in buck or boost modes. The
input impedance of this pin is 90kΩ.
SYNC (Pin 52): Switching Frequency Synchronization
or Spread Spectrum Set Pin. Applying an external clock
between 60kHz to 750kHz to this pin causes the switching frequency to synchronize to the clock signal. If SYNC
is low, a resistor from the FREQ pin to SGND sets the
switching frequency. Tying this pin to V5 allows switching
frequency spread spectrum. This pin has a 100kΩ internal
resistor to ground.
FREQ (Pin 53): Frequency Set Pin. A resistor between
this pin and SGND sets the switching frequency. This pin
sources 20µA current.
DRVSET (Pin 44): The voltage setting on this pin programs the DRVCC output voltage. There are two internal
resistors, 200kΩ and 160kΩ, connecting this pin to the
V5 and SGND, respectively.
CLKOUT (Pin 50): Clock Output Pin. Use this pin to synchronize multiple LTC7871 ICs. Signal swing is from V5
to ground.
10
EXTVCC (Pin 42): External Power Input to an Internal LDO
Connected to DRVCC. This LDO supplies DRVCC power,
bypassing the internal LDO powered from VHIGH, whenever EXTVCC is higher than its switchover threshold. Do
not exceed 60V on this pin.
ILIM (Pin 49): Current Comparator Sense Voltage Limit
Selection Pin. The input impedance of this pin is 100kΩ.
SNSD1+/SNSD2+/SNSD3+/SNSD4+/SNSD5+/SNSD6+
(Pins 19, 20, 25, 56, 61, and 62): DC Positive Current
Sense Comparator Inputs. These inputs amplify the DC
portion of the current signal to the IC’s current comparators and current sense amplifiers.
SNS1–/SNS2–/SNS3–/SNS4–/SNS5–/SNS6– (Pins 18, 21,
24, 57, 60, and 63): Negative Current Sense Comparator
Inputs. The negative input of the current comparator is
normally connected to the VLOW.
SNSA1 +/SNSA2 +/SNSA3 +/SNSA4 +/SNSA5 +/SNSA6 +
(Pins 17, 22, 23, 58, 59, and 64): AC Positive Current
Sense Comparator Inputs. These inputs amplify the AC
portion of the current signal to the IC’s current comparator.
VHIGH (Pin 48): Main VHIGH Supply. Bypass this pin to
ground with a capacitor (0.1μF to 1μF).
FAULT (Pin 35): Fault Indicator Output. Open-drain output
that pulls to ground during a fault condition.
PGOOD (Pin 30): Power Good Indictor Output for the
Regulated VHIGH/VLOW. Open drain logic out that is pulled
to ground when the regulated VHIGH/VLOW exceeds ±10%
regulation window, after the internal 40µS power bad
mask timer expires.
Rev. A
For more information www.analog.com
LTC7871
PIN FUNCTIONS
UVHIGH (Pin 14): VHIGH Undervoltage Threshold Set Pin.
A resistor divider from VHIGH is needed to set this threshold. When the voltage on this pin falls below the 1.2V
trip point, a 5μA current is sunk in to the pin to provide
externally adjustable hysteresis.
OVHIGH (Pin 13): VHIGH Overvoltage Threshold Set Pin. A
resistor divider from VHIGH is needed to set this threshold. When the voltage on this pin rises past the 1.2V trip
point, a 5μA current is sourced out of the pin to provide
externally adjustable hysteresis.
OVLOW (Pin 15): VLOW Overvoltage Threshold Set Pin. A
resistor divider from VLOW is needed to set this threshold. When the voltage on this pin rises past the 1.2V trip
point, a 5μA current is sourced out of the pin to provide
externally adjustable hysteresis.
BUCK (Pin 54): The voltage on this pin determines if the
IC is regulating the VLOW or VHIGH voltage/current. Float
or tie this pin to V5 for buck mode operation. Ground this
pin for boost mode operation.
IMON (Pin 10): Current Monitor Pin. The voltage on this
pin is directly proportional to the average inductor currents of all 6 channels. 1.25V on this pin indicates zero
average inductor current per phase.
SETCUR (Pin 11): This pin sets the maximum average
inductor current in buck or boost mode. This pin sources
16μA current and it is programmable by the SPI interface.
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 (Pins 29,
31, 32, 33, 34, and 36): (Top) Gate Signal Output. This
signal goes to the PWM or top gate input of the external
gate driver or integrated driver MOSFET. This is a threestate compatible output.
PWMEN (Pin 28): Enable Pin for External Gate Drivers.
Open drain logic that is pulled to ground when the
LTC7871 shut downs the external gate drivers. When this
pin is low, all the PWM pin outputs are high impedance.
CSB, SDO, SDI, SCLK (Pins 37, 38, 39 and 40): 4-Wire
Serial Peripheral Interface (SPI). Active low chip select
(CSB), serial clock (SCLK) and serial data in (SDI) are
digital Inputs. Serial data out (SDO) is an open-drain
NMOS output pin. SDO requires an external pull-up resistor. Refer to the Serial Port section for more details.
NC (Pins 2, 8, 12, 26, 41, 43, 47, and 55): No Connect Pins.
SGND (Pins 5, 16, 45 and Exposed Pad): Ground. Must
be soldered to PCB ground for rated thermal performance.
Connect this pin closely to negative terminal of VHIGH,
DRVCC, V5 bypass capacitors. All small signal components
and compensation components should connect here.
Rev. A
For more information www.analog.com
11
LTC7871
BLOCK DIAGRAM
Functional Diagram Shows Two Channels Only.
VHIGH
BUCK
CSB
SCLK SDI
BUCK_EN
VHIGH
VREF
–
+
+
–
VFBLOW
IDAC
VFBHIGH
VLOW_OV
+
–
VREF
BUCK_EN
–+
–
+–
+
EA_VLOW
SS
1.2V
VHIGH_OV
CONTROL
LOGIC
VHIGH_UV
VHIGH
MODE
VFBLOW
UVHIGH
+
–
IDAC
SETCUR
VLOW
VLOW
OVHIGH
VREF
EXTVCC
SPI INTERFACE
V5
OVLOW
SDO
BOOST_EN
LOGIC 1
PWM1
IREV1,2
LOGIC 2
PWM2
SNSD2+
ICMP1
ICMP2
VHIGH
+
EA_VHIGH
BUCK_EN
–
1.32V
VFBLOW
BOOST_EN
VFBHIGH
1.08V
SYNC
PHASE
DETECTOR
100k
20µA
PLL/OSC
INTERNAL
LDO REG
EXTVCC
LDO REG
DRVSET EXTVCC
+
–
SNSA1+
+
–
SNSA2+
SNS2–
SNSD1+
SNS1–
SNSA2+
+
–
+
–
SNSD2+
SNS2–
PGOOD
+
–
FAULT
VLOW_OV
VHIGH_OV
VHIGH_UV
VHIGH
CLK
CLKOUT
+
–
+
–
+
–
IMON
FREQ
DRIVER
–
1.25V + SETCUR
|1.25V – SETCUR|
ITHHIGH
SNS1–
ICMP1,2
SETCUR
SS
1.2V
SNSD1+
SNSA1+
CLK
+
VFBHIGH
VLOW
V5
VFLD
ITHLOW
DRIVER
PWMEN
1µA
5V LDO
DRVCC
V5 SGND
SS
7871 BD
12
Rev. A
For more information www.analog.com
LTC7871
OPERATION
Main Control Loop
Current Sensing with Low DCR or RSENSE
The LTC7871 is a bidirectional, constant-frequency, current mode buck or boost switching regulator controller
with six channels operating equally out of phase. The
LTC7871 is capable of delivering power from VHIGH to
VLOW as well as from VLOW back to VHIGH. When power
is delivered from VHIGH to VLOW, the LTC7871 operates
as a peak-current mode constant-frequency buck regulator; and when power delivery is reversed, it operates as a
valley current mode constant-frequency boost regulator.
Four control loops, two for current and two for voltage,
allow control of voltage or bidirectional current on either
VHIGH or VLOW. The LTC7871 uses an ADI proprietary current sensing, current mode architecture. During normal
buck mode operation, the top MOSFET is turned on every
cycle when the oscillator sets the RS latch, and turned off
when the main current comparator, ICMP, resets the RS
latch. The peak inductor current at which ICMP resets the
RS latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier, EA. The error amplifier
receives the feedback signal and compares it to the internal 1.2V reference. When the load current increases, it
causes a slight change in the feedback pin voltage relative
to the 1.2V reference, which in turn causes the ITH voltage
to change until the inductor’s average current equals the
new load current. After the top MOSFET has turned off,
the bottom synchronous MOSFET is turned on until the
beginning of the next cycle.
The LTC7871 employs a unique architecture to enhance
the signal-to-noise ratio with low current sense offsets.
This enables it to operate with a small current sense signal
from a very low value inductor DCR to improve power
efficiency, and reduce jitter due to switching noise which
could corrupt the signal. Each channel has two positive
current sense pins, SNSD+ and SNSA+, which share
the negative current sense pin SNS–. These sense pins
acquire signals and process them internally to provide
the response equivalent to a DCR sense signal that has
a 14dB (5 times) signal-to-noise ratio. Accordingly, the
current limit threshold is still a function of the inductor
peak-current and its DCR value and can be accurately set
from 10mV to 50mV in 10mV steps with the ILIM pin.
In either buck or boost mode, the two current control
loops always monitor the maximum average inductor current. When it increases above the thresholds, the current
loops will take over the ITH pin control from the voltage
loop. As a result, the maximum average inductor current
is limited.
The main control loop is shut down by pulling the RUN pin
low. Releasing the RUN pin allows an internal 2μA current
source to pull it up. When the RUN pin reaches 1.22V,
the IC is powered up and the pull-up current increases to
6μA. When the RUN pin is low, all functions are kept in a
controlled shutdown state.
DRVCC/EXTVCC/V5 Power
Power for the external top and bottom MOSFET drivers
is derived from the DRVCC pin. The DRVCC voltage can
be set to 5V, 8V, or 10V using the DRVSET pin. When
the EXTVCC pin is left open or tied to a voltage less than
the switchover voltage programmed by the DRVSET pin,
an internal linear regulator supplies DRVCC power from
VHIGH. When EXTVCC is taken above the switchover voltage, the internal regulator between VHIGH and DRVCC is
turned off, and a second internal regulator is turned on
between EXTVCC and DRVCC. Each top MOSFET driver is
biased from a floating bootstrap capacitor, which normally recharges during each off cycle through an external
diode when the top MOSFET turns off. If the input voltage, VHIGH, decreases to a voltage close to VLOW, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector detects this
and forces the top MOSFET off for about one-twelfth of
the clock period plus 160ns every fifth cycle to allow the
bootstrap capacitor to recharge.
Most of the internal circuitry is powered from the V5
rail that is generated by an internal linear regulator from
DRVCC. The V5 pin needs to be bypassed with a minimum
4.7μF external capacitor to SGND. This pin provides a 5V
output that can supply up to 20mA of current. See the
Applications Information section for more details.
Rev. A
For more information www.analog.com
13
LTC7871
OPERATION
Soft-Start (Buck Mode)
By default, the start-up of the VLOW voltage is normally
controlled by an internal soft-start ramp. The internal softstart ramp represents a noninverting input to the error
amplifier. The VFBLOW pin is regulated to the lowest of the
error amplifier’s three noninverting inputs (the internal
soft-start ramp, the SS pin or the internal 1.2V reference).
As the ramp voltage rises from 0V to 1.2V over approximately 1ms, the VLOW voltage rises smoothly from its
prebiased value to its final set value. Certain applications
can require the start-up of the converter into a non-zero
load voltage, where residual charge is stored on the VLOW
capacitor at the onset of converter switching. In order to
prevent the VLOW from discharging under these conditions, the top and bottom MOSFETs are disabled until
soft-start is greater than VFBLOW.
Soft-Start (Boost Mode)
The same internal soft-start capacitor and external softstart capacitor are also active if the controller starts with
boost mode of operation. The error amplifier for boost
mode also tries to regulate to the lowest reference during
start-up. However, the topology of the boost converter
limits the effectiveness of this soft-start mechanism until
the boost output voltage reaches its input voltage level.
Therefore, it is recommended that the controller starts in
buck mode of operation.
Shutdown and Start-Up (RUN and SS Pins)
The LTC7871 can be shut down using the RUN pin.
Pulling the RUN pin below 1.22V shuts down the main
control loop for the controller and most internal circuits,
including the DRVCC and V5 regulators. Releasing the
RUN pin allows an internal 2μA current to pull up the
pin and enable the controller. Alternatively, the RUN pin
may be externally pulled up or driven directly by logic. Be
careful not to exceed the absolute maximum rating of 6V
on this pin. The start-up of the controller’s VLOW voltage
is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 1.2V internal reference,
the LTC7871 regulates the VFBLOW voltage to the SS pin
voltage instead of the 1.2V reference. This allows the SS
14
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to SGND. An internal
1μA pull-up current charges this capacitor, creating a voltage ramp on the SS pin. As the SS voltage rises linearly
from 0V to 1.2V (and beyond), the VLOW voltage rises
smoothly from zero to its final value. When the RUN pin
is pulled low to disable the controller, or when V5 drops
below its undervoltage lockout threshold, the SS pin is
pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the external
MOSFETs are held off. External circuitry can be added to
discharge the soft-start capacitor during fault conditions
to ensure a soft-start when the faults are cleared.
Frequency Selection, Spread Spectrum, and PhaseLocked Loop (FREQ and SYNC Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
If the SYNC pin is tied to SGND, the FREQ pin can be
used to program the controller’s operating frequency
from 67kHz to 725kHz. There is a precision 20μA current
flowing out of the FREQ pin so that the user can program
the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the Applications
Information section showing the relationship between
the voltage on the FREQ pin and switching frequency
(Figure 7).
Switching regulators can be particularly troublesome for
applications when electromagnetic interface (EMI) is a
concern. To improve EMI, the LTC7871 can operate in
spread spectrum mode, which is enabled by tying the
SYNC pin to V5. This feature varies the switching frequency at low frequency rate (switching frequency/512,
by default) with a triangular frequency modulation of
±12%. For example, if the LTC7871’s frequency is programmed to switch at 200kHz, enabling spread spectrum
will modulate the frequency between 176kHz and 224kHz
at a 0.4kHz rate. These spread spectrum parameters are
programmed by the MFR_SSFM register.
Rev. A
For more information www.analog.com
LTC7871
OPERATION
A phase-locked loop (PLL) is available on the LTC7871
to synchronize the internal oscillator to an external clock
source that is connected to the SYNC pin. The PLL loop
filter network is integrated inside the LTC7871. The phase
locked loop is capable of locking to any frequency within
the range of 60kHz to 750kHz. The frequency setting
resistor should always be present to set the controller’s
initial switching frequency before locking to the external
clock. The controller operates in the user selected mode
when it is synchronized.
Undervoltage Lockout
The LTC7871 has two functions that help protect the controller in case of undervoltage conditions. Two precision
UVLO comparators constantly monitor the V5 and DRVCC
voltages to ensure that adequate voltages are present. The
switching action is stopped when V5 or DRVCC is below
the undervoltage lockout threshold. To prevent oscillation
when there is a disturbance on the V5 or DRVCC, the UVLO
comparators have precision hysteresis.
d. During a startup sequence until the SS pin charges up
past 1.2V.
e. When any channel is in overcurrent fault status.
f. When the IC is over temperature.
The OVLOW and OVHIGH thresholds are set using an external resistor divider off VLOW and VHIGH, respectively.
When the voltage at the pin exceeds the comparator
threshold of 1.2V, a 5μA hysteresis current is sourced
out of the respective pin and the FAULT signal goes low
after a 120μs delay. The UVHIGH threshold is also set using
an external resistor divider off VHIGH. When the voltage
at the pin falls below the comparator threshold of 1.2V, a
5μA hysteresis current is sunk into the UVHIGH pin and the
FAULT signal goes low after a 120μs delay. The amount of
hysteresis can be adjusted by changing the total impedance of the resistor divider, while the resistor ratio sets
the UV/OV trip point.
Besides flagging the FAULT pin, the UV/OV comparators also affect the operation of the controller, as shown
in Table 1. When the OVLOW comparator crosses its
1.2V threshold:
Another way to detect an undervoltage condition is to
monitor the VHIGH supply. Because the RUN pin has a
precision turn-on reference of 1.22V, one can use a resistor divider to VHIGH to turn on the IC when VHIGH is high
enough. An extra 4μA of current flows out of the RUN pin
once the RUN pin voltage passes 1.22V. The RUN comparator itself has about 80mV of hysteresis. Additional
hysteresis for the RUN comparator can be programmed
by adjusting the values of the resistive divider. For accurate VHIGH undervoltage detection, VHIGH needs to be
higher than 5V.
When the OVHIGH comparator crosses its 1st threshold
of 1.2V:
Fault Flag (FAULT, OVHIGH, OVLOW and UVHIGH Pins)
a. The controller stops switching in both buck and
boost modes.
The FAULT pin is connected to the open-drain of an internal N-channel MOSFET. It can be pulled high with an external resistor connected to a voltage up to 6V, such as V5
or an external bias voltage. The FAULT pin is pulled low
when at least one of the following conditions is met:
a. The RUN pin is below its turn on threshold.
b. When V5 or DRVCC is below its UVLO threshold.
a. In buck mode, the controller stops switching.
b. In boost mode, the controller continues to switch.
c. ITH and SS are unaffected in both buck and boost
modes. Whenever a fault is detected, discharge the
SS pin as needed externally.
b. ITH and SS are unaffected in both buck and boost
modes. Whenever a fault is detected, discharge the
SS pin as needed externally.
When the OVHIGH comparator crosses its 2nd threshold
of 2.4V:
a. The controller stops switching in both buck and
boost modes.
c. Any of the three OV/UV comparators has been tripped.
Rev. A
For more information www.analog.com
15
LTC7871
OPERATION
b. Both ITH and IMON pins are driven into high impedance. This feature allows the users to isolate one
LTC7871 from a multiphase system in case a fault is
detected on one particular IC.
c. The SS pin is unaffected.
When the UVHIGH comparator crosses its 1.2V threshold:
a. In buck mode, the controller stops switching after a
120μs delay, and the SS pin pulls to SGND.
b. In boost mode, the controller continues to switch. The
SS pin is unaffected.
c. ITH is unaffected in both buck and boost modes.
Table 1. OV/UV Faults
FAULT
OVLOW 1.2V
Threshold
MODE SWITCHING ITH PINS
IMON
VZERO is the IMON voltage when average output current
is zero; VZERO = 1.25V typically
K = 40 if the ILIM voltage is 0V or 1/4 VV5
K = 20 if the ILIM voltage is float, 3/4 VV5 or VV5
IL(ALL) is the total average inductor current including
all six channels
RSENSE is the current sensing resistor value.
An external voltage can be applied to the SETCUR pin
to regulate the maximum average inductor current. The
SETCUR pin voltage should be set as:
SS
VSETCUR =
Buck
Stops
No Effect No Effect
No Effect
Boost
Continues
No Effect No Effect
No Effect
Buck
Stops
No Effect No Effect
No Effect
where:
Stops
No Effect No Effect
No Effect
OVHIGH 1.2V
Threshold
Boost
OVHIGH 2.4V Buck
Threshold
Boost
Stops
Hi-Z
Hi-Z
No Effect
Stops
Hi-Z
Hi-Z
No Effect
UVHIGH 1.2V Buck
Threshold
Boost
Stops
No Effect No Effect Pulls to SGND
Continues
No Effect No Effect
No Effect
The inductor current can be sensed using either its DCR or
a RSENSE resistor. The current monitoring pin, IMON, outputs a voltage that is proportional to the average inductor
current of the six channels sensed by the LTC7871. The
operational range of IMON is 0.4V to 2.5V. When the average inductor current is zero, the IMON pin voltage rests
at 1.25V. As the inductor current increases in buck mode,
the IMON voltage proportionally increases; As the inductor current increases in boost mode, the IMON voltage
proportionally decreases. Use the following equation to
calculate the voltages on IMON:
VIMON = VZERO +
VIMON = VZERO –
K •I L( ALL ) • R SENSE
6
K •I L( ALL ) • R SENSE
6
K •I L(MAX ) • R SENSE
6
IL(MAX) is the maximum total average inductor current
including all six channels
The SETCURP and SETCURN are internally generated
voltages based on the SETCUR pin:
SETCURP = 1.25V + VSETCUR
SETCURN = |1.25V – VSETCUR|
Current Monitoring and Regulation
(IMON, SETCUR Pins)
16
where:
; Buck Mode
; Boost Mode
SETCURP, SETCURN, and IMON are the three inputs to
the current regulation loop error amplifier with SETCURP
and SETCURN acting as the reference. When the IMON pin
voltage approaches SETCURP or SETCURN, the ITH pin
control is taken over by the current loop error amplifier
from the voltage loop error amplifier.
In either buck or boost mode, both the maximum positive
average current and the maximum negative average current are regulated. There is a 16µA current flowing out of
the SETCUR pin so that a single resistor to SGND can set
both the positive average current loop and negative average current loop. The sourcing current from the SETCUR
pin is programmable through the SPI interface. For battery charging applications, SETCUR can be programmed
dynamically on-the-fly to set the charging currents to the
batteries in either buck or boost mode. SETCUR can be
used at start-up to limit the in-rush current in both buck
mode and boost mode.
Rev. A
For more information www.analog.com
LTC7871
OPERATION
To defeat the average current programming operation,
tie the SETCUR pin to V5 or voltage higher than 1.25V.
Buck and Boost Modes (BUCK Pin)
The LTC7871 can be dynamically and seamlessly switched
from buck mode to boost mode and vice versa via the
BUCK pin. Tie this pin to V5 to select buck mode and
to ground to select boost mode operation. This pin has
an internal pull up resistor that defaults to buck mode if
left floating. There are two separate error amplifiers for
VHIGH or VLOW regulation. Having two error amplifiers
allows fine tuning of the loop compensation for the buck
and boost modes independently to optimize transient
response. When buck mode is selected, the corresponding error amplifier is enabled, and ITHLOW voltage controls the peak inductor current. The other error amplifier
is disabled and ITHHIGH is parked at its zero current level.
In boost mode, ITHHIGH is enabled while ITHLOW is parked
at its zero current level. During a buck to boost or a boost
to buck transition, the internal soft-start is reset. Resetting
soft-start and parking the ITH pin at the zero current level
ensures a smooth transition to the newly selected mode.
Refer to Table 2 for a summary.
To further minimize any transients, SETCUR can be programmed to zero current level before switching between
boost and buck modes.
Table 2. ITH PIN Parking Conditions
Pin
ITHHIGH
ITHLOW
Mode
When Parked Comments
Buck
Normal
Operation
OVHIGH 2.4V Threshold Overrides Park
Boost
Prebiased
Turn-on
OVHIGH 2.4V Threshold Overrides Park
Buck
Prebiased
Turn-on
OVHIGH 2.4V Threshold and OVLOW
Override Park
Boost
Normal
Operation
OVHIGH 2.4V Threshold Overrides Park
Power Good (PGOOD Pin)
When the regulated VFBLOW/VFBHIGH voltage is not within
±10% of the 1.2V reference voltage, the PGOOD pin is
pulled low. The PGOOD pin is also pulled low when the
RUN pin is below 1.2V or when the LTC7871 is in the
soft-start or UVLO. The PGOOD pin will flag power good
immediately when the regulated VFBLOW/VFBHIGH voltage is within ±10% of the reference window. However,
there is an internal 40µs power bad mask when regulated
VFBLOW/VFBHIGH voltage goes out of the ±10% window.
The PGOOD pin is allowed to be pulled up by an external
resistor to sources of up to 6V.
Programmable VHIGH, VLOW Margining
As shown in the Figure 1, the LTC7871 has a SPI controlled 7-bit D/A converter current source. Through the
SPI interface, the LTC7871 receives a 7-bit DAC code and
converts this value to a bidirectional analog output current. The current is connected to the VFBLOW pin in buck
mode or the VFBHIGH pin in boost mode. By connecting
the DAC current to the feedback node of a voltage regulator, in buck mode, VLOW voltage is programmed with the
equation:
VLOW = 1.2V • (1 + RB/RA) – IDAC • RB
In boost mode, VHIGH voltage is programmed with
the equation:
VHIGH = 1.2V • (1 + RD/RC) – IDAC • RD
There are two different registers for VLOW and VHIGH programming, MFR_IDAC_VLOW and MFR_IDAC_VHIGH.
The current DAC selects the register value based on the
buck or boost mode. The current DAC’s LSB is 1µA. The
MSB determines the current direction. When MSB is 0,
IDAC is sourcing current (reducing VLOW or VHIGH), which
is positive current flowing out of the feedback pin. When
MSB is 1, IDAC is sinking current (increasing VLOW or
VHIGH), which is negative current flowing into the feedback pin.
VHIGH
VLOW
RD BOOST MODE
BUCK MODE
CURRENT DAC
VFBHIGH
RC
IDAC
RB
VFBLOW
IDAC
RA
7871 F01
Figure 1. Current DAC for VLOW/VHIGH Programming
Rev. A
For more information www.analog.com
17
LTC7871
OPERATION
Buck Mode Light Load Current Operation (DCM/CCM/
Burst Mode Operation)
In buck mode, the LTC7871 can be enabled to enter discontinuous conduction mode (DCM), forced continuous
conduction mode (CCM), or Burst Mode operation. To
select forced continuous operation, tie the MODE pin
to SGND. To select discontinuous conduction mode of
operation, tie the MODE pin to V5. To select Burst Mode
operation, float the MODE pin.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITHLOW pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in DCM operation. However, continuous mode has the
advantages of lower output ripple and less interference
with audio circuitry.
When the LTC7871 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though the
voltage on the ITHLOW pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier, EA, will decrease the voltage on the
ITHLOW pin. When the ITHLOW voltage drops below 1.1V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough,
the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on
the next cycle of the internal oscillator. When a controller
is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the controller
operates in discontinuous conduction mode.
When the MODE pin is connected to V5, the LTC7871
operates in discontinuous conduction mode at light loads.
18
At very light loads, the current comparator, ICMP, may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping-pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well
as low audio noise and reduced RF interference. It provides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
Boost Mode Light Load Current Operation (DCM/CCM)
In boost mode, the LTC7871 can be enabled to enter
constant-frequency discontinuous conduction mode or
forced continuous conduction mode. To select forced continuous operation, tie the MODE pin to SGND. To select
discontinuous conduction mode of operation, tie the
MODE pin to V5 or float it. In forced continuous operation,
the inductor current is allowed to reverse at light loads
or under large transient conditions. The inductor current
valley is determined by the voltage on the ITHHIGH pin,
just as in normal operation. In this mode, the efficiency
at light loads is lower. However, continuous mode has the
advantage of lower output ripple.
When the MODE pin is connected to V5 or floated, the
LTC7871 operates in discontinuous conduction mode at
light loads. At very light loads, the current comparator,
ICMP, may remain tripped for several cycles and force
the external top MOSFET to stay off for the same number
of cycles (i.e., skipping-pulses). The inductor current is
not allowed to reverse (discontinuous operation). This
mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference. It provides higher low current efficiency than
forced continuous mode.
The LTC7871 operation mode is summarized in Table 3.
Table 3. Operation Mode
MODE Pin
Buck Operation Mode
Boost Operation Mode
0V
CCM
CCM
Float
Burst Mode Operation
DCM
VV5
DCM
DCM
Rev. A
For more information www.analog.com
LTC7871
OPERATION
Overcurrent Fault Monitor (OCFT and NOCFT)
Besides the peak/valley current comparator and the maximum average current regulation loops, the LTC7871 has
an additional overcurrent fault comparator to monitor the
voltage difference between the SNSD+ and SNS– pins.
If one channel’s (VSNSD+ – VSNS–) is larger than overcurrent fault threshold (OCFT) or less than the negative overcurrent threshold (NOCFT) as shown in the
Table 4, all six channels stop switching and all PWM pins
are Hi-Z. The OCFT and NOCFT status can be obtained
through the SPI interface by the MFR_OC_FAULT and
MFR_NOC_FAULT registers.
Table 4. OCFT and NOCFT Threshold (VSNSD+ – VSNS–)
ILIM Pin
Voltage
OCFT
Threshold
NOCFT
Threshold
Hysteresis
0V
37.5mV
–37.5mV
25mV
1/4 VV5
50mV
–50mV
31mV
Float
62.5mV
–62.5mV
31mV
3/4 VV5
75mV
–75mV
31mV
VV5
87.5mV
–87.5mV
31mV
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs,
designed to drive power stages such as power blocks,
DrMOS, and drivers with MOSFETs, none of which represents a heavy capacitive load. An external resistor divider
may be used to set the PWM voltage to mid-rail while the
PWM is in the high impedance state.
The LTC7871’s PWMEN pin is used to communicate the
controller’s status with the external MOSFET drivers or
other LTC7871s. When the LTC7871 releases the PWMEN
pin but finds it is still pulled down externally, the LTC7871
will keep all the PWM pins in Hi-Z status.
Multiphase Operation
For output loads that demand high current, multiple
LTC7871s can be daisy chained to run out of phase to
provide more output current without increasing input and
output voltage ripple. The SYNC pin allows the LTC7871
to synchronize to the CLKOUT signal of another LTC7871.
The CLKOUT signal can be connected to the SYNC pin of
the following LTC7871 stage to line up both the frequency
and the phase of the entire system. When paralleling multiple ICs, please be aware of the input impedance of pins
connected to the same node.
Thermal Shutdown
The LTC7871 has a temperature sensor integrated on
the IC, to sense the die temperature. When the die temperature exceeds 180°C, all switching actions stop, and
all PWM pins become Hi-Z, thus turning off all external
MOSFETs. At the same time, all the channels are disconnected from the IMON pins, and the SS and ITHHIGH/
ITHLOW pins continue to function normally, so as not to
interfere with other LTC7871 chips that may reference the
common pins. When the temperature drops 15°C below
the trip threshold, normal operation resumes.
The PWMEN pin is an open-drain output pin. It should
be pulled up by an external resistor to V5 when the
controller starts switching. During any fault status, the
LTC7871 pulls down the PWMEN pin to disable the external MOSFET driver.
Rev. A
For more information www.analog.com
19
LTC7871
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC7871 application circuit. In general, external
component selection is driven by the load requirements,
and begins with the DCR or RSENSE and inductor value.
Next, power MOSFETs are selected. Finally, VHIGH and
VLOW capacitors are selected.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results
in a reduction of maximum inductor peak current for duty
cycles > 40%. However, the LTC7871 uses a scheme that
counteracts this compensating ramp, which allows the
maximum inductor peak current to remain unaffected
throughout all duty cycles.
Current Limit Programming
The ILIM pin is a 5-level logic input which sets the maximum current limit of the controller. Table 5 shows the five
ILIM settings. Please note that these settings represent
the peak inductor current setting. Because of the inductor
ripple current, the average output current is lower than
the peak current. Setting ILIM using a resistor divider
from V5 to SGND will allow the maximum current sense
threshold setting to not change when the 5V LDO is in
dropout at start-up. Please note that the ILIM pin has an
internal 200k pull down resistor to SGND and a 200k pull
up resistor to V5.
Table 5. ILIM Settings
Maximum Current Sense Threshold
ILIM Pin Voltage
DCR Sensing
RSENSE
0V
10mV
12.5mV
1/4 VV5
20mV
25mV
Float
30mV
37.5mV
3/4 VV5
40mV
50mV
VV5
50mV
62.5mV
20
SNSD+, SNSA+ and SNS– Pins
The SNSA+ and SNS– pins are the inputs to the current
comparators, while the SNSD+ and SNS– pins are the input
of an internal DC amplifier. The operating input voltage
range is 0V to 60V for all three sense pins. All the positive
sense pins that are connected to the current comparator
or the amplifier are high impedance with input bias currents of less than 1μA. The SNS– pin is not a high impedance pin. For VLOW voltages greater than V5, the current
comparators derive their bias currents directly from the
SNS– pins. The SNS– pins should be connected directly
to VLOW. Care must be taken not to float these pins during
normal operation. Filter components, especially capacitors, must be placed close to the LTC7871, and the sense
lines should run close together to a Kelvin connection
underneath the current sense element (Figure 2). Because
the LTC7871 is designed to be used with a very low value
sensing element to sense inductor current, without proper
care, the parasitic resistance, capacitance and inductance
will degrade the current sense signal integrity, making
the programmed current limit unpredictable. As shown in
Figure 3, resistor R1 is placed close to the output inductor and capacitors C1 and C2 are close to the IC pins to
prevent noise coupling to the sense signal.
TO SENSE FILTER LOCATED
NEXT TO THE CONTROLLER
7871 F02
COUT
Figure 2. Sense Lines Placement with Sense Resistor
Inductor DCR Sensing
The LTC7871 is specifically designed for high load current
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
milliohm range (Figure 3). The DCR is the DC winding
resistance of the inductor’s copper, which is often several
mΩ for high current inductors. In high current applications, the conduction loss of a high DCR or a sense resistor will cause a significant reduction in power efficiency.
The SNSA+ pin connects to the filter that has a R1 • C1
time constant one-fifth of the L/DCR of the inductor. The
SNSD+ pin is connected to the second filter with the time
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
constant matched to L/DCR of the inductor. For a specific
output requirement, choose the inductor with the DCR
that satisfies the maximum desired sense voltage, and
uses the relationship of the sense pin filters to output
inductor characteristics as depicted below.
DCR =
VSENSE(MAX)
IMAX +
L
DCR
∆IL
2
provides better efficiency at heavy loads. To maintain a
good signal-to-noise ratio for the current sense signal,
use a minimum of 10mV between SNSA+ and SNS– pins
or the equivalent of 2mV ripple on the current sense signal
for duty cycles less than 40%. The actual ripple voltage
across SNSA+ and SNS– pins will be determined by the
following equation:
V
V
–V
∆VSENSE = LOW • HIGH LOW
VHIGH R1• C1• fOSC
= 5 • R1• C1 = R2 • C2
SNS–
LTC7871
where:
C2
SNSD+
VSENSE(MAX) is the maximum sense voltage for a given
ILIM threshold
C1
R2
R1
SNSA+
L
SW
7871 F03
∆IL is the Inductor ripple current
+
VLOW
L and DCR are the output inductor characteristics
R1 • C1 is the filter time constant of the SNSA+ pin
Figure 3. Inductor DCR Sensing
R2 • C2 is the filter time constant of the SNSD+ pin
Sensing Using an RSENSE Resistor
To ensure that the load current will be delivered over the
full operating temperature range, the temperature coefficient of DCR resistance, approximately 0.4%/°C, should
be taken into account.
The LTC7871 can be used with an external RSENSE resistor to sense current accurately. The external components
required to accomplish this are shown in Figure 4. The
SNSD+ pin senses directly across the RS resistor through
R3 and C3 network. The R1, R2, and C1 network provide
the current signal path to the SNSA+ pin. Internally the
signals from the AC and DC paths are combined for accurate current sensing and low jitter performance. Resistor
R2 is used to divide down the DC component of the signal
seen by SNSA+ due to the DCR of the inductor. As a rule
of thumb, R2 needs to be 10 times smaller than R1 so
the DCR value can be safely ignored.
Typically, C1 and C2 are selected in the range of 0.047μF
to 0.47μF. If C1 and C2 are chosen to be 0.1μF, and an
inductor of 10μH with 2mΩ DCR is selected, R1 and R2
will be 10k and 49.9k, respectively. The bias current at
SNSD+ and SNSA+ is less than 1μA, and it introduces a
small error to the sense signal.
There will be some power loss in R1 that relates to the
duty cycle, and will be the most in continuous mode at
the maximum VHIGH voltage:
PLOSS
( VHIGH(MAX) – VLOW ) • VLOW
(R ) =
R3
SNSD+
LTC7871
C2
SNS–
R
C1
Ensure that R1 has a power rating higher than this value.
Care has to be taken for voltage coefficients of these resistors at high VHIGH voltages. Multiple resistors can be used
in series to minimize this effect. However, DCR sensing
eliminates the conduction loss of a sense resistor; it also
SNSA+
7871 F04
R2
R1
SW
L
RS
+
VLOW
Figure 4. RSENSE Resistor Sensing
Rev. A
For more information www.analog.com
21
LTC7871
APPLICATIONS INFORMATION
The R1 • C1 time constant should be selected such that:
L
RS
= 4 • R1• C1 for R1= 10 • R2
The R3 • C2 time constant should be selected such that:
R3 • C2 =
R1• R2
R1+R2
• C1
If a 6.8μH inductor and a 1mΩ sense resistor are selected
and C1 and C2 are chosen to be 0.1µF, then the values for
R1, R2 and R3 will be 16.9k, 1.69k and 1.5k, respectively
when the nearest standard value is chosen.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a prebias on the VLOW output capacitors. In
this case, it is desirable to start up without discharging
that output prebias. The LTC7871 can safely power up
into a prebiased output without discharging it.
The LTC7871 accomplishes this by disabling both the
top and bottom MOSFETs until the SS pin voltage and the
internal soft-start voltage are above the VFBLOW pin voltage. When VFBLOW is higher than SS or the internal softstart voltage, the error amp output is parked at its zero
current level. Disabling both top and bottom MOSFETs
prevents the prebiased output voltage from being discharged. When SS and the internal soft-start both cross
1.32V or VFBLOW, whichever is lower, both top and bottom
MOSFETs are enabled.
Upon removal of the short, VLOW soft starts using the
internal soft-start, thus reducing output overshoot. In
the absence of this feature, the output capacitors would
have been charged at current limit, and in applications
with minimal output capacitance this may have resulted
in output overshoot. Current limit foldback is not disabled
during an overcurrent recovery. The load must drop below
the folded back current limit threshold in order to restart
from a hard short.
In both buck and boost modes of operation, forcing a
voltage on the SETCUR pin regulates the average current.
Zero average inductor current can be obtained by forcing
0V on SETCUR.
The LTC7871 has additional overcurrent fault comparators to monitor the current of each channel. If there is
any catastrophic failure in the system which causes one
or more channel’s inductor current to be higher than the
overcurrent fault threshold, all the channels will be shut
down and both the PWMEN and the FAULT pins will be
pulled down to SGND.
Another way to protect against overcurrent is to monitor the IMON pin voltage. If the IMON voltage indicates
excessive current, an external circuit can be used to shut
down the system.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
Overcurrent Fault Protection
In the buck mode, when the output of the power supply
is loaded beyond its preset current limit, the regulated
output voltage will collapse depending on the load. The
VLOW rail may be shorted to ground through a very low
impedance path or it may be a resistive short, in which
case the output will collapse partially, until the load current equals the preset current limit. The controller will
continue to source current into the short. The amount of
current sourced depends on the ILIM pin setting and the
VFBLOW voltage as shown in the Current Foldback graph
in the Typical Performance Characteristics section.
22
IRIPPLE =
VLOW ⎛ VHIGH – VLOW ⎞
VHIGH ⎜⎝ fOSC • L ⎟⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of the maximum inductor current. Note
that the largest ripple current occurs at the highest VHIGH
voltage. To guarantee that ripple current does not exceed
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
a specified maximum, the inductor should be chosen
according to:
V
– VLOW VLOW
L ≥ HIGH
•
f
•
I
VHIGH
RIPPLE
OSC
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. Core loss is independent of
core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
At least two external power MOSFETs need to be selected:
One N-channel MOSFET for the top switch and one or
more N-channel MOSFET(s) for the bottom switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well
as the actual position (top or bottom) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an VLOW that is less
than one-third of VHIGH. In applications where VHIGH >>
VLOW, the top MOSFETs’ on-resistance is normally less
important for overall efficiency than its input capacitance
at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the top switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by
the internal DRVCC regulator voltage. Pay close attention to the BVDSS specification for the MOSFETs as well.
Selection criteria for the power MOSFETs include the onresistance RDS(ON), input capacitance, input voltage and
maximum output current. MOSFET input capacitance is
a combination of several components but can be taken
from the typical gate charge curve included on most data
sheets (Figure 5). The curve is generated by forcing a
constant input current into the gate of a common source,
current source loaded stage and then plotting the gate
voltage versus time.
VIN
MILLER EFFECT
VGS
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
+V
DS
–
7871 F05
Figure 5. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and the
gate-to-drain capacitance. The flat portion of the curve is
the result of the Miller multiplication effect of the drainto-gate capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gateto-source capacitance. The Miller charge (the increase
in coulombs on the horizontal axis from a to b while the
curve is flat) is specified for a given VDS drain voltage,
but can be adjusted for different VDS voltages by multiplying the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to
take the change in gate charge from points a and b on a
manufacturer’s data sheet and divide by the stated VDS
voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included. When
Rev. A
For more information www.analog.com
23
LTC7871
APPLICATIONS INFORMATION
the controller is operating in continuous mode the duty
cycles for the top and bottom MOSFETs are given by:
Top Switch Duty Cycle =
VLOW
VHIGH
⎛V
⎞
–V
Bottom Switch Duty Cycle = ⎜ HIGH LOW ⎟
VHIGH
⎝
⎠
The power dissipation for the top and bottom MOSFETs
at maximum output current are given by:
PTOP =
VLOW
IMAX
VHIGH
(
( VHIGH )
)
2
(1+δ)RDS(ON) +
CHIGH and MOSFETs Selection (on VHIGH and VLOW)
In continuous mode, the source current of the top
MOSFET is a square wave of duty cycle (VLOW)/(VHIGH).
To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel
must be used. In the following discussion, it is assumed
that CIN is CHIGH, COUT is CLOW, VIN is VHIGH, and VOUT is
VLOW. The maximum RMS capacitor current is given by:
2 ⎛ I MAX ⎞
⎜
⎟ (RDR ) (CMILLER ) •
⎝ 2 ⎠
⎡
1
1 ⎤
⎢
⎥• f
+
⎢⎣DRVCC – VTH(MIN) VTH(MIN) ⎥⎦
PBOT =
VHIGH – VLOW
IMAX
VHIGH
(
)
2
An optional Schottky diode across the bottom MOSFET
conducts during the dead time between the conduction
of the two large power MOSFETs in buck mode. This prevents the body diode of the bottom MOSFET from turning
on, storing charge during the dead time and requiring
a reverse-recovery period which could cost as much as
several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation
due to the relatively small average current. Larger diodes
result in additional transition loss due to their larger
junction capacitance.
(1+δ)RDS(ON)
CIN Required IRMS ≈
1/2
IMAX
⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦
VIN
IMAX = Maximum Inductor Current.
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance; VHIGH is the drain
potential and the change in drain potential in the particular
application. VTH(MIN) is the data sheet specified typical
gate threshold voltage specified in the power MOSFET
data sheet at the specified drain current. CMILLER is the
calculated capacitance using the gate charge curve from
the MOSFET data sheet and the technique described
above.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of use.
Both MOSFETs have I2R losses while the topside
N-channel equation includes an additional term for transition losses, which peak at the highest input voltage.
The bottom MOSFET losses are greatest at high VHIGH
voltage when the top switch duty factor is low or during
a VLOW short-circuit when the bottom switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
24
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet size
or height requirements in the design. Ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. X7R, X5R
and Y5V are examples of a few of the ceramic materials
used as the dielectric layer, and these different dielectrics
have very different effect on the capacitance value due to
the voltage and temperature conditions applied. Physically,
if the capacitance value changes due to applied voltage
change, there is a concomitant piezo effect which results
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
in radiating sound! A load that draws varying current at an
audible rate may cause an attendant varying input voltage
on a ceramic capacitor, resulting in an audible signal. A
secondary issue relates to the energy flowing back into
a ceramic capacitor whose capacitance value is being
reduced by the increasing charge. The voltage can increase
at a considerably higher rate than the constant current
being supplied because the capacitance value is decreasing
as the voltage is increasing! Nevertheless, ceramic capacitors, when properly selected and used, can provide the
lowest overall loss due to their extremely low ESR.
A small (0.1μF to 1μF) capacitor, CIN, placed close to
the LTC7871 between the VIN pin and ground, bypasses
switching noise to ground. A 2.2Ω to 10Ω resistor, placed
between CIN and VHIGH pins decouples the VHIGH pin from
switching noise.
The selection of COUT at VOUT is driven by the required
effective series resistance (ESR). Typically once the ESR
requirement is satisfied the capacitance is adequate for
filtering. The steady-state output ripple (∆VOUT) is determined by:
⎛
1 ⎞
ΔVOUT ≈ ΔIRIPPLE ⎜ ESR +
8fCOUT ⎟⎠
⎝
where f = operating frequency, COUT = output capacitance
and ∆IRIPPLE = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆IRIPPLE
increases with input voltage (VHIGH). The output ripple will
be less than 50mV at maximum VIN with ∆IRIPPLE = 0.4
IOUT(MAX) assuming:
COUT required ESR < N • RSENSE
Once the ESR requirement for COUT has been met, the
RMS current rating generally far exceeds the IRIPPLE(P–P)
requirement. Ceramic capacitors from AVX, Taiyo
Yuden, Murata and TDK offer high capacitance value
and very low ESR, especially applicable for low output
voltage applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the
case of tantalum, it is critical that the capacitors are surge
tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510
series of surface mount tantalums or the Panasonic SP
series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POSCAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturers for other specific recommendations.
CHIGH Capacitor Selection for Boost Operation
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct combination of output capacitors for a boost converter application.
and
COUT >
significantly different from that of an ideal capacitor and
therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon,
Nippon Chemi-Con and Sanyo should be considered for
high performance through-hole capacitors. The OS-CON
semiconductor dielectric capacitors available from Sanyo
and the Panasonic SP surface mount types have a good
(ESR)(size) product.
1
( 8f ) (RSENSE )
The emergence of very low ESR capacitors in small,
surface mount packages makes very small physical
implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin
allows a much wider selection of output capacitor types.
The impedance characteristic of each capacitor type is
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ΔV. This percentage
Rev. A
For more information www.analog.com
25
LTC7871
APPLICATIONS INFORMATION
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
One of the key benefits of multiphase operation is a reduction in the peak current supplied to the output capacitor
by the boost diodes. As a result, the ESR requirement
of the capacitor is relaxed. For a 1% contribution to the
total ripple voltage, the ESR of the output capacitor can
be determined using the following equation:
ESR COUT >
0.01• VOUT
I D(PEAK )
where:
1 ⎛ χ ⎞ IO(MAX )
•
ID(PEAK ) = • 1+
n ⎝ 2 ⎠ 1–DMAX
The factor n represents the number of phases and the
factor χ represents the percentage inductor ripple current.
For the bulk capacitance, which we assume contributes
1% to the total output ripple, the minimum required
capacitance is approximately:
C OUT ≥
IO(MAX )
0.01• n • VOUT • f
For many designs it will be necessary to use one type of
capacitor to obtain the required ESR, and another type to
satisfy the bulk capacitance. For example, using a low ESR
ceramic capacitor can minimize the ESR step, while an
electrolytic capacitor can be used to supply the required
bulk C.
The output ripple current is divided between the various
capacitors connected in parallel at the output voltage.
Although ceramic capacitors are generally known for low
ESR (especially X5R and X7R), these capacitors suffer
from a relatively high voltage coefficient. Therefore, it is
not safe to assume that the entire ripple current flows in
the ceramic capacitor. Aluminum electrolytic capacitors
are generally chosen because of their high bulk capacitance, but they have a relatively high ESR. As a result,
some amount of ripple current will flow in this capacitor.
If the ripple current flowing into a capacitor exceeds its
RMS rating, the capacitor will heat up, reducing its effective capacitance and adversely affecting its reliability. After
the output capacitor configuration has been determined
using the equations provided, measure the individual
capacitor case temperatures in order to verify good thermal performance.
Setting Output Voltage
The LTC7871 output voltage is set by two external feedback resistive dividers carefully placed across VHIGH to
ground and VLOW to ground, as shown in Figure 6. The
regulated output voltage is determined by:
⎛ R ⎞
⎛ R ⎞
VLOW = 1.2V • ⎜ 1+ B ⎟ and VHIGH = 1.2V • ⎜ 1+ D ⎟
⎝ RA ⎠
⎝ RC ⎠
To improve the frequency response, a feed forward capacitor, CFF1/CFF2, may be used. Great care should be taken
to route the feedback line away from noise sources, such
as the inductor or the SW line.
The voltage rating of the output capacitor must be greater
than the maximum output voltage, with sufficient derating
to account for the maximum capacitor temperature.
Because the ripple current in the output capacitor is a
square wave, the ripple current requirements for this
capacitor depend on the duty cycle, the number of phases
and the maximum output current. In order to choose a
ripple current rating for the output capacitor, first establish
the duty cycle range, based on the output voltage and
range of input voltage.
26
VHIGH
CFF2
RD
VLOW
RB
LTC7871
VFBHIGH
CFF1
VFBLOW
RC
RA
7871 F06
Figure 6. Setting Output Voltage
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
External Soft-Start
The LTC7871 has the ability to soft-start by itself using
the internal soft-start or at a slower rate with an external
capacitor on the SS pin. The controller is in the shutdown
state if its RUN pin voltage is below 1.14V and its SS pin
is actively pulled to ground in this shutdown state. If the
RUN pin voltage is above 1.22V, the controller powers
up. Once V5 and DRVCC pass the UVLO thresholds and
power on reset delay expires, a soft-start current of 1μA
then starts to charge the SS soft-start capacitor. Note that
soft-start is achieved not by limiting the maximum VLOW
output current of the controller but by controlling the output ramp voltage according to the ramp rate on the SS
pin. Current foldback is disabled during this phase. The
soft-start range is defined to be the voltage range from
0V to 1.2V on the SS pin. The total soft-start time can be
calculated as:
C
tSOFTSTART = 1.2 • SS
1µA
of 4.7μF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1μF ceramic capacitor placed directly adjacent to
the V5 and SGND pins is highly recommended.
Fault Conditions: Current Limit and Current Foldback
In buck mode, the LTC7871 includes current foldback to
help limit power dissipation when the VLOW is shorted to
ground. If the VLOW falls below 33% of its nominal output
level, then the maximum sense voltage is progressively
lowered from its maximum programmed value to one-third
of the maximum value. Foldback current limiting is disabled
during soft-start. Under short-circuit conditions with very
low duty cycles, the LTC7871 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short circuit ripple current is determined by the minimum on-time tON(MIN) of the
LTC7871, the VHIGH voltage and inductor value:
V
∆IL(SC ) = t ON(MIN ) • HIGH
L
The Internal LDOs
The LTC7871 features three internal PMOS LDOs. Two
provide power to DRVCC from either the VHIGH or VLOW
supply, and the third provides the V5 rail from DRVCC.
DRVCC powers the external top and bottom gate drive
circuits, and V5 powers the LTC7871’s internal circuitry.
There are two DRVCC LDOs—one that converts DRVCC
from VHIGH (LDO1) and another that converts DRVCC from
VLOW (LDO2), thus allowing the part to start up with just
one of the two rails present! Only one of those LDOs is
active at any given time. If VLOW is higher than the EXTVCC
switchover threshold, LDO2 is active; if it is below the switchover threshold, LDO1 is active. The DRVCC pin regulation voltage is determined by the state of the DRVSET pin.
The DRVSET pin uses a 3-level logic. When DRVSET is
either grounded, floated or tied to V5, the typical value for
the DRVCC voltage will be 5V, 8V and 10V, respectively.
Please note that the DRVSET pin has an internal 160kΩ pull
down resistor to SGND and a 200kΩ pull up resistor to V5.
The V5 LDO regulates the voltage at the V5 pin to 5V when
DRVCC is at least 6V. The LDO can supply a peak current of
20mA and must be bypassed to ground with a minimum
The resulting short circuit current is:
⎛
ISC = ⎜
⎝
1 V
3 SENSE(MAX )
RSENSE
⎞
1
– ∆IL(SC) ⎟
2
⎠
After a short, make sure that the load current takes the
folded back current limit into account.
Phase-Locked Loop and Frequency Synchronization
The LTC7871 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the SYNC pin. The phase detector is an edge
sensitive digital type that provides zero degrees phase
shift between the external and internal oscillators. This
type of phase detector does not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the
internal filter network. There is a precision 20μA current
Rev. A
For more information www.analog.com
27
LTC7871
APPLICATIONS INFORMATION
flowing out of the FREQ pin. This allows the user to use
a single resistor to SGND to set the switching frequency
when no external clock is applied to the SYNC pin. The
internal switch between the FREQ pin and the integrated
PLL filter network is on, allowing the filter network to be
pre-charged at the same voltage as of the FREQ pin. The
relationship between the voltage on the FREQ pin and
operating frequency is shown in Figure 7 and specified in
the Electrical Characteristics table. If an external clock is
detected on the SYNC pin, the internal switch mentioned
above turns off and isolates the influence of the FREQ
pin. Note that the LTC7871 can only be synchronized to
an external clock whose frequency is within range of the
LTC7871’s internal VCO. A simplified block diagram is
shown in Figure 8.
1000
FREQUENCY (kHz)
where, VFREQ = IFREQ (from spec table) • RFREQ
600
Or,
Frequency = RFREQ • 8.28kHz/kΩ– 163.5kHz
400
This assumes a perfect 20μA IFREQ.
200
0
Shared Pin Connections in Multichip Applications
0
0.5
1
1.5
2
2.5
VFREQ (V)
3
7871 F07
Figure 7. Relationship Between Oscillator Frequency
and Voltage at the FREQ Pin
2.4V
RFREQ
FREQ
SYNC
DIGITAL
SYNC
PHASE/
FREQUENCY
DETECTOR
VCO
7871 F08
Figure 8. Phase-Locked Loop Block Diagram
When multiple LTC7871 ICs are used together in high current applications, the customer may or may not connect
certain pins together, balancing better communication
between the ICs versus avoiding a single point failure.
The CLKOUT pin allows multiple LTC7871s to be daisy
chained together. The clock output signal on the CLKOUT
pin can be used to synchronize additional ICs in a multiphase power supply solution feeding a single high current
output, or even several outputs from the same input supply.
5V
20µA
28
Typically, the external clock (on the SYNC pin) input high
threshold is 2V, while the input low threshold is 1.1V. The
LTC7871 switching frequency is determined by:
Frequency = VFREQ • 414kHz/V – 163.5kHz
800
EXTERNAL
OSCILLATOR
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
The SS and PWMEN pins should be tied together to enable
every LTC7871 IC to start up together. Not connecting
them together may result in some phases sourcing a lot
of current and others sinking current.
The IMON pins may or may not be tied together, depending on whether the customer wants to monitor the
average current per IC or the total average current in
the application.
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
The ILIM, SETCUR, FREQ, MODE, BUCK, and DRVSET
pins may or may not be tied together based on convenience. When tying these pins together, please be aware
of the pull-up/down currents/resistors on these pins! Any
external resistor or resistor divider network must take
those into account. For example, each FREQ pin sources
20μA. When two LTC7871 ICs have their FREQ pins tied
together, that is 40μA.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the controller will begin to skip cycles.
The output voltage and current will continue to be regulated,
but the voltage ripple and current ripple will increase. The
minimum on-time for the LTC7871 is approximately 150ns,
with good PCB layout, minimum 30% inductor current ripple and at least 2mV ripple on the current sense signal or
equivalent 10mV between SNSA+ and SNS– pins.
The OVLOW, OVHIGH and UVHIGH pins of multiple LTC7871s
must be tied together. This enables the entire system to
react to an OV/UV condition appropriately. The resistor
divider used on these pins must be scaled based on the
number of LTC7871s paralleled, as these pins have 5μA
hysteresis currents that turn on and off.
The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak
sense voltage decreases, the minimum on-time gradually increases. This is of particular concern in forced
continuous applications with low ripple current at light
loads. If the duty cycle drops below the minimum ontime limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
The ITHLOW and ITHHIGH pins of multiple LTC7871s
should be tied together. Tying the ITHLOW pins together
and the ITHHIGH pins together gives the best current sharing between phases. Each error amplifier’s compensation
network must be placed local to the specific IC to minimize jitter and stability issues.
The RUN pins must be tied together – this is very critical
for boost mode operation. In boost mode, when multiple
LTC7871 have their RUN pins connected together, care
must be taken to ensure that the logic signal on the RUN
pin is a clean fast rising/falling signal so all ICs are enabled
at the same instant. If a resistor divider is used on the
RUN pin, then the part must be started up in buck mode.
Using a resistor divider on the RUN pin off VHIGH, set for
a start-up voltage higher than the UVHIGH set point, allows
the part to soft start cleanly after a UVHIGH fault is cleared.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC7871 is capable of turning on the top MOSFET.
It is determined by internal timing delays, power stage
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
tON(MIN) <
VLOW
VHIGH ( f )
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC7871 circuits: 1) IC VHIGH current, 2)
MOSFET driver current, 3) I2R losses, 4) top MOSFET
transition losses.
1. The VHIGH current is the DC supply current given in the
Electrical Characteristics table. VHIGH current typically
results in a small (1μF) supply bypass capacitors. The discharged
bypass capacitors are effectively put in parallel with CLOW,
causing a rapid drop in VLOW. No regulator can alter its
delivery of current quickly enough to prevent this sudden
step change in output voltage if the load switch resistance
is low and it is driven quickly. If the ratio of CLOAD to COUT is
greater than 1:50, the switch rise time should be controlled
so that the load rise time is limited to approximately 25 •
CLOAD. Thus a 10μF capacitor would require a 250μs rise
time, limiting the charging current to about 200mA.
The serial bus is comprised of CSB, SCLK, SDI and SDO.
Data transfers to the part are accomplished by the serial
bus master device first taking CSB low to enable the
LTC7871’s port. Input data applied on SDI is clocked on
the rising edge of SCLK, with all transfers MSB first. The
communication burst is terminated by the serial bus master returning CSB high. See Figure 9 for details.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC7871 connected in parallel on the serial bus), as SDO
is high impedance (Hi-Z) when CSB = 1, or when data is
not being read from the part. If the LTC7871 is not used
in a multidrop configuration, or if the serial port master is not capable of setting the SDO line level between
read sequences, it is recommended to attach a resistor
between SDO and V5 to ensure the line returns to V5 during Hi-Z states. The resistor value should be large enough
to ensure that the SDO output current does not exceed
10mA. See Figure 10 for details.
SERIAL PORT
The SPI-compatible serial port provides control and monitoring functionality.
MASTER–CSB
tCSS
tCKH
tCKL
tCSS
tCSH
MASTER–SCLK
tCS
MASTER–SDI
tCH
DATA
DATA
7871 F09
Figure 9. Serial Port Write Timing Diagram
MASTER–CSB
8TH CLOCK
MASTER–SCLK
tDO
LTC7871–SDO
tDO
tDO
tDO
DATA
DATA
7871 F10
Figure 10. Serial Port Read Timing Diagram
Rev. A
For more information www.analog.com
31
LTC7871
APPLICATIONS INFORMATION
Single Byte Transfers
The serial port is arranged as a simple memory map, with
status and control available in 5 read/write and 6 read only
byte-wide registers. All data bursts are comprised of at
least three bytes. The 7 most significant bits (MSB) of the
first byte are the register address, with an LSB of 1 indicating a read from the part, and LSB of 0 indicating a write
to the part. The second byte, is data from/to the specified
register address. The third byte, is the PEC (packet error
code) byte. See Figure 11 for an example of a detailed
write sequence, and Figure 12 for a read sequence. All
bytes shift with MSB first.
Figure 13 shows an example of two write communication bursts. The first byte of the first burst sent from the
MASTER-CSB
24 CLOCKS
MASTER-SCLK
7-BIT REGISTER ADDRESS
MASTER-SDI
8 BITS OF DATA
PARALLEL LOAD
8 BITS OF PEC
A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 P7 P6 P5 P4 P3 P2 P1 P0
0 = WRITE
7871 F11
LTC7871-SDO
Figure 11. Serial Port Write Sequence
MASTER-CSB
MASTER-SCLK
24 CLOCKS
7-BIT REGISTER ADDRESS
MASTER-SDI
1 = READ
A6 A5 A4 A3 A2 A1 A0 1
8 BITS OF DATA
8 BITS OF PEC
X D7 D6 D5 D4 D3 D2 D1 D0 P7 P6 P5 P4 P3 P2 P1 P0
LTC7871-SDO
7871 F12
Figure 12. Serial Port Read Sequence
MASTER–CSB
MASTER–SDI
ADDR0+WR
DATA0
PEC0
ADDR1+WR
PEC1
7871 F13
LTC7871–SDO
Figure 13. Two Write Communication Bursts
32
DATA1
For more information www.analog.com
Rev. A
LTC7871
APPLICATIONS INFORMATION
serial bus master on SDI contains the destination register
address (ADDR0) and a following 0 indicating a write.
The next byte is the DATA0 intended for the register at
address ADDR0. The third byte is the PEC0. CSB is then
taken high to terminate the transfer. The first byte of the
second burst contains the destination register address
(ADDR1) and a following 0 indicating a write. The next
byte on SDI is the DATA1 intended for the register at
address ADDR1. The third byte is the PEC1. CSB is then
taken high to terminate the transfer. Note that the written
data is transferred to the internal register at the falling
edge of the 24th clock cycle (parallel load) in each burst
after the PEC is checked as valid.
3. Update the 8-bit PEC as PEC[7] = PEC[6],
PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,
PEC[1] = IN1, PEC[0] = IN0.
4. Go back to step 2 until all data are shifted. The 8-bit
result is the final PEC byte.
An example to calculate the PEC is listed in Table 6 and
Figure 14. The PEC of the 1 byte data 0x01 is computed
as 0xC7 after the last bit of the byte clocked in.
For the serial port write sequence, the master calculates
the PEC byte for the address byte and data byte it sends
out. The master latches the PEC byte it calculates at the
15th clock falling edge and attaches the calculated PEC
byte following the data byte it shifts out. The LTC7871
also calculates PEC byte for the address byte and data
byte it receives. The LTC7871 latches the PEC byte it calculates at the 16th clock rising edge and compares it with
the PEC byte following the data byte. The data is regarded
as valid only if the PEC bytes match.
PEC Byte
The PEC byte a cyclic redundancy check (CRC) value calculated for all the bits in a register group in the order they
are passed, using the initial PEC value of 01000001 (0x41)
and the following characteristic polynomial:
x8 + x2 + x + 1
For the serial port read sequence, the LTC7871 calculates
PEC byte for the received address byte and data byte it
sends out. The LTC7871 latches the PEC byte at the 15th
clock falling edge and attaches the calculated PEC byte
following the data byte it shifts out. The master calculates
PEC byte for the address byte it sends and data byte it
receives. The master latches the PEC byte at the 16th
clock rising edge and compares it with the PEC byte following the data byte it receivers. The data is regarded as
valid only if the PEC bytes match.
To calculate the 8-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 0100 0001.
2. For each bit DIN coming into the register group, set
IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,
IN2 = PEC[1] XOR IN0.
Table 6. Procedure to Calculate PEC Byte
CLOCK
CYCLE
DIN
IN0
IN1
IN2
PEC[7]
PEC[6]
PEC[5]
PEC[4]
PEC[3]
PEC[2]
PEC[1]
PEC[0]
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
0
0
0
0
0
1
0
2
0
0
1
1
0
0
0
0
0
0
1
1
3
0
0
0
1
0
0
0
0
0
1
1
0
4
0
0
0
0
0
0
0
0
1
1
0
0
5
0
0
0
0
0
0
0
1
1
0
0
0
6
0
0
0
0
0
0
1
1
0
0
0
0
7
1
1
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
8
Rev. A
For more information www.analog.com
33
34
1
XOR
IN0
DTFF
For more information www.analog.com
END
INO = DATAIN XOR PEC[7];
PEC1 = PEC[0] XOR IN0;
PEC2 = PEC[1] XOR IN0;
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
2
3
4
2
1
BEGIN PEC[7:0] = 0x41
CLK Q
Q
PEC[0]
D
PEC Hardware and Software Example
CLOCK
BEGIN PEC[7:0] = 0x41
INO = DATAIN XOR PEC[7];
DATAIN
PEC[7]
PEC[0]
INO
XOR
PEC1
Q
DTFF
CLK Q
D
PEC[1]
PEC1 = PEC[0] XOR IN0;
PEC2
Q
DTFF
CLK Q
D
PEC[2]
PEC[2]
Q
DTFF
CLK Q
D
PEC[3]
PEC[3]
Figure 14. 8-Bit PEC Computation Circuit
XOR
PEC2 = PEC[1] XOR IN0;
PEC[1]
IN0
3
4
Q
DTFF
CLK Q
D
END
PEC[4]
PEC[4]
Q
DTFF
CLK Q
D
PEC[5]
PEC[5]
Q
DTFF
CLK Q
D
PEC[6]
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
PEC[6]
PEC[7]
Q
7871 F14
DTFF
CLK Q
D
PEC[7]
LTC7871
APPLICATIONS INFORMATION
Rev. A
LTC7871
APPLICATIONS INFORMATION
Multidrop Configuration
Several LTC7871s may share the serial bus. In this multidrop configuration, SCLK, SDI, and SDO are common between
all parts. The serial bus master must use a separate CSB for each LTC7871 and ensure that only one device has CSB
asserted at any time during the serial port read sequence. It is recommended to attach a high value resistor to SDO to
ensure the line returns to a known level during Hi-Z states.
Serial Port Register Definition
Table 7. Register Summary
Register NAME
Register
Address
(7 bits)
Description
TYPE
MFR_FAULT
0x01
One byte summary of the unit’s fault condition.
R
MFR_OC_FAULT
0x02
One byte summary of the unit’s overcurrent fault condition.
R
MFR_NOC_FAULT
0x03
One byte summary of the unit’s negative overcurrent fault condition.
R
MFR_STATUS
0x04
One byte summary of the unit’s operation status.
R
MFR_CONFIG1
0x05
One byte summary of the unit’s configuration
R
MFR_CONFIG2
0x06
One byte summary of the unit’s configuration
MFR_CHIP_CTRL
0x07
[3] = Communication Fault, [1] = Sticky Bit, [0] = Write Protection
DEFAULT
VALUE
R
R/W
0x00
MFR_IDAC_VLOW
0x08
Adjust the IDAC_VLOW to program VLOW voltage.
R/W
0x00
MFR_IDAC_VHIGH
0x09
Adjust the IDAC_VHIGH to program VHIGH voltage.
R/W
0x00
MFR_IDAC_SETCUR
0x0A
Adjust the IDAC_SETCUR to program SETCUR pin’s sourcing current.
R/W
0x00
MFR_SSFM
0x0B
Adjust the spread spectrum frequency modulation parameters.
R/W
0x00
RESERVED
0x0C
0x0D
0x0E
0x0F
SERIAL PORT REGISTER DETAILS
MFR_FAULT
The MFR_FAULT returns a one-byte summary of the most critical faults.
MFR_FAULT Register Contents:
BIT
NAME
VALUE
7
6
MEANING
Reserved
VLOW_OV
1
The OVLOW pin is higher than 1.2V threshold.
5
VHIGH_OV
1
The OVHIGH pin is higher than 1.2V threshold.
4
VHIGH_UV
1
The UVHIGH pin is less than 1.2V threshold.
3
DRVCC_UV
1
The DRVCC pin is undervoltage.
2
V5_UV
1
The V5 pin is undervoltage.
1
VREF_BAD
1
The internal reference self-check fails.
0
OVER_TEMP
1
An over temperature fault has occurred.
Rev. A
For more information www.analog.com
35
LTC7871
APPLICATIONS INFORMATION
MFR_OC_FAULT
The MFR_OC_FAULT returns a one-byte summary of overcurrent fault condition. When the voltage difference between
SNSD+ and SNS– pins is larger than the overcurrent fault threshold programmed by the ILIM pin, the corresponding
register bit will become 1.
MFR_OC_FAULT Register Contents:
BIT
NAME
VALUE
7:6
MEANING
Reserved
5
OC_FAULT_6
1
Channel 6 overcurrent fault has occurred.
4
OC_FAULT_5
1
Channel 5 overcurrent fault has occurred.
3
OC_FAULT_4
1
Channel 4 overcurrent fault has occurred.
2
OC_FAULT_3
1
Channel 3 overcurrent fault has occurred.
1
OC_FAULT_2
1
Channel 2 overcurrent fault has occurred.
0
OC_FAULT_1
1
Channel 1 overcurrent fault has occurred.
MFR_NOC_FAULT
The MFR_NOC_FAULT returns a one-byte summary of negative overcurrent fault condition. When the voltage difference
between SNSD+ and SNS– pins is less than the negative overcurrent fault threshold programmed by the ILIM pin, the
corresponding register bit will become 1.
MFR_NOC_FAULT Register Contents:
BIT
NAME
VALUE MEANING
7:6
Reserved
5
NOC_FAULT_6
1
Channel 6 negative overcurrent fault has occurred.
4
NOC_FAULT_5
1
Channel 5 negative overcurrent fault has occurred.
3
NOC_FAULT_4
1
Channel 4 negative overcurrent fault has occurred.
2
NOC_FAULT_3
1
Channel 3 negative overcurrent fault has occurred.
1
NOC_FAULT_2
1
Channel 2 negative overcurrent fault has occurred.
0
NOC_FAULT_1
1
Channel 1 negative overcurrent fault has occurred.
36
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
MFR_STATUS
The MFR_STATUS returns a one-byte summary of the operation status. The content of the MFR_STATUS register is
read only.
MFR_STATUS Register Contents:
BIT
NAME
VALUE
7:3
MEANING
Reserved
2
SS_DONE
1
The soft-start is finished.
1
MAX_CURRENT
1
The maximum current programmed by the ILIM pin is reached.
0
PGOOD
1
The regulated VLOW/VHIGH is within ±10% regulation windows.
MFR_CONFIG1
The MFR_CONFIG1 returns a one-byte summary of the configuration of the controller programmed by the pins. The
content of the MFR_CONFIG1 register is read only.
MFR_CONFIG1 Register Contents:
BIT
NAME
VALUE MEANING
7:6
5
Reserved
SERCUR_WARNING
1
The SETCUR pin is programmed to be above 1.25V.
4:3
DRVCC_SET[1:0]
00
01
10
The DRVCC is programmed to 5V.
The DRVCC is programmed to 8V.
The DRVCC is programmed to 10V.
2:0
ILIM_SET[2:0]
000
001
010
011
100
The maximum current sense threshold is programmed to 10mV.
The maximum current sense threshold is programmed to 20mV.
The maximum current sense threshold is programmed to 30mV.
The maximum current sense threshold is programmed to 40mV.
The maximum current sense threshold is programmed to 50mV.
Rev. A
For more information www.analog.com
37
LTC7871
APPLICATIONS INFORMATION
MFR_CONFIG2
The MFR_CONFIG2 returns a one-byte summary of the
configuration of the controller programmed by the pins.
The content of the MFR_CONFIG2 register is read only.
MFR_CONFIG2 Register Contents:
BIT
NAME
VALUE
7:5
MEANING
Reserved
4
BURST
1
The controller is in burst mode operation.
3
DCM
1
The controller is in DCM.
2
HIZ
1
The controller is in Hi-Z mode.
1
SPRD
1
The controller is in spread spectrum mode.
0
BUCK_BOOST
0
1
The controller is in boost mode.
The controller is in buck mode.
MFR_CHIP_CTRL
The MFR_CHIP_CTRL is for general chip control.
MFR_CHIP_CTRL Message Contents:
BIT
NAME
VALUE
7:3
MEANING
Reserved
2
CML
1
A communication fault related to PEC during writing registers has occurred. Write 1 to this bit will clear the CML.
1
RESET
1
Sticky bit, reset all R/W registers.
0
WP
0
1
Write allowed for all three IDAC registers, and MFR_SSFM register.
Write inhibited for all three IDAC registers, and MFR_SSFM register.
38
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
MFR_IDAC_VLOW
The MFR_IDAC_VLOW stores the current DAC value to program the VLOW voltage by injecting the current DAC output
to the VFBLOW pin. It is formatted as a 7-bit two’s complement value. Setting BIT[6] = 0 means sourcing current from
the VFBLOW pin; and BIT[6] = 1 means sinking current. The detail is listed in Table 8. The DAC current is only injected
to the VFBLOW pin in buck mode. Sinking current will cause VLOW to rise. The default value for this register is 0x00.
Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.
MFR_IDAC_VLOW Message Contents:
BIT
7
6
5
4
3
2
1
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MEANING
Reserved
0µA
–64µA
0µA
32µA
0µA
16µA
0µA
8µA
0µA
4µA
0µA
2µA
0µA
1µA
MFR_IDAC_VHIGH
The MFR_IDAC_VHIGH stores the current DAC value to program the VHIGH voltage by injecting the current DAC output
to the VFBHIGH pin. It is formatted as a 7-bit two’s complement value. Setting BIT[6] = 0 means sourcing current from
the VFBHIGH pin; and BIT[6] = 1 means sinking current. The detail is listed in Table 8. The DAC current is only injected
to the VFBHIGH pin in boost mode. Sinking current will cause VHIGH to rise in boost mode. The default value for this
register is 0x00. Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.
MFR_IDAC_VHIGH Message Contents:
BIT
7
6
5
4
3
2
1
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MEANING
Reserved
0µA
–64µA
0µA
32µA
0µA
16µA
0µA
8µA
0µA
4µA
0µA
2µA
0µA
1µA
Rev. A
For more information www.analog.com
39
LTC7871
APPLICATIONS INFORMATION
MFR_IDAC_SETCUR
The MFR_IDAC_SETCUR stores the current DAC value to program the sourcing current of the SETCUR pin. It is formatted as a 5-bit two’s complement value. The default value for this register is 0x00 and the SETCUR pin originally
sources 16µA. This register can program the SETCUR pin sourcing current from 0 to 31µA as shown in the Table 9.
Writes to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.
MFR_IDAC_SETCUR Message Contents:
BIT
VALUE
7:5
MEANING
RESERVED
4
0
1
16µA
0µA
3
0
1
0µA
8µA
2
0
1
0µA
4µA
1
0
1
0µA
2µA
0
0
1
0µA
1µA
MFR_SSFM
The MFR_SSFM is for spread spectrum frequency modulation control. The default value for this register is 0x00. Writes
to this register are inhibited when the WP, BIT[0] in MFR_CHIP_CTRL, is set high.
MFR_SSFM Message Contents:
BIT
NAME
VALUE MEANING
7:5
4:3
2:0
40
Reserved
Frequency Spread
Range
Modulation Signal
Frequency
00
±12%
01
±15%
10
±10%
11
±8%
000
Controller Switching Frequency/512
001
Controller Switching Frequency/1024
010
Controller Switching Frequency/2048
011
Controller Switching Frequency/4096
100
Controller Switching Frequency/256
101
Controller Switching Frequency/128
110
Controller Switching Frequency/64
111
Controller Switching Frequency/512
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
Table 8. VFBLOW/VFBHIGH PIN Current and Corresponding DAC Codes
Table 8. VFBLOW/VFBHIGH PIN Current and Corresponding DAC Codes
MFR_IDAC_VLOW/MFR_IDAC_VHIGH
MFR_IDAC_VLOW/MFR_IDAC_VHIGH
[6]
[5]
[4]
[3]
[2]
[1]
[0]
IVFBLOW/VFBHIGH (µA)
[6]
[5]
[4]
[3]
[2]
[1]
[0]
IVFBLOW/VFBHIGH (µA)
1
0
0
0
0
0
0
–64
1
1
0
0
0
0
0
–32
1
0
0
0
0
0
1
–63
1
1
0
0
0
0
1
–31
1
0
0
0
0
1
0
–62
1
1
0
0
0
1
0
–30
1
0
0
0
0
1
1
–61
1
1
0
0
0
1
1
–29
1
0
0
0
1
0
0
–60
1
1
0
0
1
0
0
–28
1
0
0
0
1
0
1
–59
1
1
0
0
1
0
1
–27
1
0
0
0
1
1
0
–58
1
1
0
0
1
1
0
–26
1
0
0
0
1
1
1
–57
1
1
0
0
1
1
1
–25
1
0
0
1
0
0
0
–56
1
1
0
1
0
0
0
–24
1
0
0
1
0
0
1
–55
1
1
0
1
0
0
1
–23
1
0
0
1
0
1
0
–54
1
1
0
1
0
1
0
–22
1
0
0
1
0
1
1
–53
1
1
0
1
0
1
1
–21
1
0
0
1
1
0
0
–52
1
1
0
1
1
0
0
–20
1
0
0
1
1
0
1
–51
1
1
0
1
1
0
1
–19
1
0
0
1
1
1
0
–50
1
1
0
1
1
1
0
–18
1
0
0
1
1
1
1
–49
1
1
0
1
1
1
1
–17
1
0
1
0
0
0
0
–48
1
1
1
0
0
0
0
–16
1
0
1
0
0
0
1
–47
1
1
1
0
0
0
1
–15
1
0
1
0
0
1
0
–46
1
1
1
0
0
1
0
–14
1
0
1
0
0
1
1
–45
1
1
1
0
0
1
1
–13
1
0
1
0
1
0
0
–44
1
1
1
0
1
0
0
–12
1
0
1
0
1
0
1
–43
1
1
1
0
1
0
1
–11
1
0
1
0
1
1
0
–42
1
1
1
0
1
1
0
–10
1
0
1
0
1
1
1
–41
1
1
1
0
1
1
1
–9
1
0
1
1
0
0
0
–40
1
1
1
1
0
0
0
–8
1
0
1
1
0
0
1
–39
1
1
1
1
0
0
1
–7
1
0
1
1
0
1
0
–38
1
1
1
1
0
1
0
–6
1
0
1
1
0
1
1
–37
1
1
1
1
0
1
1
–5
1
0
1
1
1
0
0
–36
1
1
1
1
1
0
0
–4
1
0
1
1
1
0
1
–35
1
1
1
1
1
0
1
–3
1
0
1
1
1
1
0
–34
1
1
1
1
1
1
0
–2
1
0
1
1
1
1
1
–33
1
1
1
1
1
1
1
–1
Rev. A
For more information www.analog.com
41
LTC7871
APPLICATIONS INFORMATION
Table 8. VFBLOW/VFBHIGH PIN Current and Corresponding DAC Codes
Table 8. VFBLOW/VFBHIGH PIN Current and Corresponding DAC Codes
MFR_IDAC_VLOW/MFR_IDAC_VHIGH
MFR_IDAC_VLOW/MFR_IDAC_VHIGH
[6]
[5]
[4]
[3]
[2]
[1]
[0]
IVFBLOW/VFBHIGH (µA)
[6]
[5]
[4]
[3]
[2]
[1]
[0]
IVFBLOW/VFBHIGH (µA)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
32
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
33
0
0
0
0
0
1
0
2
0
1
0
0
0
1
0
34
0
0
0
0
0
1
1
3
0
1
0
0
0
1
1
35
0
0
0
0
1
0
0
4
0
1
0
0
1
0
0
36
0
0
0
0
1
0
1
5
0
1
0
0
1
0
1
37
0
0
0
0
1
1
0
6
0
1
0
0
1
1
0
38
0
0
0
0
1
1
1
7
0
1
0
0
1
1
1
39
0
0
0
1
0
0
0
8
0
1
0
1
0
0
0
40
0
0
0
1
0
0
1
9
0
1
0
1
0
0
1
41
0
0
0
1
0
1
0
10
0
1
0
1
0
1
0
42
0
0
0
1
0
1
1
11
0
1
0
1
0
1
1
43
0
0
0
1
1
0
0
12
0
1
0
1
1
0
0
44
0
0
0
1
1
0
1
13
0
1
0
1
1
0
1
45
0
0
0
1
1
1
0
14
0
1
0
1
1
1
0
46
0
0
0
1
1
1
1
15
0
1
0
1
1
1
1
47
0
0
1
0
0
0
0
16
0
1
1
0
0
0
0
48
0
0
1
0
0
0
1
17
0
1
1
0
0
0
1
49
0
0
1
0
0
1
0
18
0
1
1
0
0
1
0
50
0
0
1
0
0
1
1
19
0
1
1
0
0
1
1
51
0
0
1
0
1
0
0
20
0
1
1
0
1
0
0
52
0
0
1
0
1
0
1
21
0
1
1
0
1
0
1
53
0
0
1
0
1
1
0
22
0
1
1
0
1
1
0
54
0
0
1
0
1
1
1
23
0
1
1
0
1
1
1
55
0
0
1
1
0
0
0
24
0
1
1
1
0
0
0
56
0
0
1
1
0
0
1
25
0
1
1
1
0
0
1
57
0
0
1
1
0
1
0
26
0
1
1
1
0
1
0
58
0
0
1
1
0
1
1
27
0
1
1
1
0
1
1
59
0
0
1
1
1
0
0
28
0
1
1
1
1
0
0
60
0
0
1
1
1
0
1
29
0
1
1
1
1
0
1
61
0
0
1
1
1
1
0
30
0
1
1
1
1
1
0
62
0
0
1
1
1
1
1
31
0
1
1
1
1
1
1
63
42
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
Table 9. SETCUR Pin Current and Corresponding DAC Codes
Table 9. SETCUR Pin Current and Corresponding DAC Codes
MFR_IDAC_SETCUR[4:0]
MFR_IDAC_SETCUR[4:0]
[4]
[3]
[2]
[1]
[0]
ISETCUR (µA)
[4]
[3]
[2]
[1]
[0]
ISETCUR (µA)
1
0
0
0
0
0
0
0
0
0
0
16
1
0
0
0
1
1
0
0
0
0
1
17
1
0
0
1
0
2
0
0
0
1
0
18
1
0
0
1
1
3
0
0
0
1
1
19
1
0
1
0
0
4
0
0
1
0
0
20
1
0
1
0
1
5
0
0
1
0
1
21
1
0
1
1
0
6
0
0
1
1
0
22
1
0
1
1
1
7
0
0
1
1
1
23
1
1
0
0
0
8
0
1
0
0
0
24
1
1
0
0
1
9
0
1
0
0
1
25
1
1
0
1
0
10
0
1
0
1
0
26
1
1
0
1
1
11
0
1
0
1
1
27
1
1
1
0
0
12
0
1
1
0
0
28
1
1
1
0
1
13
0
1
1
0
1
29
1
1
1
1
0
14
0
1
1
1
0
30
1
1
1
1
1
15
0
1
1
1
1
31
Rev. A
For more information www.analog.com
43
LTC7871
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 15. Check the following in the
PC layout:
1. The DRVCC bypass capacitor should be placed immediately adjacent to the IC between the DRVCC pin and
the GND plane. A 1μF ceramic capacitor of the X7R or
X5R type is small enough to fit very close to the IC. An
additional 4.7μF to 10μF of ceramic, tantalum or other
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
2. The V5 bypass capacitor should be placed immediately
adjacent to the IC between the V5 and the SGND pins.
A 4.7μF to 10μF capacitor of ceramic, tantalum or other
very low ESR capacitance is recommended.
3. Place the feedback divider between the + and – terminals
of CLOW/CHIGH. Route VFBLOW/VFBHIGH with minimum
PC trace spacing from the IC to the feedback dividers.
4. Are the SNSA+, SNSD+ and SNS– printed circuit traces
routed together with minimum PC trace spacing? The
filter capacitors between SNSA+, SNSD+ and SNS–
should be as close as possible to the pins of the IC.
5. Do the (+) plates of CHIGH decoupling cap connect to
the drain of the topside MOSFET as closely as possible? This capacitor provides the pulsed current to
the MOSFET.
6. Keep the switching nodes away from sensitive smallsignal nodes (SNSD+, SNSA+, SNS–, VFB). Ideally the
switch nodes printed circuit traces should be routed
away and separated from the IC and especially the
quiet side of the IC. Separate the high dV/dt traces
from sensitive small-signal nodes with ground traces
or ground planes.
7. Use a low impedance source such as a logic gate to
drive the SYNC pin and keep the PCB trace as short
as possible.
8. The ceramic capacitors between each ITH pin and signal ground should be placed as close as possible to
the IC. Figure 15 illustrates all branch currents in a
switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep
the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
CLOW ground should return to the negative terminal of
CHIGH and not share a common ground path with any
switched current paths. The left half of the circuit gives
rise to the noise generated by a switching regulator.
The ground terminations of the bottom MOSFET and
Schottky diode should return to the bottom plate(s) of
the VHIGH capacitor(s) with a short isolated PC trace
since very high switched currents are present. External
OPTI-LOOP® compensation allows overcompensation
for PC layouts which are not optimized, but this is not
the recommended design procedure.
L1
VHIGH
SW2
RHIGH
+
CHIGH
D1
VLOW
RSENSE
SW1
CLOW
+
RLOW
7871 F15
BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH
Figure 15. Branch Current Waveforms (Buck Mode Shown)
44
Rev. A
For more information www.analog.com
LTC7871
APPLICATIONS INFORMATION
Special Layout Consideration
Exceeding Absolute Max ratings on the EXTVCC pin can
result in damage to the controller. As the EXTVCC pin is
normally connected to VLOW, it is recommended to put
a Schottky diode with an appropriately high voltage rating between the VLOW and the EXTVCC pins as shown in
Figure 16(a). Choose the right Schottky diode with the
forward voltage less than 0.5V at the maximum EXTVCC
pin current.
Another method to protect on the EXTVCC pin is to use a
Schottky diode to clamp the EXTVCC pin to reduce voltage spiking below ground. The Schottky diode should be
placed close to the controller IC, with the cathode connected to the EXTVCC pin and the anode connected to
ground as shown in the Figure 16(b). Choose a minimum
1Ω RFLTR and keep the maximum voltage drop across the
RFLTR less than 0.5V.
LTC7871
VLOW
EXTVCC
1μF
(30A/phase), and f = 150kHz. The regulated output voltage
is determined by:
VLOW = 1.2V • (1 + RB/RA).
Using a 10k 1% resistor from the VFBLOW node to ground,
the top feedback resistor is (to the nearest 1% standard
value) 90.9k. The frequency is set by selecting the RFREQ
to be 37.4kΩ. The inductance values are based on a 35%
maximum ripple current assumption (10.5A for each
phase). The highest value of ripple current occurs at the
maximum VHIGH voltage:
L=
Each phase will require 6.1μH. The Sagami CVE2622C6R8M, 6.8μH, 1.8mΩ DCR inductor is chosen. At the
nominal VHIGH voltage (48V), the ripple current will be:
VLOW
RFLTR
EXTVCC
1μF
∆IL(NOM) =
TON(MIN) =
Design Example
As a design example for a six-phase single output
high current regulator, assume VHIGH = 48V (nominal),
VHIGH = 60V (maximum), VLOW = 12V, IVLOW(MAX) = 180A
VLOW
VHIGH(MAX ) • f
RSENSE(EQUIV ) =
Figure 16. Methods to Protect the EXTVCC Pin
VLOW ⎞
⎛
• 1–
⎜⎝ V
⎟
HIGH(NOM) ⎠
=
12V
= 1.33µs
60V •150kHz
With VILIM = 3/4 VV5, the equivalent RSENSE resistor value
can be calculated by using the minimum value for the
maximum current sense threshold (45mV):
7871 F16
(b)
VLOW
f •L
Each phase will have 8.8A (29.3%) ripple. The peak inductor current will be the maximum DC value plus one-half the
ripple current, or 34.4A. The minimum on-time occurs at
the maximum VHIGH, and should not be less than 150ns:
(a)
LTC7871
VLOW
VLOW ⎞
⎛
• 1–
⎜
f • ∆IL(MAX ) ⎝ VHIGH(MAX ) ⎟⎠
VSENSE(MIN)
∆IL(NOM)
ILOAD(MAX )
+
#OF PHASES
2
The equivalent required RSENSE value is 1.31mΩ. Choose
RS = 1mΩ to allow some design margin. As shown in
Figure 17, set R2 to be below 1/10th of the R1. Therefore,
the DC component of the SNSA+ filter is small enough to
be omitted. R1 • C1 should have a bandwidth that is four
times as high as the L/RS.
Rev. A
For more information www.analog.com
45
LTC7871
APPLICATIONS INFORMATION
Typically, C1 is selected in the range of 0.047μF to 0.47μF.
If C1 is chosen to be 0.1μF, R1 and R2 will be 16.9kΩ
and 1.69kΩ respectively. The bias current at SNSD+ and
SNSA+ is about 50nA, and it causes some small error to
the current sense signal. If C2 is also chosen to be 0.1μF,
R3 will be 1.5kΩ.
R3
1.5k
+
SNSD
LTC7871
SNS–
SNSA+
7871 F17
R1
R2
1.69k 16.9k
SW
L
6.8µH
RS
1mΩ
+
VLOW
Figure 17. RSENSE Resistor Sensing in Design Example
The power dissipation on the top MOSFET can be easily estimated. Set the gate drive voltage (DRVCC) to be
10V. Choosing two Infineon BSC117N08NS5 MOSFETs
results in:
RDS(ON) = 11.7mΩ (max),
VMILLER = 5V, CMILLER ≅ 19pF.
At typical VHIGH voltage with TJ (estimated) = 75°C:
⎫
⎧ 12V
2
⎪
⎪ 48V •15A
⎪
⎪
⎪ • [(1+ 0.005 • ( 75°C – 25°C))•11.7mΩ ]⎪
⎪⎪
⎪⎪
PMAIN = ⎨
⎬•2
15A
• 4Ω •19pF
⎪
⎪+48V 2 •
2
⎪
⎪
⎪
⎪
⎪
⎪ • ⎛⎜ 1 + 1⎞⎟ •150k
⎪⎭
⎪⎩ ⎝ 10 − 5 5 ⎠
= {823mW + 79mW} • 2
= 2.2W
CHIGH is chosen for an equivalent RMS current rating of
at least 20A. CLOW is chosen with an equivalent ESR of
10mΩ for low output ripple. The VLOW output ripple in
continuous mode will be highest at the maximum VHIGH
voltage. The VLOW output voltage ripple due to ESR
is approximately:
VLOWRIPPLE = RESR • ΔIL = 0.01Ω • 8.8A = 88mV
Further reductions in VLOW output voltage ripple can be
made by placing ceramic capacitors across CLOW.
If the output load is a battery, the voltage loop is first set
for the desired output voltage and then the charge current
can be regulated using the current regulation loop—via
the SETCUR and IMON pins. Selecting a maximum charge
current of 120A, the desired SETCUR pin voltage is calculated using:
VSETCUR =
K •IL(MAX ) •RSENSE
6
20 •120A •1mΩ
=
6
= 400mV
The SETCUR pin can be driven by an ADC’s output to
400mV for the best accuracy. If one is not available, the
16μA current sourced out of the SETCUR pin can be used
to set the voltage with a resistor from SETCUR to ground,
calculated using:
= 1804mW
Two Infineon BSC052N08NS5 MOSFETs, RDS(ON) =
5.2mΩ, COSS = 370pF are chosen for the bottom MOSFET.
The resulting power loss is:
46
= {1.1W} • 2
C2
0.1µF
C1
0.1µF
⎧ 48V – 12V
⎫
2
⎪ 48V •15A
⎪
PSYNC = ⎨
⎬•2
⎪
⎪
⎩ • [(1+ 0.005 • ( 75°C – 25°C))• 5.2mΩ ]⎭
RSETCUR =
400mV
= 25k
16µA
A 1% or more accurate 30.1k resistor can be chosen to
allow some design margin. The 16μA current out of the
SETCUR pin can be programmed by the SPI interface so
the maximum charge current can be changed on-the-fly.
Rev. A
For more information www.analog.com
VLOW
For more information www.analog.com
1.5k
1.69k
0.1µF
L3
6.8µH
1.69k
0.1µF
L2
6.8µH
1.69k
0.1µF
L1
6.8µH
M3
×2
VHIGH
16.9k
M6
×2
M5
×2
VHIGH
M4
×2
16.9k
16.9k
M2
×2
M1
×2
D1
D2
DT
SGND
D3
DT
SGND
BGRTN
DT
SGND
BGVCC
BST
LTC7060
TG
VCC
EN
SW
FLT
BG
PWM
0.22µF
BGRTN
BGVCC
BST
LTC7060
TG
VCC
EN
SW
FLT
BG
PWM
0.22µF
BGRTN
10k
30.1k
0Ω
PWMEN
0Ω
PWMEN
0Ω
PWMEN
499Ω
0.33µF
V5
4.7µF
0.22µF
10Ω
0.22µF
10Ω
0.22µF
10Ω
51k
1µF
DRVCC
1µF
DRVCC
45.3k
1µF
DRVCC
BUCK BOOST
499Ω
1nF
47pF
1k
V5
2.2µF
×12
SPI
INTERFACE
0.1µF
33µF
×12
BST
BGVCC
LTC7060
TG
VCC
EN
SW
FLT
BG
PWM
+
L1–L6: SAGAM CVE2622C-6R8M (6.8µH, DCR = 1.8mΩ)
D1–D6: DIODES DFLS1100
M1, M3, M5, M7, M9, M11: BSC117N08NS5
M2, M4, M6, M8, M10, M12: BSC052N08NS5
D7 = DIODES ZHCS400
1.5k
1mΩ
0.1µF
0.1µF
1.5k
1mΩ
0.1µF
1mΩ
VHIGH
0.22µF
VHIGH
30V TO 70V
PWM4
SNSA5+
SNSD5+
SNS5–
PWMEN
PWM5
SNSA6+
SNSD6+
SNS6–
DRVSET
MODE
PWM6
FREQ
CLKOUT
VFBLOW
OVLOW
EXTVCC
SYNC
7871 TA02
SNSA4+
SNSD4+
SNS4–
DRVCC
SS
V5
IMON
PGOOD SGND
SNSA3+
SNSD3+
SNS3–
ILIM
PWM3
SNSA2+
SNSD2+
SNS2–
PWM2
VHIGH
OVHIGH
UVHIGH
VFBHIGH
LTC7871
SETCUR
SNSA1+
SNSD1+
SNS1–
RUN
PWM1
BUCK
ITHLOW
ITHHIGH
FAULT
SCLK
SDI
SDO
CSB
1µF
10Ω
V5
10k
210k
0.1µF
0.22µF
0.22µF
0.22µF
DT
SGND
BGRTN
BGVCC
BST
LTC7060
VCC
TG
EN
SW
FLT
BG
PWM
D4
BGRTN
DT
SGND
BGVCC
BST
LTC7060
VCC
TG
EN
SW
FLT
BG
PWM
D5
BGRTN
DT
SGND
BGVCC
BST
LTC7060
TG
VCC
EN
SW
FLT
BG
PWM
D6
12.7k
499k
DRVCC
4.7µF
0Ω
PWMEN
0.22µF
0Ω
PWMEN
0.22µF
0Ω
PWMEN
0.22µF
D7
48.7k
3.01M
PWMEN
1µF
10Ω
1µF
10Ω
1µF
100pF
DRVCC
10k
DRVCC
V5
DRVCC
37.4k
1µF
2.2Ω
Figure 18. High Efficiency 6-Phase, 12V/180A Bidirectional Supply
M8
×2
M7
×2
VHIGH
M10
×2
M9
×2
VHIGH
M12
×2
M11
×2
VHIGH
1.69k
16.9k
0.1µF
L4
6.8µH
1.69k
16.9k
0.1µF
L5
6.8µH
1.69k
16.9k
0.1µF
L6
6.8µH
0.1µF
1.5k
0.1µF
1mΩ
1.5k
1mΩ
1.5k
0.1µF
1mΩ
+
22µF
×6
110k
10k
100µF
×6
VLOW
12V/180A
90.9k
10k
LTC7871
TYPICAL APPLICATIONS
Rev. A
47
LTC7871
PACKAGE DESCRIPTION
LWE Package
64-Lead Plastic Exposed Pad LQFP (10mm × 10mm)
(Reference LTC DWG #05-08-1982 Rev A)
10.15 – 10.25
7.50 REF
1
64
49
48
0.50 BSC
5.74 ±0.05
7.50 REF
0.20 – 0.30
10.15 – 10.25
5.74 ±0.05
16
17
PACKAGE OUTLINE
33
32
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
12.00 BSC
10.00 BSC
5.74 ±0.10
64
49
SEE NOTE: 3
1
64
49
48
48
1
12.00 BSC
10.00 BSC
A
5.74 ±0.10
A
33
16
33
16
C0.30 – 0.50
17
32
17
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
32
11° – 13°
R0.08 – 0.20
1.60
1.35 – 1.45 MAX
GAUGE PLANE
0.25
0° – 7°
LWE64 LQFP 0416 REV A
11° – 13°
0.50
BSC
0.09 – 0.20
1.00 REF
0.17 – 0.27
0.05 – 0.15
SIDE VIEW
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND
MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm
(30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT
48
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
Rev. A
For more information www.analog.com
LTC7871
REVISION HISTORY
REV
DATE
DESCRIPTION
A
07/21
Add Guarantee by Design to DRVCC/EXTVCC Peak Current in ABS MAX Rating section.
PAGE NUMBER
3
Add UNITS for V5 UVLO and EXTVCC Switchover Voltage parameters.
4, 5
SYNC (Pin 52): Update internal resistor value.
10
Update EA_VLOW.
12
Update PTOP equation.
24
Update the external clock (on the SYNC pin) input low threshold voltage.
28
Update MFR_IDAC_VLOW and MFR_IDAC_VHIGH tables.
Update inductor’s name.
38
44, 46
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
49
LTC7871
TYPICAL APPLICATION
High Efficiency 6-Phase 24V/90A Bidirectional Supply
V5
VHIGH
36V TO 70V
2.2µF
×12
+
33µF
×12
12.7k
30.1k
3.01M
267k
499k
10k
48.7k
10k
47pF
ILIM
2.2Ω
1µF
VFBLOW
OVLOW
EXTVCC
OVHIGH
UVHIGH
VFBHIGH
VHIGH
VHIGH
PWM1
1nF
LTC7060
499Ω
45.3k
100pF
V5
4.7µF
0.1µF
4.7µF
V5
SPI
INTERFACE
499Ω
0.33µF
ITHHIGH
51k
37.4k
BUCK BOOST
1k
ITHLOW
IMON
SS
SETCUR
DRVCC
V5
18.7k
0.1µF
1.69k
0.1µF
1.87k
SNSA1+
SNSD1+
SNS1–
(PHASE 2 TO PHASE 5)
VHIGH
PWMEN
PWM6
DRIVER
FREQ
SGND
BUCK
SCLK
SDI
SDO
CSB
2mΩ
15µH
DRIVER
LTC7871
0.1µF
1µF
ZHCS400
15µH
18.7k
LTC7060
SNSA6+
SNSD6+
SNS6–
0.1µF
2mΩ
10k
10k
191k
210k
22µF
×6
+
VLOW
24V/90A
33µF
×6
PINS NOT USED
IN THIS CIRCUIT:
CLKOUT
DRVSET
MODE
RUN
FAULT
PGOOD
1.69k
0.1µF
1.87k
7871 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC7060
100V Half Bridge Gate Driver with Floating Grounds
and Programmable Dead-Time
Up to 100V Supply Voltage, 6V ≤ VCC ≤ 14V, Adaptive Shoot-Through
Protection, 2mm × 3mm LFCSP and 12-LEAD MSOP
LT8228
Bidirectional Buck or Boost Controller with Fault
Protection
Up to 100V for VHIGH, and VLOW, Ideal for 48V/12V Automotive Battery
Applications
LT8708/LT8708-1
80V Synchronous 4-Switch Buck-Boost DC/DC
Controller with Flexible Bidirectional Capability
2.8V ≤ VIN ≤ 80V, 1.3V ≤ VOUT ≤ 80V, PLL Fixed Frequency 100kHz to 400kHz,
5mm × 8mm QFN-40
LTC3871
Bidirectional PolyPhase Synchronous Buck or
Boost Controller
Up to 100V VHIGH, Up to 30V VLOW, PLL Fixed Frequency 60kHz to 460kHz,
48-Lead LQFP
LTC4449
High Speed Synchronous N-Channel MOSFET Driver Up to 38V Supply Voltage, 4V ≤ VCC ≤ 6.5V, Adaptive Shoot-Through
Protection, 2mm × 3mm DFN-8
LTC3779
150V VIN and VOUT Synchronous 4-Switch
Buck-Boost Controller
4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, PLL Fixed Frequency 50kHz to
600kHz, FE38 TSSOP
LTC7813
60V Low IQ Synchronous Boost+Buck Controller,
Low EMI and Low Input/Output Ripple
4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V, 0.8V ≤
Buck VOUT ≤ 60V, IQ = 29µA, 5mm × 5mm QFN-32 Package
LTC3899
60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 29µA Burst Mode IQ
4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck VOUT
Range: 0.8V to 60V, Boost VOUT Up to 60V
LTM® 8056
58VIN, Buck-Boost µModule Regulator, Adjustable
Input and Output Current Limiting
5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, 15mm × 15mm × 4.92mm BGA Package
LTC7103
105V, 2.3A, Low EMI Synchronous
Step-Down Regulator
4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA, Fixed Frequency 200kHz,
5mm × 6mm QFN Package
50
Rev. A
06/21
www.analog.com
For more information www.analog.com
ANALOG DEVICES, INC. 2021