LTM4627
15A DC/DC µModule
Regulator
FEATURES
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DESCRIPTION
Complete 15A Switch Mode Power Supply
Wide Input Voltage Range: 4.5V to 20V
0.6V to 5V Output Range
±1.5% Total DC Output Error
Differential Remote Sense Amplifier for Precision
Regulation
Current Mode Control/ Fast Transient Response
Frequency Synchronization
Parallel Current Sharing (Up to 60A)
Selectable Pulse-Skipping or Burst Mode® Operation
Soft-Start/Voltage Tracking
Up to 93% Efficiency (12VIN, 3.3VOUT)
Overcurrent Foldback Protection
Output Overvoltage Protection
Small Surface Mount Footprint, Low Profile
15mm × 15mm × 4.32mm LGA and
15mm × 15mm × 4.92mm BGA Packages
APPLICATIONS
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Telecom Servers and Networking Equipment
ATCA and Storage Cards
Industrial Equipment
Medical Systems
The LTM®4627 is a complete 15A output high efficiency
switch mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor
and compensation components. Operating over an input
voltage range from 4.5V to 20V, the LTM4627 supports an
output voltage range of 0.6V to 5V, set by a single external
resistor. Only a few input and output capacitors are needed.
Current mode operation allows precision current sharing
of up to four LTM4627 regulators to obtain 60A output.
High switching frequency and a current mode architecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing
operation, Burst Mode operation and output voltage tracking for supply rail sequencing.
The LTM4627 is offered in thermally enhanced 15mm ×
15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA
packages. The LTM4627 is available with SnPb (BGA) or
RoHS compliant terminal finish.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule and PolyPhase
are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210.
TYPICAL APPLICATION
1.2V, 15A DC/DC µModule® Regulator
95
22µF
16V
×3
90
150pF
10k
0.1µF
VOUT
COMP
TRACK/SS
RUN
100k
+
VOUT_LCL
LTM4627
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
* SEE TABLE 4
** SEE TABLE 1
85
EXTVCC INTVCC PGOOD
VIN
GND
VFB
82pF
VOUT
1.2V
15A
470µF
6.3V
100µF*
6.3V
EFFICIENCY (%)
VIN
4.5V TO 16V
Efficiency vs Load Current
80
75
70
65
60
12VIN, 1.2VOUT
5VIN, 1.2VOUT
55
RFB**
60.4k
50
4627 TA01a
0
2
4
6
10 12
8
LOAD CURRENT (A)
14
16
4627 TA01b
4627fc
For more information www.linear.com/LTM4627
1
LTM4627
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN.............................................................. –0.3V to 22V
INTVCC, VOUT (VOUT ≤ 3.3V with
DIFF AMP), VOUT_LCL, PGOOD, EXTVCC........ –0.3V to 6V
MODE_PLLIN, fSET, TRACK/SS,
VOSNS –, VOSNS+, DIFF_OUT.................... –0.3V to INTVCC
COMP, VFB................................................. –0.3V to 2.7V
RUN (Note 5)................................................ –0.3V to 5V
INTVCC Peak Output Current (Note 6)...................100mA
Internal Operating Temperature Range (Note 2)...............
E and I-Grades.................................... –40°C to 125°C
MP-Grade........................................... –55°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Reflow (Peak Body) Temperature........................... 250°C
PIN CONFIGURATION
TOP VIEW
1
2
3
VIN
MODE_PLLIN
INTVCC
TRACK/SS
4
5
6
7
8
9
10
A
VIN
COMP
11
12
1
VIN
C
F
EXTVCC
PGOOD
VFB
G
PGOOD
E
4
5
6
7
8
9
10
COMP
11
12
RUN
fSET
B
J
VOSNS+
K
DIFF_OUT
L
VOUT_LCL
M
VOSNS–
INTVCC
D
EXTVCC
PGOOD
VFB
E
GND
F
PGOOD
G
SGND
H
VOUT
VIN
C
INTVCC
D
GND
3
A
RUN
fSET
B
2
TOP VIEW
MODE_PLLIN
INTVCC
TRACK/SS
SGND
H
VOUT
J
VOSNS+
K
DIFF_OUT
L
VOUT_LCL
M
VOSNS–
VOUT
VOUT
BGA PACKAGE
133-LEAD (15mm × 15mm × 4.92mm)
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
TJ(MAX) = 125°C, θJA = 16.6°C/W, θJCbottom = 4.6°C/W, θJCtop = 15°C/W, θJB = 5.1°C/W,
θ VALUES DETERMINED PER JESD 51-12 USING A JESD 51-9 DEFINED PCB
WEIGHT = 2.6g
TJ(MAX) = 125°C, θJA = 17.9°C/W, θJCbottom = 5.9°C/W, θJCtop = 15°C/W, θJB = 6.1°C/W,
θ VALUES DETERMINED PER JESD 51-12 USING A JESD 51-9 DEFINED PCB
WEIGHT = 2.8g
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4627EV#PBF
PAD OR BALL FINISH
Au (RoHS)
DEVICE
LTM4627V
FINISH CODE
e4
PACKAGE
TYPE
LGA
MSL
RATING
3
TEMPERATURE RANGE
(Note 2)
–40°C to 125°C
LTM4627IV#PBF
Au (RoHS)
LTM4627V
e4
LGA
3
–40°C to 125°C
LTM4627EY#PBF
SAC305 (RoHS)
LTM4627Y
e1
BGA
3
–40°C to 125°C
LTM4627IY#PBF
SAC305 (RoHS)
LTM4627Y
e1
BGA
3
–40°C to 125°C
LTM4627IY
SnPb (63/37)
LTM4627Y
e0
BGA
3
–40°C to 125°C
LTM4627MPY#PBF
SAC305 (RoHS)
LTM4627Y
e1
BGA
3
–55°C to 125°C
LTM4627MPY
SnPb (63/37)
LTM4627Y
e0
BGA
3
–55°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
2
4627fc
For more information www.linear.com/LTM4627
LTM4627
ELECTRICAL
CHARACTERISTICS l denotes the specifications which apply over the specified internal
The
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per the typical application in Figure 18.
SYMBOL
PARAMETER
VIN
Input DC Voltage
VOUT(DC)
Output Voltage, Total
Variation with Line and Load
CONDITIONS
CIN = 22µF × 3
COUT = 100µF Ceramic, 470µF POSCAP
RFB = 40.2k, MODE_PLLIN = GND
VIN = 5V to 20V, IOUT = 0A to 15A (Note 4)
MIN
l
4.5
l
1.477
1.1
TYP
MAX
UNITS
20
V
1.50
1.523
V
1.25
1.4
V
Input Specifications
VRUN
RUN Pin On Threshold
VRUNHYS
RUN Pin On Hysteresis
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A
VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A
VIN = 12V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A
Shutdown, RUN = 0, VIN = 12V
IS(VIN)
Input Supply Current
VIN = 5V, VOUT = 1.5V, IOUT = 15A
VIN = 12V, VOUT = 1.5V, IOUT = 15A
VRUN Rising
130
mV
17
25
54
40
mA
mA
mA
µA
5.05
2.13
A
A
Output Specifications
IOUT(DC)
Output Continuous Current
Range
VIN = 12V, VOUT = 1.5V (Note 4)
0
15
A
∆VOUT (Line)
VOUT
Line Regulation Accuracy
VOUT = 1.5V, VIN from 4.5V to 20V
IOUT = 0A
l
0.02
0.06
%/V
∆VOUT (Load)
VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 15A, VIN = 12V (Note 4)
l
0.2
0.45
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic, 470µF POSCAP
VIN = 12V, VOUT = 1.5V
15
mVP-P
∆VOUT(START)
Turn-On Overshoot
COUT = 100µF Ceramic, 470µF POSCAP,
VOUT = 1.5V, IOUT = 0A, VIN = 12V
20
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic, 470µF POSCAP,
No Load, TRACK/SS = 0.001µF, VIN = 12V
0.6
ms
∆VOUTLS
Peak Deviation for Dynamic
Load
Load: 0% to 50% to 0% of Full Load
COUT = 100µF Ceramic, 470µF POSCAP,
VIN = 12V, VOUT = 1.5V
60
mV
tSETTLE
Settling Time for Dynamic
Load Step
Load: 0% to 50% to 0% of Full Load VIN = 5V,
COUT = 100µF Ceramic, 470µF POSCAP
20
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 1.5V
VIN = 5V, VOUT = 1.5V
25
25
A
A
Control Section
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.5V
IFB
Current at VFB Pin
(Note 7)
VOVL
Feedback Overvoltage
Lockout
ITRACK/SS
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
tON(MIN)
Minimum On-Time
(Note 3)
RFBHI
Resistor Between VOUT_LCL
and VFB Pins
VOSNS+,
VOSNS– CM RANGE
Common Mode Input Range
VDIFF_OUT(MAX)
Maximum DIFF_OUT Voltage IDIFF_OUT = 300µA
l
l
VIN = 12V, Run > 1.4V
0.594
0.60
0.606
V
–12
–25
nA
0.65
0.67
0.69
V
1.0
1.2
1.4
µA
60.05
60.40
60.75
kΩ
90
0
INTVCC – 1.4
ns
4
V
V
4627fc
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3
LTM4627
ELECTRICAL
CHARACTERISTICS l denotes the specifications which apply over the specified internal
The
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per the typical application in Figure 18.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
VOSNS+ = VDIFF_OUT = 1.5V, IDIFF_OUT = 100µA
MIN
TYP
MAX
AV
Differential Gain
(Note 7)
1
V/V
SR
Slew Rate
(Note 6)
2
V/µs
GBP
Gain Bandwidth Product
(Note 6)
3
MHz
CMRR
Common Mode Rejection
(Note 7)
IDIFF_OUT
DIFF_OUT Current
Sourcing
PSRR
Power Supply Rejection
Ratio
5V < VIN < 20V (Note 7)
100
dB
RIN
Input Resistance
VOSNS+ to GND
80
kΩ
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
5
5.2
V
2
60
UNITS
mV
dB
2
mA
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
VINTVCC Load Reg INTVCC Load Regulation
6V < VIN < 20V
4.8
ICC = 0 to 50mA
VEXTVCC
External VCC Switchover
EXTVCC Ramping Positive
VLDO Ext
EXTVCC Voltage Drop
ICC = 25mA, VEXTVCC = 5V
0.5
l
4.5
%
4.7
50
V
100
mV
800
kHz
Oscillator and Phase-Locked Loop
fSYNC
Frequency Sync Capture
Range
MODE_PLLIN Clock Duty Cycle = 50%
250
fNOM
Nominal Frequency
VfSET = 1.2V
450
500
550
kHz
fLOW
Lowest Frequency
VfSET = 1V
350
400
450
kHz
fHIGH
Highest Frequency
VfSET ≥ 2.4V
700
770
850
kHz
IFREQ
Frequency Set Current
10
11
RMODE_PLLIN
MODE_PLLIN Input
Resistance
VIH_MODE_PLLIN
Clock Input Level High
VIL_MODE_PLLIN
Clock Input Level Low
9
250
µA
kΩ
2.0
V
0.8
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4627 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4627E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4627I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. The LTM4627MP
is guaranteed and tested over the –55°C to 125°C internal operating
V
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: The minimum on-time condition is specified for a peak-to-peak
inductor ripple current of ~40% of IMAX Load. (See the Applications
Information section)
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Limit current into the RUN pin to less than 2mA.
Note 6: Guaranteed by design.
Note 7: 100% tested at wafer level.
4627fc
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LTM4627
TYPICAL PERFORMANCE CHARACTERISTICS
100
Efficiency vs Load Current
with 8VIN
Efficiency vs Load Current
with 12VIN
100
95
95
90
90
90
85
85
85
80
75
70
1VOUT AT 400kHz
1.2VOUT AT 400kHz
1.5VOUT AT 400kHz
2.5VOUT AT 400kHz
3.3VOUT AT 650kHz
65
60
55
50
2
0
4
6
10 12
8
LOAD CURRENT (A)
14
80
75
70
1VOUT AT 400kHz
1.2VOUT AT 400kHz
1.5VOUT AT 400kHz
2.5VOUT AT 500kHz
3.3VOUT AT 600kHz
5VOUT AT 600kHz
65
60
55
50
16
2
0
4
6
10 12
8
LOAD CURRENT (A)
14
4627 G01
Burst Mode Efficiency
5VIN, 2.5VOUT Burst Mode OPERATION
EFFICIENCY (%)
EFFICIENCY (%)
12VIN, 2.5VOUT Burst Mode OPERATION
60
50
0.2
1
0.5
1.5
LOAD CURRENT (A)
2
55
16
50
4
6
10 12
8
LOAD CURRENT (A)
14
16
4627 G03
1.0V Transient Response
0A TO 7.5A
LOAD STEP
60
12VIN, 2.5VOUT
PULSE-SKIPPING MODE
40
0.1
0.2
1
0.5
1.5
LOAD CURRENT (A)
100µs/DIV
4627 G06
VIN = 12V, VOUT = 1.0V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 5 × 100µF CERAMIC X5R
2
4627 G05
1.5V Transient Response
1.8V Transient Response
50mV/DIV
50mV/DIV
50mV/DIV
0A TO 7.5A
LOAD STEP
0A TO 7.5A
LOAD STEP
0A TO 7.5A
LOAD STEP
VIN = 12V, VOUT = 1.2V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 5 × 100µF CERAMIC X5R
2
70
1.2V Transient Response
4627 G07
0
50mV/DIV
4627 G04
100µs/DIV
1VOUT AT 400kHz
1.2VOUT AT 400kHz
1.5VOUT AT 400kHz
2.5VOUT AT 650kHz
3.3VOUT AT 650kHz
5VOUT AT 700kHz
65
60
80
50
0.1
70
5VIN, 2.5VOUT
PULSE-SKIPPING MODE
90
80
40
75
Pulse-Skipping Mode Efficiency
100
70
80
4627 G02
100
90
EFFICIENCY (%)
95
EFFICIENCY (%)
EFFICIENCY (%)
100
Efficiency vs Load Current
with 5VIN
100µs/DIV
4627 G08
VIN = 12V, VOUT = 1.5V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 5 × 100µF CERAMIC X5R
100µs/DIV
4627 G09
VIN = 12V, VOUT = 1.8V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 4 × 100µF CERAMIC X5R
4627fc
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5
LTM4627
TYPICAL PERFORMANCE CHARACTERISTICS
2.5V Transient Response
3.3V Transient Response
50mV/DIV
50mV/DIV
0A TO 7.5A
LOAD STEP
0A TO 7.5A
LOAD STEP
100µs/DIV
4627 G10
100µs/DIV
4627 G11
VIN = 12V, VOUT = 2.5V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 4 × 100µF CERAMIC X5R
VIN = 12V, VOUT = 3.3V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 2 × 100µF CERAMIC X5R
5.0V Transient Response
Start-Up with Soft-Start
50mV/DIV
VOUT
500mV/DIV
IOUT
0A TO 7.5A
LOAD STEP
100µs/DIV
5A/DIV
4627 G12
50ms/DIV
4627 G13
VIN = 12V, VOUT = 5V,
CFF = 82pF, CCOMP = 33pF
OUTPUT CAPACITOR = 2 × 100µF CERAMIC X5R
VIN = 12V, VOUT = 1.5V, IOUT = 15A
INPUT CAP 150µF SANYO ELECTROLYTIC CAP
AND 22µF × 2 X5R CERAMIC CAP
OUTPUT CAP 1 × 100µF X5R CERAMIC
AND 470µF SANYO POSCAP
0.1µF CAP FROM TRACK/SS TO GND
Short-Circuit Protection No Load
Short-Circuit Protection 15A Load
VOUT
VOUT
500mV/DIV
500mV/DIV
IIN
1A/DIV
1A/DIV
IIN
4ms/DIV
VIN = 12V, VOUT = 1.5V, IOUT = 0A
4627 G14
4ms/DIV
4627 G15
VIN = 12V, VOUT = 1.5V, IOUT = 15A
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LTM4627
PIN FUNCTIONS
VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply input
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between VIN
pins and GND pins.
VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 4.
GND (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,
H1-H9): Power Ground Pins for Both Input and Output
Returns.
PGOOD (F11, G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage exceeds a ±10% regulation window. Both
pins are tied together internally.
SGND (G11, H11, H12): Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to the output capacitor GND in the application.
See layout guidelines in Figure 17.
MODE_PLLIN (A8): Forced Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to INTVCC to enable pulse-skipping mode
of operation. Connect to ground to enable forced continuous
mode of operation. Floating this pin will enable Burst Mode
operation. A clock on this pin will enable synchronization
with forced continuous operation. See the Applications
Information section.
fSET (B12): A resistor can be applied from this pin to
ground to set the operating frequency, or a DC voltage
can be applied to set the frequency. See the Applications
Information section.
TRACK/SS (A9): Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.2µA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. See the Applications
Information section.
VFB (F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT_LCL with a
60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between VFB
and ground pins. In PolyPhase® operation, tying the
VFB pins together allows for parallel operation. See the
Applications Information section for details.
COMP (A11): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together for parallel operation. The device is internally
compensated.
RUN: (A10) Run Control Pin. A voltage above 1.4V will turn
on the module. A 5.1V Zener diode to ground is internal
to the module for limiting the voltage on the RUN pin to
5V, and allowing a pull-up resistor to VIN for enabling the
device. Limit current into the RUN pin to ≤ 2mA.
INTVCC: (A7, D9) Internal 5V LDO for Driving the Control
Circuitry and the Power MOSFET Drivers. Both pins are
internally connected. The 5V LDO has a 100mA current limit.
EXTVCC (E12): External power input to an internal control
switch allows an external source greater than 4.7V, but
less than 6V to supply IC power and bypass the internal
INTVCC LDO. EXTVCC must be less than VIN at all times
during power-on and power-off sequences. See the Applications Information section.
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7
LTM4627
PIN FUNCTIONS
VOUT_LCL: (L12) This pin connects to VOUT through a 1M
resistor, and to VFB with a 60.4k resistor. The remote sense
amplifier output DIFF_OUT is connected to VOUT_LCL, and
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
DIFF_OUT effectively eliminates the 1MΩ from VOUT to
VOUT_LCL. When the remote sense amplifier is not used,
then connect VOUT_LCL to VOUT directly.
VOSNS+: (J12) (+) Input to the Remote Sense Amplifier.
This pin connects to the output remote sense point. The
remote sense amplifier is used for VOUT ≤ 3.3V. Connect
to ground when not used.
VOSNS–: (M12) (–) Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier is used for VOUT ≤ 3.3V. Connect
to ground when not used.
DIFF_OUT: (K12) Output of the Remote Sense Amplifier.
This pin connects to the VOUT_LCL pin for remote sense
applications. Otherwise float when not used.
MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7, MTP8
(A12, B11, C10, C11, C12, D10, D11, D12): Extra mounting pads used for increased solder integrity strength.
Leave floating.
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LTM4627
BLOCK DIAGRAM
INTVCC
VOUT_LCL
> 1.4V = ON
< 1.1V = OFF
MAX = 5V
R1
VOUT
1M
VIN
10k
PGOOD
VIN
RUN
1.5µF
5.1V
R2
+
VIN
4.5V TO 20V
CIN
COMP
60.4k
M1
INTERNAL
COMP
0.47µH
SGND
VFB
10µF
M2
fSET
+
INTERNAL
LOOP
FILTER
INTVCC
TRACK/SS
MODE_PLLIN
+
CSS
COUT
GND
250k
DIFF
AMP
–
INTVCC
VOSNS–
VOSNS+
+
RfSET
100k
–
RFB
90.9k
VOUT
1V
15A
VOUT
POWER
CONTROL
C
DIFF_OUT
EXTVCC
4627 F01
Figure 1. Simplified LTM4627 Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN
External Input Capacitor Requirement
(VIN = 4.5V to 20V, VOUT = 1.5V)
IOUT = 15A
COUT
External Output Capacitor Requirement
(VIN = 4.5V to 20V, VOUT = 1.5V)
IOUT = 15A
MIN
TYP
66
MAX
UNITS
µF
200
µF
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9
LTM4627
OPERATION
Power Module Description
The LTM4627 is a high performance single output standalone nonisolated switching mode DC/DC power supply.
It can provide a 15A output with few external input and
output capacitors. This module provides precisely regulated
output voltages programmable via external resistors from
0.6VDC to 5VDC over a 4.5V to 20V input range. The typical
application schematic is shown in Figure 18.
The LTM4627 has an integrated constant-frequency current mode regulator, power MOSFETs, 0.47µH inductor,
and other supporting discrete components. The switching frequency range is from 400kHz to 770kHz, and the
typical operating frequency is 500kHz. For switching
noise-sensitive applications, it can be externally synchronized from 250kHz to 800kHz, subject to minimum
on-time limitations. A single resistor is used to program
the frequency. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4627 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides cycle-by-cycle fast current
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
The LTM4627 is internally compensated to be stable over
all operating conditions. Table 4 provides a guideline for
input and output capacitances for several operating conditions. LTpowerCAD™ is available for transient and stability
analysis. The VFB pin is used to program the output voltage
with a single external resistor to ground.
A remote sense amplifier is provided for accurately sensing
output voltages ≤3.3V at the load point.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light load features will accommodate battery
operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section.
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LTM4627
APPLICATIONS INFORMATION
The typical LTM4627 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage.
Refer to Table 4 for specific external capacitor requirements
for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the VIN to VOUT step-down ratio
that can be achieved for a given input voltage. The VIN to
VOUT minimum dropout is a function of load current and
at very low input voltage and high duty cycle applications
output power may be limited as the internal top power
MOSFET is not rated for 15A operation at higher ambient
temperatures. At very low duty cycles the minimum 90ns
on-time must be maintained. See the Frequency Adjustment section and temperature derating curves.
Output Voltage Programming
The PWM controller has an internal 0.6V ±1% reference
voltage. As shown in the Block Diagram, a 60.4k internal
feedback resistor connects the VOUT_LCL and VFB pins
together. When the remote sense amplifier is used, then
DIFF_OUT is connected to the VOUT_LCL pin. If the remote
sense amplifier is not used, then VOUT_LCL connects to
VOUT. The output voltage will default to 0.6V with no feedback resistor. Adding a resistor RFB from VFB to ground
programs the output voltage:
60.4k + RFB
VOUT = 0.6V •
RFB
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT (V)
RFB (k)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5.0
Open
90.9
60.4
40.2
30.1
19.1
13.3
8.25
For a given VOUT, RFB can be determined by:
RFB =
For parallel operation of N LTM4627s, the following equation can be used to solve for RFB:
60.4k /N
RFB =
VOUT
–1
0.6V
Tie the VFB pins together for each parallel output. The
COMP pins must be tied together also.
Input Capacitors
The LTM4627 module should be connected to a low ACimpedance DC source. Additional input capacitors are
needed for the RMS input ripple current rating. The ICIN(RMS)
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~ 2A each.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
IOUT(MAX)
I CIN(RMS)=
• D • (1– D)
η%
In the previous equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor or a Polymer capacitor.
60.4k
VOUT
–1
0.6V
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LTM4627
APPLICATIONS INFORMATION
Output Capacitors
The LTM4627 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low
ESR Polymer capacitor or ceramic capacitors. The typical
output capacitance range is from 200µF to 800µF. Additional
output filtering may be required by the system designer
if further reduction of output ripple or dynamic transient
spikes is required. Table 4 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 7.5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria
are considered in the Table 4 matrix, and LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number of
phases. Application Note 77 discusses this noise reduction
versus output ripple current cancellation, but the output
capacitance should be considered carefully as a function
of stability and transient response. LTpowerCAD can be
used to calculate the output ripple reduction as the number
of implemented phases increases by N times.
drops below 0.5V, the burst comparator trips, causing
the internal sleep line to go high and turn off both power
MOSFETs.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP to rise, the internal
sleep line goes low, and the LTM4627 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4627 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. With pulse-skipping mode at light load, the
internal current comparator may remain tripped for several
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.
Forced Continuous Operation
Burst Mode Operation
The LTM4627 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply float the MODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductor is set to approximately 30% of the maximum peak
current value in normal operation even though the voltage
at the COMP pin indicates a lower value. The voltage at the
COMP pin drops when the inductor’s average current is
greater than the load requirement. As the COMP voltage
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4627’s output
voltage is in regulation.
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LTM4627
APPLICATIONS INFORMATION
Multiphase Operation
For outputs that demand more than 15A of load current,
multiple LTM4627 devices can be paralleled to provide
more output current without increasing input and output
ripple voltage. The MODE_PLLIN pin allows the LTM4627
to be synchronized to an external clock and the internal
phase-locked loop allows the LTM4627 to lock onto input
clock phase as well. The fSET resistor is selected for normal frequency, then the incoming clock can synchronize
the device over the specified range. See Figure 20 for a
synchronizing example circuit.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used. See Application Note 77.
The LTM4627 device is an inherently current mode controlled device, so parallel modules will have good current
sharing. This will balance the thermals in the design. Tie
the COMP and VFB pins of each LTM4627 together to
share the current evenly. Figure 20 shows a schematic of
the parallel design.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 2).
PLL, Frequency Adjustment and Synchronization
The LTM4627 switching frequency is set by a resistor (RfSET)
from the fSET pin to signal ground. A 10µA current (IFREQ)
flowing out of the fSET pin through RfSET develops a voltage on fSET. RfSET can be calculated as:
The relationship of fSET voltage to switching frequency is
shown in Figure 3. For low output voltages from 0.8V to
1.5V, 400kHz operation is an optimal frequency for the best
power conversion efficiency while maintaining the inductor ripple current to about 30% to 40% of maximum load
current. For output voltages from 1.8V to 3.0V, 500kHz to
600kHz is optimal. For output voltages from 3.0V to 5.0V,
750kHz operation is optimal, but due to the higher ripple
current at 5V operation the output current is limited to 10A.
The LTM4627 can be synchronized from 250kHz to 800kHz
with an input clock that has a high level above 2V and a
low level below 0.8V. However, a 400kHz low end operating
frequency is recommended to limit inductor ripple current.
See the Typical Applications section for synchronization
examples. The LTM4627 minimum on-time is limited to
approximately 90ns. Guardband the on-time to 130ns.
The on-time can be calculated as:
t ON(MIN)=
V
1
• OUT
FREQ VIN
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4627 uses an
accurate 60.4k resistor internally for the top feedback
resistor. Figure 4 shows an example of coincident tracking.
60.4k
VOUT(SLAVE) = 1+
• V TRACK
R TA
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
FREQ
1
RfSET =
+ 0.2V
500kHz / V
10µA
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LTM4627
APPLICATIONS INFORMATION
0.60
0.55
0.50
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4627 F02
Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six µModule Regulators (Phases)
900
SWITCHING FREQUENCY (kHz)
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4627 F03
Figure 3. Relationship Between Switching
Frequency and Voltage at the fSET Pin
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LTM4627
APPLICATIONS INFORMATION
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.6V. RTA
in Figure 4 will be equal to the RFB for coincident tracking.
has a control range from 0V to 0.6V. The master’s TRACK/
SS pin slew rate is directly equal to the master’s output
slew rate in volts/time. The equation:
The TRACK/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator
can be used to develop that master ramp. The LTM4627 can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.2µA current source
is used to charge the soft-start capacitor. The following
equation can be used:
MR
• 60.4k = R TB
SR
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal to 60.4k. RTA is derived from equation:
C
t SOFT-START = 0.6V • SS
1.2µA
R TA =
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin
VIN 6V
TO 16V
C7
22µF
16V
C9
22µF
16V
C10
22µF
16V
R2
10k
SOFT-START
CAPACITOR
CSS
150pF
where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k
VIN
EXTVCC INTVCC PGOOD
COMP
VOUT
TRACK/SS
RUN
R4
100k
LTM4627
C3
22µF
16V
C1
22µF
16V
C2
22µF
16V
R1
10k
MASTER RAMP
OR OUTPUT
150pF
RTA
60.4k
RTB
60.4k
MODE_PLLIN
VOSNS–
VFB
VIN
EXTVCC INTVCC PGOOD
COMP
VOUT
TRACK/SS
RUN
R3
100k
DIFF_OUT
VOSNS+
GND
LTM4627
MODE_PLLIN
VOSNS–
VFB
C8
470µF
6.3V
C11
100µF
6.3V
VOUT2
1.5V AT 15A
RFB1
40.2k
+
DIFF_OUT
VOSNS+
GND
82pF
VOUT_LCL
fSET
SGND
+
VOUT_LCL
fSET
SGND
VIN 6V
TO 16V
0.6V
V
V
V FB
+ FB – TRACK
60.4k RFB
R TB
C4
470µF
6.3V
C6
100µF
6.3V
VOUT1
1.2V
15A
82pF
RFB
60.4k
4627 F04
Figure 4. Dual Outputs (1.5V and 1.2V) with Coincident Tracking
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LTM4627
APPLICATIONS INFORMATION
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then RTA is equal to RFB with
VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in
Figure 4.
An input electronic circuit breaker or fuse can be sized to
be tripped or cleared when the bottom MOSFET is turned
on to protect against the overvoltage. Foldback current
limiting is disabled during soft-start or tracking start-up.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach its final value before the master output.
Run Enable
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB
= 75k. Solve for RTA to equal 51.1k.
For applications that do not require tracking or sequencing, simply tie the TRACK/SS pin to INTVCC to let RUN
control the turn on/off. When the RUN pin is below its
threshold or the VIN undervoltage lockout, then TRACK/
SS is pulled low.
MASTER OUTPUT
OUTPUT
VOLTAGE
SLAVE OUTPUT
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.25V, and
the pin has an internal 5.1V Zener to protect the pin. The
RUN pin can be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
VUVLO = ((R1+R2)/R2) • 1.25V.
See the Block Diagram for the example of use.
INTVCC Regulator
The LTM4627 has an internal low dropout regulator from
VIN called INTVCC. This regulator output has a 4.7µF
ceramic capacitor internal. This regulator powers the
internal controller and MOSFET drivers. The gate driver
current is ~20mA for 750kHz operation. The regulator loss
can be calculated as:
(VIN – 5V) • 20mA = PLOSS
TIME
4627 F05
Figure 5. Output Voltage Coincident Tracking
Overcurrent and Overvoltage Protection
The LTM4627 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current.
An overvoltage condition (OVP) above 10% of the regulated output voltage will force the top MOSFET off and
the bottom MOSFET on until the condition is cleared.
EXTVCC external voltage source ≥ 4.7V can be applied to
this pin to eliminate the internal INTVCC LDO power loss and
increase regulator efficiency. A 5V supply can be applied
to run the internal circuitry and power MOSFET driver. If
unused, leave pin floating. EXTVCC must be less than VIN
at all times during power-on and power-off sequences.
Stability Compensation
The LTM4627 has already been internally compensated for
all output voltages. Table 4 is provided for most application
requirements. LTpowerCAD is available for other control
loop optimization.
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LTM4627
APPLICATIONS INFORMATION
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed
on a µModule package mounted to a hardware test board
defined by JESD 51-9 (“Test Boards for Area Array Surface
Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in
JESD 51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
Many designers, in lieu of or to compliment any FEA activities, may opt to use laboratory equipment and a test
vehicle such as the demo board to anticipate the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions.
Without FEA software, the thermal resistances reported in
the Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided later in this data sheet
can be used in a manner that yields insight and guidance
pertaining to one’s application-usage, and can be adapted
to correlate thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1 θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still
air” although natural convection causes the air to move.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2 θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3 θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4 θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the
bottom of the µModule package and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured at a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD 51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 6; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
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LTM4627
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
At
BOARD-TO-AMBIENT
RESISTANCE
80421 F05
µMODULE DEVICE
Figure 6. Graphical Representation of JESD 51-12 Thermal Coefficients
Within the LTM4627, be aware there are multiple power
devices and components dissipating power, with a consequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4627 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD 51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4627 with heat sink and airflow;
(4) having solved for and analyzed these thermal resistance values and simulated various operating conditions
in the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operating the device at the same power loss as that which was
simulated. An outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.
The 1.2V and 3.3V power loss curves in Figures 7 and 8
can be used in coordination with the load current derating
curves in Figures 9 to 16 for calculating an approximate
θJA thermal resistance for the LTM4627 with various heat
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors according to the ambient temperature. These approximate factors are: 1 for 40°C; 1.05 for
50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 15A and the ambient temperature at 40°C. The
output voltages are 1.2V, and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a controlled temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without airflow.
The power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
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LTM4627
APPLICATIONS INFORMATION
Figure 11 the load current is derated to ~12A at ~80°C with
no air or heat sink and the power loss for the 12V to 1.2V
at 12A output is about 2.8W. The 2.8W loss is calculated
with the ~2.35W room temperature loss from the 12V to
1.2V power loss curve at 12A, and the 1.2 multiplying
factor at 80°C ambient. If the 80°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 40°C divided by 2.8W equals a 14°C/W
θJA thermal resistance. Table 2 specifies a 13°C/W value
which is very close. Table 2 and Table 3 provide equivalent
thermal resistances for 1.2V and 3.3V outputs with and
without airflow and heat sinking. The derived thermal
3.0
6
5VIN TO 1.2VOUT POWER LOSS
12VIN TO 1.2VOUT POWER LOSS
2.5
2.0
1.5
1.0
4
3
2
1
0.5
0
5VIN TO 3.3VOUT POWER LOSS
12VIN TO 3.3VOUT POWER LOSS
5
POWER LOSS (W)
POWER LOSS (W)
resistances in Tables 2 and 3 for the various conditions can
be multiplied by the calculated power loss as a function
of ambient temperature to derive temperature rise above
ambient, thus maximum junction temperature. Room
temperature power loss can be derived from the efficiency
curves in the Typical Performance Characteristics section
and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sinks
are listed in Table 4.
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT CURRENT (A)
4627 F08
4627 F07
Figure 8. 3.3VOUT Power Loss at 25°C
16
16
14
14
12
12
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 7. 1.2VOUT Power Loss at 25°C
10
8
6
4
0 LFM
200 LFM
400 LFM
2
0
40
50
60
70
10
8
6
4
0 LFM
200 LFM
400 LFM
2
80
90 100 110 120 130
0
40
50
60
70
80
90 100 110 120 130
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4627 F10
4627 F09
Figure 9. 5VIN to 1.2VOUT No Heat Sink
Figure 10. 5VIN to 1.2VOUT with Heat Sink
4627fc
For more information www.linear.com/LTM4627
19
LTM4627
16
16
14
14
12
12
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
APPLICATIONS INFORMATION
10
8
6
4
8
6
4
0 LFM
200 LFM
400 LFM
2
0
10
40
50
60
70
0 LFM
200 LFM
400 LFM
2
80
0
90 100 110 120 130
40
50
60
70
80
90 100 110 120 130
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4627 F12
4627 F10
Figure 12. 12VIN to 1.2VOUT with Heat Sink
14
14
12
12
10
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 11. 12VIN to 1.2VOUT No Heat Sink
8
6
4
0 LFM
200 LFM
400 LFM
2
0
40
50
60
70
8
6
4
0 LFM
200 LFM
400 LFM
2
80
0
90 100 110 120 130
40
50
AMBIENT TEMPERATURE (°C)
60
70
80
90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F14
Figure 13. 5VIN to 3.3VOUT No Heat Sink
Figure 14. 5VIN to 3.3VOUT with Heat Sink
16
16
14
14
12
12
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4627 F13
10
8
6
4
0 LFM
200 LFM
400 LFM
2
0
40
50
60
70
10
8
6
4
0 LFM
200 LFM
400 LFM
2
80
90 100 110 120 130
0
40
50
AMBIENT TEMPERATURE (°C)
60
70
80
90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F15
Figure 15. 12VIN to 3.3VOUT No Heat Sink
4627 F16
Figure 16. 12VIN to 3.3VOUT with Heat Sink
4627fc
20
For more information www.linear.com/LTM4627
LTM4627
APPLICATIONS INFORMATION
Table 2. 1.2V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIRFLOW
(LFM)
HEAT SINK
θJA (°C/W)*
Figures 9, 11
5V, 12V
Figure 7
0
None
13
Figures 9, 11
5V, 12V
Figure 7
200
None
11
Figures 9, 11
5V, 12V
Figure 7
400
None
8
Figures 10, 12
5V, 12V
Figure 7
0
BGA Heat Sink
12
Figures 10, 12
5V, 12V
Figure 7
200
BGA Heat Sink
8
Figures 10, 12
5V, 12V
Figure 7
400
BGA Heat Sink
7
Table 3. 3.3V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIRFLOW
(LFM)
HEAT SINK
θJA (°C/W)*
Figures 13, 15
5V, 12V
Figure 8
0
None
13
Figures 13, 15
5V, 12V
Figure 8
200
None
11
Figures 13, 15
5V, 12V
Figure 8
400
None
8
Figures 14, 16
5V, 12V
Figure 8
0
BGA Heat Sink
12
Figures 14, 16
5V, 12V
Figure 8
200
BGA Heat Sink
8
Figures 14, 16
5V, 12V
Figure 8
400
BGA Heat Sink
7
* θJA derived from laboratory measurements using a 95mm × 76mm PCB with 4 layers. Two outer
layers are 2oz copper and two inner layers are 1oz copper. PCB thickness is 1.6mm. BGA heat sink
references are listed in Table 4.
4627fc
For more information www.linear.com/LTM4627
21
LTM4627
APPLICATIONS INFORMATION
Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 18) 0A to 7.5A Load Step
VALUE
PART NUMBER
COUT1 AND COUT2
BULK VENDOR
VALUE
PART NUMBER
CIN
BULK VENDOR
VALUE
PART NUMBER
TDK
22µF 6.3V
C3216X7SOJ226M
Sanyo POSCAP
1000µF 2.5V
2R5TPD1000M5
Sanyo
56µF 25V
25SVP56M
Murata
22µF 16V
GRM31CR61C226KE15L
Sanyo POSCAP
470µF 2.5V
2R5TPD470M5
TDK
100µF 6.3V
C4532X5ROJ107MZ
Sanyo POSCAP
470µF 6.3V
6TPD470M
Murata
100µF 6.3V
GRM32ER60J107M
Sanyo POSCAP
COUT1 AND COUT2
CERAMIC VENDOR
VOUT
CIN
CIN
COUT1 (CERAMIC) AND
(V) (CERAMIC) (BULK)** COUT2 (CER AND BULK)
1
CFF
(pF)
CCOMP
(pF)
VIN
(V)
PEAK TO
PEAK
DROOP DEVIATION
(mV)
(mV)
RECOVERY
TIME(µs)
LOAD
STEP
(A/µs)
RFB
(kΩ)
FREQ.
(kHz)
22µF × 3
56µF
100µF × 2, 1000µF
68
150
5,12
50
100
30
7.5
90.9
400
1
22µF × 3
56µF
100µF × 2, 470µF × 2
82
150
5,12
50
100
20
7.5
90.9
400
1
22µF × 3
56µF
100µF × 4
82
33
5,12
52
108
18
7.5
90.9
400
1.2
22µF × 3
56µF
100µF × 2, 1000µF
82
150
5,12
40
80
20
7.5
60.4
400
1.2
22µF × 3
56µF
100µF, 470µF
82
150
5,12
60
120
20
7.5
60.4
400
1.2
22µF × 3
56µF
100µF × 2, 470µF × 2
82
150
5,12
40
80
25
7.5
60.4
400
1.2
22µF × 3
56µF
100µF × 4
82
33
5,12
50
114
20
7.5
60.4
400
1.5
22µF × 3
56µF
100µF × 2, 1000µF
82
150
5,12
60
120
23
7.5
40.2
400
1.5
22µF × 3
56µF
100µF, 470µF
82
47
5,12
67
130
20
7.5
40.2
400
1.5
22µF × 3
56µF
100µF × 2, 470µF × 2
82
150
5,12
60
120
25
7.5
40.2
400
1.5
22µF × 3
56µF
100µF × 3
82
33
5,12
65
130
20
7.5
40.2
400
1.8
22µF × 3
56µF
100µF × 2, 1000µF
68
150
5,12
64
130
25
7.5
30.1
400
1.8
22µF × 3
56µF
100µF, 470µF
82
150
5,12
76
135
22
7.5
30.1
400
1.8
22µF × 3
56µF
100µF × 2
82
none
5,12
66
132
20
7.5
30.1
400
2.5
22µF × 3
56µF
100µF × 2
82
none
5,12
88
164
30
7.5
19.1
500
2.5
22µF × 3
56µF
100µF, 470µF
82
150
5,12
100
200
25
7.5
19.1
500
3.3
22µF × 3
56µF
100µF × 2
82
none
5,12
100
200
30
7.5
13.3
600
3.3
22µF × 3
56µF
100µF, 470µF
82
150
5,12
100
200
30
7.5
13.3
600
5
22µF × 3
56µF
100µF × 2
68
none
12
125
250
20
7.5
8.25
700
5
22µF × 3
56µF
470µF
47
150
12
125
250
25
7.5
8.25
700
** Bulk capacitance is optional if VIN has very low input impedance.
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
AAVID Thermalloy
375424B00034G
www.aavidthermalloy.com
Cool Innovations
4-050503P to 4-050508P
www.coolinnovations.com
4627fc
22
For more information www.linear.com/LTM4627
LTM4627
APPLICATIONS INFORMATION
Safety Considerations
The LTM4627 modules do not provide isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic
failure. The device does support overvoltage protection
and overcurrent protection.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
Layout Checklist/Example
• Place test points on signal pins for testing.
The high integration of the LTM4627 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout considerations are still necessary.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize
high frequency noise.
• For parallel modules, tie the COMP and VFB pins together. Use an internal layer to closely connect these
pins together.
Figure 17 gives a good example of the recommended
layout. LGA and BGA PCB layouts are identical with the
exception of circle pads for BGA (see Package Description).
VIN
CIN
CIN
CONTROL
CONTROL
GND
SIGNAL
GROUND
CONTROL
COUT
COUT
VOUT
VOUT
4627 F17
Figure 17. Recommended PCB Layout
(LGA Shown, for BGA Use Circle Pads)
4627fc
For more information www.linear.com/LTM4627
23
LTM4627
TYPICAL APPLICATIONS
VIN
4.5V TO 20V
C3
22µF
25V
C1
22µF
25V
C2
22µF
25V
CCOMP
150pF
R1
10k
C7
0.1µF
VIN
EXTVCC INTVCC PGOOD
COMP
VOUT
TRACK/SS
RUN
R3
120k
CONTINUOUS
MODE
LTM4627
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
GND
+
VOUT_LCL
VFB
CFF
82pF
COUT1
470µF
6.3V
×2
COUT2*
100µF
6.3V
VOUT
1.5V
15A
RFB
40.2k
*SEE TABLE 4
4627 F18
Figure 18. 4.5V to 20VIN, 1.5V at 15A Design
4627fc
24
For more information www.linear.com/LTM4627
R1
200k
C14
1µF
LTC6908-1
OUT2
MOD
SET
OUT1
GND
V+
INTVCC
R2
10k
VIN
7V TO 16V
C9
22µF
16V
C10
22µF
16V
C13
0.1µF
For more information www.linear.com/LTM4627
C1
22µF
16V
C2
22µF
16V
100k
SGND
GND
VFB
VOSNS–
MODE_PLLIN
DIFF_OUT
VOSNS+
LTM4627
VOUT_LCL
fSET
RUN
TRACK/SS
VOUT
VFB
COMP
GND
EXTVCC INTVCC PGOOD
SGND
VOSNS–
VOSNS+
DIFF_OUT
VOUT_LCL
VIN
270pF
100k
MODE_PLLIN
fSET
RUN
LTM4627
VOUT
EXTVCC INTVCC PGOOD
TRACK/SS
COMP
VIN
INTVCC
Figure 19. 1V at 30A, Two Parallel Outputs with 2-Phase Operation
CLOCK SYNC 180 PHASE
C3
22µF
16V
CLOCK SYNC 0 PHASE
C7
22µF
16V
4627 F19
+
RFB1
45.3k
150pF
C4
470µF
6.3V
+
C6
100µF
6.3V
C8
470µF
6.3V
C11
100µF
6.3V
1V AT 30A
LTM4627
TYPICAL APPLICATIONS
4627fc
25
LTM4627
TYPICAL APPLICATIONS
VIN
7V TO 16V
R1
10k
C20
22µF
16V
VIN
EXTVCC INTVCC PGOOD
VOUT
COMP
TRACK/SS
RUN
VOSNS+
VOSNS–
SGND
V
C2
1µF
R2
100k
+
DIFF_OUT
MODE_PLLIN
100k
+
LTM4627
VOUT_LCL
fSET
INTVCC
4-PHASE CLOCK
VOUT
1.2V AT 60A
INTVCC
C22
22µF
16V C28
0.1µF
C24
100µF
6.3V
270pF
VFB
GND
C21
470µF
6.3V
RFB2
15k
150pF
SET
LTC6902
MOD
DIV
PH
GND
OUT1
OUT4
OUT2
OUT3
C14
22µF
16V
C18
22µF
16V
VIN
EXTVCC INTVCC PGOOD
VOUT
COMP
TRACK/SS
RUN
VOSNS+
MODE_PLLIN
VOSNS–
SGND
C9
22µF
16V
+
DIFF_OUT
fSET
100k
C7
22µF
16V
LTM4627
VOUT_LCL
C15
470µF
6.3V
C18
100µF
6.3V
VFB
GND
VIN EXTVCC INTVCC PGOOD
VOUT
COMP
TRACK/SS
RUN
LTM4627
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
100k
SGND
+
VOUT_LCL
C8
470µF
6.3V
C11
100µF
6.3V
VFB
GND
150pF
C3
22µF
16V
C1
22µF
16V
VIN EXTVCC INTVCC PGOOD
VOUT
COMP
TRACK/SS
RUN
100k
LTM4627
VOUT_LCL
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
+
GND
C4
470µF
6.3V
C6
100µF
6.3V
VFB
4627 F20
Figure 20. 1.2V, 60A, Current Sharing with 4-Phase Operation
4627fc
26
For more information www.linear.com/LTM4627
LTM4627
PACKAGE DESCRIPTION
Pin Assignment Table
(Arranged by Pin Number)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
A1 VIN
B1 VIN
C1 VIN
D1 GND
E1 GND
F1 GND
A2 VIN
B2 VIN
C2 VIN
D2 GND
E2 GND
F2 GND
A3 VIN
B3 VIN
C3 VIN
D3 GND
E3 GND
F3 GND
A4 VIN
B4 VIN
C4 VIN
D4 GND
E4 GND
F4 GND
A5 VIN
B5 VIN
C5 VIN
D5 GND
E5 GND
F5 GND
A6 VIN
B6 VIN
C6 VIN
D6 GND
E6 GND
F6 GND
A7 INTVCC
B7 GND
C7 GND
D7 -
E7 GND
F7 GND
A8 MODE_PLLIN
B8 -
C8 -
D8 GND
E8 -
F8 GND
A9 TRACK/SS
B9 GND
C9 GND
D9 INTVCC
E9 GND
F9 GND
A10 RUN
B10 -
C10 MTP3
D10 MTP6
E10 -
F10 -
A11 COMP
B11 MTP2
C11 MTP4
D11 MTP7
E11 -
F11 PGOOD
A12 MTP1
B12 fSET
C12 MTP5
D12 MTP8
E12 EXTVCC
F12 VFB
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
G1 GND
H1 GND
J1 VOUT
K1 VOUT
L1 VOUT
M1 VOUT
G2 GND
H2 GND
J2 VOUT
K2 VOUT
L2 VOUT
M2 VOUT
G3 GND
H3 GND
J3 VOUT
K3 VOUT
L3 VOUT
M3 VOUT
G4 GND
H4 GND
J4 VOUT
K4 VOUT
L4 VOUT
M4 VOUT
G5 GND
H5 GND
J5 VOUT
K5 VOUT
L5 VOUT
M5 VOUT
G6 GND
H6 GND
J6 VOUT
K6 VOUT
L6 VOUT
M6 VOUT
G7 GND
H7 GND
J7 VOUT
K7 VOUT
L7 VOUT
M7 VOUT
G8 GND
H8 GND
J8 VOUT
K8 VOUT
L8 VOUT
M8 VOUT
G9 GND
H9 GND
J9 VOUT
K9 VOUT
L9 VOUT
M9 VOUT
G10 -
H10 -
J10 VOUT
K10 VOUT
L10 VOUT
M10 VOUT
G11 SGND
H11 SGND
J11 -
K11 VOUT
L11 VOUT
M11 VOUT
G12 PGOOD
H12 SGND
J12 VOSNS+
K12 DIFF_OUT L12 VOUT_LCL
M12 VOSNS–
4627fc
For more information www.linear.com/LTM4627
27
LTM4627
PACKAGE PHOTOS
LGA
15mm
4.32mm
15mm
BGA
15mm
4.92mm
15mm
4627fc
28
For more information www.linear.com/LTM4627
aaa Z
0.630 ±0.025 Ø 133x
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
4
1.9050
PIN “A1”
CORNER
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
Y
For more information www.linear.com/LTM4627
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
X
D
3.95 – 4.05
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.20
0.30
0.15
MAX
5.12
0.70
4.42
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
DIMENSIONS
NOM
4.92
0.60
4.32
0.75
0.63
15.0
15.0
1.27
13.97
13.97
A
A2
TOTAL NUMBER OF BALLS: 133
MIN
4.72
0.50
4.22
0.60
0.60
DETAIL A
b1
0.27 – 0.37
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
MOLD
CAP
ccc Z
Øb (133 PLACES)
// bbb Z
Z
e
b
b
L
K
J
G
G
F
e
E
PACKAGE BOTTOM VIEW
H
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
TRAY PIN 1
BEVEL
BGA 133 0511 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
5. PRIMARY DATUM -Z- IS SEATING PLANE
BALL DESIGNATION PER JESD MS-028 AND JEP95
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
M
DETAIL A
COMPONENT
PIN “A1”
3
SEE NOTES
F
(Reference LTC DWG # 05-08-1897 Rev Ø)
(Reference133-Lead
LTC DWG(15mm
# 05-08-1897
Ø)
× 15mmRev
× 4.92mm)
BGA Package
133-Lead (15mm × BGA
15mm
× 4.92mm)
Package
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
LTM4627
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
PACKAGE DESCRIPTION
4627fc
29
For more information www.linear.com/LTM4627
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
4
PACKAGE TOP VIEW
3.1750
0.630
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PAD 1
CORNER
15
BSC
0.6350
0.0000
0.6350
15
BSC
Y
0.630
X
DETAIL B
4.22 – 4.42
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
LAND DESIGNATION PER JESD MO-222, SPP-010
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
eee
0.05
6. THE TOTAL NUMBER OF PADS: 133
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
M
L
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
PADS
SEE NOTES
1.27
BSC
13.97
BSC
0.12 – 0.28
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A
0.27 – 0.37
SUBSTRATE
eee S X Y
DETAIL B
MOLD
CAP
0.630 ±0.025 SQ. 133x
aaa Z
3.95 – 4.05
bbb Z
aaa Z
1.9050
(Reference LTC DWG # 05-08-1777 Rev Ø)
Z
30
3.1750
LGA Package
133-Lead (15mm × 15mm × 4.32mm)
K
G
F
E
LTMXXXXXX
µModule
PACKAGE BOTTOM VIEW
H
D
C
B
LGA 133 1008 REV Ø
A
DETAIL A
PACKAGE IN TRAY LOADING ORIENTATION
J
13.97
BSC
1
2
3
4
5
6
7
8
9
10
11
12
C(0.30)
PAD 1
LTM4627
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4627fc
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
LTM4627
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
2/11
Updated the Electrical Characteristics section.
Updated graph G13.
3, 4
6
Updated the Inductor value in the Block Diagram and in the Power Module Description section.
Updated the PLL, Frequency Adjustment and Synchronization section.
Updated Figure 3.
9, 10
13
14
B
10/11
BGA Package added. Changes reflected throughout the data sheet.
1-32
C
02/14
Add SnPb BGA package option
1, 2
4627fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
www.linear.com/LTM4627
tion that the interconnection
of its information
circuits as described
herein will not infringe on existing patent rights.
31
LTM4627
TYPICAL APPLICATION
3.3V at 10A Design
5V
C3
22µF
16V
C1
22µF
16V
C2
22µF
16V
C7
0.1µF
R1
10k
VIN
EXTVCC INTVCC PGOOD
COMP
VOUT
TRACK/SS
LTM4627
RUN
R3
174k
CONTINUOUS
MODE
VOUT_LCL
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
GND
VFB
82pF
RFB
13.3k
C4
100µF
X5R
C6
100µF
X5R
6.3V
VOUT
3.3V
10A
C5
47pF
4627 TA02
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4627fc
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4627
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4627
LT 0214 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2010
工商网监
湘ICP备2023018690号
