LTM4639
Low VIN 20A DC/DC
µModule Step-Down Regulator
DESCRIPTION
FEATURES
Complete 20A Switch Mode Power Supply
n 2.375V to 7V Input Voltage Range (V < 4.5V,
IN
Need CPWR Bias)
n 0.6V to 5.5V Output Voltage Range
n ±1.5% Maximum Total DC Output Voltage Error
(–40°C to 125°C)
n Differential Remote Sense Amplifier for Precision
Regulation (VOUT ≤ 3.3V)
n Current Mode Control/Fast Transient Response
n Parallel Multiphase Current Sharing (Up to 80A)
n Frequency Synchronization
n Selectable Pulse-Skipping or Burst Mode® Operation
n Soft-Start/Voltage Tracking
n Up to 88% Efficiency (3.3V , 1.5V
IN
OUT)
n Overcurrent Foldback Protection
n Output Overvoltage Protection
n Internal Temperature Monitor
n Overtemperature Protection
n 15mm × 15mm × 4.92mm BGA Package
The LTM®4639 is a complete 20A output high efficiency
switch mode step-down DC/DC µModule (micromodule)
regulator. Included in the package are the switching
controller, power FETs, inductor and compensation
components. Operating over an input voltage range from
2.375V to 7V, the LTM4639 supports an output voltage
range of 0.6V to 5.5V, set by a single external resistor.
Only a few input and output capacitors are needed.
n
Current mode operation allows precision current sharing of
up to four LTM4639 regulators to obtain up to 80A output.
High switching frequency and a current mode architecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing,
Burst Mode operation and output voltage tracking for
supply rail sequencing. A diode-connected PNP transistor
is included for use as an internal temperature monitor. For
up to 20V input operation, please see the LTM4637.
The LTM4639 is offered in a 15mm × 15mm × 4.92mm
BGA package. The LTM4639 is RoHS compliant.
APPLICATIONS
L, LT, LTC, LTM, PolyPhase, Burst Mode, µModule, Linear Technology, the Linear logo are
registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643.
Telecom Servers and Networking Equipment
n Industrial Equipment
n Medical Systems
n High Ambient Temperature Systems
n 3.3V Input Systems
n
TYPICAL APPLICATION
3.3V to 1.5V Efficiency
and Power Loss
3.3VIN, 1.5VOUT, 20A DC/DC µModule® Regulator
+5V BIAS
2.2µF
1µF
CCOMPA
180pF
5k
0.1µF
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
TRACK/SS
RUN
VOUT_LCL
LTM4639
fSET
100k
* SEE TABLE 5
** SEE TABLE 1
CFF*
180pF
VOSNS+
VFB
TEMP+
SGND
DIFF_OUT
100µF* +
6.3V
×2
680µF*
2.5V
×2
GND
OT_TEST
RFB**
40.2k
3.0
2.5
85
2.0
80
70
CBOT*
22pF
4.0
3.5
90
CPWR = 5V
FREQ = 400kHz
75
VOSNS–
MODE_PLLIN
TEMP–
VOUT
1.5V
20A
VOUT
COMPB
EFFICIENCY
1.5
POWER LOSS
POWER LOSS
22µF
6.3V
×4
4.5
95
EFFICIENCY (%)
VIN
3.3V
100
1.0
0.5
0
2
4
6 8 10 12 14 16 18 20
OUTPUT CURRENT (A)
4639 TA01b
0
4639 TA01a
4639f
For more information www.linear.com/LTM4639
1
LTM4639
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN, CPWR, OT_TEST................................... –0.3V to 10V
VOUT_LCL, PGOOD, EXTVCC........................... –0.3V to 6V
MODE_PLLIN, fSET, TRACK/SS,
VOSNS –, VOSNS+, DIFF_OUT.................... –0.3V to INTVCC
VFB, COMPA, COMPB (Note 7) .................. –0.3V to 2.7V
RUN (Note 5)................................................ –0.3V to 5V
INTVCC Peak Output Current (Note 6)...................100mA
Internal Operating Temperature Range
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Maximum Peak Body Reflow Temperature............ 245°C
1
2
3
VIN
TOP VIEW
COMPB
MODE_PLLIN
INTVCC
TRACK/SS COMPA
4
5
6
7
8
9
10
11
12
A
VIN
RUN C
PWR
fSET
B
OT_TEST
C
TEMP–
TEMP+
GND
INTVCC
D
F
EXTVCC
PGOOD
VFB
G
PGOOD
E
SGND
H
VOUT
J
VOSNS+
K
DIFF_OUT
L
VOUT_LCL
M
VOSNS–
BGA PACKAGE
133-LEAD (15mm × 15mm × 4.92mm)
TJ(MAX) = 125°C, θJA = 9.5°C/W, θJCbottom = 4°C/W, θJCtop = 6.7°C/W, θJB = 4.5°C/W
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.8g
θ VALUES DETERMINED PER JESD51-12
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4639EY#PBF
LTM4639IY#PBF
LTM4639IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
e1
BGA
4
–40°C to 125°C
e0
BGA
4
–40°C to 125°C
LTM4639Y
LTM4639Y
LTM4639Y
TEMPERATURE RANGE
(SEE NOTE 2)
• Consult Marketing for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking: www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
VIN Range
PARAMETER
CONDITIONS
Input DC Voltage Range
VIN < 4.5V, CPWR Bias
MIN
l
CPWR Voltage
VOUT Range
Output DC Voltage Range
VOUT(DC)
Output Voltage, Total
Variation with Line and
Load
2.375
4.5
CIN = 22µF × 3, CPWR = 5V
COUT = 100µF Ceramic, 470µF POSCAP
RFB = 40.2k, MODE_PLLIN = GND
VIN = 2.375V to 7V, IOUT = 0A to 20A (Note 4)
TYP
l
0.6
l
1.477
5
1.50
MAX
UNITS
7
V
6
V
5.5
V
1.523
V
4639f
2
For more information www.linear.com/LTM4639
LTM4639
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VRUN Rising
1.1
1.25
1.4
UNITS
Input Specifications
VRUN
RUN Pin On Threshold
VRUNHYS
RUN Pin On Hysteresis
IQ(VIN)
Input Supply Bias Current
VIN = 7V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A
VIN = 7V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A
VIN = 7V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A
Shutdown, RUN = 0, VIN = CPWR = 7V
IS(VIN)
Input Supply Current
VIN = 3.3V, VOUT = 1.5V, IOUT = 20A, CPWR = 5V
VIN = 7V, VOUT = 1.5V, IOUT = 20A, CPWR = 5V
IPWR(IN)
Control Power Current
3.3VIN to 1.5VOUT at 0A Load, CPWR = 5V
V
130
mV
25
35
68
45
mA
mA
mA
µA
10.35
4.93
A
A
28
mA
Output Specifications
IOUT(DC)
Output Continuous Current VIN = 3.3V, VOUT = 1.5V (Note 4)
Range
0
20
A
∆VOUT (Line)
VOUT
Line Regulation Accuracy
VOUT = 1.5V, VIN from 2.375V to 7V, CPWR = 5V,
IOUT = 0A
l
0.02
0.04
%/V
∆VOUT (Load)
VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 20A, VIN = 3.3V, CPWR = 5V
(Note 4)
l
0.1
0.3
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic, 470µF POSCAP
VIN = 3.3V, VOUT = 1.5V, CPWR = 5V
20
mVP-P
∆VOUT(START)
Turn-On Overshoot
COUT = 100µF Ceramic, 470µF POSCAP,
VOUT = 1.5V, IOUT = 0A, VIN = 3.3V, CPWR = 5V
15
mV
tSTART
Turn-On Time
COUT = 100µF Ceramic, 470µF POSCAP,
No Load, TRACK/SS = 0.001µF, VIN = 3.3V, CPWR = 5V
0.6
ms
∆VOUTLS
Peak Deviation for
Dynamic Load
Load: 5A to 12.5A Load Step, 1µs Rise Time
COUT = 100µF × 2 Ceramic, COUT × 2 POSCAP,
VIN = 3.3V, VOUT = 1.5V, CPWR = 5V
30
mV
tSETTLE
Settling Time for Dynamic
Load Step
Load: 5A to 12.5A Load Step, 3.3V, VIN = 5V, VOUT = 1.5V
COUT = 100µF × 2 Ceramic, 680µF POSCAP
30
µs
IOUTPK
Output Current Limit
VIN = 3.3V, VOUT = 1.5V
VIN = 7V, VOUT = 1.5V
30
30
A
A
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.5V
(Note 7)
Control Section
IFB
Current at VFB Pin
VOVL
Feedback Overvoltage
Lockout
ITRACK/SS
Track Pin Soft-Start PullUp Current
TRACK/SS = 0V
tON(MIN)
Minimum On-Time
(Note 3)
RFBHI
Resistor Between VOUT_LCL
and VFB Pins
l
0.594
0.60
0.606
V
l
0.65
–12
–25
nA
0.67
0.69
V
1.0
1.2
1.4
µA
100
60.05
60.40
ns
60.75
kΩ
Remote Sense Amplifier
VOSNS+,
VOSNS– CM RANGE
Common Mode Input
Range
VIN = 3.3V, Run > 1.4V, CPWR = 5V
VDIFF_OUT(MAX)
Maximum DIFF_OUT
Voltage
IDIFF_OUT = 300µA
VOS
Input Offset Voltage
VOSNS+ = VDIFF_OUT = 1.5V, IDIFF_OUT = 100µA
0
3.6
INTVCC – 1.4
V
V
2.5
mV
4639f
For more information www.linear.com/LTM4639
3
LTM4639
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
PARAMETER
CONDITIONS
AV
Differential Gain
(Note 7)
MIN
TYP
MAX
1
UNITS
V/V
SR
Slew Rate
(Note 6)
2
V/µs
GBP
Gain Bandwidth Product
(Note 6)
3
MHz
CMRR
Common Mode Rejection
(Note 7)
60
dB
IDIFF_OUT
DIFF_OUT Current
Sourcing
PSRR
Power Supply Rejection
Ratio
5V < VIN < 7V (Note 7)
CPWR Tracking VIN
2
100
mA
dB
RIN
Input Resistance
VOSNS+ to GND
80
kΩ
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
5
5.2
PGOOD Output
V
INTVCC Linear Regulator
VINTVCC Source Output
5V < VIN < 7V, CPWR Tracking VIN
VLDOINT
INTVCC Load Regulation
ICC = 0 to 40mA, CPWR = 5.5V
VEXTVCC
External VCC Switchover
EXTVCC Ramping Positive, CPWR = 5.5V, INTVCC Output 5V
VLDOEXT
EXTVCC Voltage Drop
ICC = 25mA, VEXTVCC = 5V, CPWR = 5.5V
4.8
2
l
4.5
V
%
4.7
75
V
220
mV
800
kHz
Oscillator and Phase-Locked Loop
fSYNC
Frequency Sync Capture
Range
MODE_PLLIN Clock Duty Cycle = 50%
250
fNOM
Nominal Frequency
VfSET = 1.2V
450
500
550
kHz
fLOW
Lowest Frequency
VfSET = 0V
210
250
290
kHz
fHIGH
Highest Frequency
VfSET ≥ 2.4V
700
770
850
kHz
10
11
IFREQ
Frequency Set Current
RMODE_PLLIN
MODE_PLLIN Input
Resistance
VIH_MODE_PLLIN
Clock Input Level High
VIL_MODE_PLLIN
Clock Input Level Low
9
250
µA
kΩ
2.0
V
0.8
V
Temperature Diode
VTEMP
TEMP Diode Voltage
TC VTEMP
Temperature Coefficient
ITEMP = 100µA
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4639 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4639E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4639I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
0.6
V
–2
mV/°C
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: The minimum on-time condition is specified for a peak-to-peak
inductor ripple current of ~40% of IMAX Load. (See the Applications
Information section)
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Limit current into the RUN pin to less than 2mA.
Note 6: Guaranteed by design.
Note 7: 100% tested at wafer level.
4639f
4
For more information www.linear.com/LTM4639
LTM4639
TYPICAL PERFORMANCE CHARACTERISTICS
3.3V Efficiency Graph
5V Efficiency Graph
100
95
95
95
90
90
90
85
80
75
70
2.5V TO 1.8V
2.5V TO 1.5V
2.5V TO 1.2V
2.5V TO 1V
CPWR = 5V
FREQ = 350kHz
0
2
4
6
8 10 12 14 16 18 20
OUTPUT CURRENT (A)
85
80
75
70
3.3V TO 2.5V
3.3V TO 1.8V
3.3V TO 1.5V
3.3V TO 1.2V
3.3V TO 1V
CPWR = 5V
FREQ = 400kHz
0
2
4
6
8 10 12 14 16 18 20
OUTPUT CURRENT (A)
4637 G01
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
2.5V Input Efficiency Graph
100
85
80
75
70
CPWR = VIN
FREQ = 500kHz
0
2
4
6
8 10 12 14 16 18 20
OUTPUT CURRENT (A)
4639 G02
4639 G03
2.5V to 1V with 7.5A/µs Load
Step, CPWR = 5V
7V Efficiency Graph
5V TO 3.3V
5V TO 2.5V
5V TO 1.8V
5V TO 1.5V
5V TO 1.2V
5V TO 1V
2.5V to 1.2V with 7.5A/µs Load
Step, CPWR = 5V
100
EFFICIENCY (%)
95
VOUT
VP-P = 80mV
VOUT
VP-P = 80mV
LOAD
STEP
0A TO 7.5A
LOAD
STEP
0A TO 7.5A
90
85
80
75
70
CPWR = VIN
FREQ = 550kHz
0
2
4
7V TO 5V
7V TO 3.3V
7V TO 2.5V
7V TO 1.8V
7V TO 1.5V
7V TO 1.2V
7V TO 1V
50µs/DIV
6
8 10 12 14 16 18 20
OUTPUT CURRENT (A)
4639 G05
50µs/DIV
4639 G06
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
3.3V to 1V with 7.5A/µs Load
Step, CPWR = 5V
3.3V to 1.2V with 7.5A/µs Load
Step, CPWR = 5V
4639 G03
2.5V to 1.5V with 7.5A/µs Load
Step, CPWR = 5V
VOUT
VP-P =
80mV
VOUT
VP-P = 80mV
VOUT
VP-P = 80mV
LOAD
STEP
0A TO
7.5A
LOAD
STEP
0A TO 7.5A
LOAD
STEP
0A TO 7.5A
50µs/DIV
4639 G07
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
50µs/DIV
4639 G08
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
50µs/DIV
4639 G09
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
4639f
For more information www.linear.com/LTM4639
5
LTM4639
TYPICAL PERFORMANCE CHARACTERISTICS
3.3V to 1.5V with 7.5A/µs Load
Step, CPWR = 5V
5V to 1.8V with 7.5A/µs Load
Step, CPWR = 5V
VOUT
VP-P =
80mV
VOUT
VP-P = 80mV
LOAD
STEP
0A TO
7.5A
LOAD
STEP
0A TO 7.5A
50µs/DIV
5V to 3.3V with 7.5A/µs Load
Step, CPWR = 5V
VOUT
VP-P =
250mV
LOAD
STEP
0A TO 7.5A
4639 G10
50µs/DIV
4639 G11
50µs/DIV
4639 G12
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2, 680µF 2.5V 6mΩ POSCAP ×2
COMPA CONNECTED TO COMPB
CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF
COUT = 100µF CER ×2, 680µF 2.5V 6mΩ POSCAP ×2
COMPA CONNECTED TO COMPB
CFF = NONE, CBOT = 22pF, CCOMPA = 180pF
COUT = 47µF CER ×1,
220µF 6.3V 15mΩ POSCAP ×2
7V to 5V with 7.5A/µs Load Step,
CPWR = 5V
Turn-On No Load
Start-Up Pre-Biased Load
SW
VOUT
VP-P =
400mV
SW
VOUT
0.5V/DIV
VOUT
0.5V/DIV
LOAD
STEP
0A TO
7.5A
RUN
1V/DIV
50µs/DIV
RUN
2V/DIV
4639 G13
20ms/DIV
4639 G14
20ms/DIV
COMPA CONNECTED TO COMPB
CFF = NONE, CBOT = 22pF, CCOMPA = 180pF
COUT = 22µF CER ×1,
150µF 6.3V 15mΩ POSCAP ×2
VIN = 5V
VOUT = 1V
IOUT = 20A
VIN = 5V
VOUT = 1V, VOUT = 0.5V BIAS
IOUT = 20A
Recycling VIN (On-Off-On)
Output Short-Circuit
Output Ripple Noise
SW
SW
4639 G15
VP-P = 8mV
IIN
200mA/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
RUN
2V/DIV
1s/DIV
VIN = 5V
VOUT = 1V
4639 G16
500µs/DIV
4639 G17
VIN = 5V
VOUT = 1V
1µs/DIV
4639 G18
VIN = 3.3V
VOUT = 1V
IOUT = 20A
4639f
6
For more information www.linear.com/LTM4639
LTM4639
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply
input voltage between these and GND pins. Recommend
placing input decoupling capacitance directly between
VIN and GND pins.
VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output
Pins. Apply output load between these and GND pins.
Recommend placing output decoupling capacitance
between these pins and GND pins. Review Table 5. Output
range 0.6V to 5.5V.
GND (C7, C9, D1-D6, D8, E1-E5, E7, E9, F1-F5, F7-F9,
G1-G9, H1-H9): Power Ground Pins for Both Input and
Output.
PGOOD (F11, G12): Output Voltage Power Good Indicator.
Open-drain logic output is pulled to ground when the
output voltage exceeds a ±10% regulation window. Both
pins are tied together internally.
SGND (G11, H11, H12): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND. See layout
guidelines in Figure 21.
TEMP+ (F6): Temperature Monitor. See Applications Information section.
TEMP– (E6): Kelvin Return of the Internal Temperature
Monitor.
MODE_PLLIN (A8): Forced Continuous Mode, Burst
Mode Operation, or Pulse-Skipping Mode Selection Pin
and External Synchronization Input to Phase Detector Pin.
Connect this pin to INTVCC to enable pulse-skipping mode.
Connect to ground to enable forced continuous mode.
Floating this pin will enable Burst Mode operation. A clock on
this pin will enable synchronization with forced continuous
operation. See the Applications Information section.
CPWR (B7): Control Bias Input. Required to operate the
LTM4639 regulator below 4.5V input. For VIN ≥4.5V up to
7V connect CPWR to VIN. To maintain soft-start function,
sequence VIN before CPWR, then enable the RUN pin. If
the RUN pin has a pull-up resistor to VIN, then sequence
CPWR after VIN.
OT_TEST (B9): Used for Test Purposes. Float this pin, or
tie to VIN to disable overtemperature protection.
fSET (B12): A resistor can be applied from this pin to
ground to set the operating frequency, or a DC voltage
can be applied to set the frequency. See the Applications
Information section.
TRACK/SS (A9): Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.2µA pull-up current source. A
capacitor from this pin to ground will set a soft-start ramp
rate. In tracking, the regulator output can be tracked to a
different voltage. See the Applications Information section.
VFB (F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT_LCL with a
60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between VFB
and ground pins. In PolyPhase® operation, tying the
VFB pins together allows for parallel operation. See the
Applications Information section.
COMPA (A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. Tie all
COMP pins together for parallel operation. This pin can
be compensated externally for optimized loop response
or connected to the COMPB pin. See the Applications
Information section.
COMPB (A12): Default Compensation Network
Corresponding to Table 5. Tie this pin to COMPA to use
default compensation. See the Applications Information
section.
RUN (A10): Run Control Pin. A voltage above 1.4V will turn
on the module. A 5.1V Zener diode to ground is internal to
the module for limiting the voltage on the RUN pin to 5V
and allowing the use of a pull-up resistor to VIN for enabling
the device. Limit current into the RUN pin to ≤ 2mA.
INTVCC (A7, D9): Internal 5V LDO for Driving the Control
Circuitry and the Power MOSFET Drivers. Both pins are
internally connected. The 5V LDO has a 100mA current
limit. INTVCC is controlled and enabled when RUN is
activated high. See Applications Section. This pin is an
output, do not drive this pin.
4639f
For more information www.linear.com/LTM4639
7
LTM4639
PIN FUNCTIONS
EXTVCC (E12): External power input to an internal control
switch allows an external source greater than 4.7V, but less
than 6V to supply IC power and bypass the internal INTVCC
LDO. EXTVCC must be less than VIN at all times during
power-on and power-off sequences. See the Applications
Information section. 5V output application can connect the
5V output to this pin to improve efficiency. The 5V output
is connected to EXTVCC in the 5V derating curves.
VOUT_LCL (L12): This pin connects to VOUT through a 1M
resistor, and to VFB with a 60.4k resistor. The remote sense
amplifier output DIFF_OUT is connected to VOUT_LCL, and
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
DIFF_OUT effectively eliminates the 1MΩ from VOUT to
VOUT_LCL. When the remote sense amplifier is not used,
then connect VOUT_LCL to VOUT directly.
VOSNS+ (J12): (+) Input to the Remote Sense Amplifier.
This pin connects to the output remote sense point. The
remote sense amplifier can be used for VOUT ≤ 3.3V.
Connect to ground when not used.
VOSNS– (M12): (–) Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier can be used for VOUT ≤ 3.3V.
Connect to ground when not used.
DIFF_OUT (K12): Output of the Remote Sense Amplifier.
This pin connects to the VOUT_LCL pin for remote sense
applications. Otherwise float when not used. The remote
sense amplifier can be used for VOUT ≤ 3.3V.
MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7, (A12,
B11, C10, C11, C12, D10, D11, D12): Extra mounting pads
used for increased solder integrity strength. Leave floating.
4639f
8
For more information www.linear.com/LTM4639
LTM4639
BLOCK DIAGRAM
PTC
OT_TEST
+
OTP
~135°C
–
VOUT_LCL
1M
VIN
400mV
10k
PGOOD
CPWR
RUN
R2
COMPB
5.1V
1.5µF
35V
60.4k
0.3µH
VOUT
1V
20A
VOUT
+
10µF
6.3V
M2
fSET
COUT
GND
INTERNAL
LOOP
FILTER
2.2Ω
SGND
INTVCC
MODE_PLLIN
+
250k
DIFF
AMP
–
INTVCC
+
TRACK/SS
2.2µF
CIN
TEMP–
POWER
CONTROL
VFB
C SOFT-START
VIN
2.375V TO 7V
PNP
47pF
SGND
+
TEMP+
M1
INTERNAL
COMP
RfSET
75k
+5V BIAS
VIN
COMPA
RFB
90.9k
INTVCC
+
–
R1
> 1.4V = ON
< 1.1V = OFF
MAX = 5V
VOUT
499k
C
VOSNS–
VOSNS+
DIFF_OUT
EXTVCC
4639 F01
Figure 1. Simplified LTM4639 Block Diagram
4639f
For more information www.linear.com/LTM4639
9
LTM4639
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN
External Input Capacitor Requirement
(VIN = 2.375V to 7V, VOUT = 1.5V),
CPWR ≥ 4.5V
IOUT = 20A, 4× 22µF Ceramic X7R Capacitors
(See Table 5)
MIN
TYP
88
MAX
UNITS
µF
COUT
External Output Capacitor Requirement
(VIN = 2.375V to 7V, VOUT = 1.5V),
CPWR ≥ 4.5V
IOUT = 20A (See Table 5)
400
µF
OPERATION
Power Module Description
The LTM4639 is a low input voltage,high performance
single output standalone nonisolated switching mode DC/
DC power supply. It can provide a 20A output with few
external input and output capacitors. This module provides
precisely regulated output voltages programmable via
external resistors from 0.6VDC to 5.5VDC over a 2.375V
to 7V input range. The typical application schematic is
shown in Figure 22.
The LTM4639 has an integrated constant-frequency current
mode regulator, power MOSFETs, 0.3µH inductor, and
other supporting discrete components. The switching
frequency range is from 250kHz to 770kHz, and the typical
operating frequency is shown in Table 5 for each VOUT. For
switching noise-sensitive applications, it can be externally
synchronized from 250kHz to 800kHz, subject to minimum
on-time limitations. A single resistor is used to program
the frequency. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4639 module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
Overtemperature protection will turn off the regulator’s
RUN pin at ~130°C to 137°C. See Applications Information.
Pulling the RUN pin below 1.1V forces the regulator
into a shutdown state. The TRACK/SS pin is used for
programming the output voltage ramp and voltage tracking
during start-up. See the Application Information section.
The LTM4639 is internally compensated to be stable over
all operating conditions with COMPA tied to COMPB. Table
5 provides a guideline for input and output capacitances
for several operating conditions. LTpowerCAD™ is available
for transient and stability analysis. Custom compensation
can be used with the COMPA pin using the LTpowerCAD
and an external compensation network. The VFB pin is
used to program the output voltage with a single external
resistor to ground.
A remote sense amplifier is provided for accurately sensing
output voltages ≤3.3V at the load point.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light load features will accommodate battery
operation. Efficiency graphs are provided for light load
operation in the Typical Performance Characteristics
section.
A TEMP+ and TEMP– pin is provided to allow the internal
device temperature to be monitored using an onboard
diode connected PNP transistor. This diode connected
PNP transistor can be used with TEMP monitor devices
like the LTC2990, LTC2997, LTC2974 and LTC2978.
4639f
10
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
The typical LTM4639 application circuit is shown in Figure 22. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
VIN to VOUT Step-Down Ratios
There are restrictions in the VIN to VOUT step-down ratio
that can be achieved for a given input voltage. The duty
cycle is 94% typical at 500kHz operation. The VIN to VOUT
minimum dropout is a function of load current and operation
at very low input voltage and high duty cycle applications.
At very low duty cycles the minimum 100ns on-time must
be maintained. See the Frequency Adjustment section and
temperature derating curves.
Input Capacitors
The LTM4639 module should be connected to a low ACimpedance DC source. Additional input capacitors are
needed for the RMS input ripple current rating. The ICIN(RMS)
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~ 2A each.
A 47µF to 100µF surface mount aluminum electrolytic bulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. If low impedance power
planes are used, then this bulk capacitor is not needed.
For a buck converter, the switching duty cycle can be
estimated as:
Output Voltage Programming
The PWM controller has an internal 0.6V ±1% reference
voltage. As shown in the Block Diagram, a 60.4k internal
feedback resistor connects the VOUT_LCL and VFB pins
together. When the remote sense amplifier is used, then
DIFF_OUT is connected to the VOUT_LCL pin. If the remote
sense amplifier is not used, then VOUT_LCL connects to
VOUT. The output voltage will default to 0.6V with no
feedback resistor. Adding a resistor RFB from VFB to ground
programs the output voltage:
VOUT = 0.6V •
60.4k+R FB
R FB
RFB (k)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5.0
Open
90.9
60.4
40.2
30.1
19.1
13.3
8.25
For parallel operation of N LTM4639s, the following
equation can be used to solve for RFB:
RFB=
VOUT
VIN
Without considering the inductor ripple current, for each
output the RMS current of the input capacitor can be
estimated as:
I CIN(RMS)=
IOUT(MAX)
η%
• D•(1–D)
where η% is the estimated efficiency of the power module.
The bulk capacitor can be a switcher-rated aluminum
electrolytic capacitor or a Polymer capacitor.
Output Capacitors
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT (V)
D=
60.4k / N
VOUT
–1
0.6V
Tie the VFB pins together for each parallel output. The
COMP pins must be tied together also.
The LTM4639 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance
(ESR) to meet the output voltage ripple and transient
requirements. COUT can be a low ESR tantalum capacitor,
low ESR Polymer capacitor or ceramic capacitors. The
typical output capacitance range is from 200µF to 800µF.
Additional output filtering may be required by the system
designer if further reduction of output ripple or dynamic
transient spikes is required. Table 5 shows a matrix
of different output voltages and output capacitors to
minimize the voltage droop and overshoot during a 10A/µs
transient. The table optimizes total equivalent ESR and total
bulk capacitance to optimize the transient performance.
4639f
For more information www.linear.com/LTM4639
11
LTM4639
APPLICATIONS INFORMATION
Stability criteria are considered in the Table 5 matrix, and
LTpowerCAD is available for stability analysis and custom
compensation for loop optimization using the COMPA pin.
Multiphase operation will reduce effective output ripple
as a function of the number of phases. Application Note
77 discusses this noise reduction versus output ripple
current cancellation, but the output capacitance should be
considered carefully as a function of stability and transient
response. LTpowerCAD can be used to calculate the output
ripple reduction as the number of implemented phases
increase by N times.
Burst Mode Operation
The LTM4639 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply float the MODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductor is set to approximately 30% of the maximum peak
current value in normal operation even though the voltage
at the COMPA pin indicates a lower value. The voltage at
the COMPA pin drops when the inductor’s average current
is greater than the load requirement. As the COMPA voltage
drops below 0.5V, the burst comparator trips, causing
the internal sleep line to go high and turn off both power
MOSFETs.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMPA to rise, the internal
sleep line goes low, and the LTM4639 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
Pulse-Skipping Mode Operation
In applications where low output ripple and high efficiency at intermediate currents are desired, pulseskipping mode should be used. Pulse-skipping operation
allows the LTM4639 to skip cycles at low output loads,
thus increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTVCC enables pulse-skipping
operation. With pulse-skipping mode at light load, the
internal current comparator may remain tripped for several
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
output loads, the COMPA voltage is in control of the current
comparator threshold throughout, and the top MOSFET
always turns on with each oscillator pulse. During start-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4639’s output
voltage is in regulation.
Multiphase Operation
For outputs that demand more than 20A of load current,
multiple LTM4639 devices can be paralleled to provide
more output current without increasing input and output
ripple voltage. The MODE_PLLIN pin allows the LTM4639
to be synchronized to an external clock and the internal
phase-locked loop allows the LTM4639 to lock onto input
clock phase as well. The fSET resistor is selected for normal
frequency, then the incoming clock can synchronize
the device over the specified range. See Figure 24 for a
synchronizing example circuit.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used. See Application Note 77.
The LTM4639 device is an inherently current mode
controlled device, so parallel modules will have good
current sharing. This will balance the thermals in the
design. Tie the COMPA and VFB pins of each LTM4639
4639f
12
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current
cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases
(see Figure 2).
PLL, Frequency Adjustment and Synchronization
The LTM4639 switching frequency is set by a resistor (RfSET)
from the fSET pin to signal ground. A 10µA current (IFREQ)
flowing out of the fSET pin through RfSET develops a voltage
on fSET. RfSET can be calculated as:
FREQ
1
RfSET =
+0.2V
500kHz / V
10µA
0.60
0.55
0.50
The relationship of fSET voltage to switching frequency is
shown in Figure 3. For low output voltages from 0.6V to
1.2V, 300kHz operation is an optimal frequency for the
best power conversion efficiency while maintaining the
inductor current to about 40% to 50% of maximum load
current. For output voltages from 1.5V to 1.8V, 450kHz
is optimal. For output voltages from 2.5V to 5V, 600kHz
900
800
SWITCHING FREQUENCY (kHz)
together to share the current evenly. Figure 24 shows a
schematic of the parallel design.
700
600
500
400
300
200
100
0
0
0.5
1
1.5
fSET PIN VOLTAGE (V)
2
2.5
4639 F03
Figure 3. Relationship Between Switching
Frequency and Voltage at the fSET Pin
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
4639 F02
Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)
4639f
For more information www.linear.com/LTM4639
13
LTM4639
APPLICATIONS INFORMATION
is optimal. See efficiency graphs for optimal frequency
set point.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4639 uses an
accurate 60.4k resistor internally for the top feedback
resistor. Figure 4 shows an example of coincident tracking.
The LTM4639 can be synchronized from 250kHz to
800kHz with an input clock that has a high level above 2V
and a low level below 0.8V. See the Typical Applications
section for synchronization examples. The LTM4639
minimum on-time is limited to approximately 100ns.
Guardband the on-time to 110ns. The on-time can be
calculated as:
t ON(MIN)=
1 V OUT
•
FREQ VIN
60.4k
VOUT(SLAVE) = 1+
• V TRACK
R TA
+5V BIAS
VIN
3.3V
2.2µF
14µF
CIN1
22µF
16V
×4
SOFT-START
CAPACITOR
R2
5k
CSS
180pF
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
VOUT
COMPB
VOUT_LCL
TRACK/SS
RUN
LTM4639
fSET
R4
100k
DIFF_OUT
VFB
TEMP+
TEMP
SGND
180pF
VOSNS+
C8
680µF
2.5V
×2
C11
100µF
6.3V
×2
C4
680µF
2.5V
×2
C6
100µF
6.3V
×2
VOSNS–
MODE_PLLIN
–
+
VOUT2
1.5V
20A
GND
OT_TEST
RFB1
40.2k
22pF
2.2µF
VIN
3.3V
CIN2
22µF
16V
×4
+5V BIAS
MASTER RAMP
OR OUTPUT
R1
5k
RTA
60.4k
180pF
RTB
60.4k
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
VOUT
COMPB
VOUT_LCL
TRACK/SS
RUN
LTM4639
fSET
R3
100k
SGND
180pF
VOSNS+
VFB
TEMP+
TEMP
DIFF_OUT
VOSNS–
MODE_PLLIN
–
+
VOUT1
1.2V
20A
GND
OT_TEST
RFB
60.4k
22pF
4639 F04
Figure 4. Dual Outputs (1.5V and 1.2V) with Tracking
4639f
14
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.6V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue
to its final value from the slave’s regulation point (see
Figure 5). Voltage tracking is disabled when VTRACK is
more than 0.6V. RTA in Figure 4 will be equal to RFB for
coincident tracking.
MASTER OUTPUT
OUTPUT
VOLTAGE
R TA =
0.6V
V FB V FB V TRACK
+
–
60.4k RFB
R TB
where VFB is the feedback voltage reference of the regulator,
and VTRACK is 0.6V. Since RTB is equal to the 60.4k top
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then RTA is equal to RFB with VFB =
VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 4.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. RTB can be solved for when SR
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach its final value before the master output.
SLAVE OUTPUT
TIME
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus RTB
is equal to 60.4k. RTA is derived from equation:
4639 F05
Figure 5. Output Voltage Coincident Tracking Characteristics
The TRACK/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator can
be used to develop that master ramp. The LTM4639 can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.2µA current source
is used to charge the soft-start capacitor. The following
equation can be used:
C
t SOFT-START = 0.6V • SS
1.2µA
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin
has a control range from 0V to 0.6V. The master’s
TRACK/SS pin slew rate is directly equal to the master’s
output slew rate in volts/time. The equation:
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB
= 75k. Solve for RTA to equal 51.1k.
For applications that do not require tracking or
sequencing, simply tie the TRACK/SS pin to INTVCC to
let RUN control the turn on/off. When the RUN pin is
below its threshold or the VIN undervoltage lockout, then
TRACK/SS is pulled low.
Overcurrent and Overvoltage Protection
The LTM4639 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current. An
overvoltage condition (OVP) above 10% of the regulated
output voltage will force the top MOSFET off and the bottom
MOSFET on until the condition is cleared. Foldback current
limiting is disabled during soft-start or tracking start-up.
MR
• 60.4k = R TB
SR
4639f
For more information www.linear.com/LTM4639
15
LTM4639
APPLICATIONS INFORMATION
Temperature Monitoring
Measuring the absolute temperature of a diode is possible
due to the relationship between current, voltage and
temperature described by the classic diode equation:
V
ID = IS • e D
η • VT
or
I
VD = η • VT • ln D
IS
where ID is the diode current, VD is the diode voltage, η is
the ideality factor (typically close to 1.0) and IS (saturation
current) is a process dependent parameter. VT can be
broken out to:
VT =
k•T
q
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable
temperature sensors. The IS term in the equation above
is the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The IS term
varies from process to process, varies with temperature,
and by definition must always be less than ID. Combining
all of the constants into one term:
KD =
η•k
q
where KD = 8.62−5, and knowing ln(ID/IS) is always positive
because ID is always greater than IS, leaves us with the
equation that:
I
VD = T(KELVIN) • KD • ln D
IS
where VD appears to increase with temperature. It is
common knowledge that a silicon diode biased with a
current source has an approximate –2mV/°C temperature
relationship (Figure 6), which is at odds with the equation.
In fact, the IS term increases with temperature, reducing the
ln(ID/IS) absolute value yielding an approximate –2mV/°C
composite diode voltage slope.
1.0
DIODE VOLTAGE (V)
ID = 100µA
ID = 10µA
0.8
∆VD
0.6
0.4
–173
–73
27
TEMPERATURE (°C)
127
4639 F06
Figure 6. Diode Voltage VD vs Temperature T(°C)
for Different Bias Currents
4639f
16
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
To obtain a linear voltage proportional to temperature,
we cancel the IS variable in the natural logarithm term to
remove the IS dependency from the following equation.
This is accomplished by measuring the diode voltage at
two currents I1, and I2, where I1 = 10 • I2
Subtracting we get:
∆VD = T(KELVIN) • KD •In
I2
I1
− T(KELVIN) • KD •In
IS
IS
Combining like terms, then simplifying the natural log
terms yields:
∆VD = T(KELVIN) • KD • In(10)
Run Enable
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.25V, and
the pin has an internal 5.1V Zener to protect the pin. The
RUN pin can be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
VUVLO = ((R1+R2)/R2) • 1.25V
See Figure 1, Simplified Block Diagram.
INTVCC Regulator
The LTM4639 has an internal low dropout regulator from
VIN called INTVCC. This regulator output has a 2.2µF
ceramic capacitor internal. An additional 2.2µF ceramic
capacitor is needed on this pin to ground. This regulator
powers the internal controller and MOSFET drivers. The
gate driver current is ~20mA for 750kHz operation. The
regulator loss can be calculated as:
and redefining constant
K’D = KD • In(10) = 198µV/k
yields
∆VD = K’D • T(KELVIN)
Solving for temperature:
(VIN – 5V) • 20mA = PLOSS
∆V
T(KELVIN) = D ,
K'D
T(KELVIN) = [°C]+ 273.15,
[°C] = T(KELVIN)− 273.15
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198µV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
The diode connected PNP transistor at the TEMP+, TEMP–
pins can be used to monitor the internal temperature of
the LTM4639. A general temperature monitor can be
implemented by connecting a resistor between TEMP+
and VIN to set the current to 100µA, grounding the TEMP–
pin, and then monitoring the diode voltage drop with
temperature. A more accurate temperature monitor can
be achieved with a circuit injecting two currents that are
at a 10:1 ratio. See Figure 22 for an example.
Overtemperature Protection
The internal overtemperature protection monitors the
internal temperature of the module and shuts off the
regulator at ~130°C to 137°C. Once the regulator cools
down the regulator will restart.
EXTVCC external voltage source ≥ 4.7V can be applied to
this pin to eliminate the internal INTVCC LDO power loss and
increase regulator efficiency. A 5V supply can be applied
to run the internal circuitry and power MOSFET driver. If
unused, leave pin floating. EXTVCC must be less than VIN
at all times during power-on and power-off sequences.
Stability Compensation
The LTM4639 has already been internally compensated for
all output voltages. Table 5 is provided for most application
requirements. LTpowerCAD is available for other control
loop optimization.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those
parameters defined by JESD51-12 and are intended for use
with finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
in found in JESD51-12 (“Guidelines for Reporting and
Using Electronic Package Thermal Information”).
For more information www.linear.com/LTM4639
4639f
17
LTM4639
APPLICATIONS INFORMATION
Many designers may opt to use laboratory equipment and a
test vehicle such as the demo board to predict the µModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are, in and of themselves, not relevant to providing
guidance of thermal performance; instead, the derating
curves provided in this data sheet can be used in a
manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coefficients
explicitly defined in JESD51-12; these coefficients are
quoted or paraphrased below:
1 θJA, the thermal resistance from junction to ambient,
is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
2 θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through
the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambient environment. As a result, this thermal resistance
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3 θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4 θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the θJCbottom and the thermal resistance of
the bottom of the part through the solder joints and a
portion of the board. The board temperature is measured
a specified distance from the package.
A graphical representation of the aforementioned thermal
resistances is given in Figure 7; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through
bottom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4639, be aware there are multiple power
devices and components dissipating power, with a
consequence that the thermal resistances relative to
different junctions of components or die are not exactly
linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the LTM4639 and the specified PCB with all of
the correct material coefficients along with accurate power
loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
4639f
18
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4639 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields the set of derating curves
shown in this data sheet.
The 1V, 2.5V and 5V power loss curves in Figures 8 to 10
can be used in coordination with the load current derating
curves in Figures 11 to 20 for calculating an approximate
θJA thermal resistance for the LTM4639 with various
heat sinking and airflow conditions. The power loss
curves are taken at room temperature and are increased
with a multiplicative factor according to the junction
temperature, which is 1.4 for 120°C. The derating curves
are plotted with the output current starting at 20A and the
ambient temperature at ~40°C. The output voltages are
1V, 2.5V and 5V. These are chosen to include the lower,
middle and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived
from several temperature measurements in a controlled
temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without airflow.
The power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating
temperature specifies how much module temperature rise
can be allowed, as an example, in Figure 13 the load current
is derated to ~17A at ~80°C with no air or heat sink and
the power loss for the 7V to 1.0V at 17A output is about
4.2W. The 4.2W loss is calculated with the ~3W room
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4639 F07
µMODULE DEVICE
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
4639f
For more information www.linear.com/LTM4639
19
LTM4639
APPLICATIONS INFORMATION
temperature loss from the 7V to 1.0V power loss curve at
17A, and the 1.4 multiplying factor at 120°C junction. If the
80°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 40°C divided
by 4.2W equals a 9.5°C/W θJA thermal resistance. Table
2 specifies a 10°C/W value which is very close. Table 2
through Table 4 provides equivalent thermal resistances
for 1.0V, 2.5V and 5V outputs with and without airflow and
heat sinking. The derived thermal resistances in Tables 2
thru 4 for the various conditions can be multiplied by the
4.0
4.0
3.0
2.5
2.0
3.5
3.0
4.0
2.5
3.5
3.0
2.5
2.0
1.5
1.5
1.5
1.0
1.0
1.0
0.5
0.5
0.5
0
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
0
10 12 14 16 18 20
20
15
10
5
0 LFM
200 LFM
400 LFM
60
40
80
TEMPERATURE (°C)
OUTPUT CURRENT (A)
20
OUTPUT CURRENT (A)
20
10
100
120
4639 F11
Figure 11. 5VIN to 1.0VOUT No Heat Sink
8
10 12 14 16 18 20
Figure 10. 7V Input Power Loss Curves
Figure 9. 5V Input Power Loss Curves
25
15
6
4639 F10
25
20
4
OUTPUT CURRENT (A)
25
0
2
4639 F09
Figure 8. 3.3V Input Power Loss Curves
0
0
OUTPUT CURRENT (A)
4639 F08
5
7V TO 5V POWER LOSS
7V TO 3.3V POWER LOSS
7V TO 2.5V POWER LOSS
7V TO 1.8V POWER LOSS
7V TO 1.5V POWER LOSS
7V TO 1.2V POWER LOSS
7V TO 1V POWER LOSS
4.5
2.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
5.0
5V TO 3.3V POWER LOSS
5V TO 2.5V POWER LOSS
5V TO 1.8V POWER LOSS
5V TO 1.5V POWER LOSS
5V TO 1.2V POWER LOSS
5V TO 1V POWER LOSS
4.5
EFFICIENCY (%)
3.5
POWER LOSS (W)
5.0
3.3V TO 1.8V POWER LOSS
3.3V TO 1.5V POWER LOSS
3.3V TO 1.2V POWER LOSS
3.3V TO 1V POWER LOSS
4.5
EFFICIENCY (%)
5.0
calculated power loss as a function of ambient temperature
to derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick four layer board with
two ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
95mm × 76mm. The BGA heat sinks are listed in Table 6.
0
20
60
40
80 100
TEMPERATURE (°C)
10
5
0 LFM
200 LFM
400 LFM
0
15
120
140
4639 F12
Figure 12. 5VIN to 1.0VOUT with Heat Sink
0
0 LFM
200 LFM
400 LFM
0
20
60
40
80 100
TEMPERATURE (°C)
120
140
4639 F13
Figure 13. 7VIN to 1.0VOUT No Heat Sink
4639f
20
For more information www.linear.com/LTM4639
LTM4639
25
20
20
20
15
10
5
0
20
15
10
5
0 LFM
200 LFM
400 LFM
0
OUTPUT CURRENT (A)
25
OUTPUT CURRENT (A)
25
60
40
80 100
TEMPERATURE (°C)
120
140
0
0
20
60
40
80 100
TEMPERATURE (°C)
120
20
15
10
60
40
80 100
TEMPERATURE (°C)
20
60
40
80 100
TEMPERATURE (°C)
120
10
0
140
0 LFM
200 LFM
400 LFM
0
20
60
40
80 100
TEMPERATURE (°C)
20
20
OUTPUT CURRENT (A)
25
0
0
20
60
40
80 100
TEMPERATURE (°C)
15
10
5
0 LFM
200 LFM
400 LFM
120
140
0
4639 F19
Figure 19. 7VIN to 5VOUT No Heat Sink,
EXTVCC = 5V, CPWR = 7V
140
Figure 18. 7VIN to 2.5VOUT with Heat Sink
25
10
120
4639 F18
Figure 17. 7VIN to 2.5VOUT No Heat Sink
15
140
15
4639 F17
5
120
Figure 16. 5VIN to 2.5VOUT with Heat Sink
5
0 LFM
200 LFM
400 LFM
20
0
4639 F16
Figure 15. 5VIN to 2.5VOUT No Heat Sink
20
0
0 LFM
200 LFM
400 LFM
4639 F15
25
0
0
140
25
5
10
5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 14. 7VIN to 1.0VOUT with Heat Sink
15
0 LFM
200 LFM
400 LFM
4639 F14
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
APPLICATIONS INFORMATION
0 LFM
200 LFM
400 LFM
0
20
60
40
80 100
TEMPERATURE (°C)
120
140
4639 F20
Figure 20. 7VIN to 5VOUT with Heat Sink,
EXTVCC = 5V, CPWR = 7V
4639f
For more information www.linear.com/LTM4639
21
LTM4639
APPLICATIONS INFORMATION
Table 2. 1V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIRFLOW
(LFM)
HEAT SINK
θJA (°C/W)
Figures 11, 13
5V, 7V
Figure 8
0
None
10
Figures 11, 13
5V, 7V
Figure 8
200
None
8
Figures 11, 13
5V, 7V
Figure 8
400
None
7
Figures 12, 14
5V, 7V
Figure 8
0
BGA Heat Sink
9
Figures 12, 14
5V, 7V
Figure 8
200
BGA Heat Sink
6.5
Figures 12, 14
5V, 7V
Figure 8
400
BGA Heat Sink
5.5
Table 3. 2.5V Output
DERATING
CURVE
VIN
POWER LOSS
CURVE
AIRFLOW
(LFM)
HEAT SINK
θJA (°C/W)
Figures 15, 17
5V, 7V
Figure 9
0
None
12
Figures 15, 17
5V, 7V
Figure 9
200
None
11
Figures 15, 17
5V, 7V
Figure 9
400
None
10
Figures 16, 18
5V, 7V
Figure 9
0
BGA Heat Sink
10.5
Figures 16, 18
5V, 7V
Figure 9
200
BGA Heat Sink
9.5
Figures 16, 18
5V, 7V
Figure 9
400
BGA Heat Sink
8
AIRFLOW
(LFM)
HEAT SINK
θJA (°C/W)
Table 4. 5V Output (5V Output Connected to EXTVCC Pin)
DERATING
CURVE
VIN
POWER LOSS
CURVE
Figures 19
7V
Figure 10
0
None
12
Figures 19
7V
Figure 10
200
None
11
Figures 19
7V
Figure 10
400
None
10
Figures 20
7V
Figure 10
0
BGA Heat Sink
10.5
Figures 20
7V
Figure 10
200
BGA Heat Sink
8
Figures 20
7V
Figure 10
400
BGA Heat Sink
7
4639f
22
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
Table 5*. Output Voltage Response vs Component Matrix (Refer to Figure 22). Typical Measured Values
COUT1 AND COUT2
CERAMIC VENDORS
VALUE
PART NUMBER
TDK
22µF, 6.3V
C3216X7S0J226M
Murata
22µF, 10V
GRM31CR61C226KE15L
Murata
47µF, 10V
GRM31CR61A476KE15L
TDK
100µF, 6.3V
C4532X5R0J107MZ
Murata
100µF, 6.3V
GRM32ER60J107M
AVX
100µF, 6.3V
18126D107MAT
COUT1 AND COUT2
BULK VENDORS
VALUE
PART NUMBER
680µF, 2.5V
2R5TPF680M6L
Panasonic
220µF, 4V
EEFCXOG221ER
Sanyo POSCAP
150µF, 10V
10TBF150M
VALUE
PART NUMBER
100µF, 16V
16SVP100M
Sanyo POSCAP
CIN BULK VENDOR
Sanyo
Standard Internal Compensation COMPA and COMPB Tied Together
PEAK-TOPEAK
RECOVERY LOAD
COUT2
(CERAMIC CFF CBOT CCOMPA VIN DROOP DEVIATION
TIME
STEP RFB
VOUT
CIN
CIN
COUT1
(µs)
(A/µs) (kΩ)
(V)
(mV)
(mV)
(V) (CERAMIC) (BULK)* (CERAMIC) AND BULK) (pF) (pF) (pF)
1
22µF × 4
100µF 100µF × 2 680µF × 2 180 22
180 2.5, 3.3, 34
72
34
7.5
90.9
5, 7
1.2 22µF × 4
100µF 100µF × 2 680µF × 2 180 22
180 2.5, 3.3, 37
72
34
7.5
60.4
5, 7
1.5 22µF × 4
100µF 100µF × 2 680µF × 2 180 22
180 2.5, 3.3, 37
80
34
7.5
40.2
5, 7
1.8 22µF × 4
100µF 100µF × 2 680µF × 2 180 22
180 2.5, 3.3, 38
80
34
7.5
30.1
5, 7
2.5 22µF × 4
100µF
47µF
220µF
22
180
3.3,
111
225
24
7.5
19.1
5, 7
3.3 22µF × 4
100µF
22µF
150µF
22
180
5,7
150
300
24
7.5
13.3
5
22µF × 4
100µF
22µF
150µF
22
180
7
187
370
24
7.5
8.25
*Bulk capacitance is optional if VIN has very low input impedance.
Additional Bulk Capacitance may be required for ≤ 3.3V input
Depends on Source Impedance
FREQ (kHz)
TRACK
VIN 2.5V,
3.3V,5V,7V
350, 400,
500, 500
350, 400,
500, 500
350, 400,
500, 500
350, 400,
500, 500
400, 500,
550
500, 550
550
4639f
For more information www.linear.com/LTM4639
23
LTM4639
APPLICATIONS INFORMATION
Table 6*. Output Voltage Response vs Component Matrix (Refer to Figure 22). Typical Measured Values
COUT1 AND COUT2
CERAMIC VENDORS
VALUE
PART NUMBER
Murata
220µF, 4V
GRM31CR60G227M
Murata
47µF, 10V
GRM31CR61A476KE15L
LTpowerCAD Can Be Used to Optimize the Control Loop Response. Examples Are Shown Using Ceramic Only for High Performance
Transient Response
VOUT
CIN
CIN
(V) (CERAMIC) (BULK)*
1
22µF × 4
100µF
COUT2
COUT1 (CER & CFF
(CER) BULK) (pF)
200µF
68
×6
CBOT
(pF)
22
RS
(k)
20
CS
(pF)
1200
CP
(pF)
100
1.2
22µF × 4
100µF
200µF
×6
-
68
22
20
1200
100
1.5
22µF × 4
100µF
200µF
×4
-
68
22
20
1200
100
1.8
22µF × 4
100µF
200µF
×4
-
68
22
20
1200
100
2.5
22µF × 4
100µF
47µF
47
22
4
×2
3.3 22µF × 4
100µF
47µF
47
22
4
×2
5
22µF × 4
100µF
47µF
22
4
×2
*Bulk capacitance is optional if VIN has very low input impedance.
Additional Bulk Capacitance may be required for ≤ 3.3V input
Depends on Source Impedance
4700
47
4700
47
4700
47
PEAK-TOPEAK
REC.
VIN DROOP DEVIATION TIME
(µs)
(V) (mV)
(mV)
2.5,
40
80
24
3.3,
5, 7
2.5,
43
88
24
3.3,
5, 7
2.5,
60
122
24
3.3,
5, 7
2.5,
64
130
28
3.3,
5, 7
3.3,
179
320
33
5, 7
5,7
219
400
33
7
250
500
24
FREQ (kHz)
TRACK
VIN 2.5V,
3.3V,5V,7V
350, 400,
500, 500
LOAD
STEP
(A/µs)
7.5
RFB
(kΩ)
90.9
7.5
60.4
350, 400,
500, 500
7.5
40.2
350, 400,
500, 500
7.5
30.1
350, 400,
500, 500
5
19.1
5
13.3
400, 500,
550
500, 550
5
8.25
550
Table 7. Recommended Heat Sinks
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
AAVID Thermalloy
375424B00034G
www.aavidthermalloy.com
Cool Innovations
4-050503P to 4-050508P
www.coolinnovations.com
4639f
24
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
Safety Considerations
The LTM4639 does not provide galvanic isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled internal
bottom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
LTM4639 does support overvoltage protection, overcurrent
protection and overtemperature protection.
Layout Checklist/Example
The high integration of the LTM4639 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output
capacitors next to the VIN, GND and VOUT pins to
minimize high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Place test points on signal pins for testing.
• Use a separated SGND ground copper area for
components connected to signal pins. Connect the
SGND to GND underneath the unit.
• For parallel modules, tie the COMP and VFB pins
together. Use an internal layer to closely connect these
pins together.
Figure 21 gives a good example of the recommended layout.
CPWR
CONTROL
C1
VIN
CIN
CIN
A1
COMPA COMPB
OT_TEST
CONTROL
PGND
TEMP–
TEMP+
SIGNAL
GROUND
CONTROL
COUT
COUT
VOUT
VOUT
4639 F21
Figure 21. Recommended PCB Layout
4639f
For more information www.linear.com/LTM4639
25
LTM4639
TYPICAL APPLICATIONS
+5V BIAS
VIN
2.375V TO 7V
0.1µF
D+
470pF
D–
VCC
VREF
LTC2997
GND
VPTAT
180pF*
R1
10k
1.8V
C7
0.1µF
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
VOUT
COMPB
V
TRACK/SS
4mV/K
RUN
R3
100k
2.2µF
1µF
CIN
22µF
25V
×4
INTVCC
INTVCC
LTM4639
CFF*
180pF
DIFF_OUT
+
VOSNS
fSET
CONTINUOUS
MODE
+
OUT_LCL
VOSNS–
MODE_PLLIN
VFB
TEMP+
TEMP–
SGND
COUT1*
680µF
2.5V
×2
VOUT
1.5V
COUT2* 20A
100µF
6.3V
×2
GND
OT_TEST
RFB*
40.2k
C30*
22pF
*SEE TABLE 5
4639 F22
Figure 22. 2.375V to 7VIN, 1.5V at 20A Design
4639f
26
For more information www.linear.com/LTM4639
C14
1µF
R1
287k
350kHz
220µF
10V
OUT2
MOD
GND
SET
LTC6908-1
OUT1
V+
INTVCC
+
VIN
2.375V TO 7V
R2
10k
C9
22µF
16V
C10
22µF
16V
C13
0.1µF
For more information www.linear.com/LTM4639
C1
22µF
16V
C2
22µF
16V
75k
180pF
75k
SGND
2.2µF
OT_TEST
VFB
VOSNS–
VOSNS+
DIFF_OUT
VOUT_LCL
VOUT
TEMP
–
TEMP+
SGND
GND
LTM4639
MODE_PLLIN
fSET
RUN
TRACK/SS
COMPB
COMPA
OT_TEST
VFB
VOSNS–
VOSNS
+
DIFF_OUT
VOUT_LCL
VOUT
VIN CPWR EXTVCC INTVCC PGOOD
+5V BIAS
1µF
TEMP
–
TEMP+
GND
LTM4639
MODE_PLLIN
fSET
RUN
TRACK/SS
COMPB
COMPA
VIN CPWR EXTVCC INTVCC PGOOD
INTVCC
2.2µF
Figure 23. 1V at 40A, Two Parallel Outputs with 2-Phase Operation, 350kHz
CLOCK SYNC 180 PHASE
C3
22µF
16V
CLOCK SYNC 0 PHASE
C7
22µF
16V
1µF
+5V BIAS
4639 F23
+
C4
680µF
2.5V
×2
RFB1
45.3k
180pF
C6
100µF
6.3V
×2
22pF
+
C8
680µF
2.5V
×2
C11
100µF
6.3V
×2
1V
40A
LTM4639
TYPICAL APPLICATIONS
4639f
27
LTM4639
TYPICAL APPLICATIONS
2.2µF
VIN
3.3V TO 7V
+5V BIAS
+
C20
22µF
16V
220µF
6.3V
C22
22µF
16V
R1
10k
180pF
INTVCC
COMPA
C28
0.22µF
VOUT
COMPB
TRACK/SS
RUN
VOUT_LCL
VOSNS–
TEMP
4-PHASE CLOCK
SGND
GND
SET
LTC6902
MOD
DIV
GND
PH
OUT1
OUT2
RFB2
15k
OT_TEST
R2
143k
V+
C2
1µF
C14
22µF
16V
C18
22µF
16V
COMPA
VOUT
COMPB
OUT3
TRACK/SS
RUN
350kHz
VOUT_LCL
GND
C8
680µF
2.5V
×2
C11
100µF
6.3V
×2
+
C4
680µF
2.5V
×2
C6
100µF
6.3V
×2
OT_TEST
2.2µF
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
VOUT
COMPB
VOUT_LCL
TRACK/SS
RUN
DIFF_OUT
LTM4639
VOSNS+
fSET
VOSNS–
MODE_PLLIN
75k
VFB
TEMP+
TEMP–
SGND
GND
C1
22µF
16V
OT_TEST
2.2µF
+5V BIAS
C3
22µF
16V
+
VFB
SGND
+5V BIAS
C9
22µF
16V
C18
100µF
6.3V
×2
VOSNS–
TEMP+
TEMP–
C15
680µF
2.5V
×2
VOSNS+
MODE_PLLIN
75k
+
DIFF_OUT
LTM4639
fSET
22µF
25V
22pF
VIN CPWR EXTVCC INTVCC PGOOD
OUT4
C7
22µF
16V
C24
100µF
6.3V
×2
2.2µF
+5V BIAS
22µF
25V
C21
680µF
2.5V
×2
VFB
TEMP+
–
470pF
VOSNS+
MODE_PLLIN
75k
+
DIFF_OUT
LTM4639
fSET
INTVCC
VOUT
1.2V AT 80A
VIN CPWR EXTVCC INTVCC PGOOD
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
VOUT
COMPB
VOUT_LCL
TRACK/SS
RUN
LTM4639
fSET
VFB
TEMP+
TEMP–
VOSNS+
VOSNS–
MODE_PLLIN
75k
DIFF_OUT
SGND
GND
OT_TEST
4639 F24
Figure 24. 1.2V, 80A, Current Sharing with 4-Phase Operation
4639f
28
For more information www.linear.com/LTM4639
LTM4639
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Pin Assignment Table (Arranged by Pin Number)
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
A1
VIN
B1
VIN
C1
VIN
D1
GND
E1
GND
F1
GND
A2
VIN
B2
VIN
C2
VIN
D2
GND
E2
GND
F2
GND
A3
VIN
B3
VIN
C3
VIN
D3
GND
E3
GND
F3
GND
A4
VIN
B4
VIN
C4
VIN
D4
GND
E4
GND
F4
GND
A5
VIN
B5
VIN
C5
VIN
D5
GND
E5
GND
F5
GND
GND
E6
TEMP–
F6
TEMP+
A6
VIN
B6
VIN
C6
VIN
D6
A7
INTVCC
B7
CPWR
C7
GND
D7
–
E7
GND
F7
GND
A8
MODE_PLLIN
B8
–
C8
–
D8
GND
E8
–
F8
GND
A9
TRACK/SS
B9
OT_TEST
C9
GND
D9
INTVCC
E9
GND
F9
GND
A10
RUN
B10
–
C10
MTP2
D10
MTP5
E10
–
F10
–
A11
COMPA
B11
MTP1
C11
MTP3
D11
MTP6
E11
–
F11
PGOOD
A12
COMPB
B12
fSET
C12
MTP4
D12
MTP7
E12
EXTVCC
F12
VFB
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
FUNCTION
G1
GND
H1
GND
J1
VOUT
K1
VOUT
L1
VOUT
M1
VOUT
G2
GND
H2
GND
J2
VOUT
K2
VOUT
L2
VOUT
M2
VOUT
G3
GND
H3
GND
J3
VOUT
K3
VOUT
L3
VOUT
M3
VOUT
G4
GND
H4
GND
J4
VOUT
K4
VOUT
L4
VOUT
M4
VOUT
G5
GND
H5
GND
J5
VOUT
K5
VOUT
L5
VOUT
M5
VOUT
G6
GND
H6
GND
J6
VOUT
K6
VOUT
L6
VOUT
M6
VOUT
G7
GND
H7
GND
J7
VOUT
K7
VOUT
L7
VOUT
M7
VOUT
G8
GND
H8
GND
J8
VOUT
K8
VOUT
L8
VOUT
M8
VOUT
G9
GND
H9
GND
J9
VOUT
K9
VOUT
L9
VOUT
M9
VOUT
G10
–
H10
–
J10
VOUT
K10
VOUT
L10
VOUT
M10
VOUT
G11
SGND
H11
SGND
J11
–
K11
VOUT
L11
VOUT
M11
VOUT
G12
PGOOD
H12
SGND
J12
VOSNS+
K12
DIFF_OUT
L12
VOUT_LCL
M12
VOSNS–
4639f
For more information www.linear.com/LTM4639
29
LTM4639
PACKAGE PHOTO
2.2µF
VIN
7V
22µF
10V
×4
CCOMPA
180pF
5k
0.1µF
VIN CPWR EXTVCC INTVCC PGOOD
COMPA
COMPB
TRACK/SS
RUN
VOUT_LCL
LTM4639
fSET
140k
SGND
VOSNS+
VFB
TEMP+
TEMP
22µF
6.3V
DIFF_OUT
+
150µF
6.3V
VOSNS–
MODE_PLLIN
–
VOUT
5V
20A
VOUT
GND
OT_TEST
RFB
8.25k
CBOT
22pF
4639 F25
Figure 25. 7VIN, 5V at 20A Design
4639f
30
For more information www.linear.com/LTM4639
aaa Z
0.630 ±0.025 Ø 133x
3.1750
3.1750
SUGGESTED PCB LAYOUT
TOP VIEW
1.9050
PACKAGE TOP VIEW
E
0.6350
0.0000
0.6350
4
1.9050
PIN “A1”
CORNER
6.9850
5.7150
4.4450
4.4450
5.7150
6.9850
Y
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
Forofmore
information
www.linear.com/LTM4639
that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
X
D
3.95 – 4.05
aaa Z
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
NOM
4.92
0.60
4.32
0.75
0.63
15.0
15.0
1.27
13.97
13.97
DIMENSIONS
0.15
0.10
0.20
0.30
0.15
MAX
5.12
0.70
4.42
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
A2
TOTAL NUMBER OF BALLS: 133
MIN
4.72
0.50
4.22
0.60
0.60
DETAIL A
b1
0.27 – 0.37
SUBSTRATE
A1
ddd M Z X Y
eee M Z
DETAIL B
MOLD
CAP
ccc Z
Øb (133 PLACES)
// bbb Z
A
(Reference LTC DWG # 05-08-1962 Rev Ø)
Z
(Reference
DWG× #15mm
05-08-1962
Rev Ø)
133-LeadLTC
(15mm
× 4.92mm)
BGA Package
BGA Package
133-Lead (15mm × 15mm × 4.92mm)
e
b
L
K
J
G
G
F
e
E
PACKAGE BOTTOM VIEW
H
D
C
B
A
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
7
TRAY PIN 1
BEVEL
!
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
1
2
3
4
5
6
7
8
9
10
11
12
7
SEE NOTES
PIN 1
BGA 133 1113 REV Ø
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
COMPONENT
PIN “A1”
3
SEE NOTES
F
b
M
DETAIL A
LTM4639
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4639f
31
LTM4639
TYPICAL APPLICATION
1.8V at 20A Design with Input Current and Temperature Monitoring
CIN
22µF
25V
×4
+5V INPUT
R1
5k
10mΩ
MEASURE IIN
CP
100pF
C7
0.1µF
RS
20k
CS
1200pF
COMPA
VOUT
COMPB
VOUT_LCL
TRACK/SS
0.1µF
2-WIRE
I2C
INTERFACE
VIN CPWR EXTVCC INTVCC PGOOD
RUN
VCC V1
SDA
SCL
V2
LTC2990
ADR0
ADR1 GND
R3
125k
CONTINUOUS MODE
fSET
470pF
–
TEMP
SGND
DIFF_OUT
CFF
68pF
VOSNS+
VOSNS–
MODE_PLLIN
VFB
TEMP+
V3
V4
LTM4639
C4
220µF
6.3V
X5R
×6
VOUT
1.8V
AT 20A
GND
OT_TEST
RFB
30.1k
CBOT
22pF
4639 TA02
MEASURE TEMP
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
•
Selector Guides
•
Demo Boards and Gerber Files
•
Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
•
Quick Start Guide
•
PCB Design, Assembly and Manufacturing Guidelines
•
Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4637
Higher VIN Range Than the LTM4639
4.5V ≤ VIN ≤ 20V, 20A
LTM4611
Lower VIN Range Than the LTM4639
1.5V ≤ VIN ≤ 5.5V,15A, Auxiliary VBIAS Not Required
LTM4644
Quad Output, 4A Each
2.375V ≤ VIN ≤ 14V, Low VIN Required Auxiliary VBIAS, Current Share to 16A
LTM4615
Triple Output, 4A, 4A, 1.5A
2.375V ≤ VIN ≤ 5.5V, Auxiliary VBIAS Not Required
LTM4616
Dual Output, 8A Each
2.7V ≤ VIN ≤ 5.5V, Current Share to 16A, Auxiliary VBIAS Not Required
LTM4608A
Lower IOUT and Smaller Package Than the LTM4639
2.7V ≤ VIN ≤ 5.5V, 8A, 9mm × 15mm × 2.8mm
4639f
32 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM4639
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM4639
LT 0914 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014
工商网监
湘ICP备2023018690号
