LTM4671
Quad DC/DC µModule Regulator with
Configurable Dual 12A, Dual 5A Output Array
FEATURES
DESCRIPTION
Quad Output Step-Down µModule® Regulator with
Dual 12A and Dual 5A Output
n Wide Input Voltage Range: 3.1V to 20V
n Dual 12A DC Output from 0.6V to 3.3V
n Dual 5A DC Output from 0.6V to 5.5V
n Up to 7W Power Dissipation (T = 60°C, 200LFM,
A
No Heat Sink)
n ±1.5% Total Output Voltage Regulation
n Dual Differential Sensing Amplifier
n Current Mode Control, Fast Transient Response
n Parallelable for Higher Output Current
n Selectable Burst Mode® Operation
n Output Voltage Tracking
n Internal Temperature Sensing Diode Output
n External Frequency Synchronization
n Overvoltage, Current and Temperature Protection
n 9.5mm × 16mm × 4.72mm BGA Package
The LTM®4671 is a quad DC/DC step-down µModule
(micromodule) regulator offering dual 12A and dual 5A
output. Included in the package are the switching controllers, power FETs, inductors and support components.
Operating over an input voltage range of 3.1V to 20V, the
LTM4671 supports an output voltage range of 0.6V to
3.3V for two 12A channels and 0.6V to 5.5V for two 5A
channels, each set by a single external resistor. Only bulk
input and output capacitors are needed.
APPLICATIONS
* Note 4
n
n
n
Multirail Point-of-Load Regulation
FPGAs, DSPs and ASICs Applications
Fault protection features include overvoltage, overcurrent
and overtemperature protection. The LTM4671 is offered
in 9.5mm × 16mm × 4.72mm BGA package.
Configurable Output Array*
12A
12A
5A
5A
24A
12A
12A
24A
5A
5A
10A
10A
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
4V to 20V Input, 12A, 12A, 5A, 5A DC/DC Step-Down µModule Regulator
CIN
22µF
×2
VIN
VOUT0
VOSNS0+
VOSNS0–
SVIN0
SVIN3
FB0
RUN0
RUN1
RUN2
RUN3
COMP0a
COMP0b
COMP1
COMP2
VOUT1
VOSNS1+
FB1
LTM4671
FB2
COMP3a
COMP3b
0.1μF
0.1μF
0.1μF
19.1k
COUT1
47µF
13.3k
COUT2
47µF
VOUT3
VOSNS3+
VOSNS3–
90.9k
FB3
TRACK/SS0
TRACK/SS1
TRACK/SS2
TRACK/SS3
0.1μF
VOUT2
VOSNS2+
60.4k
TMON
COUT0
100µF ×4
COUT3
100µF ×4
100
VOUT0
1.2V/12A
95
VOUT1
2.5V/5A
VOUT2
3.3V/5A
VOUT3
1.0V/12A
EFFICIENCY (%)
VIN
5V TO 20V
12VIN Efficiency vs Load Current
90
85
80
VOUT = 1.0
VOUT = 1.2
VOUT = 2.5
VOUT = 3.3
75
70
0
2
4
6
8
LOAD CURRENT (A)
10
12
4671 TA01b
GND
4671 TA01a
Rev. B
Document Feedback
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1
LTM4671
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, SVIN0, SVIN3......................................... –0.3V to 22V
VOUT0, VOUT3.............................................. –0.3V to 3.6V
VOUT1, VOUT2................................................. –0.3V to 6V
INTVCC0, INTVCC12, INTVCC3,.................... –0.3V to 3.6V
FREQ0, FREQ12, FREQ3,............................ –0.3V to 3.6V
FB0, FB1, FB2, FB3,.................................... –0.3V to 3.6V
COMP0a, COMP0b, COMP3a, COMP3b,
COMP1, COMP2,.................................... –0.3V to 3.6V
RUN0, RUN1, RUN2, RUN3......................... –0.3V to 22V
TRACK/SS0, TRACK/SS1, TRACK/SS2,
TRACK/SS3,.......................................... –0.3V to 3.6V
PGOOD0, PGOOD1, PGOOD2, PGOOD3,.... –0.3V to 3.6V
VOSNS0+, VOSNS0 –, VOSNS3+,
VOSNS3–,.............................................. –0.3V to 3.6V
VOSNS1, VOSNS2......................................... –0.3V to 6V
TSENSE0+, TSENSE0 –, TSENSE3+,
TSENSE3–.............................................. –0.3V to 0.8V
TMON........................................................ –0.3V to 3.6V
MODE/CLKIN0, CLKOUT0, MODE/CLKIN3,
CLKOUT3, MODE/CLKIN12.................... –0.3V to 3.6V
Operating Junction Temperature (Note 2).–40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Solder Reflow Body Temperature.................. 245°C
PIN CONFIGURATION
(See Pin Functions, Component BGA Pinout Table)
TOP VIEW
TSENSE0– TSENSE0+
A
B
VOUT0
C
D
VIN
PHMODE0 INTVCC0
GND
SVIN0
CLKOUT0 PGOOD0
E
VOSNS0– TRACK/SS0 FREQ0
RUN0
F
GND
GND
MODE/
CLKIN0
TRACK/SS1 VOSNS0+
FB0
PGOOD1
FB1
COMP0a COMP0b
RUN1
GND
VOSNS1 COMP1
GND
G
H
VOUT1
GND
VIN
J
TMON INTVCC12 FREQ12
K
GND
GND
GND
RUN2
MODE/
CLKIN12 VOSNS2
GND
L
VIN
VOUT2
PGOOD2
FB2
GND
COMP2
FB3
VOSNS3+
M
TRACK/
SS2 COMP3b COMP3a
N
GND
GND
CLKOUT3
RUN3
FREQ3
TRACK/
SS3 VOSNS3–
GND
P
MODE/
PHMODE3 PGOOD3 CLKIN3
INTVCC3
SVIN3
R
VIN
T
GND
VOUT3
U
GND
V
GND
TSENSE3+ TSENSE3–
W
1
2
3
4
5
6
7
8
9
10
11
BGA PACKAGE
209-LEAD (9.5mm × 16mm × 4.72mm)
TJMAX = 125°C, θJCTOP = 12.8°C/W, θJCBOTTOM = 1.5°C/W, θJA = 12°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT: 1.94g
Rev. B
2
For more information www.analog.com
LTM4671
ORDER INFORMATION
PART MARKING*
PART NUMBER
LTM4671EY#PBF
LTM4671IY#PBF
PAD OR BALL FINISH
SAC305 (RoHS)
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
e1
BGA
3
LTM4671Y
LTM4671Y
• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
• This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go
to Recommended BGA PCB Assembly and Manufacturing
Procedures.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: (12A Channels)
VIN
Input DC Voltage
VIN(AFTER START-UP) Input DC Voltage After Start-Up
l
3.1
l
20
V
l
2.9
20
V
0.6
3.3
V
l
1.482
1.518
V
VOUT(RANGE)
Output Voltage Range
VOUT(DC)
Output Voltage, Total Variation with
Line and Load
CIN = 22µF, COUT = 100µF Ceramic
RFB = 40.2k, Continuous Current Mode
SVIN = VIN = 3.1V to 20V, IOUT = 0A to 12A
IQ(VIN)
Input Supply Bias Current
SVIN = VIN = 12V, VOUT = 1.5V, Continuous Current Mode
SVIN = VIN = 12V, RUN = 0, Shutdown
75
70
mA
µA
IS(VIN)
Input Supply Current
SVIN = VIN = 12V, VOUT = 1.5V, IOUT = 12A
1.6
A
IOUT(DC)
Output Continuous Current Range
SVIN = VIN = 12V, VOUT = 1.5V (Note 4)
1.50
0
12
A
∆VOUT(LINE)/VOUT
Line Regulation Accuracy
VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A
l
0.001
0.05
%/V
∆VOUT(LOAD)/VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 12A
l
0.2
0.5
%
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic
SVIN = VIN = 12V, VOUT = 1.5V
6
mV
∆VOUT(START)
Turn-On Overshoot
IOUT = 0A, COUT = 100µF Ceramic,
SVIN = VIN = 12V, VOUT = 1.5V
15
mV
tSTART
Turn-On Time
TRACK/SS = 0.01µF,
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
1
ms
∆VOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 25% to 0% of Full Load
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
±50
mV
tSETTLE
Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load
SVIN = VIN = 12V, VOUT = 1.5V, COUT = 3× 100µF Ceramic
50
µs
IOUTPK
Output Current Limit
SVIN = VIN = 12V, VOUT = 1.5V
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.5V
IFB
Current at VFB Pin
(Note 6)
RFB(TOP)
Resistor Between VOUT and VFB Pins
14
l
0.594
A
0.6
0.606
V
±50
nA
60.05 60.40 60.75
kΩ
Rev. B
For more information www.analog.com
3
LTM4671
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VRUN
RUN Pin ON Threshold
VRUN Rising
Hysteresis
1.10
1.20
150
1.30
V
mV
UVLO
Undervoltage Lockout
INTVCC Falling
Hysteresis
2.4
2.55
0.4
2.7
V
V
ITRACK/SS
Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V
6
µA
tON(MIN)
Minimum On-Time
(Note 5)
25
ns
tOFF(MIN)
Minimum Off-Time
(Note 5)
80
ns
VPGOOD
PGOOD Trip Level
VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
RPGOOD
PGOOD Pull-Down Resistance
1mA Load
INTVCC
Internal VCC Voltage
FREQ
Default Switching Frequency
CLKIN_H
CLKIN_H Input High Threshold
CLKIN_H Input Low Threshold
–10
6
3.2
–8
8
–6
10
%
%
8
15
Ω
3.3
3.4
600
1
V
kHz
0.3
V
V
Switching Regulator Section: (5A Channels)
VIN
Input DC Voltage
VIN(AFTER START-UP) Input DC Voltage After Start-Up
VOUT(RANGE)
Output Voltage Range
VOUT(DC)
Output Voltage, Total Variation with
Line and Load
CIN = 22µF, COUT = 100µF Ceramic
RFB = 40.2k, Continuous Current Mode
VIN = 3.1V to 20V, IOUT = 0A to 5A
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, Continuous Current Mode
VIN = 12V, VOUT = 1.5V, Burst Mode Operation (IOUT = 0.5A
VIN = 12V, RUN = 0V, Shutdown
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 1.5V, IOUT = 5A
IOUT(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V (Note 4)
l
3.1
20
V
l
2.9
20
V
l
0.6
l
1.477
1.50
5.5
V
1.523
V
18
82
75
mA
mA
µA
0.7
0
A
5
A
∆VOUT(LINE)/VOUT
Line Regulation Accuracy
VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A
l
0.001
0.05
%/V
∆VOUT(LOAD)/VOUT
Load Regulation Accuracy
VOUT = 1.5V, IOUT = 0A to 5A
l
0.2
0.5
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100µF Ceramic
VIN = 12V, VOUT = 1.5V
8
mV
∆VOUT(START)
Turn-On Overshoot
IOUT = 0A, COUT = 100µF Ceramic,
VIN = 12V, VOUT = 1.5V
15
mV
tSTART
Turn-On Time
TRACK/SS = 0.01µF,
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
5
ms
∆VOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 25% to 0% of Full Load
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
30
mV
tSETTLE
Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load
VIN = 12V, VOUT = 1.5V, COUT = 100µF Ceramic
70
µs
IOUTPK
Output Current Limit
VIN = 12V, VOUT = 1.5V
VFB
Voltage at VFB Pin
IOUT = 0A, VOUT = 1.5V
IFB
Current at VFB Pin
(Note 6)
RFB(TOP)
Resistor Between VOUT and VFB Pins
VRUN
RUN Pin ON Threshold
VRUN Rising
Hysteresis
6
l
0.592
A
0.6
0.608
±30
V
nA
60.05 60.40 60.75
kΩ
1.15
V
mV
1.25
200
1.35
Rev. B
4
For more information www.analog.com
LTM4671
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), SVIN = VIN = 12V, unless otherwise
noted. Per the typical application in Figure 30.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UVLO
Undervoltage Lockout
INTVCC Falling
Hysteresis
2.2
2.4
0.5
2.6
ITRACK/SS
Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V
1.4
µA
tON(MIN)
Minimum On-Time
(Note 5)
20
ns
tOFF(MIN)
Minimum Off-Time
(Note 5)
45
ns
VPGOOD
PGOOD Trip Level
VFB with Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
RPGOOD
PGOOD Pull-Down Resistance
10mA Load
INTVCC
Internal VCC Voltage
FREQ
Default Switching Frequency
MODE/CLKIN_L
MODE/CLKIN_L High Threshold
MODE/CLKIN_L Low Threshold
TMON12
Temperature Monitor
Temperature Monitor Slop
–10
5
–8
8
–5
10
25
3.1
3.3
TA = 25°C
3.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4671 is tested under pulsed load conditions such
that TJ ≈ TA. The LTM4671E is guaranteed to meet performance
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4671I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
%
%
V
MHz
0.3
1.5
200
V
V
Ω
1
1
UNITS
V
V
V
°C/V
Note 3: The minimum on-time is tested at wafer sort.
Note 4: See output current derating curves for different VIN, VOUT and TA.
Note 5: Guaranteed by design.
Note 6: 100% tested at wafer level.
Rev. B
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5
LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Dual 12A Channels
Efficiency vs Load Current
from 3.3VIN
Efficiency vs Load Current
from 5VIN
95
95
90
90
90
85
VOUT = 0.9V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
80
75
70
0
2
4
6
8
LOAD CURRENT (A)
10
85
VOUT = 0.9V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
80
75
12
100
70
0
2
4
6
8
LOAD CURRENT (A)
10
12
EFFICIENCY (%)
95
EFFICIENCY (%)
100
EFFICIENCY (%)
100
Efficiency vs Load Current
from 12VIN
85
VOUT = 0.9V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
80
75
70
0
4
6
8
LOAD CURRENT (A)
4671 G02
4671 G01
1.0V Output Transient Response
1.2V Output Transient Response
VOUT
(AC-COUPLED)
50mV/DIV
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
50μs/DIV
12
1.5V Output Transient Response
VOUT
(AC-COUPLED)
50mV/DIV
4671 G04
10
4671 G03
VOUT
(AC-COUPLED)
50mV/DIV
50μs/DIV
2
50μs/DIV
4671 G05
4671 G06
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
VIN = 12V, VOUT = 1.2V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
VIN = 12V, VOUT = 1.5V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
1.8V Output Transient Response
2.5V Output Transient Response
3.3V Output Transient Response
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
100mV/DIV
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
50μs/DIV
4671 G07
VIN = 12V, VOUT = 1.8V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
50μs/DIV
4671 G08
VIN = 12V, VOUT = 2.5V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
50μs/DIV
4671 G09
VIN = 12V, VOUT = 3.3V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
EXT COMP, CTH = 2200pF, RTH = 5k, CFF = 33pF
3A (25%) LOAD STEP, 1A/μs
Rev. B
6
For more information www.analog.com
LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Dual 12A Channels
Start-Up Waveform with No Load
Current Applied
Start-Up Waveform with 12A Load
Current Applied
RUN
10V/DIV
PGOOD
5V/DIV
RUN
10V/DIV
PGOOD
5V/DIV
LIN
200mA/DIV
LIN
200mA/DIV
VOUT
1V/DIV
VOUT
1V/DIV
2ms/DIV
LIN
500mA/DIV
VOUT
500mV/DIV
2ms/DIV
4671 G10
4671 G11
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 1× 330μF POSCAP,
2× 100μF CERAMIC CAPACITORS
CSS = 0.1μF
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 1× 330μF POSCAP,
2× 100μF CERAMIC CAPACITORS
CSS = 0.1μF
Short-Circuit Waveform with 12A
Load Current Exist
Output Ripple
50μs/DIV
4671 G12
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 1× 330μF POSCAP,
2× 100μF CERAMIC CAPACITORS
Start Into Pre-Biased Output
RUN
10V/DIV
PGOOD
5V/DIV
LIN
500mA/DIV
VOUT
(AC-COUPLED)
10mV/DIV
VOUT
500mV/DIV
Short-Circuit Waveform with No
Load Current Exist
VOUT
1V/DIV
LIN
100mA/DIV
50μs/DIV
1μs/DIV
4671 G13
2ms/DIV
4671 G14
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 3× 100μF CERAMIC CAPACITORS
VIN = 12V, VOUT = 1V, fSW = 600kHz
COUT = 1× 330μF POSCAP,
2× 100μF CERAMIC CAPACITORS
4671 G15
VIN = 12V, VOUT = 1.5V, fSW = 600kHz
COUT = 1× 330μF POSCAP +
2× 100μF CERAMIC CAPACITORS
VOUT = PREBIASED TO 0.9V
Dual 5A Channels
Efficiency vs Load Current
from 5VIN
Efficiency vs Load Current
from 12VIN
100
100
95
95
95
90
90
90
85
80
75
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
70
65
60
0
1
2
3
LOAD CURRENT (A)
4
85
80
75
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
70
65
5
4671 F16
EFFICIENCY (%)
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current
from 3.3VIN
60
0
1
2
3
LOAD CURRENT (A)
4
85
80
75
VOUT = 5.0V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
70
65
5
4671 F17
60
0
1
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
2
3
LOAD CURRENT (A)
4
5
4671 F18
Rev. B
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7
LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
1.0V Output Transient Response
1.2V Output Transient Response
1.5V Output Transient Response
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
50mV/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500mA/DIV
50μs/DIV
50μs/DIV
4671 G19
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
1.8V Output Transient Response
50μs/DIV
4671 G20
VIN = 12V, VOUT = 1.2V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
VIN = 12V, VOUT = 1.5V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
2.5V Output Transient Response
3.3V Output Transient Response
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
50mV/DIV
VOUT
(AC-COUPLED)
100mV/DIV
LOAD STEP
500mA/DIV
LOAD STEP
500A/DIV
LOAD STEP
500A/DIV
50μs/DIV
50μs/DIV
4671 G22
VIN = 12V, VOUT = 1.8V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
5V Output Transient Response
VOUT
(AC-COUPLED)
100mV/DIV
LOAD STEP
500A/DIV
50μs/DIV
4671 G25
VIN = 12V, VOUT = 1.8V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
4671 G21
50μs/DIV
4671 G23
4671 G24
VIN = 12V, VOUT = 2.5V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
1.25A (25%) LOAD STEP, 1A/μs
Start-Up Waveform with No Load
Current Applied
Start-Up Waveform with 5A Load
Current Applied
RUN
10V/DIV
PGOOD
5V/DIV
RUN
10V/DIV
PGOOD
5V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
LIN
200mA/DIV
LIN
200mA/DIV
20ms/DIV
4671 G26
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF, CSS = 0.1μF
20ms/DIV
4671 G27
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF, CSS = 0.1μF
Rev. B
8
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LTM4671
TYPICAL PERFORMANCE CHARACTERISTICS
Short-Circuit Waveform with No
Load Current Exist
Short-Circuit Waveform with 5A
Load Current Exist
LIN
500mA/DIV
LIN
500mA/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
50μs/DIV
50μs/DIV
4671 G28
4671 G29
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
Output Ripple
Start Into Pre-Biased Output
RUN
10V/DIV
PGOOD
5V/DIV
VOUT
2V/DIV
LIN
5mV/DIV
LIN
100mA/DIV
500ns/DIV
2ms/DIV
4671 G30
VIN = 12V, VOUT = 1V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF
4671 G31
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
COUT = 2× 47μF + 10μF CERAMIC CAPACITORS
CFF = 100pF, VOUT PREBIASED 2V
Rev. B
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9
LTM4671
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VIN (D7-D11, E8, H6, J5-J6, L5-L6, M6, R10, T7‑T11):
Power Input. Pins connect to the drain of the internal top
MOSFET and Signal VIN to the internal 3.3V regulator for
the control circuitry for each switching mode regulator
channel. Apply input voltages between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between each of VIN pins and GND pins.
GND (A4-A5, A8-A11, B4-B11, C4-C11, D4-D6, E3-E5,
F1-F7, G1-G6, G10, H5, H7, J7, J9, K1-K7, K11, L7,
L11, M5, M7, M10, N1-N6, P1-P5, P11, R3-R5, T4-T6,
U4-U11, V4-V11, W4-W5, W8-W11): Power Ground Pins
for Both Input and Output Returns. Use large PCB copper
areas to connect all GND together.
PINS FOR DUAL 12A CHANNELS:
VOUT0 (A1-A3, B1-B3, C1-C3, D1-D3, E1-E2), VOUT3
(R1‑R2, T1-T3, U1-U3, V1-V3, W1-W3): Power Output
Pins of Each 12A Switching Mode Regulator Channel.
Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly
between these pins and GND pins. See the Applications
Information section for paralleling outputs.
PGOOD0 (E11), PGOOD3 (R7): Output Power Good with
Open-Drain Logic of Each 12A Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage on
the FB pin is not within ±10% of the internal 0.6V reference.
INTVCC0 (E7), INTVCC3 (R11): Internal 3.3V Regulator
Output of Each 12A Switching Mode Regulator Channel.
The internal power drivers and control circuits are powered from this voltage. Decouple each pin to GND with a
minimum of 2.2µF local low ESR ceramic capacitor.
RUN0 (F11), RUN3 (P7): Run Control Input of Each 12A
Switching Mode Regulator Channel. Enable regulator
operation by tying the specific RUN pin above 1.2V. Tying
it below 1.1V shuts down the specific regulator channel.
COMP0a (H10), COMP3a (N9): Current Control Threshold and Error Amplifier Compensation Point of Each 12A
Switching Mode Regulator Channel. The internal current
comparator threshold is linearly proportional to this voltage.
Tie the COMPa pins from different channels together for
parallel operation. The device is internally compensated.
Connect to COMP0b or COMP3b, respectively, to use the
internal compensation. Or connect to a Type-II C-R-C
network to use customized compensation.
COMP0b (H11), COMP3b (N8): Internal Loop Compensation Network for Each 12A Switching Mode Regulator
Channel. Connect to COMP0a or COMP3a, respectively, to
use the internal compensation in majority of applications.
FB0 (G9), FB3 (N10): The Negative Input of the Error
Amplifier for Each 12A Switching Mode Regulator Channel.
This pin is internally connected to VOSNS0+ or VOSNS3+,
respectively, with a 60.4kΩ precision resistor. Output
voltages can be programmed with an additional resistor
between FB and VOSNS– pins. In PolyPhase® operation,
tying the FB pins together allows for parallel operation.
See the Applications Information section for details.
TRACK/SS0 (F9), TRACK/SS3 (P9): Output Tracking and
Soft-Start Pin of Each 12A Switching Mode Regulator
Channel. Allows the user to control the rise time of the
output voltage. Putting a voltage below 0.6V on this pin
bypasses the internal reference input to the error amplifier, instead it servos the FB pin to the TRACK voltage.
Above 0.6V, the tracking function stops and the internal
reference resumes control of the error amplifier. There’s
an internal 6µA pull-up current from INTVCC on this pin,
so putting a capacitor here provides soft-start function.
See the Applications Information section for details.
Rev. B
10
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LTM4671
PIN FUNCTIONS
FREQ0 (F10), FREQ3 (P8): Switching Frequency Program
Pin of Each 12A Switching Mode Regulator Channel. Frequency is set internally to 600kHz. An external resistor can
be placed from this pin to GND to increase frequency, or
from this pin to INTVCC to reduce frequency. See the Applications Information section for frequency adjustment.
VOSNS0+ (G8), VOSNS3+ (N11): Positive Input to the Dif-
ferential Remote Sense Amplifier of Each 12A Switching
Mode Regulator Channel. Internally, this pin is connected
to VFB with a 60.4k 0.5% precision resistor. See the Applications Information section for details.
VOSNS0– (F8), VOSNS3– (P10): Negative Input to the
Differential Remote Sense Amplifier of Each 12A Switching Mode Regulator Channel. Connect an external resistor
between FB and VOSNS– pin to set the output voltage of
the specific channel. See the Applications Information
section for details.
MODE/CLKIN0 (G11), MODE/CLKIN3 (R8): Discontinuous Mode Select Pin and External Synchronization Input
to Phase Detector of Each 12A Switching Mode Regulator Channel. Tie MODE/CLKIN to GND for discontinuous
mode of operation. Floating MODE/CLKIN or tying it to
a voltage above 1V will select forced continuous mode.
Furthermore, connecting MODE/CLKIN to an external clock
will synchronize the system clock to the external clock and
puts the part in forced continuous mode. See Applications
Information section for details.
CLKOUT0 (E10), CLKOUT3 (P6): Output Clock Signal for
PolyPhase Operation of Each 12A Switching Mode Regulator Channel. The phase of CLKOUT with respect to CLKIN
is determined by the state of the respective PHMODE pin.
CLKOUT’s peak-to-peak amplitude is INTVCC to GND. See
Applications Information section for details.
PHMODE0 (E6), PHMODE3 (R6): Control Input to the
Phase Selector of Each 12A Switching Mode Regulator
Channel. Determines the phase relationship between internal oscillator and CLKOUT. Tie it to INTVCC for 2-phase
operation, tie it to SGND for 3-phase operation, and floating for 4-phase operation. See Applications Information
section for details.
TSENSE0+ (A7), TSENSE3+ (W6): Temperature Monitor
of Each 12A Switching Mode Regulator Channel. An internal diode connected PNP transistor is placed between
TSENSE+ and TSENSE– pins. See the Applications Information section.
TSENSE0– (A6), TSENSE3– (W7): Low Side of the Internal
Temperature Monitor.
SVIN0 (E9), SVIN3 (R9): Signal VIN. Filtered input voltage
to the on-chip 3.3V regulator. Tie this pin to the VIN pin in
most applications or connect SVIN to an external voltage
supply of at least 4V which must also be greater than VOUT.
PINS FOR DUAL 5A CHANNELS:
VOUT1 (H1-H4, J1-J4), VOUT2 (L1-L4, M1-M4): Power
Output Pins of Each 5A Switching Mode Regulator Channel.
Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly
between these pins and GND pins. See the Applications
Information section for paralleling outputs.
PGOOD1 (H8), PGOOD2 (M8): Output Power Good with
Open-Drain Logic of Each 5A Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage on
the FB pin is not within ±10% of the internal 0.6V reference.
INTVCC12 (K9): Internal 3.3V Regulator Output for Both 5A
Switching Mode Regulator Channels. The internal power
drivers and control circuits are powered from this voltage.
Decouple each pin to GND with a minimum of 2.2µF local
low ESR ceramic capacitor.
RUN1 (J8), RUN2 (L8): Run Control Input of Each 5A
Switching Mode Regulator Channel. Enable regulator
operation by tying the specific RUN pin above 1.2V. Tying
it below 1.1V shuts down the specific regulator channel.
COMP1 (J11), COMP2 (M11): Current Control Threshold
and Error Amplifier Compensation Point of Each 5A Switching Mode Regulator Channel. The internal current comparator threshold is linearly proportional to this voltage. Tie the
COMP pins from different channels together for parallel
operation. These channels are internally compensated.
Rev. B
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11
LTM4671
PIN FUNCTIONS
FB1 (H9), FB2 (M9): The Negative Input of the Error
Amplifier for Each 5A Switching Mode Regulator Channel.
This pin is internally connected to VOSNS1 or VOSNS2,
respectively, with a 60.4kΩ precision resistor. Output
voltages can be programmed with an additional resistor
between FB and GND pins. In PolyPhase operation, tying
the FB pins together allows for parallel operation. See the
Applications Information section for details.
TRACK/SS1 (G7), TRACK/SS2 (N7): Output Tracking
and Soft-Start Pin of Each 5A Switching Mode Regulator
Channel. Allows the user to control the rise time of the
output voltage. Putting a voltage below 0.6V on this pin
bypasses the internal reference input to the error amplifier,
instead it servos the FB pin to the TRACK voltage. Above
0.6V, the tracking function stops and the internal reference
resumes control of the error amplifier. There’s an internal
1.4µA pull-up current from INTVCC on this pin, so putting
a capacitor here provides soft-start function. See the Applications Information section for details.
FREQ12 (K10): Switching Frequency Program Pin for Both
5A Switching Mode Regulator Channels. Frequency is
set internally to 1MHz. An external resistor can be placed
from this pin to GND to increase frequency, or from this
pin to INTVCC to reduce frequency. See the Applications
Information section for frequency adjustment.
VOSNS1 (J10), VOSNS2 (L10): Output Voltage Sense Pin
of Each 5A Switching Mode Regulator Channel. Internally,
this pin is connected to VFB with a 60.4k 0.5% precision
resistor. See the Applications Information section for
details. It is very important to connect these pins to the
VOUT since this is the feedback path, and cannot be left
open. See the Applications Information section for details.
MODE/CLKIN12 (L9): Mode Select and External Synchronization Input Pin for Both 5A Switching Mode Regulator
Channels. Tie this pin to GND to force continuous synchronous operation. Floating this pin or tying it to INTVCC12
enables high efficiency Burst Mode operation at light
loads. When driving this pin with an external clock, the
phase-locked loop will force the channel 1 turn on signal
to be synchronized with the rising edge of the CLKIN12
signal. channel 2 will also be synchronized with the rising
edge of the CLKIN12 signal with a 180° phase shift. See
Applications Information section for details.
TMON (K8): Temperature Monitor for 5A Output Channels.
A voltage proportional to the measured on-die temperature
will appear at this pin. The voltage-to-temperature scaling
factor is 200°K/V. See the Applications Information section
for detailed information on the TMON function. Tie this pin
to INTVCC12 to disable the temperature monitor circuit.
Rev. B
12
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LTM4671
BLOCK DIAGRAM
MODE/CLKIN0
PGOOD0
100k
INTVCC0
VIN
CLKOUT0
0.22µF
0.33µH
INTVCC0
2.2µF
0.1µF
47µF
GND
POWER CONTROL
VOSNS0–
RUN0
FB0
COMP0a
15pF
60.4k
FREQ0
PGOOD3
INTERNAL
FILTER
INTERNAL COMP
90.9k
VOSNS0+
COMP0b
100k
INTVCC3
VIN
274k
0.22µF
MODE/CLKIN3
0.33µH
INTVCC3
2.2µF
VOUT3
1.2V
12A
VOUT3
1µF
TRACK/SS3
0.1µF
VOUT0
1.0V
12A
VOUT1
1µF
TRACK/SS0
VIN
4V TO 20V
10µF
47µF
GND
POWER CONTROL
VOSNS3–
RUN3
COMP3a
FB3
15pF
COMP3b
60.4k
INTERNAL
FILTER
INTERNAL COMP
FREQ3
60.4k
VOSNS3+
CLKOUT3
274k
VOSNS2
FB2
VOSNS1
13.3k
60.4k
60.4k
FB1
19.1k
INTVCC12
PGOOD1
10k
PGOOD2
10k
2.2µF
INTVCC12
VIN
MODE/CLKIN12
0.22µF
TRACK/SS1
1µH
0.1µF
VOUT1
TRACK/SS2
0.1µF
INTVCC12
1µF
RUN1
GND
POWER CONTROL
RUN2
47µF
VOUT1
2.5V
5A
COMP1
INTERNAL COMP
0.22µF
COMP2
1µH
INTERNAL COMP
FREQ12
VOUT2
3.3V
5A
VOUT2
1µF
47µF
GND
324k
Figure 1. Simplified LTM4671 Block Diagram
Rev. B
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13
LTM4671
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CIN
External Input Capacitor Requirement
(VIN = 3.1V to 20V, VOUT = 1.5V)
COUT0, COUT3
External Output Capacitor Requirement
(VIN = 3.1V to 20V, VOUT = 1.5V)
COUT1, COUT2
External Output Capacitor Requirement
(VIN = 3.1V to 20V, VOUT = 1.5V)
CONDITIONS
MIN
TYP
MAX
UNITS
44
66
µF
IOUT = 12A
100
200
µF
IOUT = 5A
22
47
µF
OPERATION
The LTM4671 is a quad output standalone non-isolated
switch mode DC/DC power supply. It has built-in four
separate regulator channels which can deliver 12A, 12A,
5A, 5A continuous output current with few external input
and output capacitors. Two 12A regulator provides precisely regulated output voltage programmable from 0.6V
to 3.3V via a single external resistor over 3.1V to 20V
input voltage range while the other two 5A regulator can
support output voltage from 0.6V to 5.5V. Dual true differential remote sensing amplifiers are included in the high
current channels to get accurate regulation at load point.
The typical application schematic is shown in Figure 30.
The LTM4671 has integrated four separate constant ontime valley current mode regulators, power MOSFETs,
inductors, and other supporting discrete components.
For switching noise-sensitive applications, the switching
frequency can be adjusted by external resistors and the
µModule can be externally synchronized to a clock. See
the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4671 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors. For Dual 12A output rails, an optional Type II
C-R-C external compensation network is allowed to customize the stability and transient performance.
Current mode control provides the flexibility of paralleling
any of the separate regulator channels with accurate current sharing. With a build in clock interleaving between
each two regulator channels, the LTM4671 could easily
employ a 2+1+1 or 2+2 channels parallel operation which
is more than flexible in a multirail POL application like
FPGA. Furthermore, the LTM4671 has CLKIN and CLKOUT
pins for frequency synchronization or PolyPhase multiple
devices which allow up to 8 phases of 12A or 5A channels
can be cascaded to run simultaneously.
Current mode control also provides cycle-by-cycle fast current monitoring. An internal overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if the
output feedback voltage exits a ±10% window around the
regulation point. Furthermore, in an overvoltage condition,
internal top FET is turned off and bottom FET is turned on
and held on until the overvoltage condition clears.
Pulling the RUN pin below 0.6V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents,
Burst Mode operation can be enabled to achieve higher
efficiency compared to continuous mode for the dual 5A
channels by setting MODE/PLLIN pin floating or tying
to INTVCC. The TRACK/SS pin is used for power supply
tracking and soft-start programming. See the Applications
Information section.
Three different temperature sensing pins are included inside the module to monitor the temperature of the module
for different channels. See the Applications Information
section for details.
Rev. B
14
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LTM4671
APPLICATIONS INFORMATION
The typical LTM4671 application circuit is shown in Figure
30. External component selection is primarily determined
by the input voltage, the output voltage and the maximum load current. Refer to Table 3 for specific external
capacitor requirements for a particular application.
VIN TO VOUT STEP-DOWN RATIOS
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of each regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
D (MAX ) = 1– t OFF(MIN) • fSW
where tOFF(MIN) is the minimum off-time, 80ns typical for
LTM4671, and fSW is the switching frequency. Conversely,
the minimum on-time limit imposes a minimum duty cycle
of the converter which can be calculated as:
D (MIN) = t ON(MIN) • fSW
where TON(MIN) is the minimum on-time, 25ns typical
for LTM4671. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain in
regulation, but the switching frequency will decrease from
its programmed value. These constraints are shown in
the Typical Performance Characteristic curve labeled “VIN
to VOUT Step-Down Ratio.” Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
OUTPUT VOLTAGE PROGRAMMING
The PWM controller has an internal 0.6V reference voltage.
For the 12A channels (CH0, CH3), a 60.4k 0.5% internal
feedback resistor connects each regulator channel VOSNS+
and FB pin together. Adding a resistor RFB from FB pin to
VOSNS– programs the output voltage.
For the 5A channels (CH1, CH2), a 60.4k 0.5% internal
feedback resistor connects each regulator channel VOSNS
and FB pin together. Adding a resistor RFB from FB pin to
GND programs the output voltage:
VOUT = 0.6V •
60.4k + R FB
For parallel operation of N-channels, tie the VOUT, the FB
pins and VOSNS– pins together but only hooking up one
VOSNS+ (VOSNS) pin to the VOUT so that all the paralleling channels can share the same error amplifier and same
top 60.4k feedback resistor. See PolyPhase Operation for
details.
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT(V)
RFB(k)
0.6
1.0
1.2
1.5
1.8
2.5
3.3
5.0
OPEN
90.9
60.4
40.2
30.1
19.1
13.3
8.25
INPUT DECOUPLING CAPACITORS
The LTM4671 module should be connected to a low ACimpedance DC source. For each 12A regulator channel,
one piece 22µF input ceramic capacitor is required, for
each 5A regulator channel, one piece 10µF input ceramic
capacitor is required for RMS ripple current decoupling.
Bulk input capacitor is only needed when the input source
impedance is compromised by long inductive leads, traces
or not enough source capacitance. The bulk capacitor can be
an electrolytic aluminum capacitor and polymer capacitor.
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
IOUT(MAX )
η%
• D • (1– D)
where η% is the estimated efficiency of the power module.
OUTPUT DECOUPLING CAPACITORS
With an optimized high frequency, high bandwidth design,
only single piece of low ESR output ceramic capacitor is
required for each regulator channel to achieve low output
voltage ripple and very good transient response. Additional
output filtering may be required by the system designer,
if further reduction of output ripples or dynamic transient
spikes is required. Table 3 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 25% load step transient.
Multiphase operation will reduce effective output ripple as
a function of the number of phases. Application Note 77
discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more
R FB
Rev. B
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15
LTM4671
APPLICATIONS INFORMATION
a function of stability and transient response. The Analog
Devices LTpowerCAD® Design Tool is available to download
online for output ripple, stability and transient response
analysis and calculating the output ripple reduction as
the number of phases implemented increases by N times.
FORCED CONTINUOUS CURRENT MODE (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation should
be used. In this mode, inductor current is allowed to reverse
during low output loads, the COMP voltage is in control
of the current comparator threshold throughout, and the
top MOSFET always turns on with each oscillator pulse.
For the 12A channels (CH0, CH3), CCM can be enabled
by tying the MODE/CLKIN0 or MODE/CLKIN3 pin to the
respective INTVCC or simply floating it.
For the 5A channels (CH1, CH2), CCM can be enabled by
tying the MODE/CLKIN12 pin to GND.
During start-up, forced continuous mode is disabled and
inductor current is prevented from reversing until the
LTM4671’s output voltage is in regulation.
DISCONTINUOUS MODE/BURST MODE OPERATION
In applications where high efficiency at intermediate current
is desired, discontinuous mode or Burst Mode operation
can be achieved.
For the 12A channels (CH0, CH3), discontinuous mode
(DCM) can be achieved by tying the MODE/CLKIN0 or
MODE/CLKIN3 pin to GND. In discontinuous mode, the
reverse current comparator will sense the inductor current
and turn of bottom MOSFET when the inductor current
drops to zero and becomes negative. Both power MOSFETs will remain off with the output capacitor supplying
the load current until the COMP voltage rises above its
zero current threshold to initiate the next switching cycle.
For the 5A channels (CH1, CH2), Burst Mode operation
can be achieved by tying MODE/CLKIN12 pin to INTVCC12
or simply floating. In Burst Mode operation, a current
reversal comparator (IREV) detects the negative inductor
current and shuts off the bottom power MOSFET, resulting
in discontinuous operation and increased efficiency. Both
power MOSFETs will remain off until the ITH voltage rises
above the zero current level to initiate another cycle. During
this time, the output capacitor supplies the load current
and the part is placed into a low current sleep mode.
OPERATING FREQUENCY
The operating frequency of the LTM4671 is optimized
to achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
The default operating frequency is internally set to 600kHz
for 12A channels and 1MHz for 5A channels. In most applications, no additional frequency adjusting is required.
For the 12A channels (CH0, CH3), if an operating frequency
other than 600kHz is required by the application, the operating frequency can be increased by adding a resistor,
RFSET, between the FREQ0 or FREQ3 pins and SGND. The
operating frequency can be calculated as:
f (Hz ) =
1.6e 11
274k ||R FSET ( Ω )
The programmable operating frequency range is from
400kHz to 3MHz.
For the 5A channels (CH1, CH2), If an operating frequency
other than 1MHz is required by the application, the operating frequency can be increased by adding a resistor,
RFSET, between the FREQ12 pin and SGND. The operating
frequency can be calculated as:
f (Hz ) =
3.2e 11
324k ||R FSET ( Ω )
The programmable operating frequency range is from
400kHz to 3MHz.
Also the µModule can be externally synchronized to a clock
at ±30% around set operating frequency.
Rev. B
16
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LTM4671
APPLICATIONS INFORMATION
FREQUENCY SYNCHRONIZATION AND CLOCK IN
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
be locked to the rising edge of the same external clock.
The external clock frequency range must be within ±30%
around the set frequency.
MODE/CLKIN0
VOUT0
INTVCC0
PHMODE0
CLKOUT0
180°
24A
MODE/CLKIN3
VOUT3
A pulse detection circuit is used to detect a clock on the
MODE/CLKIN0 pin for CH0 (12A) channel, MODE/CLKIN3
pin for CH3 (12A) channel and MODE/CLKIN12 pin for both
CH1 and CH2 5A channels to turn on the phase-locked loop.
The pulse width of the clock has to be at least 400ns.
The clock high level must be above 1V and clock low
level below 0.3V. During the start-up of the regulator, the
phase-locked loop function is disabled. When the module
is driven with an external clock, forced continuous mode
(CCM) is automatically enabled.
CH0
(0°)
CH3
(180°)
PHMODE3
FLOAT
CLKOUT3
90°
MODE/CLKIN12
VOUT1
CH1
(270°)
180°
10A
VOUT2
CH2
(90°)
LTM4671
MULTICHANNEL PARALLEL OPERATION
4671 F02
For the application that demand more than 12A of output
current, the LTM4671 multiple regulator channels can be
easily paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
For the 12A channels (CH0, CH3), each channel has its
own MODE/CLKIN and CLKOUT pin. The CLKOUT signal
can be connected to the CLKIN pin of the following stage to
line up both frequency and the phase of the entire system.
Tying the PHMODE pin to INTVCC, SGND or floating the pin
generates a phase difference between the clock applied on
the MODE/CLKIN pin and CLKOUT of 180° degrees, 120°
degrees, or 90° degrees respectively, which corresponds
to 2-phase, 3-phase, or 4-phase operation.
For the 5A channels (CH1, CH2), a preset built-in 180°
phase different between channel 1 and channel 2. MODE/
CLKIN12 allows both channels to be synchronized to
an external clock or the CLKOUT signal from any of the
12A channels.
Figure 2 shows a 2 + 2 and a 4-channels parallel concept
schematic for clock phasing.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
Figure 2. 2 + 2 Parallel Concept Schematic
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
The LTM4671 device is an inherently current mode controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Please tie RUN, TRACK/SS, FB and COMP pins
of each paralleling channel together. Figure 31 shows an
example of parallel operation and pin connection.
INPUT RMS RIPPLE CURRENT CANCELLATION
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current
cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved
phases. Figure 3 shows this graph.
Rev. B
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17
LTM4671
APPLICATIONS INFORMATION
0.60
0.55
0.50
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (VOUT/VIN)
4671 F03
Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
The TRACK/SS pin provides a means to either soft-start
of each regulator channel or track it to a different power
supply. A capacitor on the TRACK/SS pin will program the
ramp rate of the output voltage. An internal soft-start current source will charge up the external soft-start capacitor
towards INTVCC voltage. When the TRACK/SS voltage is
below 0.6V, it will take over the internal 0.6V reference
voltage to control the output voltage. The total soft-start
time can be calculated as:
C
SS
t SS = 0.6 • I
SS
where CSS is the capacitance on the TRACK/SS pin and
the ISS is the soft-start current which equals 6µA for the
12A output channels (CH0, CH3) and 1.4µA for the 5A
output channels (CH1, CH2).
Figure 4 and Figure 5 show an example waveform and
schematic of a ratiometric tracking where the slave
regulator’s (VOUT2, VOUT3 and VOUT0) output slew rate is
proportional to the master’s (VOUT1).
VOUT1 = 3.3V
VOUT2 = 2.5V
OUTPUT VOLTAGE
SOFT-START AND OUTPUT VOLTAGE TRACKING
VOUT3 = 1.2V
VOUT0 = 1.0V
TIME
4671 F04
Figure 4. Output Ratiometric Tracking Waveform
Output voltage tracking can also be programmed externally
using the TRACK/SS pin of each regulator channel. The
output can be tracked up and down with another regulator.
Rev. B
18
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LTM4671
APPLICATIONS INFORMATION
RTR(TOP)2
60.4k
LTM4671
VIN0
SVIN0
RUN0
RFB(SL)3
60.4k
TRACK/SS0
VOUT0
FB0
TRACK/SS3
VOUT3
FB3
CH0
1.0V/12A
RFB(SL)2
19.1k
1.2V/12A
RFB1
13.3k
2.5V/5A
CSS
0.1µF
CH3
TRACK/SS2
VOUT2
FB2
TRACK/SS1
CH2
3.3V/5A
VOUT1
FB1
CH1
VIN3
SVIN3
RUN3
RUN2
VIN2
VIN1
RUN1
VIN
4V TO 20V
RFB(SL)0
90.6k
4671 F05
RTR(BOT)2
13.3k
RTR(TOP)3
60.4k
RTR(BOT)3
13.3k
RTR(TOP)0
60.4k
RTR(BOT)0
13.3k
Figure 5. Output Ratiometric Tracking Schematic
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during the start-up.
VOUT(SL ) •
R FB(SL )
R FB(SL ) + 60.4k
= VOUT(MA ) •
R TR(BOT )
R TR(TOP) + R TR(BOT )
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 5.
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in Volts/
Time is determined by:
R FB(SL)
MR
SR
=
R FB(SL) + 60.4k
R TR(BOT)
For example, VOUT(MA) = 3.3V, MR = 3.3V/ms and VOUT(SL) =
1.0V, SR = 1.0V/ms as VOUT1 and VOUT0 from the equation,
we could solve out that RTR(TOP)0 = 60.4k and RTR(BOT)0 =
13.3k is a good combination. Follow the same equation,
we can get the same RTR(TOP)/RTR(BOT) resistor divider
value for VOUT2 and VOUT3.
The TRACK pins will have the 1.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
The coincident output tracking can be recognized as a
special ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), see Figure 6.
R TR(TOP) + R TR(BOT)
Rev. B
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19
LTM4671
APPLICATIONS INFORMATION
reduction, an additional 10pF to 15pF phase boost cap is
required between VOUT and FB pins.
VOUT1 = 3.3V
For specific optimized requirement for the dual 12A channels, disconnect COMPb from COMPa and apply a Type II
C-R-C compensation network from COMPa to SGND to
achieve external compensation.
OUTPUT VOLTAGE
VOUT2 = 2.5V
VOUT3 = 1.2V
VOUT0 = 1.0V
The LTpowerCAD design tool is available to download
online to perform specific control loop optimization and
analyze the control stability and load transient performance.
TIME
4671 F06
Figure 6. Output Coincident Tracking Waveform
R FB(SL)
R FB(SL) + 60.4k
=
R TR(BOT)
R TR(TOP) + R TR(BOT)
From the equation, we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider.
For example, RTR(TOP)3 = 60.4k and RTR(BOT)3 = 60.4k
is a good combination for coincident tracking for
VOUT(MA) = 3.3V and VOUT(SL) =1.2V application.
POWER GOOD
The PGOOD pins are open-drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. A resistor
can be pulled up to a particular supply voltage for monitoring. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4671’s PGOOD
falling edge includes a blanking delay of approximately
52 switching cycles.
RUN ENABLE
Pulling the RUN pin of each regulator channel to ground
forces the regulator into its shutdown state, turning off both
power MOSFETs and most of its internal control circuitry.
Bringing the RUN pin above 0.7V turns on the internal
reference only, while still keeping the power MOSFETs
off. Further increasing the RUN pin voltage above 1.2V
will turn on the entire regulator channel.
TEMPERATURE MONITORING
The 12A Channels (CH0, CH3):
Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage
and temperature described by the classic diode equation:
⎛ V ⎞
ID = IS • e ⎜ D ⎟
⎝ η • VT ⎠
or
STABILITY COMPENSATION
The LTM4671 module internal compensation loop of each
regulator channel is designed and optimized for low ESR
ceramic output capacitors only application (COMPb tied
to COMPa for 12A channels). Table 3 is provided for most
application requirements using the optimized internal
compensation. In case of all ceramic output capacitors
is required for output ripples or dynamic transient spike
I
VD = η • VT •In D
IS
where ID is the diode current, VD is the diode voltage, η
is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can
be broken out to:
VT =
k•T
q
Rev. B
20
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LTM4671
APPLICATIONS INFORMATION
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. VT is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable temperature sensors. The IS term in the previous equation is
the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The IS term
varies from process to process, varies with temperature,
and by definition must always be less than ID. Combining
all of the constants into one term:
KD =
DIODE VOLTAGE (V)
0.5
0.3
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
4671 F07
Figure 7. Diode Voltage VD vs Temperature T(°C)
To obtain a linear voltage proportional to temperature
we cancel the IS variable in the natural logarithm term to
remove the IS dependency from the equation 1. This is
accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2) and subtracting we get:
I
I
∆VD = T(KELVIN) • K D •IN 1 – T(KELVIN) • K D •IN 2
IS
IS
Combining like terms, then simplifying the natural log
terms yields:
∆VD = T(KELVIN) • KD • lN(10)
and redefining constant
198µV
yields
∆VD = K’D • T(KELVIN)
Solving for temperature:
I
VD = T (KELVIN ) • K D •In D
IS
K'D = K D •IN(10) =
0.6
0.4
q
where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current
source has an approximate –2mV/°C temperature relationship (Figure 7), which is at odds with the equation. In
fact, the IS term increases with temperature, reducing the
ln(ID/IS) absolute value yielding an approximate –2mV/°C
composite diode voltage slope.
0.7
η•k
where KD = 8.62−5, and knowing ln(ID/IS) is always positive because ID is always greater than IS, leaves us with
the equation that:
0.8
T(KELVIN) =
∆VD
K'D
(°CELSIUS) = T(KELVIN) – 273.15
where
300°K = 27°C
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
The diode connected NPN transistor across the TSENSEn+
and pin and TSENSEn− pins can be used to monitor the
internal temperature of the LTM4671 channel 0 and 3.
The 5A Channels (CH1, CH2):
The LTM4671 produces a voltage at the TMON pin
proportional to the measured junction temperature. The
junction temperature-to-voltage scaling factor is 200°K/V.
Thus, to obtain the junction temperature in degrees Kelvin,
simply multiply the voltage provided at the TMON pin by
the scaling factor. To obtain the junction temperature in
degrees Celsius, subtract 273 from the value obtained in
degrees Kelvin.
K
Rev. B
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21
LTM4671
APPLICATIONS INFORMATION
1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2.0
1.9
TMON VOLTAGE (V)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
4671 F08
Figure 8. TMON Voltage
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation, and
correlation to hardware evaluation performed on a µModule
package mounted to a hardware test board—also defined
by JESD51-9 (“Test Boards for Area Array Surface Mount
Package Thermal Measurements”). The motivation for
providing these thermal coefficients in found in JESD51-12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their
application at various electrical and environmental operating conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in-and-of themselves not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in the data sheet
can be used in a manner that yields insight and guidance
pertaining to one’s application-usage, and can be adapted
to correlate thermal performance to one’s own application.
2. θJCbottom, the thermal resistance from junction to
ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
4. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
5. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below.
Rev. B
22
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LTM4671
APPLICATIONS INFORMATION
A graphical representation of the aforementioned thermal resistances is given in Figure 9; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal operating conditions of a μModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the
µModule—as the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all of
the correct material coefficients along with accurate power
loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JSED 51-9 to
predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due-diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory tests have been performed and correlated to
the µModule model, then the θJB and θBA are summed
together to correlate quite well with the µModule model
with no airflow or heat sinking in a properly define chamber.
This θJB + θBA value is shown in the Pin Configuration
section and should accurately equal the θJA value because
approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top
mounted heat sink.
JUNCTION-TO-AMBIENT RESISTANCE (JESD51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
4671 F09
µModule DEVICE
Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
Rev. B
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23
LTM4671
APPLICATIONS INFORMATION
The 1V to 5V power loss curves in Figure 10 to Figure
16 can be used in coordination with the load current
derating curves in Figure 17 to Figure 26 for calculating
an approximate θJA thermal resistance for the LTM4671
with various heat sinking and airflow conditions. The
power loss curves are taken at room temperature and
are increased with a multiplicative factor according to
the junction temperature. This approximate factor is 1.3
considering internal junction temperature hitting 120°C at
the point of derating starts. The derating curves are taken
with three different output power combinations, low power
(VOUT0 = VOUT3 = 1V, VOUT1 = VOUT2 = 1.5V), medium
power (VOUT0 = VOUT3 = 1.8V, VOUT1 = VOUT2 = 3.3V) and
high power (VOUT0 = VOUT3 = 3.3V, VOUT1 = VOUT2 = 5V).
Output current starting at 100% of the full load current
(IOUT0 = IOUT3 = 12A, IOUT1 = IOUT2 = 5A) and the ambient
temperature starting at 30°C. These are chosen to include
the lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled temperature chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operating
temperature specifies how much module temperature rise
can be allowed. The printed circuit board for this test is a
1.6mm thick six layers board with two ounce copper for
the two outer layers and one ounce copper for the four
inner layers. The PCB dimensions are 121mm × 112mm.
Figure 27 and Figure 28 display the maximum power loss
allowance curves vs ambient temperature with various
heat sinking and airflow conditions. This data was derived
from the thermal derating curves in Figure 17 to Figure 26
with the junction temperature measured at 120°C. This
maximum power loss limitation serves as a guideline when
designing multiple output rails with different voltages and
currents by calculating the total power loss. For example,
to determine the maximum ambient temperature when
VIN = 12V, VOUT0 = 1V at 10A, VOUT1 = 1.8V at 3A, VOUT2
= 3.3V at 2A, VOUT3 = 1.5V at 10A, without a heat sink
and any airflow, simply add up the total power loss for
each channel read from Figure 10 to Figure 16 which in
this example equals 4.8W (1.6W + 0.7W + 0.6W + 1.9W),
then multiply by the 1.3 coefficient for 120°C junction
temperature and compare the total power loss number,
6.3W with Figure 27. Figure 27 indicates with a 6.3W total
power loss, the maximum ambient temperature for this
application is around 66°C. Also from Figure 27, it is easy
to determine with a 6.3W total power loss, the maximum
ambient temperature is around 73°C with 200LFM airflow
and 77°C with 400LFM airflow.
Rev. B
24
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LTM4671
0
2
4
6
8
LOAD CURRENT (A)
10
12
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
LOAD CURRENT (A)
10
4671 F10
4
6
8
LOAD CURRENT (A)
10
12
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
0
2
4
6
8
LOAD CURRENT (A)
10
4671 F13
12
10
12
10
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
0
2
4
6
8
LOAD CURRENT (A)
10
12
Figure 14. 2.5V Output Power Loss
Figure 15. 3.3V Output Power Loss
120
100
80
60
40
20
0
12
4671 F15
0LFM
200LFM
400LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F16
Figure 16. 5V Output Power Loss
4
6
8
LOAD CURRENT (A)
4671 F14
120
LOAD CURRENT PERCENTAGE (%)
POWER LOSS (W)
Figure 13. 5V Output Power Loss
4.0
3.8 12V , CH1, CH2
IN
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
LOAD CURRENT (A)
2
Figure 12. 1.5V Output Power Loss
POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)
2
0
4671 F12
Figure 11. 1.2V Output Power Loss
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
0
12
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
4671 F11
Figure 10. 1V Output Power Loss
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
POWER LOSS (W)
5VIN, CH1, CH2
12VIN, CH1, CH2
5VIN, CH0, CH3
12VIN, CH0, CH3
LOAD CURRENT PERCENTAGE (%)
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
POWER LOSS (W)
POWER LOSS (W)
APPLICATIONS INFORMATION
4671 F17
Figure 17. 5VIN Derating Curve,
No Heat Sink CH0 and CH3
Paralleled to 1V/24A CH1 and
CH2 Paralleled to 1.5V/10A
100
80
60
40
0LFM
200LFM
400LFM
20
0
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F18
Figure 18. 5VIN Derating Curve,
with Heat Sink CH0 and CH3
Paralleled to 1V/24A CH1 and CH2
Paralleled to 1.5V/10A
Rev. B
For more information www.analog.com
25
LTM4671
APPLICATIONS INFORMATION
120
LOAD CURRENT PERCENTAGE (%)
LOAD CURRENT PERCENTAGE (%)
120
100
80
60
40
0LFM
200LFM
400LFM
20
0
30
40
100
80
60
40
20
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F19
4671 F20
Figure 19. 12VIN Derating Curve, No Heat
Sink CH0 and CH3 Paralleled to 1V/24A
CH1 and CH2 Paralleled to 1.5V/10A
Figure 20. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1V/24A
CH1 and CH2 Paralleled to 1.5V/10A
120
LOAD CURRENT PERCENTAGE (%)
LOAD CURRENT PERCENTAGE (%)
120
100
80
60
40
20
0
0LFM
200LFM
400LFM
30
40
100
80
60
40
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
20
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F21
4671 F22
Figure 21. 5VIN Derating Curve, No Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A
Figure 22. 5VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A
120
LOAD CURRENT PERCENTAGE (%)
LOAD CURRENT PERCENTAGE (%)
120
100
80
60
40
20
0
0LFM
200LFM
400LFM
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
100
80
60
40
20
0
0LFM
200LFM
400LFM
30
4671 F23
Figure 23. 12VIN Derating Curve, No Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A
26
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F24
Figure 24. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 1.8V/24A
CH1 and CH2 Paralleled to 3.3V/10A
For more information www.analog.com
Rev. B
LTM4671
APPLICATIONS INFORMATION
120
LOAD CURRENT PERCENTAGE (%)
LOAD CURRENT PERCENTAGE (%)
120
100
80
60
40
20
0
0LFM
200LFM
400LFM
30
40
100
80
60
40
0
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0LFM
200LFM
400LFM
20
30
40
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F25
4671 F26
Figure 26. 12VIN Derating Curve, with Heat
Sink CH0 and CH3 Paralleled to 3.3V/24A
CH1 and CH2 Paralleled to 5V/10A
12
12
11
11
10
10
9
9
8
8
POWER LOSS (W)
POWER LOSS (W)
Figure 25. 12VIN Derating Curve, No Heat
Sink CH0 and CH3 Paralleled to 3.3V/24A
CH1 and CH2 Paralleled to 5V/10A
7
6
5
4
6
5
4
3
3
2
30
40
0LFM
200LFM
400LFM
2
0LFM
200LFM
400LFM
1
0
7
1
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
0
30
50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
4671 F28
4671 F27
Figure 27. Power Loss Allowance vs
Ambient Temperature No Heat Sink
40
Figure 28. Power Loss Allowance vs
Ambient Temperature with Heat Sink
Rev. B
For more information www.analog.com
27
LTM4671
APPLICATIONS INFORMATION
Table 2. Different Output, Junction-to-Ambient Thermal Resistance (θJA)
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θJA(°C/W)
Figure 27
5, 12
Figure 27
5, 12
Figure 10 to Figure 16
0
None
8.5
Figure 10 to Figure 16
200
None
7
Figure 27
5, 12
Figure 10 to Figure 16
400
None
6.5
Figure 28
5, 12
Figure 10 to Figure 16
0
BGA Heat Sink
8
Figure 28
5, 12
Figure 10 to Figure 16
200
BGA Heat Sink
6
Figure 28
5, 12
Figure 10 to Figure 16
400
BGA Heat Sink
5.5
Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 30) 0A to 4A Load Step Typical Measured Values
CIN (CERAMIC)
COUT (CERAMIC)
PART NUMBER
VENDORS
VALUE
Murata
22μF, 25V, X5R, 1206 GRT31CR61E226ME01L Murata
47μF, 6.3V, X5R, 0805
GRM21BR60J476ME15K Panasonic
Murata
22μF, 25V, X5R, 1210 GRM32ER61E226KE15K Murata
100μF, 6.3V, X5R, 1210
GRM32ER60J107ME20L
Taiyo Yuden
47μF, 6.3V, X5R, 0805
JMK212BBJ476MG-T
Taiyo Yuden
100μF, 6.3V, X5R, 1210
JMK325BJ107MM-T
Taiyo Yuden 22μF, 25V, X5R, 1206 TMK316BBJ226ML-T
VALUE
COUT (BULK)
VENDORS
PART NUMBER
VENDORS
VALUE
PART NUMBER
680μF, 6.3V, 25mΩ 6TPE330ML
CH0 and CH3 Transient Response
COUT2
COUT1
CIN
VOUT (CERAMIC) CIN* (CERAMIC) (BULK)
(μF)
(μF)
(μF)
(BULK)
(V)
1
22 × 2
100
CTH
(pF)
RTH
(kΩ)
CFF
(pF)
VIN
(V)
5, 12
100 × 3
NA
1500
5
33
P-P
DERIVATION RECOVERY
(mV)
TIME (μs)
79.7
30
LOAD
STEP
(A)
LOAD STEP
SLEW RATE
(A/μs)
RFB
(k)
3
10
90.9
1
22 × 2
100
100
330
1000
8
NA
5, 12
76.3
30
3
10
90.9
1.2
22 × 2
100
100 × 3
NA
1500
5
33
5, 12
83.7
30
3
10
60.4
1.2
22 × 2
100
100
330
1000
8
NA
5, 12
80
30
3
10
60.4
1.5
22 × 2
100
100 × 3
NA
1500
5
33
5, 12
90.4
30
3
10
40.2
1.5
22 × 2
100
100
330
1000
8
NA
5, 12
89.7
40
3
10
40.2
1.8
22 × 2
100
100 × 3
NA
1500
5
33
5, 12
103.8
30
3
10
30.1
1.8
22 × 2
100
100
330
1000
8
NA
5, 12
99.1
40
3
10
30.1
2.5
22 × 2
100
100
330
1000
8
NA
5, 12
147.3
50
3
10
19.1
3.3
22 × 2
100
100
330
1000
8
NA
5, 12
203
50
3
10
13.3
CTH
(pF)
RTH
(kΩ)
CFF
(pF)
VIN
(V)
LOAD
STEP
(A)
LOAD STEP
SLEW RATE
(A/μs)
RFB
(k)
CH1 and CH2 Transient Response
COUT2
COUT1
CIN
VOUT (CERAMIC) CIN* (CERAMIC) (BULK)
(μF)
(μF)
(μF)
(BULK)
(V)
P-P
DERIVATION RECOVERY
(mV)
TIME (μs)
1
22
100
47 × 2
NA
Internal Internal
100
5, 12
56.9
50
1.25
10
90.9
1.2
22
100
47 × 2
NA
Internal Internal
100
5, 12
57.8
60
1.25
10
60.4
1.5
22
100
47 × 2
NA
Internal Internal
100
5, 12
62.3
60
1.25
10
40.2
1.8
22
100
47 × 2
NA
Internal Internal
100
5, 12
67.6
70
1.25
10
30.1
2.5
22
100
47 × 2
NA
Internal Internal
100
5, 12
85.7
70
1.25
10
19.1
3.3
22
100
47 × 2
NA
Internal Internal
100
12
115
70
1.25
10
13.3
5
22
100
47 × 2
NA
Internal Internal
100
12
167
70
1.25
10
8.25
*Optional
Rev. B
28
For more information www.analog.com
LTM4671
APPLICATIONS INFORMATION
• Place a dedicated power ground layer underneath
the unit.
SAFETY CONSIDERATIONS
The LTM4671 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection.
•
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to GND underneath the unit.
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4671 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout considerations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN, GND, VOUT1 and VOUT2. It helps to
minimize the PCB conduction loss and thermal stress.
•
For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
•
Bring out test points on the signal pins for monitoring.
Figure 29 gives a good example of the recommended layout.
• Place high frequency ceramic input and output
capacitors next to the VIN, PGND and VOUT pins to
minimize high frequency noise.
GND
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
VOUT2
VOUT1
GND
VOUT0
VOUT3
GND
GND
GND
VIN
4671 F29
Figure 29. Recommended PCB Layout
Rev. B
For more information www.analog.com
29
LTM4671
SVIN0
SVIN3
RUN0
RUN1
RUN2
RUN3
INTVCC0
INTVCC3
INTVC12
VIN1
MODE/CLKIN12
CIN
22µF
×4
MODE/CLKIN3
CLKOUT3
VIN
5V TO 20V
MODE/CLKIN0
CLKOUT0
TYPICAL APPLICATIONS
FB0
VOUT1
VOSNS1+
FB1
COMP0a
COMP0b
COMP1
COMP2
VOUT2
VOSNS2+
LTM4671
FB2
COMP3a
COMP3b
PGOOD0
PGOOD1
PGOOD2
PGOOD3
COUT0
100µF ×4
30.1k
COUT1
47µF ×2
13.3k
COUT2
47µF ×2
COUT3
100µF ×4
VOUT0
0.8V/12A
VOUT1
1.8V/5A
VOUT2
3.3V/5A
VOUT3
1.0V/12A
GND
0.1μF
TMON
0.1μF
FREQ12
FREQ3
FREQ0
0.1μF
182k
VOUT3
VOSNS3+
VOSNS3–
90.9k
FB3
TRACK/SS0
TRACK/SS1
TRACK/SS2
TRACK/SS3
PHMODE3
PHMODE0
0.1μF
VOUT0
VOSNS0+
VOSNS0–
4671 F30
Figure 30. 5V to 20V Input, Quad Output Design
Rev. B
30
For more information www.analog.com
LTM4671
TYPICAL APPLICATIONS
SVIN0
SVIN3
RUN0
RUN1
RUN2
RUN3
INTVCC0
INTVCC3
INTVC12
VIN1
MODE/CLKIN12
CIN
22µF
×4
MODE/CLKIN3
CLKOUT3
VIN
5V TO 20V
MODE/CLKIN0
CLKOUT0
INTVCC0
VOUT0
VOUT3
VOSNS0–
VOSNS3–
COMP1
COMP2
FB0
FB3
LTM4671
13.3k
GND
FB1
FB2
TMON
PGOOD0
PGOOD1
PGOOD2
PGOOD3
FREQ12
FREQ3
FREQ0
0.1μF
VOUT1
3.3V/10A
COUT1
47µF ×4
VOSNS1+
VOSNS2+
TRACK/SS0
TRACK/SS1
TRACK/SS2
TRACK/SS3
PHMODE0
PHMODE3
0.1μF
90.0k
VOUT1
VOUT2
COMP3a
COMP3b
0.1μF
COUT0
100µF ×6
VOSNS0+
VOSNS3+
COMP0a
COMP0b
0.1μF
VOUT0
1.0V/24A
4671 F31
400k
400k
INTVCC0
CH0
Phase Shift
Phase
180°
0°
CH1
CH2
90°
180°
270°
CH3
180°
90°
Figure 31. Parallel Operation with 1MHz Clock and Interleaved Phases
Rev. B
For more information www.analog.com
31
LTM4671
SVIN0
SVIN3
RUN0
RUN1
RUN2
RUN3
INTVCC0
INTVCC3
INTVC12
VIN1
MODE/CLKIN12
CIN
22µF
×4
MODE/CLKIN3
CLKOUT3
VIN
3.3V
MODE/CLKIN0
CLKOUT0
TYPICAL APPLICATIONS
VOUT0
VOSNS0+
VOSNS0–
FB0
VOUT1
VOSNS1+
COMP0a
COMP0b
COMP1
COMP2
FB1
VOUT2
VOSNS2+
LTM4671
FB2
COMP3a
COMP3b
182k
VOUT1
1.8V/5A
30.1k
COUT1
47µF ×2
60.4k
COUT2
47µF ×2
VOUT3
VOSNS3+
VOSNS3–
90.9k
FB3
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
TMON
TRACK/SS0
TRACK/SS1
FREQ12
FREQ3
FREQ0
PHMODE3
PHMODE0
VOUT0
COUT0
0.8V/12A
100µF ×4
VOUT2
1.2V/5A
VOUT3
COUT3
1.0V/12A
100µF ×4
60.4k
0.1µF
60.4k
60.4k
30.1k
30.1k
TRACK/SS2
TRACK/SS3
4671 F32
30.1k
Figure 32. 3.3VIN , 1.8V, 1.2V, 1V, 0.8V with Ratiometric Tracking
Rev. B
32
For more information www.analog.com
LTM4671
COMPONENT BGA PINOUT
PIN ID
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
FUNCTION
VOUT0
VOUT0
VOUT0
GND
GND
TSENSE0–
TSENSE0+
GND
GND
GND
GND
PIN ID
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
FUNCTION
VOUT0
VOUT0
VOUT0
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
FUNCTION
VOUT0
VOUT0
VOUT0
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
FUNCTION
VOUT0
VOUT0
VOUT0
GND
GND
GND
VIN
VIN
VIN
VIN
VIN
PIN ID
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
FUNCTION
VOUT0
VOUT0
GND
GND
GND
PHMODE0
INTVCC0
VIN
SVIN0
CLKOUT0
PGOOD0
PIN ID
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
FUNCTION
GND
GND
GND
GND
GND
GND
GND
VOSNS0–
TRACK/SS0
FREQ0
RUN0
PIN ID
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
FUNCTION
GND
GND
GND
GND
GND
GND
TRACK/SS1
V0SNS0+
FB0
GND
MODE/CLKIN0
PIN ID
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
FUNCTION
VOUT1
VOUT1
VOUT1
VOUT1
GND
VIN
GND
PGOOD1
FB1
COMP0a
COMP0b
PIN ID
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
FUNCTION
VOUT1
VOUT1
VOUT1
VOUT1
VIN
VIN
GND
RUN1
GND
VOSNS1+
COMP1
PIN ID
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
FUNCTION
GND
GND
GND
GND
GND
GND
GND
TMON
INTVCC12
FREQ12
GND
PIN ID
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
FUNCTION
VOUT2
VOUT2
VOUT2
VOUT2
VIN
VIN
GND
RUN2
MODE/CLKIN12
V0SNS2+
GND
PIN ID
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
FUNCTION
VOUT2
VOUT2
VOUT2
VOUT2
GND
VIN
GND
PGOOD2
FB2
GND
COMP2
PIN ID
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
FUNCTION
GND
GND
GND
GND
GND
GND
TRACK/SS2
COMP3b
COMP3a
FB3
V0SNS3+
PIN ID
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
FUNCTION
GND
GND
GND
GND
GND
CLKOUT3
RUN3
FREQ3
TRACK/SS3
V0SNS3–
GND
PIN ID
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
FUNCTION
VOUT3
VOUT3
GND
GND
GND
PHMODE3
PGOOD3
MODE/CLKIN3
SVIN3
VIN
INTVCC3
PIN ID
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
FUNCTION
VOUT3
VOUT3
VOUT3
GND
GND
GND
VIN
VIN
VIN
VIN
VIN
PIN ID
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
FUNCTION
VOUT3
VOUT3
VOUT3
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
FUNCTION
VOUT3
VOUT3
VOUT3
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
FUNCTION
VOUT3
VOUT3
VOUT3
GND
GND
TSENSE3+
TSENSE3–
GND
GND
GND
GND
Rev. B
For more information www.analog.com
33
LTM4671
PACKAGE DESCRIPTION
BGA Package
209-Lead (16mm × 9.50mm × 4.72mm)
(Reference LTC DWG# 05-08-1561 Rev B)
2×
E
A2
X
SEE NOTES
11
10
9
8
7
6
5
4
3
2
PIN 1
A
A1
PIN “A1”
CORNER
7
1
3
Z
Y
SEE NOTES
DETAIL A
A
aaa Z
B
ccc Z
C
4
b
D
E
b1
MOLD
CAP
F
SUBSTRATE
// bbb Z
H2
D
G
H1
H
J
DETAIL B
F
K
L
M
e
Øb (209 PLACES)
N
ddd M Z X Y
eee M Z
P
R
T
U
V
DETAIL A
2×
W
aaa Z
e
DETAIL B
PACKAGE SIDE VIEW
4.00
3.20
G
2.40
1.60
0.80
0.00
0.80
1.60
2.40
3.20
4.00
PACKAGE TOP VIEW
DIMENSIONS
6.40
5.60
4.80
4.00
3.20
2.40
1.60
0.80
0.00
0.80
1.60
2.40
3.20
4.00
4.80
5.60
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
4.53
0.30
4.23
0.45
0.37
NOM
4.72
0.40
4.32
0.50
0.40
16.00
9.50
0.80
14.40
8.00
0.32
4.00
MAX
4.91
0.50
4.41
0.55
0.43
PACKAGE BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
7.20
0.40 ±0.025 Ø 209x
b
NOTES
BALL HT
BALL DIMENSION
PAD DIMENSION
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
BALL DESIGNATION PER JEP95
4
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
5. PRIMARY DATUM -Z- IS SEATING PLANE
6
!
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
SUBSTRATE THK
MOLD CAP HT
0.15
0.20
0.20
0.15
0.08
TOTAL NUMBER OF BALLS: 209
6.40
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
7.20
LTMXXXX
µModule
PACKAGE IN TRAY LOADING ORIENTATION
BGA 209 0218 REV B
SUGGESTED PCB LAYOUT
TOP VIEW
Rev. B
34
For more information www.analog.com
LTM4671
REVISION HISTORY
REV
DATE
DESCRIPTION
A
08/19
Corrected value of Start-Up Waveform graphs from 2ms/DIV to 20ms/DIV
B
01/20
Added text and formula to set operating frequency
Added Temperature Monitering section
Changed MAX Value of Line Regulation Accuracy to 0.05%
PAGE NUMBER
8
16
20, 21, 22
3, 4
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
35
LTM4671
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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For more information www.analog.com
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