MAX3100
LE
AVAILAB
SPI/MICROWIRE-Compatible
UART in QSOP-16
General Description
____________________________Features
The MAX3100 universal asynchronous receiver transmitter (UART) is the first UART specifically optimized for
small microcontroller-based systems. Using an
SPI™/MICROWIRE™ interface for communication with
the host microcontroller (µC), the MAX3100 comes in a
compact 16-pin QSOP. The asynchronous I/O is suitable
for use in RS-232, RS-485, IR, and opto-isolated data
links. IR-link communication is easy with the MAX3100’s
infrared data association (IrDA) timing mode.
The MAX3100 includes a crystal oscillator and a baudrate generator with software-programmable divider ratios
for all common baud rates from 300 baud to 230k baud.
A software- or hardware-invoked shutdown lowers quiescent current to 10µA, while allowing the MAX3100 to
detect receiver activity.
♦ Small TQFN and QSOP Packages Available
♦ Full-Featured UART:
—IrDA SIR Timing Compatible
—8-Word FIFO Minimizes Processor
Overhead at High Data Rates
—Up to 230k Baud with a 3.6864MHz Crystal
—9-Bit Address-Recognition Interrupt
—Receive Activity Interrupt in Shutdown
♦ SPI/MICROWIRE-Compatible µC Interface
♦ Lowest Power:
—150µA Operating Current at 3.3V
—10µA in Shutdown with Receive Interrupt
♦ +2.7V to +5.5V Supply Voltage in Operating Mode
An 8-word-deep first-in/first-out (FIFO) buffer minimizes
processor overhead. This device also includes a flexible
interrupt with four maskable sources, including address
recognition on 9-bit networks. Two hardware-handshaking control lines are included (one input and one output).
The MAX3100 is available in 14-pin plastic DIP and small,
16-pin QSOP packages in the commercial and extended
temperature ranges.
♦ Schmitt-Trigger Inputs for Opto-Couplers
♦ TX and RTS Outputs Sink 25mA for Opto-Couplers
Ordering Information
PART
TEMP RANGE
MAX3100CPD+
0°C to +70°C
14 Plastic DIP
PIN-PACKAGE
16 QSOP
________________________Applications
MAX3100CEE+
0°C to +70°C
Handheld Instruments
Intelligent Instrumentation
MAX3100EPD+
MAX3100EEE+
-40°C to +85°C
-40°C to +85°C
14 Plastic DIP
16 QSOP
UART in SPI Systems
Functional
Diagrams
Small Networks in HVAC
or Building Control
MAX3100ETG+
-40°C to +85°C
24 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
EP = Exposed pad.
Isolated RS-232/RS-485: Directly Drives Opto-Couplers
Low-Cost IR Data Links for Computers/Peripherals
CS 4
IRQ 5
MAX3100
11 RTS
10 CTS
9
X1
GND 7
8
X2
CTS
N.C.
RTS
N.C.
RX
14
13
+
12 N.C.
N.C. 20
11 X1
TX 21
10 X2
MAX3100
VCC 22
9
DIN 23
N.C. 24
*EP
+
1
N.C.
SHDN 6
15
2
3
4
5
6
N.C.
12 RX
16
IRQ
13 TX
SCLK 3
17
CS
DOUT 2
18
N.C. 19
SCLK
14 VCC
DOUT
+
DIN 1
Pin
Pin Configurations
Configurations
N.C.
TOP VIEW
Typical Operating Circuit appears at end of data sheet.
GND
8
SHDN
7
N.C.
DIN 1
16 VCC
DOUT 2
15 TX
SCLK 3
14 RX
CS 4
MAX3100
13 RTS
N.C. 5
12 N.C.
IRQ 6
11 CTS
10 X1
SHDN 7
GND 8
Pin Configurations appearDIP
at end of data sheet.
TQFN-EP
Functional Diagrams continued at end of data sheet.
*EP
=
EXPOSED
PAD,
CONNECT
EP TO GROUND
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI
is a
a trademark
trademark of
of Motorola,
Motorola, Inc.
Inc. MICROWIRE
MICROWIRE is
is a
a trademark
trademark of
of National
National Semiconductor
Semiconductor Corp.
Corp.
SPI is
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
9
X2
QSOP
19-1259; Rev 2; 1/09
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................................+6V
Input Voltage to GND
(CS, SHDN, X1, CTS, RX, DIN, SCLK) ....-0.3V to (VCC + 0.3V)
Output Voltage to GND
(DOUT, RTS, TX, X2) ..............................-0.3V to (VCC + 0.3V)
IRQ...........................................................................-0.3V to 6V
TX, RTS Output Current ....................................................100mA
X2, DOUT, IRQ Short-Circuit Duration
(to VCC or GND) .........................................................Indefinite
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.00mW/°C above +70°C) .......... 800mW
QSOP (derate 8.30mW/°C above +70°C) .....................667mW
TQFN (derate 33.3mW/°C above +70°C) ................2666.7mW
Operating Temperature Ranges
MAX3100C_ _ ......................................................0°C to +70°C
MAX3100E_ _ ...................................................-40°C to +85°C
Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (soldering, 10s) ................................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at 9600 baud at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
VHYST
Input Leakage
IIL
Input Capacitance
CIN
0.7 x VCC
VCC = 3.3V
V
0.3 x VCC
V
±1
µA
0.05 x VCC
V
5
pF
OSCILLATOR INPUT (X1)
Input High Voltage
VIH
0.7 x VCC VCC / 2
Input Low Voltage
VIL
VCC / 2
Input Current
IIN
VX1 = 0V and 5.5V
Input Capacitance
CIN
VX1 = 0V and 5.5V
V
0.2 x VCC
Active mode
25
Shutdown mode
2
5
V
µA
pF
OUTPUTS (DOUT, TX, RTS)
Output High Voltage
VOH
Output Low Voltage
VOL
Output Leakage
ILK
Output Capacitance
ISOURCE = 5mA
VCC - 0.5
ISOURCE = 25µA, TX only
VCC - 0.5
V
TX, RTS: ISINK = 25mA
0.9
DOUT, TX, RTS: ISINK = 4mA
0.4
DOUT only, CS = VCC
±1
COUT
5
V
µA
pF
IRQ OUTPUT (Open Drain)
Output Low Voltage
Output Leakage
Output Capacitance
VOL
ISINK = 4mA
ILK
V IRQ = 5.5V
COUT
0.4
V
±1
µA
5
pF
POWER REQUIREMENTS
2
VCC Supply Current in
Normal Mode
ICC
VCC Supply Current in
Shutdown
ICC
Supply Voltage
VCC
With 1.8432MHz crystal;
all other logic inputs are at
0V or VCC
VCC = 5V
0.27
1
VCC = 3.3V
0.15
0.4
mA
SHDN bit = 1 or SHDN = 0,
logic inputs are at 0V or VCC
2.7
10
µA
5.5
V
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AC TIMING (Figure 1)
CS Low to DOUT Valid
tDV
CLOAD = 100pF
100
ns
CS High to DOUT Tri-State
tTR
CLOAD = 100pF, R CS = 10kΩ
100
ns
CS to SCLK Setup Time
tCSS
100
CS to SCLK Hold Time
tCSH
0
SCLK Fall to DOUT Valid
tDO
ns
ns
CLOAD = 100pF
100
ns
DIN to SCLK Setup Time
tDS
100
ns
DIN to SCLK Hold Time
tDH
0
ns
SCLK Period
tCP
238
ns
SCLK High Time
tCH
100
ns
SCLK Low Time
tCL
100
ns
SCLK Rising Edge
to CS Falling
tCS0
(Note 1)
100
ns
CS Rising Edge
to SCLK Rising
tCS1
(Note 1)
200
ns
CS High Pulse Width
tCSW
200
ns
Output Rise Time
tr
TX, RTS, DOUT: CLOAD = 100pF
10
ns
Output Fall Time
tf
TX, RTS, DOUT, IRQ: CLOAD = 100pF
10
ns
Note 1: tCS0 and tCS1 specify the minimum separation between SCLK rising edges used to write to other devices on the SPI bus
and the CS used to select the MAX3100. A separation greater than tCS0 and tCS1 ensures that the SCLK edge is ignored.
•••
CS
tCSH
tCSS
tCL
SCLK
tCH
tCSH
•••
tDS
tDH
•••
DIN
tDV
DOUT
tDO
tTR
•••
Figure 1. Detailed Serial-Interface Timing
Maxim Integrated
3
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
700
600
500
VCC = 5V
400
300
VCC = 3.3V
200
7
6
5
4
3
0
40
20
60
80
MAX3100-03
200
-20
0
20
40
60
80
0
100
1
2
4
3
5
TEMPERATURE (°C)
EXTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs. BAUD RATE
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = 3.3V)
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = 5V)
300
5V
STANDBY
250
200
3V
TRANSMITTING
100
RTS
TX
40
30
DOUT
20
10
3V
STANDBY
50
10k
BAUD RATE (bps)
100k
1M
80
70
RTS
60
TX
50
DOUT
40
30
20
10
0
0
1000
MAX3100-05
60
50
90
MAX3100-04
70
MAX3100-03a
5V
TRANSMITTING
OUTPUT SINK CURRENT (mA)
1.8432 MHz
CRYSTAL
100
VCC = 3.3V
300
TEMPERATURE (°C)
400
150
400
0
-40
100
VCC = 5V
100
0
-20
500
VCC = 5V
1
-40
SUPPLY CURRENT (μA)
600
8
2
0
4
MAX3100-02
9
100
350
700
OUTPUT SINK CURRENT (mA)
SUPPLY CURRENT (μA)
800
1.8432MHz CRYSTAL
SUPPLY CURRENT (μA)
900
10
MAX3100-01
1.8432MHz CRYSTAL
TRANSMITTING AT
115.2 kbps
SHUTDOWN CURRENT (μA)
1000
SUPPLY CURRENT vs.
EXTERNAL CLOCK FREQUENCY
SHUTDOWN CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOLTAGE (V)
VOLTAGE (V)
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Pin Description
PIN
NAME
FUNCTION
QSOP
DIP
TQFN-EP
1
1
23
DIN
2
2
2
DOUT
SPI/MICROWIRE Serial-Data Output. High impedance when CS is high.
3
3
3
SCLK
SPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input.
4
4
4
CS
Active-Low Chip-Select Input. DOUT goes high impedance when CS is high,
IRQ, TX, and RTS are always active. Schmitt-trigger input.
6
5
5
IRQ
Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.
7
6
8
SHDN
Hardware-Shutdown Input. When shut down (SHDN = 0), the oscillator turns
off immediately without waiting for the current transmission to end, reducing
supply current to just leakage currents.
8
7
9
GND
Ground
9
8
10
X2
Crystal Connection. Leave X2 unconnected for external clock. See CrystalOscillator Operation—X1, X2 Connection section.
10
9
11
X1
Crystal Connection. X1 also serves as an external clock input. See CrystalOscillator Operation—X1, X2 Connection section.
11
10
15
CTS
General-Purpose Active-Low Input. Read via the CTS register bit; often used
for RS-232 clear-to-send input (Table 1).
13
11
16
RTS
General-Purpose Active-Low Output. Controlled by the CTS register bit. Often
used for RS-232 request-to-send output or RS-485 driver enable.
14
12
17
RX
Asynchronous Serial-Data (receiver) Input. The serial information received
from the modem or RS-232/RS-485 receiver. A transition on RX while in
shutdown generates an interrupt (Table 5).
Asynchronous Serial-Data (transmitter) Output
SPI/MICROWIRE Serial-Data Input. Schmitt-trigger input.
15
13
21
TX
16
14
22
VCC
Positive Supply Pin (2.7V to 5.5V)
5, 12
—
1, 6, 7, 12,
13, 14, 18,
19, 20, 24
N.C.
No Connection. Not internally connected.
—
—
—
EP
Exposed Pad. Connect EP to ground or leave unconnected.
Detailed Description
The MAX3100 universal asynchronous receiver transmitter (UART) interfaces the SPI/MICROWIRE-compatible, synchronous serial data from a microprocessor
(µP) to asynchronous, serial-data communication ports
(RS-232, RS-485, IrDA). Figure 2 shows the MAX3100
functional diagram.
The MAX3100 combines a simple UART and a baudrate generator with an SPI interface and an interrupt
generator. Configure the UART by writing a 16-bit word
to a write-configuration register, which contains the
baud rate, data-word length, parity enable, and enable
of the 8-word receive first-in/first-out (FIFO). The write
configuration selects between normal UART timing and
IrDA timing, controls shutdown, and contains 4 interrupt
mask bits.
Maxim Integrated
Transmit data by writing a 16-bit word to a write-data
register, where the last 7 or 8 bits are actual data to be
transmitted. Also included is the state of the transmitted
parity bit (if enabled). This register controls the state of
the RTS output pin. Received words generate an interrupt if the receive-bit interrupt is enabled.
Read data from a 16-bit register that holds the oldest
data from the receive FIFO, the received parity data,
and the logic level at the CTS input pin. This register
also contains a bit that is the framing error in normal
operation and a receive-activity indicator in shutdown.
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B0 to B3 in
the write-configuration register determine the baud-rate
divisor (BRD), which divides down the X1 oscillator frequency. The baud clock is 16 times the data rate (baud
rate).
5
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
9
Pt
TX-BUFFER REGISTER
9
TX-SHIFT REGISTER
D0t–D7t
Pt
TX
SHDN
DIN
CS
SCLK
X1
SPI
INTERFACE
DOUT
B0
B1
B2
B3
XTAL
BAUD-RATE
GENERATOR
RA
ACTIVITY
DETECT
X2
FE START/STOPBIT DETECT
Pr
RX-SHIFT REGISTER
D0r–D7r
RX
9
(SOURCES)
T R Pr RA/FE
(MASKS)
Pr
RX-BUFFER REGISTER
Pr
RX-BUFFER REGISTER
CTS
I/O
TRANSMIT-DONE (TM)
IRQ
INTERRUPT
LOGIC
DATA-RECEIVED (RM)
RTS
9
PARITY (PM)
FRAMING ERROR (RAM)/
RECEIVE ACTIVITY
Figure 2. Functional Diagram
The transmitter section accepts SPI/MICROWIRE data,
formats it, and transmits it in asynchronous serial format
from the TX output. Data is loaded into the transmit-
6
buffer register from the SPI/MICROWIRE interface. The
MAX3100 adds start and stop bits to the data and
clocks the data out at the selected baud rate (Table 7).
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ONE BAUD PERIOD
RX
A
BAUD
BLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MAJORITY
CENTER
SAMPLER
Figure 3. Start-Bit Timing
DATA
UPDATED
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
1
1
FEN
SHDN
TM
RM
PM
RAM
IR
ST
PE
L
B3
B2
B1
B0
DOUT
R
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4. SPI Interface (Write Configuration)
The receiver section receives data in serial form. The
MAX3100 detects a start bit on a high-to-low RX transition (Figure 3). An internal clock samples data at 16
times the data rate. The start bit can occur as much as
one clock cycle before it is detected, as indicated by
the shaded portion. The state of the start bit is defined
as the majority of the 7th, 8th, and 9th sample of the
internal 16x baud clock. Subsequent bits are also
majority sampled. Receive data is stored in an 8-word
FIFO. The FIFO is cleared if it overflows.
The on-board oscillator can use a 1.8432MHz or
3.6864MHz crystal, or it can be driven at X1 with a 45%
to 55% duty-cycle square wave.
Maxim Integrated
SPI Interface
The bit streams for DIN and DOUT consist of 16 bits,
with bits assigned as shown in the MAX3100
Operations section. DOUT transitions on SCLK’s falling
edge, and DIN is latched on SCLK’s rising edge (Figure
4). Most operations, such as the clearing of internal
registers, are executed only on CS’s rising edge. The
DIN stream is monitored for its first two bits to tell the
UART the type of data transfer being executed (Write
Config, Read Config, Write Data, Read Data).
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Every time CS goes low, a new
16-bit stream is expected. An example of a write configuration is shown in Figure 4.
7
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
MAX3100 Operations
MAX3100. The device enters test mode if bit 0 = 1. In
this mode, if CS = 0, the RTS pin acts as the 16x clock
generator’s output. This may be useful for direct baudrate generation (in this mode, TX and RX are in digital
loopback).
Normally, the write-data register loads the TX-buffer
register. To change the RTS pin’s state without writing
data, set the TE bit. Setting the TE bit high inhibits the
write command (Table 3).
Reading data clears the R bit and interrupt IRQ (Table 4).
Write Operations
Table 1 shows write-configuration data. A 16-bit
SPI/MICROWIRE write configuration clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed, the registers are updated when the transmission is over (T = 0).
The write-configuration bits (FEN, SHDNi, IR, ST, PE, L,
B3–B0) take effect after the current transmission is
over. The mask bits (TM, RM, PM, RAM) take effect
immediately after the 16th clock’s rising edge at SCLK.
Register Functions
Table 5 shows read/write operation and power-on reset
state (POR), and describes each bit used in programming the MAX3100. Figure 5 shows parity and wordlength control.
Read Operations
Table 2 shows read-configuration data. This register
reads back the last configuration written to the
Table 1. Write Configuration (D15, D14 = 1, 1)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
1
1
FEN
SHDNi
TM
RM
PM
RAM
IR
ST
PE
L
B3
B2
B1
B0
DOUT
R
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2. Read Configuration (D15, D14 = 0, 1)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TEST
DOUT
R
T
FEN
SHDNo
TM
RM
PM
RAM
IR
ST
PE
L
B3
B2
B1
B0
Table 3. Write Data (D15, D14 = 1, 0)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
1
0
0
0
0
TE
RTS
Pt
D7t
D6t
D5t
D4t
D3t
D2t
D1t
D0t
DOUT
R
T
0
0
0
RA/FE
CTS
Pr
D7r
D6r
D5r
D4r
D3r
D2r
D1r
D0r
Table 4. Read Data (D15, D14 = 0, 0)
8
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DOUT
R
T
0
0
0
RA/FE
CTS
Pr
D7r
D6r
D5r
D4r
D3r
D2r
D1r
D0r
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Table 5. Bit Descriptions
BIT
NAME
READ/
WRITE
POR
STATE
B0–B3
w
0000
Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
B0–B3
r
0000
Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
CTS
r
No
change
D0t–D7t
w
X
D0r–D7r
r
00000000
FEN
w
0
FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled.
FEN
r
0
FIFO-Enable Readback. FEN’s state is read.
IR
w
0
Enables the IrDA timing mode when IR = 1.
IR
r
0
Reads the value of the IR bit.
L
w
0
Bit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1).
L
r
0
Reads the value of the L bit.
Pt
w
X
Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be
useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is
ignored in transmit mode (see the Nine-Bit Networks section).
Pr
r
X
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive
data (see the Nine-Bit Networks section).
w
0
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt
bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to
be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not
calculate parity.
PE
r
0
Reads the value of the Parity-Enable bit.
PM
w
0
Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 6).
PM
r
0
Reads the value of the PM bit (Table 6).
R
r
0
Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the
receive register or FIFO.
RM
w
0
Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 6).
RM
r
0
Reads the value of the RM bit (Table 6).
RAM
w
0
Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 6).
RAM
r
0
Reads the value of the RAM bit (Table 6).
RTS
w
0
Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS
bit = 0 sets the RTS pin = logic high).
PE
Maxim Integrated
DESCRIPTION
Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic
high).
Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.
Eight data bits read from the receive FIFO or the receive register. These will be all 0s when
the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0.
9
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Table 5. Bit Descriptions (continued)
BIT
NAME
RA/FE
READ/
WRITE
r
POR
STATE
DESCRIPTION
0
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a framing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next properly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error can be cleared with a write configuration. The
FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit.
Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1.
Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer
to the Pin Description for hardware shutdown (SHDN input).
Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART
is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T =
1). This tells the processor when it may shut down the RS-232 driver. This bit is also set immediately when the device is shut down through the SHDN pin.
SHDNi
w
0
SHDNo
r
0
ST
w
0
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmitted when ST = 1. The receiver only requires one stop bit.
ST
r
0
Reads the value of the ST bit.
T
r
1
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
TE
w
0
Transmit-Enable Bit. If TE = 1, then only the RTS pin will be updated on CS’s rising edge. The
contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0.
TM
w
0
Mask for T bit. IRQ is asserted if TM = 1 and T = 1 (Table 6).
TM
r
0
Reads the value of the TM bit (Table 6).
PE = 0, L = 0
IDLE
START
IDLE
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
STOP
D2
D3
D4
D5
D6
STOP
STOP
IDLE
D2
D3
D4
D5
D6
D7
Pt
D2
D3
D4
D5
D6
Pt
STOP
IDLE
PE = 0, L = 1
D0
D1
PE = 1, L = 0
IDLE
START
IDLE
START
D0
D1
STOP
STOP
IDLE
PE = 1, L = 1
D0
TIME
D1
STOP
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 5. Parity and Word-Length Control
10
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Interrupt Sources and Masks
A Read Data operation clears the interrupt IRQ. Table
6 gives the details for each interrupt source. Figure 6
shows the functional diagram for the interrupt sources
and mask blocks.
Table 6. Interrupt Sources and Masks—Bit Descriptions
BIT
NAME
MASK
BIT
MEANING
WHEN SET
DESCRIPTION
Pr
PM
Received parity bit = 1
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0), or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value that will be read by a Read Data operation.
R
RM
Data available
The R bit is set when new data is available to be read from the receive register/
FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long
as R = 1 and RM = 1.
RA/FE
T
RAM
Transition on RX when
in shutdown; framing
error when not in
shutdown
Transmit buffer is
empty
TM
This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3100 exits shutdown. IRQ is asserted
when RA is set and RAM = 1.
FE is determined solely by the currently received data, and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character. IRQ is asserted
when FE is set and RAM = 1.
The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted
low if TM = 1 and the transmit buffer becomes empty. This source is cleared on
CS’s rising edge during a Read Data operation. Although the interrupt is cleared,
T may be polled to determine transmit-buffer status.
R
T
Q
S
R
NEW DATA AVAILABLE
DATA READ
RM MASK
S
TRANSMIT BUFFER EMPTY
Q
R
DATA READ
TM MASK
IRQ
N
Pr
Q
S
R
PE = 1 AND RECEIVED PARITY BIT = 1
PE = 0 OR RECEIVED PARITY BIT = 0
PM MASK
RA
FE
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASK
Figure 6. Interrupt Sources and Masks Functional Diagram
Maxim Integrated
11
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Table 7. Baud-Rate Selection Table*
B3
BAUD
B2 B1 B0
DIVISION
RATIO
BAUD
RATE
(fOSC =
1.8432MHz)
BAUD
RATE
(fOSC =
3.6864MHz)
0
0
0
0**
1
115.2k**
230.4k**
0
0
0
1
2
57.6k
115.2k
0
0
1
0
4
28.8k
57.6k
0
0
1
1
8
14.4k
28.8k
0
1
0
0
16
7200
14.4k
0
1
0
1
32
3600
7200
0
1
1
0
64
1800
3600
0
1
1
1
128
900
1800
1
0
0
0
3
38.4k
76.8k
1
0
0
1
6
19.2k
38.4k
Driving Opto-Couplers
1
0
1
0
12
9600
19.2k
1
0
1
1
24
4800
9600
1
1
0
0
48
2400
4800
1
1
0
1
96
1200
2400
1
1
1
0
192
600
1200
1
1
1
1
384
300
600
Figure 7 shows the MAX3100 in an isolated serial interface. The MAX3100 Schmitt-trigger inputs are driven
directly by opto-coupler outputs. Isolated power is provided by the MAX253 transformer driver and linear regulator shown. A significant feature of this application is
that the opto-coupler’s skew does not affect the asynchronous serial output’s timing. Only the set-up and
hold times of the SPI interface need to be met.
*Standard baud rates shown in bold
**Default baud rate
Clock-Oscillator Baud Rates
Bits B0–B3 of the write-configuration register determine
the baud rate. Table 7 shows baud-rate divisors for given
input codes, as well as the given baud rate for
1.8432MHz and 3.6864MHz crystals. Note that the baud
rate = crystal frequency / 16x division ratio.
Shutdown Mode
In shutdown, the oscillator turns off to reduce power
dissipation (ICC < 10µA). The MAX3100 enters shutdown in one of two ways: by a software command
(SHDNi bit = 1) or by a hardware command (SHDN =
logic low). The hardware shutdown is effective immediately and will immediately terminate any transmission in
progress. The software shutdown, requested by setting
SHDNi bit = 1, is entered upon completing the transmission of the data in both the transmit register and the
transmit-buffer register. The SHDNo bit is set when the
MAX3100 enters shutdown (either hardware or software). The microcontroller (µC) can monitor the SHDNo
bit to determine when all data has been transmitted,
and shut down any external circuitry (such as RS-232
transceivers) at that time.
12
Shutdown clears the receive FIFO, R, A, RA/FE,
D0r–D7r, Pr, and Pt registers and sets the T bit high.
Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L,
B0-3, and RTS) can be modified when SHDNo = 1 and
CTS can also be read. Even though RA is reset upon
entering shutdown, it will go high when any transitions
are detected on the RX pin. This allows the UART to
monitor activity on the receiver when in shutdown.
The command to power up (SHDNi = 0) turns on the
oscillator when CS goes high if SHDN pin = logic high,
with a start-up time of about 25ms. This is done through
a write configuration, which clears all registers but RTS
and CTS. Since the crystal oscillator typically requires
25ms to start, the first received characters will be garbled, and a framing error may occur.
__________Applications Information
Figure 8 shows a bidirectional opto-isolated interface
using only two opto-isolators. Over 81% power savings
is realized using IrDA mode due to its 3/16-wide baud
periods.
Crystal-Oscillator Operation—
X1, X2 Connection
The MAX3100 includes a crystal oscillator for baud-rate
generation. For standard baud rates, use a 1.8432MHz
or 3.6864MHz crystal. The 1.8432MHz crystal results in
lower operating current; however, the 3.6864MHz crystal may be more readily available in surface mount.
Ceramic resonators are low-cost alternatives to crystals
and operate similarly, though the “Q” and accuracy are
lower. Some ceramic resonators are available with integral load capacitors, which can further reduce cost.
The tradeoff between crystals and ceramic resonators
is in initial frequency accuracy and temperature drift.
The total error in the baud-rate generator should be
kept below 1% for reliable operation with other systems.
This is accomplished easily with a crystal, and in most
cases can be achieved with ceramic resonators. Table
8 lists the different types of crystals and resonators and
their suppliers.
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ISO
+5V
2kΩ
VCC 6N136
DIN
470Ω
MAX3100
DOUT
ISO
+5V
2kΩ
VCC
MAX3222
6N136
SCLK
TX
RX
470Ω
CTS
SCLK
VCC
RTS
2k
470Ω
6N136
DIN
DOUT
2kΩ
VCC
6N136
CS
470Ω
CS
+5V
MBR0520
MAX667
LINEAR
REGULATOR
ISO
5V
MAX253
TRANSFORMER
DRIVER
HALO
TGM-010P3
Figure 7. Driving Optocouplers
Maxim Integrated
13
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ISO +5V
+5V
2kΩ
VCC
VCC
TX
RX
CS
CS
470Ω
SCLK
DIN
SCLK
MAX3100
MAX3100
DOUT
DIN
DOUT
+5V
2kΩ
RX
TX
GND
470Ω
GND
Figure 8. Bidirectional Opto-Isolated Interface
Table 8. Component and Supplier List
DESCRIPTION
FREQUENCY
(MHz)
TYPICAL
C1, C2 (pF)
SUPPLIER
Through-Hole Crystal
(HC-49/U)
1.8432
25
ECS International, Inc.
ECS-18-13-1
(913) 782-7787
Through-Hole
Resonator
1.8432
47
Murata North America
CSA1.84MG
(800) 831-9172
Through-Hole Crystal
(HC-49/US)
3.6864
33
ECS International, Inc.
ECS-36-18-4
(913) 782-7787
SMT Crystal
3.6864
39
ECS International, Inc.
ECS-36-20-5P
(913) 782-7787
SMT Resonator
3.6864
None
(integral)
AVX/Kyocera
PBRC-3.68B
(803) 448-9411
This oscillator supports parallel-resonant mode crystals
and ceramic resonators, or can be driven from an
external clock source. Internally, the oscillator consists
of an inverting amplifier with its input, X1, tied to its output, X2, by a bias network that self-biases the inverter
at approximately VCC / 2. The external feedback circuit,
usually a crystal, from X2 to X1 provides 180° of phase
shift, causing the circuit to oscillate. As shown in the
standard application circuit, the crystal or resonator is
connected between X1 and X2, with the load capacitance for the crystal being the series combination of C1
and C2. For example, a 1.8432MHz crystal with a spec-
14
PART
NUMBER
PHONE
NUMBER
ified load capacitance of 11pF would use capacitors of
22pF on either side of the crystal to ground. Series-resonant mode crystals have a slight frequency error, typically oscillating 0.03% higher than specified seriesresonant frequency, when operated in parallel mode.
It is very important to keep crystal, resonator, and
load-capacitor leads and traces as short and direct as
possible. The X1 and X2 trace lengths and ground
tracks should be tight, with no other intervening traces.
This helps minimize parasitic capacitance and noise
pickup in the oscillator, and reduces EMI. Minimize
capacitive loading on X2 to minimize supply current.
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
The MAX3100 X1 input can be driven directly by an
external CMOS clock source. The trip level is approximately equal to VCC / 2. No connection should be made
to X2 in this mode. If a TTL or non-CMOS clock source
is used, AC couple with a 10nF capacitor to X1. The
peak-to-peak swing on the input should be at least 2V
for reliable operation.
The parity/9th-bit interrupt is controlled only by the data
in the receive register, and is not affected by data in the
FIFO, so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled,
received nonaddress words can be ignored and not
even read from the UART.
9-Bit Networks
The MAX3100’s IrDA mode can be used to communicate
with other IrDA SIR-compatible devices, or to reduce
power consumption in opto-isolated applications.
In IrDA mode, a bit period is shortened to 3/16 of a
baud period (1.6µs at 115,200 baud) (Figure 9). A data
zero is transmitted as a pulse of light (TX pin = logic
low, RX pin = logic high).
The MAX3100 supports a common multidrop communication technique referred to as 9-bit mode. In this mode,
the parity bit is set to indicate a message that contains a
header with a destination address. The MAX3100 parity
mask can be set to generate interrupts for this condition.
Operating a network in this mode reduces the processing overhead of all nodes by enabling the slave controllers to ignore most message traffic. This can relieve
the remote processor to handle more useful tasks.
STOP
NORMAL UART
TX
START
In 9-bit mode, the MAX3100 is set up with 8 bits plus
parity. The parity bit in all normal messages is clear, but
is set in an address-type message. The MAX3100 parity-interrupt mask is enabled to generate an interrupt on
high parity. When the master sends an address message with the parity bit set, all MAX3100 nodes issue an
interrupt. All nodes then retrieve the received byte to
compare to their assigned address. Once addressed,
the node continues to process each received byte. If the
node was not addressed, it ignores all message traffic
until a new address is sent out by the master.
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
IrDA
TX
0
START
NORMAL
RX
DATA BITS
UART FRAME
Figure 9. IrDA Timing
Maxim Integrated
STOP
IrDA
RX
SIR IrDA Mode
In receive mode, the RX signal’s sampling is done
halfway into the transmission of a high level. The sampling is done once, instead of three times, as in normal
mode. The MAX3100 ignores pulses shorter than
approximately 1/16 of the baud period. The IrDA device
that is communicating with the MAX3100 must be set to
transmit pulses at 3/16 of the baud period. For compatibility with other IrDA devices, set the format to 8-bit
data, one stop, no parity.
IrDA Module
The MAX3100 was optimized for direct optocoupler
drive, whereas IrDA modules contain inverting buffers.
Invert the RX and TX outputs as shown in Figure 10.
8051 Example: IrDA to RS-232 Converter
Figure 10 shows the MAX3100 with an 8051 µC. This
circuit receives IrDA data and outputs standard RS-232
data. Although the 8051 contains an internal UART, it
does not support IrDA or high-speed communications.
The MAX3100 can easily interface to the 8051 to support these high-performance communications modes.
The 8051 does not have an SPI interface, so communication with the MAX3100 is accomplished with port pins
and a short software routine (Figure 12a).
The software routine polls the IRQ output to see if data
is available from the MAX3100 UART. It then shifts the
data out, using the 8051 port pins, and transmits it out
the RS-232 side through the MAX3221 driver. The 8051
simultaneously monitors its internal UART for incoming
communications from the RS-232 side, and transmits
this data out the IrDA side through the MAX3100. The
low-level routine (UTLK) is the core routine that sends
and receives data over the port pins to simulate an SPI
port on the 8051. This technique is useful for any 8051based MAX3100 port-pin-interfaced application.
15
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
DIRECT
OPTO-COUPLER
DRIVE
IR MODULE
DRIVE
OR
+5V
330Ω
MAX3221
IR LED
TX
+5V
100Ω
MAX3100
TXD
TX
8051
1/6 HC00
IR
MODULE
3100
0.1μF
IRQ
RX
1.8432MHz
22pF
RXD
RX
10kΩ
1/6 HC00
22pF
Figure 10. Bidirectional RS-232 IrDA Using an 8051
Interface to PIC Processor
(“Quick Brown Fox” Generator)
Figure 11 illustrates the use of the MAX3100 with the
PIC®. This circuit is a “Quick Brown Fox” generator that
repeatedly transmits “THE QUICK BROWN FOX JUMPS
OVER THE LAZY DOG” (covering the entire alphabet)
over an RS-232 link with adjustable baud rate, word
length, and delay. Although a software-based UART
could be implemented on the PIC, features like accurate variable baud rates, high baud rates, and simple
protocol selection would be difficult to implement reliably. The 16C54 in the example is the most basic of the
PICs. Thus, it is possible to implement the example on
any member of the PIC family.
The software routine (Figure 12) begins by reading the
DIP switch on port RB. The switch data includes 4 bits
for the baud rate, 1 bit for number of stop bits, 1 bit for
a word length of 7 or 8 bits, and 1 bit for delay between
messages. The PIC reads the switch only at initialization (reset), and programs the parameters into the
MAX3100. It then begins sending the message repeatedly. If the delay bit is set, it inserts a 1sec delay
between transmissions. As in the 8051 example, the
main routine is called UTLK, and can be used in any
PIC-based, port-pin-interfaced application.
PIC is a registered trademark of Microchip Corporation.
16
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
VCC
RB7
GO
100kΩ
PIC16C54
RB6
Y/N 1μs Delay
RA0
DIN
MAX3221
100kΩ
MAX3100
1/2 STOP BITS
RB5
RA1
DOUT
RB4
RA2
SCLK
RB3
RA3
CS
TX
TX
100kΩ
7/8 BITS
100kΩ
B3
100kΩ
X1
X2
RB2
B2
100kΩ
1. 8432MHz
22pF
22pF
RB1
B1
100kΩ
RB0
B0
100kΩ
Figure 11. Quick Brown Fox Generator
Maxim Integrated
17
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
__________MAX3100 Synchronous-to-Asynchronous SPI UART at a Glance
Table 9. Synchronous Data Input Format (DIN pin from microprocessor, SPI MOSI)
Bit Number
Operation
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Config
1
1
FEN
SHDNi
TM
RM
PM
RAM
IR
(IrDA)
ST
PE
L
B3
B2
B1
B0
Read
Config
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TEST
Write
Data
1
0
0
0
0
TE
RTS
Pt
D7t
D6t
D5t
D4t
D3t
D2t
D1t
D0t
Read
Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 10. Synchronous Data Output Format (DOUT pin to microprocessor, SPI MISO)
Bit Number
Operation
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Write
Config
R
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read
Config
R
T
FEN
SHDNo
TM
RM
PM
RAM
IR
(IrDA)
ST
PE
L
B3
B2
B1
B0
Write
Data
R
T
0
0
0
RA/
FE
CTS
Pr
D7r
D6r
D5r
D4r
D3r
D2r
D1r
D0r
Read
Data
R
T
0
0
0
RA/
FE
CTS
Pr
D7r
D6r
D5r
D4r
D3r
D2r
D1r
D0r
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Table 11. Bit Definitions*
Register
Bit
Name
Config
FEN
Config
SHDNi
Config
TM
Bit Set (1)
Bit Clear (0)
Disable FIFO
buffer
Enable FIFO
buffer
Shutdown
Operate
Enable transmitdone interrupt
Disable transmitdone interrupt
Register
Bit
Name
Config
L
Write
Data
Bit Set (1)
Bit Clear (0)
Word length =
7 bits
Word length =
8 bits
TE
Inhibit TX output
Enable normal
operation
Write
Data
RTS
Drive RTS output
pin low
Drive RTS output pin high
Write
Data
Pt
Transmit
parity = 1
Transmit
parity = 0
Config
RM
Enable datareceived interrupt
Disable datareceived
interrupt
Config
PM
Enable parity
interrupt
Disable parity
interrupt
Read
Data
RA/FE
Data overrun or
framing error
Normal
Config
RAM
Enable framingerror interrupt
Disable framingerror interrupt
Read
Data
CTS
CTS input pin is
low
CTS input pin is
high
Config
IR
Enable IrDA
timing mode
Standard
timing
All
R
Data has been
received
Data buffer is
empty
Config
ST
Two stop bits
One stop bit
Config
PE
Parity enabled
Parity disabled
All
T
Transmit buffer
is empty
UART is busy
transmitting
*Default setting is clear
Table 13. 1.8432MHz Baud Rates
Table 12. Field Definitions
Register
Field Name
Config
B3–B0
Write Data
D7t–D0t
Read Data
Pr
Read Data
Maxim Integrated
D7r–D0r
B3...B0
BRD
Baud
B3...B0
BRD
Baud
Baud-rate divisor
0 0 0 0
1
115.2k
1 0 0 0
3
38.4k
Transmit data
0 0 0 1
2
56k
1 0 0 1
6
19.2k
Received parity bit
0 0 1 0
4
28k
1 0 1 0
12
9600
Received data
0 0 1 1
8
14k
1 0 1 1
24
4800
0 1 0 0
16
7200
1 1 0 0
48
2400
0 1 0 1
32
3600
1 1 0 1
96
1200
0 1 1 0
64
1800
1 1 1 0
192
600
0 1 1 1
128
900
1 1 1 1
384
300
Meaning
19
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Figure 12a. 8051 IrDA/RS-232 Code
20
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Figure 12b. MAX3100 Using PIC µC
Maxim Integrated
21
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Figure 12b. MAX3100 Using PIC µC (continued)
22
Maxim Integrated
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
___________________________________________________Typical Operating Circuit
μC
MAX3223
MAX3100
SPI/MICROWIRE
RS-232 I/O
DIN
TX
DOUT
RX
SCLK
CTS
CS
RTS
IRQ
C1
C2
___________________Chip Information
PROCESS: BiCMOS
SUBSTRATE CONNECTED TO GND
Maxim Integrated
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
14 Plastic DIP
P14-3
21-0043
16 QSOP
E16-1
21-0055
24 TQFN-EP
T2444-4
21-0139
23
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Revision History
REVISION
NUMBER
REVISION
DATE
1
12/01
Changed pin labeling
2
1/09
Added 24 TQFN information
DESCRIPTION
PAGES
CHANGED
17
1, 2, 5, 24
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
24
© Maxim Integrated
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
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