19-3141; Rev 1; 6/05
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
Features
The MAX8537/MAX8539 controllers provide a complete
power-management solution for both double-data-rate
(DDR) and combiner supplies. The MAX8537 and
MAX8539 are configured for out-of-phase and in-phase
DDR power-supply operations, respectively, and generate three outputs: the main memory voltage (VDDQ), the
tracking sinking/sourcing termination voltage (VTT), and
the termination reference voltage (VTTR). The MAX8538
is configured as a dual out-of-phase controller for pointof-load supplies. Each buck controller can source or
sink up to 25A of current, while the termination reference can supply up to 15mA output.
♦ MAX8537/MAX8539: Complete DDR Supplies
♦ MAX8538: Dual Nontracking Controller
♦ Out-of-Phase (MAX8537/MAX8538) or In-Phase
(MAX8539) Operation
♦ 4.5V to 23V Wide Input Range (Operate Down to
1.8V Input with External 5V Supply)
♦ Tracking Supply Maintains VTT = VTTR = 1/2 VDDQ
♦ Adjustable Output from 0.8V to 3.6V with 1%
Accuracy
The MAX8537/MAX8538/MAX8539 use constantfrequency voltage-mode architecture with operating
frequencies of 200kHz to 1.4MHz. An internal highbandwidth (25MHz) operational amplifier is used as an
error amplifier to regulate the output voltage. This
allows fast transient response, reducing the number of
output capacitors. An all-N-FET design optimizes efficiency and cost. The MAX8537/MAX8538/MAX8539
have a 1% accurate reference. The second synchronous buck controller in the MAX8537/MAX8539 and the
VTTR amplifier generate 1/2 VDDQ voltage for VTT and
VTTR, and track the VDDQ within ±1%.
This family of controllers uses a high-side current-sense
architecture for current limiting. ILIM pins allow the setting of an adjustable, lossless current limit for different
combinations of load current and RDSON. Alternately,
more accurate overcurrent limit is achieved by using
a sense resistor in series with the high-side FET.
Overvoltage protection is achieved by latching off the
high-side MOSFET and latching on the low-side MOSFET
when the output voltage exceeds 17% of its set output.
Independent enable, power-good, and soft-start features
enhance flexibility.
♦ VTTR Reference Sources and Sinks Up to 15mA
♦ 200kHz to 1.4MHz Adjustable Switching
Frequency
♦ All-Ceramic Design Achievable
♦ >90% Efficiency
♦ Independent POK_ and EN_
♦ Adjustable Soft-Start and Soft-Stop for Each
Output
♦ Lossless Adjustable-Hiccup Current Limit
♦ Output Overvoltage Protection
♦ 28-Pin QSOP Package
Ordering Information
PART
TEMP RANGE
PINPACKAGE
OPERATION
MAX8537EEI
-40°C to +85°C
28 QSOP
Out-of-phase
tracking
MAX8537EEI+
-40°C to +85°C
28 QSOP
Out-of-phase
tracking
MAX8538EEI
-40°C to +85°C
28 QSOP
Out-of-phase
nontracking
DDR Memory Power Supplies
Notebooks and Desknotes
Servers and Storage Systems
Broadband Routers
XDSL Modems and Routers
MAX8538EEI+
-40°C to +85°C
28 QSOP
Out-of-phase
nontracking
MAX8539EEI
-40°C to +85°C
28 QSOP
In-phase
tracking
MAX8539EEI+
-40°C to +85°C
28 QSOP
In-phase
tracking
Power DSP Core Supplies
Power Combiner in Advanced VGA Cards
Networking Systems
RAMBUS Memory Power Supplies
+Denotes lead-free package.
Applications
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8537/MAX8538/MAX8539
General Description
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +25V
AVL, VL to GND........................................................-0.3V to +6V
PGND to GND .......................................................-0.3V to +0.3V
FB_, EN_, POK_ to GND...........................................-0.3V to +6V
REFIN, VTTR, FREQ, SS_, COMP_ to GND....-0.3V to (AVL + 0.3V)
BST_, ILIM_ to GND ...............................................-0.3V to +30V
DH1 to LX1 ...............................................-0.3V to (BST1 + 0.3V)
DH2 to LX2 ...............................................-0.3V to (BST2 + 0.3V)
LX_ to BST_ ..............................................................-6V to +0.3V
LX_ to GND................................................................-2V to +25V
DL_ to PGND ................................................-0.3V to (VL + 0.3V)
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ..........................……+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN_ = VL, BST_ = 6V, LX_ = 1V, VL load = 0mA, CVL = 10µF (ceramic), REFIN = 1.25V, PGND = AGND = FB_ = ILIM_ =
0V, CSS = 10nF, CVTTR = 1µF, RFREQ = 20kΩ, DH_ = open, DL_ = open, POK_ = open, circuit of Figure 1, TA = 0°C to +85°C, unless
otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
23.0
V
GENERAL
V+ Operating Range
VL regulator drops out below 5.5V (Note 1)
4.5
V+/ VL Operating Range
VL is externally generated (Note 1)
4.5
5.5
V
V+ Operating Supply Current
IL(VL) = 0, FB_ forced 50mV above threshold
3.5
7
mA
V+ Standby Supply Current
IL(VL) = 0, BST_ = VL, EN = LX_ = FB_ = 0V
350
700
µA
VL REGULATOR
Output Voltage
5.5V < V+ < 23V, 1mA < ILOAD < 70mA
4.75
5
5.25
V
VL Undervoltage-Lockout Trip
Level
Rising edge, hysteresis = 550mV (typ) (trip level is
typically 85% of VL)
4.18
4.3
4.42
V
Output Current
This is for gate current of DL_ /DH_ drivers, C(VL) =
1µF/10mA ceramic capacitor
70
mA
Thermal Shutdown
Rising temperature, typical hysteresis = 10°C
+160
°C
CURRENT-LIMIT THRESHOLD (all current limits are tested at V+ = VL = 4.5V and 5.5V)
ILIM Sink Current
ILIM_ = LX - 200mV, 1.8V < LX < 23V, BST = LX +5V
180
200
220
µA
SOFT-START
Soft-Start Source Current
SS_ = 100mV
-7
-5
-3
µA
Soft-Start Sink Current
SS_ = 0.8 or REFIN
3
5
7
µA
0.8 or
REFIN
Soft-Start Full-Scale Voltage
V
FREQUENCY
Low End of Range
RFREQ = 100kΩ, V+ = VL = 5V
160
200
240
kHz
Intermediate Range
RFREQ = 20kΩ, V+ = VL = 5V
800
1000
1200
kHz
High End of Range
RFREQ = 14.3kΩ, V+ = VL = 5V
1120
1400
1680
kHz
Maximum Duty Cycle
2
RFREQ = 100kΩ
95
RFREQ = 20kΩ
80
RFREQ = 14.3kΩ
72
_______________________________________________________________________________________
%
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
(V+ = 12V, EN_ = VL, BST_ = 6V, LX_ = 1V, VL load = 0mA, CVL = 10µF (ceramic), REFIN = 1.25V, PGND = AGND = FB_ = ILIM_ =
0V, CSS = 10nF, CVTTR = 1µF, RFREQ = 20kΩ, DH_ = open, DL_ = open, POK_ = open, circuit of Figure 1, TA = 0°C to +85°C, unless
otherwise noted.)
PARAMETER
Minimum Duty Cycle
TYP
MAX
RFREQ = 100kΩ
CONDITIONS
MIN
2.4
4
RFREQ = 20kΩ
12
18
16
25
DH_ Minimum Off-Time
RFREQ = 14.3kΩ
140
200
DH_ Minimum On-Time
120
UNITS
%
ns
ns
ERROR AMPLIFIER
FB_ Input Bias Current
VFB_ = 0.8V
250
nA
FB1 Input-Voltage Set Point
Over line and load
0.792
0.800
0.808
V
MAX8538
0.792
0.800
0.808
MAX8537/MAX8539, REFIN = 0.9V
0.894
0.900
0.906
72
>80
dB
Op-Amp Gain Bandwidth
25
MHz
Op-Amp Output-Voltage Slew
Rate
15
V/µs
Break-Before-Make Time
30
ns
DH1, DH2 On-Resistance in Low
State
0.9
2.5
Ω
DH1, DH2 On-Resistance in High
State
1.3
2.5
Ω
DL1, DL2 On-Resistance in Low
State
0.7
1.5
Ω
DL1, DL2 On-Resistance in High
State
1.6
2.8
Ω
0.8
V
FB2 Input-Voltage Set Point
Op-Amp Open-Loop Voltage
Gain
COMP_ = 1.3V to 2.3V
V
DRIVERS
LOGIC INPUTS (EN_)
Input Low Level
4.5V < VL < 5.5V
Input High Level
4.5V < VL < 5.5V
2.4
Input Bias Current
0V to 5.5V
-1
VTTR Output Voltage Range
Source or sink 15mA
0.5
VTTR Output Accuracy
-15mA ≤ IVTTR ≤ +15mA, REFIN = 0.9V or 1.25V
-1.0
REFIN = 0.9V or 1.25V
-250
V
+0.1
+1
µA
2.5
V
+1.0
%
+250
nA
VTTR
REFIN
REFIN
REFIN Input Bias Current
_______________________________________________________________________________________
3
MAX8537/MAX8538/MAX8539
ELECTRICAL CHARACTERISTICS (continued)
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, EN_ = VL, BST_ = 6V, LX_ = 1V, VL load = 0mA, CVL = 10µF (ceramic), REFIN = 1.25V, PGND = AGND = FB_ = ILIM_ =
0V, CSS = 10nF, CVTTR = 1µF, RFREQ = 20kΩ, DH_ = open, DL_ = open, POK_ = open, circuit of Figure 1, TA = 0°C to +85°C, unless
otherwise noted.)
PARAMETER
CONDITIONS
REFIN Input Voltage Range
REFIN Undervoltage-Lockout Trip
Level
MIN
TYP
0.5
Rising and falling edge, hysteresis = 15mV
MAX
UNITS
2.5
V
0.4
0.45
0.5
V
OUTPUT-VOLTAGE FAULT COMPARATORS
Upper FB2 Fault Threshold
Rising voltage, hysteresis = 15mV
115
117
120
% of
REFIN
Lower FB2 Fault Threshold
Falling voltage, hysteresis = 15mV
68
70
72
% of
REFIN
Upper FB1 Fault Threshold
Rising voltage, hysteresis = 15mV
115
117
120
% of
0.8V
Lower FB1 Fault Threshold
Falling voltage, hysteresis = 15mV
68
70
72
% of
0.8V
POWER-OK OUTPUT (POK_)
POK_ Delay
Clock
cycles
64
Upper FB2 POK_ Threshold
Rising voltage, hysteresis = 20mV
110
112
114
% of
REFIN
Lower FB2 POK_ Threshold
Falling voltage, hysteresis = 20mV
86
88
90
% of
REFIN
Upper FB1 POK_ Threshold
Rising voltage, hysteresis = 20mV
110
112
114
% of
0.8V
Lower FB1 POK_ Threshold
Falling voltage, hysteresis = 20mV
86
88
90
% of
0.8V
POK_ Output Low Level
ISINK = 2mA
0.4
V
POK_ Output High Leakage
POK_ = 5.5V
1
µA
ELECTRICAL CHARACTERISTICS (Note 2)
(V+ = 12V, EN_ = VL, BST_ = 6V, LX_ = 1V, VL load = 0mA, CVL = 10µF (ceramic), REFIN = 1.25V, PGND = AGND = FB_ = ILIM_ =
0V, CSS = 10nF, CVTTR = 1µF, RFREQ = 20kΩ, DH_ = open, DL_ = open, POK_ = open, circuit of Figure 1, TA = -40°C to +85°C,
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V+ Operating Range
VL regulator drops out below 5.5V (Note 1)
4.75
23.00
V
FB_ Input-Voltage Set Point
Over line and load
0.788
0.800
0.812
V
FB2 Input-Voltage Set Point
MAX8537/MAX8539, REFIN = 0.9V
0.891
0.900
0.909
V
VTTR Output Accuracy
-15mA < IVTTR ≤ +15mA, REFIN = 0.9V or 1.25V
-1
REFIN
+1
%
Note 1: Operating supply range is guaranteed by the VL line-regulation test. User must short V+ to VL if a fixed 5V supply is used
(i.e., if V+ is less than 5.5V).
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
4
_______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
VDDQ = 1.8V
75
70
80
2.51
VDDQ = 1.8V
75
70
65
60
60
55
55
2.49
2.47
50
100
10
2.45
1
LOAD CURRENT (A)
MAX8537 toc04
1.30
1.28
1.27
1.26
1.26
VTTR
1.27
1.25
1.25
1.24
1.24
1.23
1.23
1.22
1.22
1.21
1.21
1.20
OUTPUT VOLTAGE (V)
1.28
1.20
0
3
6
9
12
15
0
LOAD CURRENT (A)
5
10
15
20
25
20
VDDQ
IOUT_VDDQ = 20A
IOUT_VTT = 12A
IOUT_VTTR = 15mA
VTT AND VTTR
14
13
STARTUP AND SHUTDOWN
MAX8537 toc08
V+
VIN
5V/div
VDDQ
1V/div
VDDQ
VTT
8.5V/div
VTTR
8.5V/div VTT
15
INPUT VOLTAGE (V)
POWER-DOWN
MAX8537 toc07
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
12
LOAD CURRENT (mA)
POWER-UP
10
OUTPUT VOLTAGE vs. INPUT VOLTAGE
VIN = 12V
1.29
5
LOAD CURRENT (A)
VTTR vs. LOAD CURRENT
VIN = 12V
1.29
0
LOAD CURRENT (A)
VTT vs. LOAD CURRENT
1.30
100
10
MAX8537 toc05
1
VTT
2.53
85
65
50
MAX8537 toc03
90
VIN = 12V
MAX8537 toc06
80
SENSE RESISTOR = 3mΩ
VIN = 12V
VDDQ = 2.5V
VDDQ vs. LOAD CURRENT
2.55
VDDQ
85
95
EFFICIENCY (%)
EFFICIENCY (%)
SENSE RESISTOR = 0Ω
VIN = 12V
VDDQ = 2.5V
90
MAX8537 toc01
95
VDDQ EFFICIENCY vs. LOAD CURRENT
100
MAX8537 toc02
VDDQ EFFICIENCY vs. LOAD CURRENT
100
MAX8537 toc09
5V/div
EN1/EN2
5V/div
2V/div
VDDQ
2V/div
VTT
1V/div
2V/div
2V/div
VVTTR
4ms/div
4ms/div
MAX8537/MAX8538/MAX8539
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25°C, 400kHz switching frequency, VIN = 12V, unless otherwise noted.)
VTTR
1V/div
1ms/div
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, 400kHz switching frequency, VIN = 12V, unless otherwise noted.)
POWER-OK
VDDQ LOAD TRANSIENT
AND VTT TRACKING
VTT STARTUP AND SHUTDOWN
MAX8537 toc10
MAX8537 toc11
VDDQ
2V/div
VTT
1V/div
VTT
1V/div
VTTR
1V/div
POK2
5V/div
VDDQ
2V/div
IOUT_VDDQ = 20A
IOUT_VTT = 8A
VTT
50mV/div
VTTR
50mV/div
20A
di/dt = 5A/µs
10A
VDDQ_IOUT
10A/div
VTT_IOUT = 12A
VTTR = 15mA
2ms/div
2ms/div
200µs/div
VDDQ = 2.5V AT 20A BODE PLOT,
VIN = 12V
VTT LOAD-TRANSIENT RESPONSE
MAX8537 toc13
di/dt = 1A/µs
-8A
160
140
120
dB (DEGREES)
8A
MAX8537 toc14
180
VTT
AC-COUPLED
50mV/div
VTTR
AC-COUPLED
50mV/div
VDDQ
AC-COUPLED
50mV/div
100
80
60
40
20
VTT_IOUT
10A/div
IOUT_VDDQ = 20A
IOUT_VTTR = 15mA
0
-20
-40
200µs/div
100
1k
10k
1M
100k
kHz
VTT = 1.25V AT 12A BODE PLOT,
VIN = 12V
SHORT CIRCUIT AND RECOVERY
MAX8537 toc16
MAX8537 toc15
150
125
VOUT1
1V/div
VOUT2
1V/div
100
75
50
IL1
10V/div
IIN
5A/div
25
0
-25
-50
102
103
104
105
106
10ms/div
Hz
6
MAX8537 toc12
VDDQ
100mV/div
EN2
5V/div
POK1
5V/div
dB (DEGREES)
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
_______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
PIN
NAME
(MAX8537/
MAX8539)
NAME
(MAX8538)
1
BST2
BST2
Bootstrap Input to Power Internal High-Side Driver for Step-Down 2. Connect to an
external capacitor and diode according to Figure 1.
2
DH2
DH2
High-Side Gate-Driver Output for Step-Down 2. Swings from LX2 to BST2.
3
LX2
LX2
External Inductor Input for Step-Down 2. Connect to the switched side of the inductor.
LX2 serves as the lower supply-voltage rail for the DH2 high-side gate driver and the
current-limit circuitry.
FUNCTION
4
ILIM2
ILIM2
Output Current-Limit Setting for Step-Down 2. Connect a resistor from ILIM2 to the
drain of the step-down 2 high-side MOSFET, or to the junction of the source of the
high-side MOSFET and the current-sense resistor to set the current-limit threshold.
See the Current-Limit Setting section.
5
POK1
POK1
Open-Drain Output. High impedance when step-down 1 is within 12% of its regulation
voltage. POK1 is pulled low in shutdown.
6
DL2
DL2
7
POK2
POK2
8
EN2
EN2
Enable Input for Step-Down 2 (also for VTTR for the MAX8537 and MAX8539)
9
EN1
EN1
Enable Input for Step-Down 1
10
FREQ
FREQ
11
COMP2
COMP2
12
FB2
FB2
Feedback Input for Step-Down 2 with VREFIN as the Threshold. User must have
impedance 0.64V), and 4) the thermal
limit is not exceeded. Once the MAX8537/MAX8538/
MAX8539 assert the internal enable signal, the controller starts switching and enables soft-start.
High-Side Gate-Drive Supply (BST)
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit (Figure 1).
The capacitor between BST and LX is alternately
charged from the VL supply and placed in parallel to
the high-side MOSFET’s gate-source terminals.
_______________________________________________________________________________________
9
MAX8537/MAX8538/MAX8539
DC-DC Controller
The MAX8537/MAX8538/MAX8539 step-down DC-DC
converters use a PWM voltage-mode control scheme.
An internal high-bandwidth (25MHz) operational amplifier is used as an error amplifier to regulate the output
voltage. The output voltage is sensed and compared
with an internal 0.8V reference or REFIN to generate an
error signal. The error signal is then compared with a
fixed-frequency ramp by a PWM comparator to give the
appropriate duty cycle to maintain output voltage regulation. At the rising edge of the internal clock, and with DL
(the low-side MOSFET gate drive) at 0V, the high-side
MOSFET turns on. When the ramp voltage reaches the
error-amplifier output voltage, the high-side MOSFET
latches off until the next clock pulse. During the highside MOSFET on-time, current flows from the input,
through the inductor, and to the output capacitor and
load. At the moment the high-side MOSFET turns off,
the energy stored in the inductor during the on-time is
released to support the load as the inductor current
ramps down by commutation through the low-side
MOSFET body diode. After a fixed delay, the low-side
MOSFET turns on to shunt the current from its body
diode for lower voltage drop and increased efficiency.
The low-side MOSFET turns off at the rising edge of the
next clock pulse, and when its gate voltage discharges
to zero, the high-side MOSFET turns on and another
cycle starts.
The controllers sense peak inductor current and provide hiccup-mode overload and short-circuit protection
(see the Current Limit section).
The MAX8537/MAX8538/MAX8539 operate in forcedPWM mode where the inductor current is always continuous, so even under light load the controller maintains
a constant switching frequency to minimize noise and
possible interference with system circuitry.
10
EN1
EN2
POK2
POK1
VOUT2
1.25V/
±12A
R19
100kΩ
C11, C30,
C31, C32
680µF
N1
R5
100kΩ
R12
510Ω
R10
10.0kΩ
C19
8.2nF
R20
100kΩ
R1
0.005Ω
L2
0.8uH
C2
10µF
C27
1000µF
C26
1000µF
C1
1000µF
VL
R11
51kΩ
R6
100kΩ
C41
47nF
R24
3.3Ω
C23
0.01µF
C18
15pF
C17
3.9nF
R9
51.1kΩ
C8
47pF
Figure 1. Typical Application Circuit: MAX8537 DDR Memory Application (400kHz Switching)
______________________________________________________________________________________
C25
220pF
R17
10.0kΩ
N5
R2
402Ω
C5
0.47µF
POK1
DL2
ILIM2
LX2
DH2
BST2
COMP2
FREQ
EN1
EN2
REFIN
SS2
R18
10.0kΩ
14
13
12 FB2
11
10
9
8
7 POK2
5
6
4
3
2
1
U1
VL
MAX8537
D1
VTTR
AVL
V+
VL
DL1
PGND
ILIM1
LX1
DH1
BST1
16
17
18
19
20
21
22
23
24
25
26
27
28
GND 15
SS1
FB1
COMP1
D2
C24
0.01µF
C20
39pF
C21
3.9nF
R8
4.7Ω
C42
0.15µF
R16
10.0kΩ
R14
22kΩ
R25
3.3Ω
R3
402Ω
C13
10µF
C15
1µF
VL
C9
47pF
C6
0.47µF
C4
10µF
C14
1µF
R15
21.5kΩ
N7
N3
C22
820pF
C16
1µF
R4
0.003Ω
N8
R13
1.2kΩ
N4
C29
1000µF
C28
1000µF
C3
1000µF
C12, C36
220µF
L1
0.9µH
VTTR
R7
2.2Ω
VOUT1
2.5V/20A
VIN (10.8V TO 13.2V)
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
EN1
EN2
POK2
POK1
VOUT2
0.9V/
±7A
R19
100kΩ
C11, C30,
C31, C32
680uF
R2
750Ω
C7
0.1µF
R5
100kΩ
R12
2.2kΩ
R10
10.0kΩ
C19
2.2nF
R20
100kΩ
L2
0.5uH
C39
1.0nF
R21 N1
2.2Ω
C2
10µF
R11
82kΩ
R6
100kΩ
VL
C23
0.01µF
C18
10pF
C17
1.8nF
R9
51.1kΩ
C25
220pF
R17
10.0kΩ
N5
R24
1Ω
C5
0.47µF
POK1
DL2
ILIM2
LX2
COMP2
FREQ
EN1
EN2
REFIN
SS2
R18
10.0kΩ
14
13
12 FB2
11
10
9
8
7 POK2
5
6
4
3
2 DH2
1 BST2
U1
VL
MAX8539
D1
VTTR
AVL
V+
VL
DL1
PGND
ILIM1
LX1
DH1
BST1
16
17
18
19
20
21
22
23
24
25
26
27
28
GND 15
SS1
FB1
COMP1
D2
C24
0.01µF
C20
56pF
C21
15nF
R8
4.7Ω
C13
10µF
C15
1µF
VL
R25
1Ω
C6
0.47µF
R16
10.0kΩ
R14
12kΩ
R3
1.0kΩ
C10
0.1µF
C4
10µF
C14
1µF
N7
R15
12.7kΩ
R13
2.2kΩ
N3
C12, C36, C37
680µF
N8
L1
0.8µH
N4 R22
1.5Ω
C22
2.7nF
C16
1µF
C29
1000µF
C28
1000µF
C3
1000µF
VTTR
R7
2.2Ω
C40
2.2nF
VOUT1
1.8V/15A
VOUT1
VIN (10.8V TO 13.2V)
MAX8537/MAX8538/MAX8539
VOUT1
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
Figure 2. MAX8539 DDR Memory Application (400kHz Switching)
______________________________________________________________________________________
11
EN1
EN2
POK2
POK1
R19
100kΩ
C11
470µF
VOUT2
2.5V/
5A
N1
C19
1.8nF
R2
511Ω
C7
0.1µF
R5
100kΩ
R23
10.0kΩ
R12
1.0kΩ
R10
21.5kΩ
L2
3.2µH
R20
100kΩ
C39
1.0nF
R21
2.2Ω
C2
10µF
C1
1000µF
R11
21.5kΩ
R6
100kΩ
VL
N5
R24
1Ω
Figure 3. MAX8538 PowerPC™ Application (400kHz Switching)
PowerPC is a trademark of Motorola, Inc.
12 ______________________________________________________________________________________
POK1
DL2
ILIM2
LX2
DH2
COMP2
FREQ
EN1
EN2
13
SS2
12 FB2
11
10
9
8
7 POK2
5
6
4
3
2
BST2
C23
0.01µF 14 N.C.
C18
10pF
C17
6.8nF
R9
51.1kΩ
C5
0.47µF
1
U1
VL
MAX8538
D1
GND
AVL
V+
VL
DL1
PGND
ILIM1
LX1
DH1
BST1
16
17
18
19
20
21
22
23
24
25
26
27
28
GND 15
SS1
FB1
COMP1
D2
C24
0.01µF
C20
47pF
R16
10.0kΩ
C21
R14
0.010µF 14kΩ
R8
4.7Ω
C13
10µF
C15
1µF
VL
R25
1Ω
C6
0.47µF
R3
1.0kΩ
C10
0.1µF
C4
10µF
C14
1µF
R15
12.7kΩ
R13
2.2kΩ
N7
N3
C29
1000µF
C28
1000µF
C3
1000µF
C22
2.2nF
N8
C12, C26
680µF
L1
1.0µH
N4 R22
1.5Ω
R7
2.2Ω
C40
2.2nF
VOUT1
1.8V/15A
VIN (10.8V TO 13.2V)
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
______________________________________________________________________________________
VOUT2
2.5V/
10A
EN1
EN2
POK2
POK1
C11
330µF
R19
100kΩ
C30
330µF
N1
C19
1nF
C7
0.1µF
R5
100kΩ
R2
1.0kΩ
R23
10.0kΩ
R12
4.3kΩ
R10
21.5kΩ
L2
0.66µH
R20
100kΩ
C39
2.2nF
R21
1.5Ω
C2
10µF
C1
1000µF
25V
R11
21.5kΩ
R6
100kΩ
VL
N5
R24
1Ω
C23
0.01µF
C18
15pF
C17
3.9nF
R9
20.0kΩ
C5
0.47µF
POK1
DL2
ILIM2
LX2
DH2
BST2
COMP2
FREQ
EN1
EN2
SS2
14 N.C.
13
12 FB2
11
10
9
8
7 POK2
5
6
4
3
2
1
U1
VL
MAX8538
D1
21
22
23
24
25
26
27
28
GND
19
AVL 20
V+
VL
DL1
PGND
ILIM1
LX1
DH1
BST1
16
GND 15
SS1
FB1 17
COMP1 18
D2
C20
10pF
C24
0.01µF
R3
1.21kΩ
R16
10.0kΩ
R8
4.7Ω
C21
R14
2.7nF 33kΩ
C13
10µF
C15
1µF
VL
R25
1Ω
C6
0.47µF
C10
0.1µF
C4
10µF
C14
1µF
R15
31.6kΩ
R13
6.2kΩ
N7
N3 R22
1.5Ω
C29
1000µF
25V
C28
1000µF
25V
C3
1000µF
25V
C22
680pF
Q1
C12, C36
330µF
L1
0.66µH
C40
2.2nF
R7
68Ω
VIN (10.8V TO 13.2V)
VOUT1
3.3V/12A
MAX8537/MAX8538/MAX8539
C26
1000µF
25V
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
Figure 4. MAX8538 Dual-Output Application (1MHz Switching)
13
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
Power-Good Signal (POK_)
The power-good signal (POK_) is an open-drain output.
The MOSFET turns on and POK_ is held low until FB_ is
±12% from its nominal threshold (0.8V for FB1 and
VREFIN for FB2). Then there is a 64 clock-cycle delay
before POK_ goes high impedance. For 400kHz switching frequency, this delay is 160µs. To obtain a logic
voltage output, connect a pullup resistor from POK_ to
VL. A 100kΩ resistor works well for most applications. If
unused, leave POK_ grounded or unconnected.
Enable (EN_), Soft-Start, and Soft-Stop
Outputs of the MAX8537/MAX8538/MAX8539 can be
turned on with logic high and off with logic low independently at EN1 and EN2. EN1 controls step-down 1,
and EN2 controls step-down 2 and VTTR (MAX8537/
MAX8539 only).
On the rising edge of EN_, the controller enters softstart. Soft-start gradually ramps up the reference voltage seen by the error amplifier to control the output’s
rate of rise and reduce the input surge current during
startup. The soft-start period is determined by a 5µA
pullup current, the external soft-start capacitor connected from SS_ to ground, and the reference voltage (0.8V
for FB1 and VREFIN for FB2, on the MAX8537/MAX8539;
0.8V for FB2 on the MAX8538). The output reaches regulation when soft-start is completed. On the falling edge
of EN_, the controller enters soft-stop, which reverses
the soft-start ramp. However, there is a delay due to 1V
overcharge on the soft-start capacitor. The delay time
can be calculated as tDELAY = CSS x 1V / 5µA. At the
end of soft-stop, DH is low and DL is high.
Current Limit
The MAX8537/MAX8538/MAX8539 DC-DC step-down
controllers sense the peak inductor current either
through the on-resistance of the high-side MOSFET for
lossless sensing, or with a series resistor for more
accurate sensing. In either case, when peak voltage
across the sensing circuit (which occurs at the peak of
the inductor current) exceeds the current-limit threshold
set by the ILIM pin, the controller turns off the high-side
MOSFET and turns on the low-side MOSFET. The
MAX8537/MAX8538/MAX8539 current-limit threshold
can be set by an external resistor that works in conjunction with an internal 200µA current sink. See the
Design Procedure section for how to set the ILIM with
an external resistor.
As the output load current increases above the threshold required to trip the peak current limit, the output
voltage sags because the truncated duty cycle is insufficient to support the load current. When FB_ is 30%
below its nominal threshold, output undervoltage pro14
tection is triggered and the controller enters hiccup
mode to limit the power dissipation in a fault condition.
See the Output Undervoltage Protection (UVP) section
for a description of hiccup operation.
Output Undervoltage Protection (UVP)
Output UVP begins when the controller is at its current
limit, FB_ is 30% below its nominal threshold, and softstart is complete. This condition causes the controller to
drive DH and DL low, and to discharge the soft-start
capacitor with a 5µA pulldown current until VSS reaches
50mV. Then the controller begins switching and enables
soft-start. If the overload condition still exists when softstart is complete, UVP triggers again. The result is hiccup mode, where the controller attempts to restart
periodically as long as the overload condition exists. In
hiccup mode, the soft-start capacitor voltage ramps
from the nominal FB_ threshold + 12% down to 50mV.
For the MAX8537/MAX8539, the tracking step-down
must also have VREFIN > 0.45V to trigger UVP. Then the
soft-start capacitor voltage ramps from VREFIN + 12%
down to 50mV. Additionally, in the MAX8537/MAX8539 if
output 1 is shorted, output 2 latches off. Recycle the
input power or enable to restart output 2.
Output Overvoltage Protection (OVP)
The output voltages are continuously monitored for
overvoltage. If the output voltage is more than 17%
above the reference of the error amplifier, OVP is triggered after a 10µs delay and the controller turns off.
The DL low-side gate driver is latched high until EN_ is
toggled or V+ power is cycled below 3.75V. This action
turns on the synchronous-rectifier MOSFET with 100%
duty cycle and, in turn, rapidly discharges the output
filter capacitor and forces the output to ground.
Note that DL latching high causes the output voltage to
go slightly negative due to energy stored in the output
LC at the instant OVP activates. If the load cannot tolerate being forced to a negative voltage, it can be desirable to place a power Schottky diode across the output
to act as a reverse-polarity clamp.
For step-down 2 of the MAX8537/MAX8539, the OVP
threshold is 560mV for VREFIN ≤ 0.45V, and the OVP
threshold is VREFIN + 17% for VREFIN > 0.45V.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8537/MAX8538/MAX8539. When the
junction temperature exceeds TJ = +160°C, a thermal
sensor shuts down the device, forcing DH and DL low
and allowing the IC to cool. The thermal sensor turns
the part on again after the junction temperature cools
______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
During a thermal event, the switching converters are
turned off, POK1 and POK2 are pulled low, and the
soft-starts are reset.
Design Procedure
Output Voltage Setting
The output voltage can be set by a resistive divider network. Select R2, the resistor from FB to GND, between
5kΩ and 15kΩ. Then calculate R1 by:
R1 = R2 x [(VOUT / 0.8) -1]
Inductor Selection
There are several parameters that must be examined
when determining which inductor to use: input voltage,
output voltage, load current, switching frequency, and
LIR. LIR is the ratio of inductor current ripple to DC load
current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. A good compromise between size and efficiency is
a 30% LIR. Once all the parameters are chosen, the
inductor value is determined as follows:
L=
VOUT × (VIN − VOUT )
VIN × fS × ILOAD(MAX) × LIR
where fS is the switching frequency. Choose a standard
value close to the calculated value. The exact inductor
value is not critical and can be adjusted in order to
make trade-offs among size, cost, and efficiency.
Lower inductor values minimize size and cost, but also
increase the output ripple and reduce the efficiency
due to higher peak currents. On the other hand, higher
inductor values increase efficiency, but eventually
resistive losses due to extra turns of wire exceed the
benefit gained from lower AC current levels. Find a lowloss inductor with the lowest possible DC resistance
that fits the allotted dimensions. Ferrite cores are often
the best choice, although powdered iron is inexpensive
and can work well up to 300kHz. The chosen inductor’s
saturation current rating must exceed the peak inductor
current determined as:
⎛ LIR ⎞
IPEAK = ILOAD(MAX) + ⎜
⎟ × ILOAD(MAX)
⎝ 2 ⎠
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
IRMS =
[IOUT12 × VOUT1 × (VIN − VOUT1)] + [IOUT2 2 × VOUT2 × (VIN − VOUT2 )]
VIN
Combinations of large electrolytic and small ceramic
capacitors in parallel are recommended. Almost all of
the RMS current is supplied from the large electrolytic
capacitor, while the smaller ceramic capacitor supplies
the fast rise and fall switching edges. Choose the electrolytic capacitor that exhibits less than 10°C temperature rise at the maximum operating RMS current for
optimum long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requirements, which
affect the overall stability, output ripple voltage, and
transient response.
The output ripple has three components: variations in
the charge stored in the output capacitor, voltage drop
across the capacitor’s ESR, and voltage drop across
the capacitor’s ESL, caused by the current into and out
of the capacitor. The following equations estimate the
worst-case ripple:
VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL)
VRIPPLE(ESR) = IP−P ESR
VRIPPLE(C) = IP−P / (8 × COUT × fSW )
VRIPPLE(ESL) = VIN × ESL / (L + ESL)
⎛ V −V
⎞⎛ V
⎞
IP−P = ⎜ IN OUT ⎟ ⎜ OUT ⎟
⎝ fSW L ⎠ ⎝ VIN ⎠
where IP-P is the peak-to-peak inductor current (see the
Inductor Selection section). Higher output current
requires paralleling multiple capacitors to meet the output ripple voltage.
The MAX8537/MAX8538/MAX8539s’ response to a load
transient depends on the selected output capacitor.
After a load transient, the output instantly changes by
(ESR x ∆ILOAD) + (ESL x dI/dt). Before the controller
can respond, the output deviates further depending on
the inductor and output capacitor values. After a short
period of time (see the Typical Operating Characteristics), the controller responds by regulating the output
voltage back to its nominal state. The controller
response time depends on the closed-loop bandwidth.
With higher bandwidth, the response time is faster, pre-
______________________________________________________________________________________
15
MAX8537/MAX8538/MAX8539
by 10°C, resulting in a pulsed output during continuous
thermal-overload conditions.
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
venting the output capacitor voltage from further deviation from its regulating value.
Do not exceed the capacitor’s voltage or ripple
current ratings.
MOSFET Selection
The MAX8537/MAX8538/MAX8539 controllers drive two
external, logic-level, N-channel MOSFETs as the circuitswitch elements. The key selection parameters are:
1) On-resistance (RDS(ON)): the lower, the better.
2) Maximum drain-to-source voltage (VDSS): should be
at least 20% higher than the input supply rail at the
high-side MOSFET’s drain.
3) Gate charges (Qg, Qgd, Qgs): the lower, the better.
Choose MOSFETs with RDS(ON) rated at VGS = 4.5V. For
a good compromise between efficiency and cost,
choose the high-side MOSFET that has conduction loss
equal to the switching loss at the nominal input voltage
and maximum output current. For the low-side MOSFET,
make sure it does not spuriously turn on due to dV/dt
caused by the high-side MOSFET turning on, as this
results in shoot-through current degrading the efficiency.
MOSFETs with a lower Qgd/Qgs ratio have higher immunity to dV/dt.
For proper thermal-management design, the power dissipation must be calculated at the desired maximum
operating junction temperature, maximum output current, and worst-case input voltage (for low-side
MOSFET, worst case is at V IN(MAX) ; for high-side
MOSFET, it could be either at VIN(MIN) or VIN(MAX)).
High-side and low-side MOSFETs have different loss
components due to the circuit operation. The low-side
MOSFET, operates as a zero-voltage switch; therefore,
the major losses are the channel conduction loss
(PLSCC) and the body-diode conduction loss (PLSDC):
PLSCC = [1 - (VOUT / VIN)] x (ILOAD)2 x RDS,ON
Use RDS,ON at TJ(MAX):
PLSDC = 2 x ILOAD x VF x tdt x fS
where VF is the body-diode forward voltage drop, tdt is
the dead-time between the high-side MOSFET and the
low-side MOSFET switching transitions, and fS is the
switching frequency.
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses: the channel
conduction loss (PHSCC), the V I overlapping switching
loss (PHSSW), and the drive loss (PHSDR). The high-side
MOSFET does not have body-diode conduction loss
because the diode never conducts current.
16
PHSCC = (VOUT / VIN) x I2LOAD x RDS(ON)
Use RDS(ON) at TJ(MAX):
PHSSW = VIN x ILOAD x fS x [(Qgs + Qgd) / IGATE]
where I GATE is the average DH-high driver outputcurrent capability determined by:
IGATE(ON) = 2.5 / (RDH + RGATE)
where RDH is the high-side MOSFET driver’s average
on-resistance (1.1Ω typ) and RGATE is the internal gate
resistance of the MOSFET (~2Ω):
PHSDR = Qgs x VGS x fS x RGATE / (RGATE + RDH)
where VGS ~ VL = 5V.
In addition to the losses above, approximately 20% more
for additional losses due to MOSFET output capacitances and low-side MOSFET body-diode reverse-recovery charge dissipated in the high-side MOSFET that
exists, but is not well defined in the MOSFET data sheet.
Refer to the MOSFET data sheet for thermal-resistance
specification to calculate the PC board area needed to
maintain the desired maximum operating junction temperature with the above-calculated power dissipation.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFETs, so be sure this does not
overheat the MOSFETs.
The minimum load current must exceed the high-side
MOSFET’s maximum leakage current over temperature
if fault conditions are expected.
Current-Limit Setting
The MAX8537/MAX8538/MAX8539 controllers sense
the peak inductor current to provide constant current
and hiccup current limit. The peak current-limit threshold is set by an external resistor together with the internal current sink of 200µA. The voltage drop across the
resistor RILIM_with 200µA current through it sets the
maximum peak inductor current that can flow through
the high-side MOSFET or the optional current-sense
resistor by the equations below:
IPEAK(MAX) = 200µA x RILIM_ / RDSON(HSFET)
or
IPEAK(MAX) = 200µA x RILIM_ / RSENSE
RILIM_ should be less than 1.5kΩ for optimum currentlimit accuracy. The actual corresponding maximum
load current is lower than the IPEAK(MAX) above by half
______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
The circuit parasitic capacitance (CPAR) at LX is
then equal to 1/3rd the value of the added capacitance above. The circuit parasitic inductance (LPAR)
is calculated by:
LPAR =
1
(2πfR )
2
× CPAR
The resistor for critical dampening (RSNUB) is equal to 2π
x fR x LPAR. Adjust the resistor value up or down to tailor
the desired damping and the peak voltage excursion.
The capacitor (CSNUB) should be at least 2 to 4 times
the value of the C PAR in order to be effective. The
power loss of the snubber circuit is dissipated in the
resistor (PRSNUB) and can be calculated as:
PRSNUB = CSNUB × ( VIN )
2
× fSW
where VIN is the input voltage and fSW is the switching
frequency. Choose an RSNUB power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Additionally, there is parasitic inductance of the current-sensing element, whether the high-side MOSFET
R DS(ON) (L SENSE_FET ) or the actual current-sense
resistor RSENSE (LRSENSE) are used, which is in series
with the output filter inductor. This parasitic inductance,
together with the output inductor, form an inductive
divider and cause error in the current-sensing voltage.
To compensate for this error, a series RC circuit can be
added in parallel with the sensing element (see Figure
1). The RC time constant should equal L RSENSE /
RSENSE, or LSENSE_FET / RDS(ON). First, set the value of
R equal to or less than RILIM_ / 100. Then, the value of
C can be calculated as:
C = LRSENSE / (RSENSE x R) or
C = LSENSE_FET / (RDS(ON) x R)
Any PC board trace inductance in series with the sensing element and output inductor should be added to
the specified FET or resistor inductance per the
respective manufacturer’s data sheet. For the case of
the MOSFET, it is the inductance from the drain to the
source lead.
An additional switching noise filter may be needed at
ILIM_ by connecting a capacitor in parallel with RILIM_
(in the case of RDS(ON) sensing) or from ILIM_ to LX (in
the case of resistor sensing). For the case of RDS(ON)
sensing, the value of the capacitor should be:
C > 50 / (3.1412 x fS x RILIM_)
For the case of resistor sensing:
C < 25 x 10-9 / RILIM_
Soft-Start Capacitor Setting
The two step-down converters have independent,
adjustable soft-start. External capacitors from SS1/SS2
to ground are charged by an internal 5µA current
source to the corresponding feedback threshold.
Therefore, the soft-start time can be calculated as:
TSS = CSS x VFB / 5µA
For example, 0.01µF from SS1 to ground corresponds
to approximately a 1.6ms soft-start period for stepdown 1.
Compensation Design
The MAX8537/MAX8538/MAX8539 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
The error amplifier is an operational amplifier with
25MHz bandwidth to provide fast response. The output
lowpass LC filter creates a double pole at the resonant
frequency that introduces a gain drop of 40dB per
decade and a phase shift of 180 degrees per decade.
The error amplifier must compensate for this gain drop
and phase shift to achieve a stable high-bandwidth
closed-loop system.
The basic regulator loop can be thought of as consisting of a power modulator and an error amplifier. The
power modulator has DC gain set by VIN / VRAMP, with
a double pole, fP_LC, and a single zero, fZ_ESR, set by
the output inductor (L), the output capacitor (CO), and
its equivalent series resistance (RESR). Below are the
equations that define the power modulator:
______________________________________________________________________________________
17
MAX8537/MAX8538/MAX8539
of the inductor ripple current (see the Inductor
Selection section). If RDS(ON) of the high-side MOSFET
is used for current sensing, make sure to use the maximum RDS(ON) at the highest operating junction temperature to avoid fault tripping of the current limit at
elevated temperature. Consideration should also be
given to the tolerance of the 200µA current sink.
When RDS(ON) of the high-side MOSFET is used for current sensing, ringing on the LX voltage waveform can
interfere with the current limit. Below is the procedure for
selecting the value of the series RC snubber circuit:
1) Connect a scope probe to measure VLX to GND,
and observe the ringing frequency, fR.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
GMOD(DC) =
VIN
VRAMP
, where VRAMP = 1V (typ)
1
2π L C O
1
fZ _ ESR =
2π × RESR × CO
fP _ LC =
When the output capacitor is composed of paralleling n
number of the same capacitors, then:
CO = n × CEACH
and
RESR =
RESR _ EACH
n
Thus, the resulting fZ_ESR is the same as that of a single capacitor.
The total closed-loop gain must be equal to unity at the
crossover frequency, where the crossover frequency is
less than or equal to 1/5th the switching frequency (fS):
fC ≤ fS / 5
So the loop-gain equation at the crossover frequency is:
GEA(FC) x GMOD(FC) = 1
where GEA(FC) is the error-amplifier gain at f C, and
GMOD(FC) is the power-modulator gain at fC.
The loop compensation is affected by the choice of output filter capacitor due to the position of its ESR-zero frequency with respect to the desired closed-loop crossover
frequency. Ceramic capacitors are used for higher
switching frequencies (above 750kHz) and have low
capacitance and low ESR; therefore, the ESR-zero frequency is higher than the closed-loop crossover frequency. Electrolytic capacitors (e.g., tantalum, solid polymer,
and OS-CON) are needed for lower switching frequencies and have high capacitance and higher ESR; therefore, the ESR-zero frequency is lower than the
closed-loop crossover frequency. Thus, the compensation design procedures are separated into two cases:
Case 1: Crossover frequency is less than the outputcapacitor ESR-zero (fC < fZ_ESR).
The modulator gain at fC is:
GMOD(FC) = GMOD(DC) x (fP_LC / fC)2
Since the crossover frequency is lower than the output
capacitor ESR-zero frequency and higher than the LC
double-pole frequency, the error-amplifier gain must
have a +1 slope at fC so that, together with the -2 slope
of the LC double pole, the loop crosses over at the
desired -1 slope.
18
The error amplifier has a dominant pole at a very low
frequency (~0Hz), and two additional zeros and two
additional poles as indicated by the equations below
and illustrated in Figure 6:
fZ1_EA = 1 / (2π x R4 x C2)
fZ2_EA = 1 / (2π x (R1 + R3) x C1)
fP2_EA = 1 / (2π x R3 x C1)
fP3_EA = 1 / (2π x R4 x (C2 x C3 / (C2 + C3)))
Note that fZ2_EA and fP2_EA are chosen to have the
converter closed-loop crossover frequency, fC, occur
when the error-amplifier gain has +1 slope, between
fZ2_EA and fP2_EA. The error-amplifier gain at fC must
meet the requirement below:
GEA(FC) = 1 / GMOD(FC)
The gain of the error amplifier between f Z1_EA and
fZ2_EA is:
GEA(fZ1_EA - fZ2_EA) = GEA(FC) x fZ2_EA / fC =
fZ2_EA / (fC x GMOD(FC))
This gain is set by the ratio of R4/R1, where R1 is calculated in the Output Voltage Setting section. Thus:
R4 = R1 x fZ2_EA / (fC x GMOD(FC))
where fZ2_EA = fP_LC.
Due to the underdamped (Q > 1) nature of the output
LC double pole, the first error-amplifier zero frequency
must be set less than the LC double-pole frequency in
order to provide adequate phase boost. Set the erroramplifier first zero, fZ1_EA, at 1/4th the LC double-pole
frequency. Hence:
C2 = 2 / (π x R4 x fP_LC)
Set the error amplifier fP2_EA at fZ_ESR and fP3_EA equal
to half the switching frequency. The error-amplifier gain
between fP2_EA and fP3_EA is set by the ratio of R4/RI
and is equal to:
GEA(fZ1_EA - fZ2_EA) x (fZ_ESR / fP_LC)
where RI = R1 x R3 / (R1 + R3). Then:
RI = R4 x fP_LC / (GEA(fZ1_EA - fZ2_EA) x fZ_ESR) =
R4 x fC x GMOD(FC) / fZ_ESR
The value of R3 can then be calculated as:
R3 = R1 x RI / (R1 – RI)
Now we can calculate the value of C1 as:
C1 = 1 / (2π x R3 x fZ_ESR)
and C3 as:
C3 = C2 / ((2π x C2 x R4 x fP3_EA) - 1)
______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
MAX8537/MAX8538/MAX8539
C3
C2
R4
C1
VOUT
R3
R1
FB
EA
R2
GAIN
(dB)
COMP
REF
CLOSED-LOOP GAIN
EA GAIN
0
fz1
fZ2
fP2
FREQUENCY
fP3
fC
Figure 6. Error-Amplifier Compensation Circuit; Closed-Loop and Error-Amplifier Gain Plot for Case 1
CLOSED-LOOP GAIN
GAIN
(dB)
EA GAIN
0
fZ1
fZ2
fP3
fP2
FREQUENCY
fC
Figure 7. Closed-Loop and Error-Amplifier Gain Plot for Case 2
______________________________________________________________________________________
19
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
MAX8537/MAX8538/MAX8539
MAX8537/MAX8539 Functional Diagram
ILIM1
IMAX
SENSE
200µA
BST1
FREQ
DH1
OSC
CONTROL
LOGIC
1V
LX1
VL
PWM
DL1
PGND
EN1
REF
V+
0.80V
VL
SOFT-START
VL
EAMP
COMP1
0.936V
SS1
OVP1
0.560V
UVP1
FB1
SOFT-START
REFIN
REFIN
EAMP
0.896V
0.704V
POK1
SS2
VTTR
ILIM2
IMAX
SENSE
AVL
200µA
BIAS
BST2
GND
DH2
CONTROL
LOGIC
LX2
VL
PWM
DL2
EN2
PGND
REFIN
COMP2
1.12REFIN
0.88REFIN
POK2
EAMP
FB2
UVP2
OVP2
0.7REFIN
20
1.17REFIN
______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
TOP VIEW
BST2 1
28 BST1
BST2 1
28 BST1
DH2 2
27 DH1
DH2 2
27 DH1
LX2 3
26 LX1
LX2 3
26 LX1
ILIM2 4
25 ILIM1
ILIM2 4
POK1 5
24 PGND
POK1 5
MAX8537
MAX8539
25 ILIM1
24 PGND
MAX8538
23 DL1
DL2 6
POK2 7
22 VL
POK2 7
22 VL
EN2 8
21 V+
EN2 8
21 V+
EN1 9
20 AVL
EN1 9
20 AVL
19 VTTR
FREQ 10
19 GND
DL2 6
FREQ 10
COMP2 11
18 COMP1
COMP2 11
23 DL1
18 COMP1
FB2 12
17 FB1
FB2 12
17 FB1
SS2 13
16 SS1
SS2 13
16 SS1
REFIN 14
15 GND
N.C. 14
15 GND
QSOP
Case 2: Crossover frequency is greater than the
output-capacitor ESR zero (fC > fZ_ESR).
The modulator gain at fC is:
GMOD(FC) = GMOD(DC) x (fP_LC)2 / (fZ_ESR x fC)
Since the output-capacitor ESR-zero frequency is higher than the LC double-pole frequency but lower than
the closed-loop crossover frequency, where the modulator already has -1 slope, the error-amplifier gain must
have zero slope at fC so the loop crosses over at the
desired -1 slope.
The error-amplifier circuit configuration is the same as
case 1 above; however, the closed-loop crossover frequency is now between fP2 and fP3 as illustrated in
Figure 7.
The equations that define the error amplifier’s zeros
(fZ1_EA, fZ2_EA) and poles (fP2_EA, fP3_EA) are the same
as case 1; however, f P2_EA is now lower than the
closed-loop crossover frequency. Therefore, the erroramplifier gain between fZ1_EA and fZ2_EA is now calculated as:
GEA(fZ1_EA - fZ2_EA) = GEA(FC) x fZ2_EA / fP2_EA =
fZ2_EA / (fP2_EA x GMOD(FC))
This gain is set by the ratio of R4/R1, where R1 is calculated in the Output Voltage Setting section. Thus:
QSOP
R4 = R1 x fZ2_EA / (fP2_EA x GMOD(FC))
where fZ2_EA = fP_LC and fP2_EA = fZ_ESR.
Similar to case 1, C2 can be calculated as:
C2 = 2 / (π x R4 x fP_LC)
Set the error-amplifier third pole, f P3_EA, at half the
switching frequency, and let RI = (R1 x R3) / (R1 + R3).
The gain of the error amplifier between f P2_EA and
f P3_EA is set by the ratio of R4/R I and is equal to
GEA(FC) = 1 / GMOD(FC). Then:
RI = R4 x GMOD(FC)
Similar to case 1, R3, C1, and C3 can be calculated as:
R3 = R1 x Ri / (R1 - RI)
C1 = 1 / (2π x R3 x fZ_ESR)
C3 = C2 / ((2π x C2 x R4 x fP3_EA) - 1)
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching-power stage requires particular attention.
Follow these guidelines for good PC board layout:
1) Place the decoupling capacitors as close to the IC
pins as possible.
______________________________________________________________________________________
21
MAX8537/MAX8538/MAX8539
Pin Configurations
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
2) Keep separate the power ground plane (connected
to the sources of the low-side MOSFETs, pin 24,
input capacitor ground, output capacitor ground,
and VL decoupling capacitor ground) and the signal
ground plane (connected to GND pin and the rest of
the circuit ground returns). Place the input decoupling ceramic capacitor as directly and close to the
high-side MOSFET drain and the low-side MOSFET
source as possible. Place the RC snubber circuit as
close to the low-side MOSFET as possible.
3) Keep the high-current paths as short as possible.
4) Connect the drains of the MOSFETs to a large land
area to help cool the devices and further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors as close to the
IC as possible.
6) Route high-speed switching nodes away from sensitive analog areas (FB, COMP).
7) Refer to the evaluation kit for a sample board layout.
Chip Information
TRANSISTOR COUNT: 5504
PROCESS: BiCMOS
22
______________________________________________________________________________________
Dual-Synchronous Buck Controllers for Point-ofLoad, Tracking, and DDR Memory Power Supplies
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX8537/MAX8538/MAX8539
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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