19-3290; Rev 2; 6/06
KIT
ATION
EVALU
E
L
B
A
IL
AVA
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
The MAX8563/MAX8564/MAX8564A ultra-low-output dual
and triple LDO controllers allow flexible and inexpensive
point-of-load voltage conversion in motherboards,
desknotes, notebooks, and other applications.
These parts feature a 0.5V reference voltage with ±1%
accuracy providing tight regulation of the output voltage. The MAX8563 has three n-channel MOSFET controller outputs, and the MAX8564/MAX8564A has two
controller outputs.
Each controller output is adjustable from 0.5V to 3.3V
when VDD = 12V and between 0.5V and 1.8V when VDD
= 5V. Each output is independently enabled and asserts
a POK signal when the output reaches 94% of the set
value. Each output is protected against a soft short-circuit
condition by an undervoltage comparator that disables
the output when it drops to under 80% of the set voltage
for more than 50µs. For a catastrophic short condition, the
regulators are shut down immediately if the output drops
below 60% of the set voltage.
The MAX8563 is available in a 16-pin QSOP
package, and the MAX8564/MAX8564A are available
in a 10-pin µMAX® package.
Features
♦ MAX8563: 3 Outputs
♦ MAX8564/MAX8564A: 2 Outputs
♦ ±1% Feedback Regulation
♦ Adjustable Output Voltage Down to 0.5V
♦ Can Use Ceramic Output Capacitors
♦ Wide Supply Voltage Range Permits Operation
from 5V or 12V Rails
♦ Individual Enable Control and POK Signal Allows
Sequencing
♦ Overload Protection Against Soft Short-Circuit
Condition
♦ Undervoltage Short-Circuit Protection
♦ Drive n-Channel MOSFETs
Ordering Information
Applications
Motherboards
Dual/Triple Power Supplies
Desknotes and Notebooks
Graphic Cards
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX8563EEE
-40°C to +85°C
16 QSOP
E16-1
MAX8564EUB
-40°C to +85°C
10 µMAX
U10-2
MAX8564AEUB+
-40°C to +85°C
10 µMAX
U10-2
PART
Ultra-Low-Dropout
Voltage Regulators
Low-Voltage DSP, µP, and
Microcontroller Power
Supplies
+Denotes lead-free package.
Pin Configurations appear at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Typical Operating Circuit
1.8V ±5% IN
C1
5V OR 12VIN
1.2V ±5% IN
C2
C3
Q1
OUT1
1.5V/1.5A
C5
R2
Q2
DRV1
C4
VDD
R1
R4
FB1
R3
C7
R5
ON
EN1
OFF
OUT2
1.05V/3A
C6
DRV2
MAX8563
FB2
ON
POK1
3.3V ±5% IN
POK1
EN2
GND
POK2
N.C.
N.C.
DRV3
POK3
OFF
C8
POK2
R6
Q3
C10
OUT3
2.5V/2A*
R7
C9
POK3
ON
FB3
EN3
OFF
R8
R9
*2.5V OUTPUT ONLY WITH VDD = 12V
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8563/MAX8564/MAX8564A
General Description
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................-0.3V to +14V
DRV1, DRV2, DRV3, EN1, EN2,
EN3 to GND............................................-0.3V to (VDD + 0.3V)
FB1, FB2, FB3, POK1, POK2, POK3 to GND ...........-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
VDD Voltage Range
VDD Undervoltage-Lockout Threshold
VDD Quiescent Current
VDD Shutdown Current
4.5
13.2
V
3.76
4.00
V
VEN_ = VDD = 12V (MAX8563)
930
1600
VEN_ = VDD = 12V (MAX8564/MAX8564A)
660
1200
Rising, 200mV hysteresis (typ)
3.56
EN1 = EN2 = EN3 = GND, VDD = 12V
25
µA
µA
LDOs
FB_ Accuracy
FB_ Input Bias Current
DRV_ Soft-Start Charging Current
TA = 0°C to +85°C
0.494
TA = -40°C to +85°C
0.489
TA = +25°C
-100
TA = +85°C
+100
-8
100
MAX8564A
10
VFB_ = 0.45V
DRV_ Max Sinking Current
VFB_ = 0.6V
0.504
0.509
MAX8563, MAX8564
DRV_ Max Sourcing Current
DRV_ Max Voltage
0.5
TA = 0°C to +85°C
4
TA = -40°C to +85°C
3
TA = 0°C to +85°C
TA = -40°C to +85°C
VDD = 5V, VFB_ = 0.46V
4.7
VDD = 13.2V, VFB_ = 0.46V
8.0
nA
µA
mA
7
3
1.8
V
mA
7
10.9
V
FB_ Slow Short-Circuit Threshold
Measured at FB_ (falling)
400
mV
FB_ Fast Short-Circuit Threshold
Measured at FB_ (falling)
300
mV
Slow Short-Circuit Timer
50
FB_ to DRV_ Transconductance
0.115
0.24
µs
0.460
Mho
0.7
V
LOGIC
EN_ Input Low Level
EN_ Input High Level
EN_ Input Leakage Current
2
1.3
VEN_ = 0 and VDD,
VDD = 13.2V
TA = +25°C
TA = +85°C
V
-0.1
+0.1
0.001
_______________________________________________________________________________________
µA
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
MIN
TYP
MAX
UNITS
POK_ Threshold Falling
PARAMETER
Measured at FB_ (falling)
CONDITIONS
425
440
455
mV
POK_ Threshold Rising at Startup
Measured at FB_ (rising)
455
470
485
mV
POK_ Output Low Level
Sinking 1mA, VDD = 4.5V, VFB_ = 0.4V
0.1
V
POK_ Output High Leakage
VDD = 5.5V
TA = +25°C
0.1
TA = +85°C
µA
0.001
Note 1: Specifications are production tested at TA = +25°C. Maximum and minimum specifications over temperature are guaranteed by
design.
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25°C.)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.5
VDD = 12V
1.4
1.3
1.2
VOUT3
2.4
2.2
OUTPUT VOLTAGE (V)
VOUT1
OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX8563 toc02
MAX8563 toc01
VDD = 5V
2.6
2.0
1.8
VOUT1
1.6
1.4
1.1
VOUT2
1.2
VOUT2
1.0
1.0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
INPUT VOLTAGE (V)
FEEDBACK VOLTAGE
vs. TEMPERATURE
VDD = 5V
0.4996
3.0
VOUT2
0
3.4
0.5
1.0
1.5
2.0
PSRR vs. FREQUENCY
LOAD TRANSIENT
3.0
IOUT2
2A/div
0
VOUT2
20mV/div
AC-COUPLED
VIN2
200mV/div
AC-COUPLED
60
50
40
30
0.4990
2.5
MAX8563 toc06
VOUT1 = 1.5V
VIN1 = 2V
LOAD = 1.25Ω
VDD = 12V
70
0.4992
2.6
VOUT1
OUTPUT CURRENT (A)
80
VDD = 12V
0.4994
2.2
VDD = 12V
VOUT3
INPUT VOLTAGE (V)
90
PSRR (dB)
FEEDBACK VOLTAGE (V)
0.4998
1.8
100
MAX8563 toc04
0.5000
1.4
MAX8563 toc05
1.0
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
MAX8563 toc03
OUTPUT VOLTAGE vs. INPUT VOLTAGE
OUTPUT VOLTAGE vs. INPUT VOLTAGE
1.6
20
0.4988
VDRV2
10
0
0.4986
-40
-15
10
35
TEMPERATURE (°C)
60
85
MAX8563/MAX8564/MAX8564A
ELECTRICAL CHARACTERISTICS (continued)
100
1k
10k
100k
VDD = 12V
FIGURE 1, C7 = 100μF 6TPE100MI
2V/div
0
10μs/div
FREQUENCY (Hz)
_______________________________________________________________________________________
3
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C.)
POWER-ON SEQUENCING WITH VDD
POWER-ON SEQUENCING WITH VIN
MAX8563 toc07
VDD
VOUT1
MAX8563 toc08
20V/div
0
VDD
2V/div
VIN1
ENABLE CONFIGURED AS
SHOWN IN FIGURE 4
RD = 100kΩ, RE = 4kΩ
2V/div
0
VIN1
2V/div
0
2V/div
0
VOUT1
0
2V/div
VPOK1
2V/div
VPOK1
0
0
20ms/div
10ms/div
ENABLE-ON SEQUENCING
SHORT-CIRCUIT PROTECTION
MAX8563 toc09
VIN1
20V/div
0
MAX8563 toc10
2V/div
0
2V/div
EN1
IOUT1
5A/div
0
0
2V/div
0
VOUT1
2V/div
VPOK1
VOUT1
1V/div
0
VDRV1
0
2V/div
0
20ms/div
4
20μs/div
_______________________________________________________________________________________
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
VDD
VL
UVLO
0.5V
REF
MAX8563
MAX8564
MAX8564A
GND
VDD
VDD
0.5V
EN1
GM
DRV1
VL
POK1
POK
COMPARATOR
LDO
CONTROLLER 1
EN2
POK2
DRV2
LDO
CONTROLLER 2
EN3
POK3
FB1
FB2
DRV3
LDO
CONTROLLER 3
FB3
Pin Description
NAME
PIN
FUNCTION
MAX8563
MAX8564/
MAX8564A
1
DRV1
DRV1
Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1.
DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
2
FB1
FB1
Feedback Input for Output 1. Connect to the center of a resistor-divider between output 1 and GND to
set the output voltage of output 1. The feedback regulation voltage is 0.500V. See the Output Voltage
Setting section.
3
EN1
EN1
Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the
output. Connect to VDD for always-on operation.
4
POK1
POK1
Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the
nominal regulated voltage.
5
GND
GND
Ground
—
POK2
Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the
nominal regulated voltage.
N.C.
—
6
No Internal Connection
_______________________________________________________________________________________
5
MAX8563/MAX8564/MAX8564A
Functional Diagram
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
MAX8563/MAX8564/MAX8564A
Pin Description (continued)
NAME
PIN
MAX8564/
MAX8564A
—
EN2
DRV3
—
—
FB2
Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and
GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.
FB3
—
Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and
GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.
—
DRV2
EN3
—
—
VDD
POK3
—
Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is 12% below the
nominal regulated voltage.
11
N.C.
—
No Internal Connection
12
POK2
—
Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the
nominal regulated voltage.
13
EN2
—
Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the
output. Connect to a VDD for always-on operation.
14
FB2
—
Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and
GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.
15
DRV2
—
Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2.
DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
16
VDD
—
+5V or +12V Supply Input. Connect to an external +5V or +12V supply rail. Bypass with a 0.1µF
ceramic or larger capacitor.
7
8
9
10
6
FUNCTION
MAX8563
Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the
output. Connect to VDD for always-on operation.
Output 3 n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 3.
DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2.
DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the
output. Connect to VDD for always-on operation.
+5V or +12V Supply Input. Connect to external +5V or +12V supply rail. Bypass with a 0.1µF
ceramic or larger capacitor.
_______________________________________________________________________________________
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
MAX8563: Triple Output
1.8V ±5% IN
5V OR 12VIN
C1
1.2V ±5% IN
C2
C3
Q1
OUT1
1.5V/1.5A
C5
R2
Q2
DRV1
C4
VDD
R1
C7
DRV2
FB1
OUT2
1.05V/3A
C6
R4
R3
R5
ON
EN1
OFF
MAX8563
FB2
ON
POK1
3.3V ±5% IN
POK1
EN2
GND
POK2
N.C.
N.C.
DRV3
POK3
OFF
C8
Q3
OUT3
2.5V/2A*
C10
POK2
R6
R7
C9
R8
POK3
ON
FB3
EN3
OFF
R9
*2.5V OUTPUT ONLY WITH VDD = 12V
Figure 1. MAX8563 Typical Application Circuit
_______________________________________________________________________________________
7
MAX8563/MAX8564/MAX8564A
Typical Application Circuits
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
Typical Application Circuits (continued)
MAX8564/MAX8564A: Dual Output
1.8V ±5% IN
5V OR 12VIN
C15
1.2V ±5% IN
C11
C17
Q4
OUT1
1.5V/1.5A
C20
R18
Q5
DRV1
C14
VDD
R16
C18
R15
FB1
C12
R17
ON
OFF
EN1
OUT2
1.05V/3A
DRV2
MAX8564
MAX8564A
R14
FB2
ON
POK1
POK1
EN2
GND
POK2
OFF
POK2
R13
Figure 2. MAX8564/MAX8564A Typical Application Circuit
MAX8563 External Component List
COMPONENTS QTY
C1, C3, C8
C2
2.2µF, 10V X5R ceramic capacitors
(optional 100µF, 18mΩ, 6.3V
aluminum electrolytic, Sanyo
GTPE100MI in parallel)
1
0.1µF, 16V X7R ceramic capacitor
C4, C7, C9
3
100µF, 18mΩ, 6.3V aluminum
electrolytic capacitors
Sanyo GTPE100MI
C5, C6, C10
3
1µF, 16V X7R ceramic capacitors
Q1/Q2 (dual)
1
Dual n-channel MOSFETs, 30V, 18mΩ
Vishay Si4922DY
Q3
R1
1
1
n-channel MOSFET, 30V, 50mΩ
Fairchild Semiconductor FDD6630A
665Ω ±1% resistor
COMPONENTS QTY
DESCRIPTION
C11
1
0.1µF, 16V X7R ceramic capacitor
C12, C14
2
100µF, 18mΩ, 6.3V aluminum
electrolytic capacitors
Sanyo GTPE100MI
C15, C17
2
2.2µF, 10V X5R ceramic capacitors
(optional 100µF, 18mΩ, 6.3V
aluminum electrolytic, Sanyo
GTPE100MI in parallel)
C18, C20
2
1µF, 16V X7R ceramic capacitors
Q4/Q5 (dual)
1
Dual n-channel MOSFETs, 30V, 18mΩ
Vishay Si4922DY
R13
1
165Ω ±1% resistor
R14
1
182Ω ±1% resistor
1
390Ω ±5% resistor
R2
1
620Ω ±5% resistor
R15
R3
1
332Ω ±1% resistor
R16
1
665Ω ±1% resistor
390Ω ±5% resistor
R17
1
332Ω ±1% resistor
R18
1
620Ω ±5% resistor
R4
8
3
DESCRIPTION
MAX8564/MAX8564A External
Component List
1
R5
1
182Ω ±1% resistor
R6
1
165Ω ±1% resistor
R7
1
910Ω ±5% resistor
R8
1
1kΩ ±1% resistor
R9
1
249Ω ±1% resistor
_______________________________________________________________________________________
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
The MAX8563/MAX8564/MAX8564A triple and dual
LDO controllers allow flexible and inexpensive voltage
conversion by controlling the gate of an external
n-MOSFET in a source-follower configuration. The
MAX8563/MAX8564/MAX8564A consist of multiple
identical LDO controllers. Each LDO controller features
an enable input (EN_) and a power-OK output (POK_).
The MAX8563/MAX8564/MAX8564A also include a 0.5V
reference, an internal regulator, and an undervoltage
lockout (UVLO). The transconductance amplifier measures the feedback voltage on FB_ and compares it to
an internal 0.5V reference connected to the positive
input. If the voltage on FB_ is lower than 0.5V, the current output on the gate-drive output DRV_ is increased.
If the voltage on FB_ is higher than 0.5V, the current output on the gate-drive output is decreased.
Bias Voltage (VDD), UVLO, and Soft-Start
The MAX8563/MAX8564/MAX8564A bias current
for internal circuitry is supplied by VDD. The VDD voltage
range is from 4.5V to 13.2V. If VDD drops below 3.76V
(typ), the MAX8563/MAX8564/MAX8564A assume that
the supply and reference voltages are too low and activate the UVLO circuitry. During UVLO, the internal regulator (VL) and the internal bandgap reference are forced
off, DRV_ is pulled to GND, and POK_ is pulled low.
Before any internal startup circuitry is activated, VDD must
be above the UVLO threshold. After UVLO indicates that
VDD is high enough, the internal VL regulator, the internal
bandgap reference, and the bias currents are activated.
If EN_ is logic-high after the internal reference and bias
currents are activated, then the corresponding DRV_ output initiates operation in soft-start mode. Once the voltage
on FB_ reaches 94% of the regulation threshold, the full
output current of the LDO controller is permitted.
When an LDO is activated, the respective DRV_ is pulled
up from GND with a typical soft-start current of DRV softstart. The soft-start current limits the slew of the output
voltage and limits the initial spike of current that the drain
of the external n-MOSFET receives. The size of the compensation capacitor (CC) limits the slew rate (see Figure
3). This output voltage slew rate is equal to (DRV_softstart /CC)mV/ms, where CC is in µF. The maximum startup
drain current is the ratio of COUT to CC multiplied by the
soft-start current.
Input Voltage (Drain Voltage of the
External n-MOSFET)
The minimum input voltage to the drain of the n-MOSFET
is a function of the desired output voltage and the
dropout voltage of the n-MOSFET. Details on calculating
VIN_
Q1
OUT1
CC
MAX8563
MAX8564
DRV_ MAX8564A
RC
COUT
Figure 3. Soft-Start and Compensation Schematic
this value are covered in the Power MOSFET Selection
section.
The maximum input voltage to the drain of the n-MOSFET
is a function of the breakdown voltage and the thermal
conditions during operation. The breakdown voltage from
drain to source is normally provided in the MOSFET data
sheet. The theoretical maximum input voltage is the set
output voltage plus the breakdown voltage. The thermal
constraint is usually the largest concern when discussing
maximum input voltage. Details on calculating this value
are covered in the Power MOSFET Selection section. The
MOSFET package and thermal relief on the board are
the largest contributors to removing heat from the
n-MOSFET. Since output voltage is normally set and
maximum output current is fixed, the input voltage
becomes the only variable that determines the maximum power dissipated. Thus, the maximum input voltage is limited by the power capability of the n-MOSFET,
if it is less than the breakdown voltage, which is most
often the case. Ensure input capacitors handle the
maximum input voltage.
During a power-up sequence where VDD and EN_ rise
before the input to the drain of the n-MOSFET, the
MAX8563/MAX8564/MAX8564A drive DRV_ high but the
output does not rise. As DRV_ rails and VFB_ is still below
80% of the regulation voltage, the MAX8563/MAX8564/
MAX8564A assume that an output short-circuit fault is
present and shut down that regulator. To avoid this error
condition, connect a resistor-divider from VDD to IN_ with
the middle node connected to the respective EN_ (see
Figure 4). Use the following equations to calculate the
resistor values.
When VIN_ is off or at a low-voltage state:
⎛ RE ⎞
0.7 > ⎜
⎟ × VDD − VIN _ + VIN _
⎝ RE + RD ⎠
(
)
When VIN_ is on or at a high-voltage state:
_______________________________________________________________________________________
9
MAX8563/MAX8564/MAX8564A
Detailed Description
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
VDD
MAX8563
MAX8564
MAX8564A
RD
EN_
RE
The POK_ is an open-drain output that provides the status of the output voltage and pulls low depending upon
circuit conditions. During startup, once the FB_ reaches
the POK_ threshold, the POK_ signal goes high. The
POK_ threshold has 30mV of hysteresis. When the output voltage drops 12% below the nominal regulated
voltage, POK_ pulls low. All POK_ outputs pull low
when UVLO is activated or when the internal VL regulator and reference are not ready.
IN_
Figure 4. Voltage-Divider on EN_
⎛ RE ⎞
1.3 < ⎜
⎟ × VDD − VIN _ + VIN _
⎝ RE + RD ⎠
(
)
Set RD = 100kΩ. The above equations also assume that
VDD > VIN_ > 1V when VIN_ is on or at a high-voltage
state, and that VDD > 3V.
Example: Connect 100kΩ from EN to VDD and 4kΩ from
EN_ to IN_. Thus, when VDD = 12V and VIN_ = 0V, then
VEN_ = 0.46V. When VDD = 12V and VIN_ = 1.2V, then
VEN_ = 1.6V.
Alternately, to avoid fault shutdown due to the delay of
VIN relative to VDD, pull EN_ low with a separate control
logic and only drive high when VIN reaches a steadystate value.
Output Voltage
The output voltage range at the source of the n-MOSFET
is from 0.5V to 3.3V when VDD is 12V and from 0.5V to
1.8V when VDD is 5V. The maximum output voltage is a
function of the minimum gate-to-source voltage (VGS) of
the MOSFET and VDD.
The external n-MOSFET contains a parasitic diode from
source to drain. If the output is ever anticipated to
exceed the input, current flows from source to drain. If
this is undesirable, external protection is needed. A
simple solution is the placement of a diode in series,
from IN_ to the drain of the n-MOSFET, so that reverse
current is not possible. Due to the forward-voltage drop
of the diode, the maximum output voltage is reduced
and additional power is consumed in the diode.
Output Undervoltage and
Overload Protection
When an overload event or short circuit occurs, the
device that is most vulnerable is the external n-MOSFET.
The MAX8563/MAX8564/MAX8564A monitor the output
voltage to protect the MOSFET. When DRV_ is at its maximum voltage and the output voltage drops below 80%
but is still greater than 60% of its nominal voltage for
more than 50µs, the MAX8563/MAX8564/MAX8564A
shut down that particular regulator output by pulling
DRV_ to GND. Note that there is an additional inherent
delay in turning off the MOSFET. The delay is a function
of the compensation capacitor and the MOSFET. If the
output recovers to greater than 80% within 50µs, it is not
considered to be in overload and no action is taken.
When the output voltage drops below 60% of its nominal
voltage, the MAX8563/MAX8564/MAX8564A immediately
shut down that particular regulator output by pulling
DRV_ to GND. To restart that particular LDO, VDD must
be recycled below the UVLO or the corresponding EN_
must be recycled. The overload protection is shown in
the Typical Operating Characteristics.
Design Procedure
Output Voltage Setting
The minimum output voltage for each controller of the
MAX8563/MAX8564/MAX8564A is typically 0.5V. The
maximum output voltage is adjustable up to 3.3V with
VDD = 12V, and up to 1.8V with VDD = 5V. To set the output voltage, connect the FB_ pin to the center of a voltage-divider between OUT_ and GND (Figure 5). The
resistor-divider current should be at least 1mA per 1A of
maximum output current; i.e., for a 3A maximum output
current, set the resistor-divider bias current to ≥ 3mA:
IOUT(MIN) ≥
Enable and POK
The MAX8563/MAX8564/MAX8564A have independent
enable control inputs (EN1, EN2, and EN3). Drive EN1
high to enable output 1. Drive EN2 high to enable output 2. Drive EN3 high to enable output 3. When EN_ is
driven low, the corresponding DRV_ is internally pulled
to GND and POK_ is internally pulled low.
10
RB ≤
IOUT(MAX)
1000
VFB
VFB
500
= 1000 ×
=
IOUT(MIN)
IOUT(MAX)
IOUT(MAX)
______________________________________________________________________________________
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
To set the output voltage to 0.5V, disconnect RB from
FB_ and connect it to OUT_; this change maintains the
minimum load requirement on the output. In this case,
RA can vary from 1kΩ to 10kΩ.
OUT_
MAX8563
MAX8564
MAX8564A
RA
FB_
RB
Input and Output Capacitor Selection
The input filter capacitor aids in providing low input
impedance to the regulator and also reduces peak currents drawn from the power source during transient
conditions. Use a minimum 2.2µF ceramic capacitor
from IN_ (drain of the external pass n-MOSFET) to GND
(see Figures 1 and 2). If large line transients or load
transients are expected, increase the input capacitance to help minimize output voltage changes.
The output filter capacitor and its equivalent series
resistance (ESR) contribute to the stability of the regulator (see the Stability Compensation section) and affect
the load-transient response. If large step loads (no load
to full load) are expected, and a very fast response
(less than a few microseconds) is required, use a
100µF, 18mΩ POSCAP for the output capacitor. If a
larger capacitance is desired, keep the capacitance
ESR product (COUT x RESR) in the 1µs to 5µs range.
If the application expects smaller load steps (less than
50% of full load), then use a 6.8µF ceramic capacitor or
larger per ampere of maximum output current. This
option reduces the size and cost of the regulator circuit.
Note that some ceramic dielectrics exhibit large capacitance variation with temperature. Use X7R or X5R
dielectrics to ensure sufficient capacitance at all operating temperatures. Tantalum and aluminum capacitors
are not recommended.
Power MOSFET Selection
The MAX8563/MAX8564/MAX8564A use an n-channel
MOSFET as the series pass transistor instead of a pchannel MOSFET to reduce cost. The selected MOSFET must have a gate threshold voltage that meets the
following criteria:
VGS_MAX ≤ VDD - VOUT_
where VDD is the controller bias voltage, and VGS_MAX
is the maximum gate voltage required to yield the onresistance (RDS_ON) specified by the manufacturer’s
data sheet. RDS_ON multiplied by the maximum output
Figure 5. Adjustable Output Voltage
current (load current) is the maximum voltage dropout
across the MOSFET, VDS_MIN. Make sure that VDS_MIN
meets the condition below to avoid entering dropout,
where output voltage starts to decrease and any ripple
on the input also passes through to the output:
VIN_MIN > VDS_MIN + VOUT
where VIN_MIN is the minimum input voltage at the drain
of the MOSFET. VDS_MIN has a positive temperature
coefficient; therefore, the value of VDS_MIN at the highest
operating junction temperature should be used.
For thermal management, the maximum power dissipation in the MOSFET is calculated by:
PD = (VIN_MAX - VOUT) x IOUT_MAX
The MOSFET is typically in an SMT package. Refer to
the MOSFET data sheet for the PC board area needed
to meet the maximum operating junction temperature
required.
Stability Compensation
Connect a resistor, RC, and a capacitor, CC, in series
from the DRV_ pin to GND. The values of the compensation network depend upon the external MOSFET
characteristics, the output current range, and the programmed output voltage. The following parameters are
needed from the MOSFET data sheet: the input capacitance (CISS at VDS = 1V), the typical forward transconductance (g FS ), and the current at which g FS was
measured (IDFS). Calculate the transconductance of
the FET at the maximum load current (IOUT_MAX):
gC(MAX) = gFS ×
IOUT _ MAX
IDFS
______________________________________________________________________________________
11
MAX8563/MAX8564/MAX8564A
⎡⎛ V
⎤
⎞
RA = RB × ⎢⎜ OUT ⎟ − 1⎥ = RB × (2 × VOUT − 1)
⎢⎣⎝ VFB ⎠
⎥⎦
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
For the best transient response in applications with
large step loads (see the Input and Output Capacitor
Selection section for output capacitance requirements),
use the following equations to select the compensation
components:
⎡0.16 × VOUT × COUT ×
⎤
⎢
⎥
⎢⎣gC(MAX) × gC(MAX) × RESR + 1 ⎥⎦
CC =
2
gC(MAX) × VOUT + IOUT _ MAX
(
(
RC = 59 ×
)
(
)
CC = 0.16 x
−
CISS
RC = 59 x
)
CC x gC(MAX) × VOUT + IOUT _ MAX
COUT x gC(MAX)
gC(MAX) x VOUT + IOUT _ MAX
(
RC = 15 x
)
−
CISS
COUT
CC x gC(MAX)
Example
OUTPUT 1 of Figure 1 is used in this example. Table 1
shows the values required to calculate the compensation. The values were taken from the appropriate data
sheets and Figure 1.
Table 1. Parameters Required to
Calculate Compensation
PARAMETER CONDITIONS
2
−
VALUE
UNITS
VDS = 1V
2500
pF
MOSFET GFS
IDFS = 8.8A
30
S
VOUT1
Figure 1
1.5
V
IOUT_MAX
Figure 1
1.5
A
COUT1
Figure 1
100
µF
RESR
Figure 1
18
mΩ
1.5V x 100μF x (12.4S x 18mΩ + 1)
1μF(12.4S x 1.5V + 1.5A )
PC Board Layout Guidelines
Due to the high-current paths and tight output accuracy
required by most applications, careful PC board layout is
required. An evaluation kit (MAX8563EVKIT) is available
to speed design.
It is important to keep all traces as short as possible to
maximize the high-current trace dimensions to reduce the
effect of undesirable parasitic inductance. The MOSFET
dissipates a fair amount of heat due to the high currents
involved, especially during large input-to-output voltage
differences. To dissipate the heat generated by the
MOSFET, make power traces very wide with a large
amount of copper area. An efficient way to achieve good
power dissipation on a surface-mount package is to lay
out copper areas directly under the MOSFET package on
multiple layers and connect the areas through vias. Use a
ground plane to minimize impedance and inductance. In
addition to the usual high-power considerations, here are
four tips to ensure high output accuracy:
•
•
MOSFET CISS
12
x 1.5V + 1.5A )
= 599.4Ω, use 620Ω.
)
where COUT is the output capacitance and RESR is the
ESR of COUT.
To use a low-cost ceramic capacitor (see the Input and
Output Capacitor Selection section for load-transient
response characteristics), use the following equations
to select the compensation components:
CC =
(12.4S
2500pF = 0.90μF, use 1μF.
VOUT x COUT gC(MAX) x RESR + 1
(
1.5A
= 12.4S
8.8A
⎛12.4S x ⎞
1.5V x 100μF x 12.4S x ⎜
⎟
⎝18mΩ + 1⎠
gC(MAX) = 30S x
•
•
Ensure that the feedback connection to COUT_ is
short and direct.
Place the feedback resistors next to the FB pin.
Place RC and CC next to the DRV_ pin.
Ensure FB_ and DRV_ traces are away from noisy
sources to ensure tight accuracy.
______________________________________________________________________________________
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
TOP VIEW
DRV1 1
16 VDD
FB1 2
15 DRV2
EN1 3
14 FB2
POK1 4
MAX8563
13 EN2
12 POK2
GND 5
DRV1 1
FB1
10 VDD
2
MAX8564
MAX8564A
9
DRV2
8
FB2
N.C. 6
11 N.C.
EN1
3
DRV3 7
10 POK3
POK1
4
7
EN2
GND
5
6
POK2
9
FB3 8
QSOP
EN3
μMAX
Chip Information
TRANSISTOR COUNT: 1801
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX8563/MAX8564/MAX8564A
Pin Configurations
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX8563/MAX8564/MAX8564A
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
14
______________________________________________________________________________________
F
1
1
±1%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
10LUMAX.EPS
e
4X S
10
10
INCHES
H
Ø0.50±0.1
0.6±0.1
1
1
0.6±0.1
BOTTOM VIEW
TOP VIEW
D2
MILLIMETERS
MAX
DIM MIN
0.043
A
0.006
A1
0.002
A2
0.030
0.037
D1
0.120
0.116
0.118
D2
0.114
E1
0.116
0.120
0.118
E2
0.114
0.199
H
0.187
L
0.0157 0.0275
L1
0.037 REF
b
0.007
0.0106
e
0.0197 BSC
c
0.0035 0.0078
0.0196 REF
S
α
0°
6°
MAX
MIN
1.10
0.15
0.05
0.75
0.95
3.05
2.95
2.89
3.00
3.05
2.95
2.89
3.00
4.75
5.05
0.40
0.70
0.940 REF
0.177
0.270
0.500 BSC
0.090
0.200
0.498 REF
0°
6°
E2
GAGE PLANE
A2
c
A
b
A1
α
E1
L
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0061
REV.
1
1
Revision History
Pages changes at Rev 2: 1, 12, 14, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX8563/MAX8564/MAX8564A
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
工商网监
湘ICP备2023018690号
