MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
General Description
Features
The MAX8952 high-efficiency DC-to-DC step-down
switching regulator delivers up to 2.5A of output current.
The device operates from a 2.5V to 5.5V input voltage
range, supporting commonly-used battery technologies
in handsets. The output voltage is I2C programmable
from 0.77V to 1.40V. Remote sense ensures precise DC
regulation at the load. Total output error is less than
±1.5% over load, line, and temperature.
The IC operates at a 3.25MHz fixed frequency. The high
operating frequency minimizes the size of external components. The switching frequency of the converter can be
synchronized to the master clock of the application. When
synchronizing to an external clock, the IC measures the
frequency of the external clock to ensure that the clock is
stable before changing the switching frequency to the
external clock frequency.
An on-board DAC allows adjustment of the output voltage in 10mV steps. The output voltage can be programmed directly through the I 2 C interface, or by
preloading a set of on-board registers and using the
two VID logic signals to select the appropriate register.
Other features include internal soft-start control circuitry
to reduce inrush current, output overvoltage, overcurrent, and overtemperature protection.
o 2.5A Guaranteed Output Current
o I2C Programmable VOUT (770mV to 1.40V in 10mV
Steps)
o Initial Accuracy ±0.5% at 1.40V Output
o ±1.5% Output Accuracy Over Load, Line, and
Temperature (DCR ≤ 38.5mΩ)
o Power-Save Mode Increases Light Load Efficiency
o Fixed 3.25MHz PWM Switching Frequency
o Small 1.0µH Inductor
o Synchronizes to 13MHz, 19.2MHz, or 26MHz
System Clock When Available
o Overvoltage and Overcurrent Protection
o Operates from 2.5V to 5.5V Input Supply
o Thermal Shutdown Protection
o On-Chip FET and Synchronous Rectifier
o 400kHz I2C Interface
o < 1µA Shutdown Current
o 16-Bump, 2mm x 2mm WLP Package
Applications
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8952EWE+T
-40°C to +85°C
16-Bump WLP
(0.5mm pitch)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Cell Phones and Smartphones
PDAs and MP3 Players
Visit www.maximintegrated.com/products/patents for
product patent marking information.
Tablet PCs
Typical Operating Circuit
Bump Configuration
TOP VIEW
(BUMPS ON BOTTOM)
+
IN1
AGND
VID1
IN2
A1
A2
A3
A4
SNS+
EN
LX
LX
B1
B2
B3
B4
SNS-
VID0
PGND
PGND
C1
C2
C3
C4
VDD
SDA
SCL
SYNC
1.8V TO
3.6V
2.5V TO
5.5V
MAX8952
IN2
VDD
10µF
1µH
LX
SCL
11Ω
10µF
0.1µF
0.1µF
2.5V TO
5.5V
10µF
SDA
0.1µF
VOUT
(0.77V TO
1.40V)
PGND
IN1
D1
D2
D3
D4
2.2µF
0.1µF
SYNC
SNS+
EN
VID0
CPU
SNS-
VID1
AGND
WLP 0.5mm PITCH
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5318; Rev 1; 6/11
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
ABSOLUTE MAXIMUM RATINGS
IN1, IN2 to AGND ..................................................-0.3V to +6.0V
VDD to AGND.........................................................-0.3V to +4.0V
LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (VIN1 + 0.3V)
SCL, SDA, SYNC to AGND.........................-0.3V to (VDD + 0.3V)
PGND, SNS- to AGND...........................................-0.3V to +0.3V
RMS LX Current ..............................................................2500mA
Continuous Power Dissipation (TA = +70°C)
16-Bump WLP 0.5mm Pitch
(derate 20.4mW/°C above +70°C) .........................1632mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (θJA) ...........49°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7 using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
MAX
UNITS
IN1, IN2 Operating Range
PARAMETER
2.5
5.5
V
VDD Operating Range
1.8
3.6
V
1.35
V
VDD Undervoltage Lockout
(UVLO) Threshold
CONDITIONS
MIN
VDD falling
0.54
VDD UVLO Hysteresis
IN_ Undervoltage Lockout
(UVLO) Threshold
TYP
0.865
50
VIN_ falling
2.10
IN_ UVLO Hysteresis
2.15
mV
2.20
70
VDD Shutdown Supply Current
VIN1 = VIN2 = 5.5V,
EN = VDD = AGND
TA = +25°C
0.01
TA = +85°C
0.01
IN1, IN2 Shutdown Supply
Current
VIN1 = VIN2 = 5.5V,
EN = VDD = AGND
TA = +25°C
0.25
TA = +85°C
0.25
IN1, IN2 Standby Supply Current
VIN1 = VIN2 = 5.5V, SCL = SDA =
VDD, EN = AGND, I2C ready
VDD Standby Supply Current
TA = +25°C
0.35
TA = +85°C
0.35
VIN1 = VIN2 = VDD = 3.6V,
SCL = SDA = VDD, EN = AGND,
I2C ready
TA = +25°C
0.02
TA = +85°C
0.02
Logic Input High Voltage (VIH)
VIN1 = VIN2 = 2.5V to 5.5V,
VDD = 1.8V to 3.6V
EN, VID0, VID1
Logic Input Low Voltage (VIL)
VIN1 = VIN2 = 2.5V to 5.5V,
VDD = 1.8V to 3.6V
EN, VID0, VID1
SDA, SCL, SYNC Logic Input
Current
VIL = 0V or VIH = 3.6V,
EN = AGND
V
mV
1
1
1
µA
µA
µA
1
µA
LOGIC INTERFACE
2
SYNC, SCL, SDA
1.4
V
0.7 x VDD
0.4
SYNC, SCL, SDA
TA = +25°C
TA = +85°C
0.3 x VDD
-1
0.01
0.01
+1
V
µA
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
320
450
kΩ
2
VID0, VID1, EN Logic Input
Pulldown Resistor
Controlled by I C command:
VID0_PD = 1
VID1_PD = 1
EN_PD = 1
I2C INTERFACE
SDA Output Low Voltage
ISDA = 3mA
0.03
I2C Clock Frequency
0.4
V
400
kHz
Bus-Free Time Between START
and STOP
tBUF
1.3
Hold Time REPEATED START
Condition
tHD_STA
0.6
0.1
µs
SCL Low Period
tLOW
1.3
0.2
µs
SCL High Period
tHIGH
0.6
0.2
µs
Setup Time REPEATED START
Condition
tSU_STA
0.6
0.1
µs
SDA Hold Time
tHD_DAT
0
-0.01
µs
SDA Setup Time
tSU_DAT
0.1
0.05
µs
Setup Time for STOP Condition
tSU_STO
0.6
0.1
µs
µs
STEP-DOWN DC-DC REGULATOR
IN1 + IN2
Supply Current
FPWM_EN_ = 0, VOUT = 1.27V, no switching
54
FPWM_EN_ = 1, VOUT = 1.27V, fsw = 3.25MHz
9
mA
Minimum Output Capacitance
Required for Stability
VOUT = 0.77V to 1.40V,
IOUT = 0 to 2.5A
10
µF
OUT Voltage Range
10mV steps
0.770
Output Overvoltage Protection
Rising, 50mV hysteresis (typ)
1.65
Maxim Integrated
1.8
80
µA
1.400
V
1.9
V
3
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
OUT Voltage Accuracy
Load Regulation
RAMP Timer
CONDITIONS
MIN
TYP
MAX
No load, VIN_ = 2.5V to 5.5V, VOUT = 1.27V,
FPWM_EN_ = 1
-0.5
+0.5
No load, VIN_ = 2.5V to 5.5V, VOUT = 0.77V,
FPWM_EN_ = 1
-1.0
+1.0
No load, VIN_ = 2.5V to 5.5V, VOUT = 1.40V,
FPWM_EN_ = 1
-0.5
+0.5
RL is the resistance from LX to SNS+ (output)
RL/25
RAMP[2:0] = 000
32.50
RAMP[2:0] = 001
16.25
RAMP[2:0] = 010
8.125
RAMP[2:0] = 011
4.063
RAMP[2:0] = 100
2.031
RAMP[2:0] = 101
1.016
RAMP[2:0] = 110
0.508
RAMP[2:0] = 111
0.254
Peak Current Limit
(p-Channel MOSFET)
UNITS
%
V/A
mV/µs
3.45
4.2
4.8
A
Valley Current Limit
(n-Channel MOSFET)
Hysteretic mode
2.7
3.6
4.5
A
Negative Current Limit
(n-Channel MOSFET)
PWM mode
2.0
2.5
3.0
A
n-Channel Zero-Crossing
Threshold
50
mA
LX pFET On-Resistance
IN2 to LX, ILX = -200mA
0.08
0.16
Ω
LX nFET On-Resistance
FPWM_EN_ = 0,
LX to PGND, ILX = 200mA
0.06
0.12
Ω
LX Leakage
VLX = 5.5V or 0V
0.03
+1
Operating Frequency
4
TA = +25°C
-1
TA = +85°C
0.05
Internal oscillator, PWM mode
2.82
3.25
3.56
Internal oscillator, power-save mode before entering
PWM mode
2.43
3.25
4.06
13MHz = fSYNC, SYNC[1:0] = 01
fSYNC/4
19.2MHz = fSYNC, SYNC[1:0] = 10 or 11
fSYNC/6
26MHz = fSYNC, SYNC[1:0] = 00
fSYNC/8
µA
MHz
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
Minimum Duty Cycle
CONDITIONS
MIN
Maximum Duty Cycle
60
Minimum On- and Off-Time
30
OUT Discharge Resistance
TYP
Forced-PWM mode (FPWM_EN = 1),
minimum duty cycle = 0%
During shutdown or UVLO, from SNS+ to PGND
MAX
UNITS
16
%
50
ns
%
40
Ω
650
SNS+, SNS- Input Impedance
VOUT = 0.77V (OUT_MODEx [5:0] = 0b000000)
Time Delay from PWM
to Power-Save Mode
Time required for error amplifier to stabilize before
switching mode
70
µs
Time Delay from Power-Save
Mode to PWM
Time required for error amplifier to stabilize before
switching mode
140
µs
400
600
850
kΩ
SYNCHRONIZATION (SYNC)
SYNC Capture Range
SYNC Pulse Width
SYNC[1:0] = 00
18.9
26.0
SYNC[1:0] = 1X
14.2
19.2
38.0
28.5
SYNC[1:0] = 01
9.5
13.0
19.0
MHz
13
ns
20
°C
+160
°C
PROTECTION CIRCUITS
Thermal-Shutdown Hysteresis
Thermal Shutdown
Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design.
Maxim Integrated
5
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
60
VIN = 3.2V
3.6V
4.2V
50
40
30
FORCED PWM
40
0.001
0.01
0.1
1
20
0.001
0.01
0.1
1
0
0.0001
10
0.001
0.01
0.1
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, 26MHz SYNC)
EFFICIENCY vs. LOAD CURRENT
(1.4V OUTPUT, 26MHz SYNC)
40
70
60
40
30
30
20
20
FORCED PWM
10
0.001
0.01
0.1
VIN = 3.2V
3.6V
4.2V
50
80
70
60
VIN = 3.2V
3.6V
4.2V
50
40
20
FORCED PWM
0
0.0001
10
TRANSITION TO PWM
POWER SAVE
90
30
10
1
100
EFFICIENCY (%)
VIN = 3.2V
3.6V
4.2V
POWER SAVE
80
EFFICIENCY (%)
60
TRANSITION TO PWM
90
MAX8952 toc05
MAX8952 toc04
70
50
100
0.001
0.01
0.1
FORCED PWM
10
1
0
0.0001
10
0.001
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
SWITCHING FREQUENCY
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (POWER SAVE)
1.5
POWER SAVE
1.0
0
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
3.4
3.3
3.2
2.5
MAX8952 toc09
10
0.5
0.4
26MHz SYNC
0.3
0.2
NO SYNC
3.1
VIN = 3.6V
VOUT = 1.4V
0.5
3.5
SUPPLY CURRENT (mA)
TRANSITION TO PWM
2.0
0.6
MAX8952 toc08
FORCED PWM
2.5
3.6
SWITCHING FREQUENCY (MHz)
MAX8952 toc07
3.5
10
1
EFFICIENCY vs. LOAD CURRENT
(1.0V OUTPUT, 26MHz SYNC)
80
0
FORCED PWM
LOAD CURRENT (A)
POWER SAVE
3.0
40
LOAD CURRENT (A)
TRANSITION TO PWM
0
0.0001
VIN = 3.2V
3.6V
4.2V
50
LOAD CURRENT (A)
100
90
60
10
0
0.0001
10
70
30
FORCED PWM
10
0
0.0001
EFFICIENCY (%)
VIN = 3.2V
3.6V
4.2V
20
10
SWITCHING FREQUENCY (MHz)
60
50
80
30
20
6
70
TRANSITION TO PWM
POWER SAVE
90
MAX8952 toc03
80
100
MAX8952 toc06
70
TRANSITION TO PWM
POWER SAVE
90
EFFICIENCY (%)
EFFICIENCY (%)
80
100
EFFICIENCY (%)
TRANSITION TO PWM
POWER SAVE
90
MAX8952 toc01
100
EFFICIENCY vs. LOAD CURRENT
(1.4V OUTPUT, SYNC OFF)
EFFICIENCY vs. LOAD CURRENT
(1.1V OUTPUT, SYNC OFF)
MAX8952 toc02
EFFICIENCY vs. LOAD CURRENT
(1.0V OUTPUT, SYNC OFF)
0.1
NO SYNC
1.3V OUTPUT, 500mA LOAD
0
3.0
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
OUTPUT VOLTAGE vs. LOAD CURRENT
OUTPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
14
12
26MHz SYNC
10
TA = +25°C
1.41
8
6
TA = +85°C
1.40
1.39
TA = -40°C
POWER SAVE
1.38
1.110
OUTPUT VOLTATGE (V)
NO SYNC
16
OUTPUT VOLTAGE vs. LOAD CURRENT
1.115
MAX8952 toc11
18
1.42
MAX8952 toc10
20
MAX8952 toc12
NO-LOAD SUPPLY CURRENT vs.
SUPPLY VOLTAGE (FORCED PWM)
FORCED PWM
1.105
1.100
1.095
POWER SAVE
4
1.37
2
0
1.090
VIN = 3.6V
VOUT = 1.4V
1.36
2.5
3.5
5.5
4.5
1.085
0
0.5
1.0
SUPPLY VOLTAGE (V)
1.5
2.5
2.0
0
0.5
LOAD CURRENT (A)
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
LIGHT LOAD SWITCHING WAVEFORMS
OUTPUT VOLTAGE vs. LOAD CURRENT
MAXMAX8952 toc14
MAX8952 toc13
1.010
FORCED PWM
1.005
OUTPUT VOLTATGE (V)
VIN = 3.6V
VOUT = 1.1V
VOUT
20mV/div
1.000
VLX
2V/div
0.995
0.990
POWER SAVE
0.985
IL
VIN = 3.6V
VOUT = 1.0V
0.980
0
0.5
1.0
1.5
2.0
200mA/div
10mA LOAD, VOUT = 1.3V
2.5
2µs/div
LOAD CURRENT (A)
MEDIUM LOAD SWITCHING
WAVEFORMS
HEAVY LOAD SWITCHING WAVEFORMS
MAX8952 toc16
MAX8952 toc15
VOUT
20mV/div
VLX
IL
2V/div
500mA LOAD
VOUT = 1.3V
500mA/div
200ns/div
Maxim Integrated
20mV/div
VOUT
VLX
IL
2V/div
1A/div
1.8A LOAD
VOUT = 1.3V
200ns/div
7
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
LIGHT LOAD STARTUP WAVEFORMS
HEAVY LOAD STARTUP WAVEFORMS
10I LOAD
1I LOAD
MAX8952 toc17
VOUT
MAX8952 toc18
1V/div
IIN
VOUT
400mA
1V/div
100mA/div
IIN
200mA/div
IL
500mA/div
500mA/div
IL
VEN
5V/div
VEN
5V/div
200µs/div
200µs/div
PREBIAS STARTUP WAVEFORMS
(FORCED PWM)
LINE TRANSIENT RESPONSE (4.2V TO
3.2V TO 4.2V), SYNC OFF
MAX8952 toc19
MAX8952 toc20
OUTPUT PREBIASED TO 1.3V
STARTUP TO 1.1V
VOUT
1V/div
VIN
500mV/div
VOUT
IL
20mV/div
1A/div
200mA/div
IL
VEN
300mA LOAD
5V/div
200µs/div
20µs/div
LINE TRANSIENT RESPONSE (4.2V TO
3.2V TO 4.2V), 26MHz SYNC
LOAD TRANSIENT RESPONSE
(1mA TO 1A)
MAX8952 toc21
MAX8952 toc22
1V/div
VIN
VOUT
50mV/div
VOUT
20mV/div
IL
500mA/div
IL
200mA/div
300mA LOAD
8
1A/div
IOUT
20µs/div
40µs/div
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25°C, unless otherwise noted.)
LOAD TRANSIENT RESPONSE
(1A to 1mA)
LOAD TRANSIENT RESPONSE
(5mA TO 1.8A)
MAX8952 toc23
MAX8952 toc24
50mV/div
VOUT
VOUT
50mV/div
IL
500mA/div
IOUT
IL
1A/div
1A/div
1A/div
IOUT
40µs/div
40µs/div
LOAD TRANSIENT RESPONSE
(1.8A to 5mA)
SYNCHRONIZATION RESPONSE
(26MHz SYNC)
MAX8952 toc26
MAX8952 toc25
FORCED PWM, NO LOAD
VSYNC
VOUT
100mV/div
IL
2V/div
VOUT
20mV/div
1A/div
VLX
IOUT
2V/div
IL
1A/div
200mA/div
1µs/div
20µs/div
OUTPUT VOLTAGE CHANGE RESPONSE
MAX8952 toc27
10I LOAD,
POWER SAVE
32mV/µs RAMP
VVID0
2V/div
1.3V
0.9V
0.9V
VOUT
500mV/div
IL
200mA/div
40µs/div
Maxim Integrated
9
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Bump Description
10
PIN
NAME
FUNCTION
A1
IN1
A2
AGND
A3
VID1
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
A4
IN2
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 2x 10µF and 0.1µF ceramic
capacitor as close as possible to the IC. Connect IN1 and IN2 to the same power source.
B1
SNS+
Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.
B2
EN
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.
B3, B4
LX
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel
MOSFETs. LX is high impedance during shutdown.
C1
SNS-
Output Voltage Sense, Negative Input. Connect to a quiet ground directly at the IC.
C2
VID0
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
C3, C4
PGND
Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Install an 11Ω resistor between
IN1 and the input supply. Bypass the IN1 to AGND with a 0.1µF ceramic capacitor as close as
possible to the IC. Connect IN1 and IN2 to the same power source.
Analog Ground. Connect AGND to the PCB ground plane.
Power Ground. Connect both PGND bumps to the PCB ground plane.
D1
VDD
Logic Input Supply Voltage. Connect VDD to the logic supply driving SDA, SCL, and SYNC. Bypass
VDD to AGND with a 0.1µF ceramic capacitor. When VDD drops below the UVLO threshold, the I2C
registers are reset, but the EN control is still active in this mode.
D2
SDA
I2C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.
D3
SCL
I2C Clock Input
D4
SYNC
External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.
The DC-DC regulator can be forced to synchronize to this external clock depending on I2C setting. See
Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
SYNC
OSC
CLOCK GEN
IN2
VDD
SCL
I2C INTERFACE
LX
PWM LOGIC
SDA
IN1
PGND
EN
VID0
VID1
IN1
VDAC
VOLTAGE
CONTROL, VREF,
BIAS, ETC.
SNS+
AGND
SNS-
Figure 1. Block Diagram
Detailed Description
The MAX8952 high-efficiency, 3.25MHz step-down
switching regulator delivers up to 2.5A of output current. The device operates from a 2.5V to 5.5V input
voltage range, and the output voltage is I2C programmable from 0.77V to 1.40V in 10mV increments.
Remote sense ensures precise DC regulation at the
load. Total output error is less than ±1.5% over load,
line, and temperature.
Dynamic Voltage Scaling
The output voltage is dynamically adjusted by use of
the VID0 and VID1 logic inputs, allowing selection
between four predefined operation modes/voltage
configurations.
For each of the different output modes, the following
parameters are programmable:
• Output voltage from 0.77V to 1.40V in 10mV steps
•
•
Mode of operation: Forced PWM or power save
Enable/disable of synchronization of switching
frequency to external clock source
The relation between the VID0/VID1 and operation
mode is given by Table 1.
The VID_ inputs have internal pulldown resistors. These
pulldown resistors can be disabled through the CONTROL register after the IC is enabled, achieving lowest
possible quiescent current. When EN is low, the CONTROL register is reset to default, enabling the pulldown
resistors.
Table 1. VID0 and VID1 Configuration
VID1
VID0
MODE
I2C REGISTER
DEFAULT
SWITCHING
MODE
DEFAULT
SYNCHRONIZATION
DEFAULT
OUTPUT
VOLTAGE (V)
0
0
MODE0
Table 3
POWER SAVE
OFF
1.40
0
1
MODE1
Table 4
POWER SAVE
OFF
1.00
1
0
MODE2
Table 5
POWER SAVE
OFF
1.40
1
1
MODE3
Table 6
POWER SAVE
OFF
1.10
Maxim Integrated
11
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Enable
The MAX8952 DC-DC step-down regulator is
enabled/disabled using the EN logic input. The EN
input is able to handle input voltages up to VIN1, ensuring that the EN logic input can be controlled by a wide
variety of signals/supplies.
The EN input has an internal pulldown resistor that
ensures EN is discharged during off conditions. This pulldown resistor can be disabled through the CONTROL
register (see Table 7) once the IC is enabled, achieving
lowest possible quiescent current. When EN is low, the
CONTROL register is reset to default, enabling the pulldown resistors on EN, VID0, and VID1. See Figures 2
and 3 for detailed information on power-up and powerdown sequencing and operation mode changes.
DC-DC Regulator Operating Modes
The IC operates in one of four modes determined by
the state of the VID_ inputs (see Table 1). At power-up,
the IC is set to operate in power-save operation for
MODE0 through MODE3. For each of the operation
modes, the DC-DC step-down regulator can be set to
operate in either power-save mode or forced-PWM
mode. This is done by writing to the MODE_ registers
(see Table 3 to Table 6). The mode of operation can be
changed at any time.
A
B
In power-save mode, the MAX8952 PWM switching frequency depends on the load current. For medium to
high load condition, the IC operates in fixed-frequency
PWM mode. For light load conditions, the IC operates
in hysteretic mode. The proprietary hysteretic PWM
control scheme ensures high efficiency, fast switching,
and fast transient response. This control scheme is
simple: when the output voltage is below the regulation threshold, the error comparator begins a switching
cycle by turning on the high-side switch. This switch
remains on until the minimum on-time expires and the
output voltage is above the regulation threshold plus
hysteresis or the inductor current is above the currentlimit threshold. Once off, the high-side switch remains
off until the minimum off-time expires and the output
voltage falls again below the regulation threshold.
During the off period, the low-side synchronous rectifier turns on and remains on until either the high-side
switch turns on again or the inductor current
approaches zero. The internal synchronous rectifier
eliminates the need for an external Schottky diode.
The transition between PWM and hysteretic operation is
based on the number of consecutive zero-crossing
cycles. When more than 16 consecutive zero-crossing
cycles are detected, the DC-DC step-down converter
enables the bias for hysteretic operation. Once correctC
D
E
IN_
1.40V
1.40V
1.10V
OUT
EN
VID1
VID0
VDD
A: POWER CONNECTED TO IN1 AND IN2.
B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I2C REGISTER FOR MODE0 (SEE TABLE 1).
C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I2C REGISTER FOR MODE2.
D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I2C REGISTER FOR MODE3.
E: VDD PULLED HIGH, ENABLING I2C INTERFACE.
Figure 2. Power-Up Sequence
12
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
A
B
IN_
OUT
EN
VDD
A: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE.
B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.
Figure 3a. Shutdown by Pulling VDD Low Before EN
A
B
IN_
OUT
EN
VDD
A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I2C READY MODE, OUTPUT DISABLED.
B: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3b. Shutdown by Pulling EN Low Before VDD
A
IN_
OUT
EN
VDD
A: IN_ DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3c. Shutdown Due to IN1 Undervoltage Lockout
Maxim Integrated
13
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
ly biased and the number of consecutive zero-crossing
cycles exceeds 24, the DC-DC step-down converter
begins hysteretic operation.
During hysteretic operation, there is a silent DC offset
due to the use of valley regulation. See Figure 4.
When operating in power-save mode and the load current is increased so that the number of consecutive
zero-crossing cycles is less than 16, the PWM mode is
biased. Once fully biased and the number of zerocrossing cycles drops below 8, the DC-DC converter
then begins PWM operation. Since there is a delay
between the increase in load current and the
DC-DC converter starting PWM, the converter supports
full current on the output during hysteretic operation.
See Figure 5 for a detailed state diagram.
Power-save operation offers improved efficiency at light
loads by changing to hysteretic mode, reducing the
REGULATION
THRESHOLD
OUTPUT
RIPPLE
Figure 4. Output Regulation in Hysteretic Operation
switching frequency depending on the load condition.
With moderate to heavy loading, the regulator switches
at a fixed switching frequency as it does in forced-PWM
mode. In power-save mode, the transition from hysteretic mode to fixed-frequency switching occurs at the
load current specified in the following equation:
V −V
VOUT
IOUT = IN OUT ×
2×L
VIN × fOSC
In forced-PWM mode, the regulator operates with a
constant (3.25MHz or synchronized to external clock
source) switching frequency regardless of output load.
Forced-PWM mode is ideal for low-noise systems
because switching harmonics occur at multiples of the
constant switching frequency and are easily filtered.
However, light-load power consumption in forced-PWM
mode is higher than that of power-save mode.
Soft-Start
The IC includes internal soft-start circuitry that eliminates
inrush current at startup, reducing transients on the
input source (see the Typical Operating Charac-
MORE THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
PWM MODE
WITH POWER-SAVE
MODE BIASED
PWM
MODE
POWER SAVE NOT READY
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
AND POWER-SAVE MODE READY
LESS THAN 8 CONSECUTIVE
ZERO-CROSSING CYCLES
AND PWM MODE READY
MORE THAN 24 CONSECUTIVE
ZERO-CROSSING CYCLES
PWM NOT READY
POWER-SAVE
MODE WITH
PWM BIASED
POWER-SAVE
MODE
LESS THAN 16 CONSECUTIVE
ZERO-CROSSING CYCLES
Figure 5. Mode Change for DC-DC Step-Down Converter
14
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
teristics). Soft-start is particularly useful for high-impedance input sources, such as Li+ and alkaline cells.
When enabling the IC into a prebiased output, the IC
performs a complete soft-start cycle.
Synchronous Rectification
An internal n-channel synchronous rectifier eliminates
the need for an external Schottky diode and improves
efficiency. The synchronous rectifier turns on during the
second half of each switching cycle (off-time). During
this time, the voltage across the inductor is reversed,
and the inductor current ramps down. In PWM mode,
the synchronous rectifier turns off at the end of the
switching cycle. In power-save mode, the synchronous
rectifier turns off when the inductor current falls below
50mA (typ) or at the end of the switching cycle,
whichever occurs first.
Ramp-Rate Control
The MAX8952 output voltage has an actively controlled
variable ramp rate, set with the I 2 C interface (see
Figures 6, 7, and 8). The value set in the RAMP register
controls the output voltage ramp rate. The
RAMP_DOWN bit controls the active ramp-down
behavior in power-save mode. When the regulator is set
for power-save mode and the RAMP_DOWN bit is
cleared, the ramp-down is not actively controlled, and
the regulator output voltage ramps down at the rate
determined by the output capacitance and the external
load. Small loads result in an output-voltage decay that
is slower than that specified by RAMP; large loads
result in an output-voltage decay that is no faster than
that specified by RAMP When the RAMP_DOWN bit is
set in power-save mode, the zero-cross comparator is
disabled during the ramp-down condition. Active rampdown functionality is inherent in forced-PWM operation.
Calculate the maximum and minimum values for the
ramp rate as follows:
V
1
tRAMP _ MIN = OUT _ LSB ×
RAMP
_ CODE
tCLK _ MAX 2
V
1
tRAMP _ MAX = OUT _ LSB ×
tCLK _ MIN 2RAMP _ CODE
where:
VOUT _ LSB = 10mV
tCLK _ MAX =
1
fSW _ MIN
tCLK _ MIN =
1
fSW _ MAX
fSW = 3.25MHz ±10% for PWM operation
fSW = 3.25MHz ±25% for hysteretic operation
f
fSW = SYNC
n
OUTPUT
VOLTAGE
DELTA V = 10mV
fSYNC = frequency of external clock
n = 4 for 13MHz, 6 for 19.2MHz, and 8 for 26MHz
VOUT'
RAMP_CODE = value of the RAMP[2:0] register (see
Table 9)
10mV/RAMP RATE
Thermal-Overload Protection
VOUT
TIME
Thermal-overload protection limits total power dissipation in the IC. When internal thermal sensors detect a
Figure 6. Ramp-Up Function
FINAL
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
VOUT
DELTA
V = 10mV
VOUT'
10mV/RAMP
RATE
TIME
Figure 7. Ramp-Down Function
Maxim Integrated
MODE CHANGE
TO HIGHER VOUT
MODE CHANGE
TO LOWER VOUT
Figure 8. Mode Change Before Final Value is Reached
15
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA ALLOWED
Figure 9. I2C Bit Transfer
die temperature in excess of +160°C (typ), the
DC-DC step-down regulator is shut down, allowing the
IC to cool. The DC-DC step-down regulator is turned on
again after the junction cools by 20°C (typ), resulting in
a pulsed output during continuous thermal-overload
conditions.
During thermal overload, the I 2 C interface remains
active and all register values are maintained.
I2C Interface
An I2C-compatible, 2-wire serial interface controls the
step-down converter output voltage, ramp rate, operating mode, and synchronization. The serial bus consists
of a bidirectional serial-data line (SDA) and a serialclock input (SCL). The master initiates data transfer on
the bus and generates SCL to permit data transfer.
I2C is an open-drain bus. SDA and SCL require pullup
resistors (500Ω or greater). Optional (24Ω) in series
with SDA and SCL protect the device inputs from highvoltage spikes on the bus lines. Series resistors also
minimize crosstalk and undershoot on bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse (see Figure 9).
Changes in SDA while SCL is high are control signals
(see the START and STOP Conditions section for more
information).
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9
bits long; 8 bits of data followed by the acknowledge
16
bit. The IC supports data transfer rates with SCL frequencies up to 400kHz.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by
issuing a START condition. A START condition is a
high-to-low transition on SDA with SCL high. A STOP
condition is a low-to-high transition on SDA, while SCL
is high (Figure 10).
A START condition from the master signals the beginning of a transmission to the IC. The master terminates
transmission by issuing a not acknowledge followed by
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 10. I2C START and STOP Conditions
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
SLAVE
TRANSMITTER/RECEIVER
SLAVE RECEIVER
Figure 11. I2C Master/Slave Configuration
a STOP condition (see the Acknowledge section for
more information). The STOP condition frees the bus.
To issue a series of commands to the slave, the master
can issue REPEATED START (Sr) commands instead of
a STOP command to maintain control of the bus. In
general, a REPEATED START command is functionally
equivalent to a regular START command.
When a STOP condition or incorrect address is detected, the IC internally disconnects SCL from the serial
interface until the next START condition, minimizing digital noise and feedthrough.
System Configuration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the message is a receiver. The device that controls the message is the master and the devices that are controlled
by the master are called slaves. See Figure 11.
Acknowledge
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowledge bit. The acknowledge bit is a low-level signal put
on SDA by the receiver during which time the master
generates an extra acknowledge-related clock pulse. A
slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master
receiver must generate an acknowledge after each
byte it receives that has been clocked out of the slave
transmitter. See Figure 12.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the
SDA line is stable low during the high period of the
Maxim Integrated
SDA OUTPUT
FROM TRANSMITTER
D7
D6
D0
NOT ACKNOWLEDGE
SDA OUTPUT
FROM RECEIVER
SCL FROM
MASTER
START CONDITION
ACKNOWLEDGE
1
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 12. I2C Acknowledge
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP condition.
Register Reset
The I2C resisters reset back to their default values when
the voltage at either IN1 or V DD drops below the
corresponding UVLO threshold (see the Electrical
Characteristics table).
Update of Output Operation Mode
If updating the output voltage or Operation Mode register for the mode that the IC is currently operating in, the
17
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
A
B
C
D
E
OUT
SDA
S
SLAVE ID
ASr
REG PTR
ASr
DATA
A
P
VID0
VID1
VDD
A: I2C START COMMAND.
B: I2C SLAVE ADDRESS OF MAX8952 SEND OUT.
C: MAX8952 I2C REGISTER POINTER SEND OUT.
D: MAX8952 DATA SEND OUT.
E: MAX8952 ISSUES ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I2C SETTINGS.
Figure 13. Update Output Operation
output voltage/operation mode is updated at the same
time the IC sends the acknowledge for the I2C data
byte (see Figure 13).
Slave Address
A bus master initiates communication with a slave
device (MAX8952) by issuing a START condition followed by the slave address. The slave address byte
consists of 7 address bits (1100 000x) and a read/write
bit (R/W). After receiving the proper address, the IC
issues an acknowledge by pulling SDA low during the
ninth clock cycle.
Other slave addresses can be assigned. Contact the
factory for details.
Write Operations
The IC recognizes the write byte protocol as defined in
the SMBus™ specification and shown in Figures 14a and
14b. The write byte protocol allows the I2C master device
to send 1 byte of data to the slave device. The write byte
protocol requires a register pointer address for the subsequent write. The IC acknowledges any register pointer
even though only a subset of those registers actually
exists in the device. The write byte protocol is as follows:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
9) The master sends a STOP condition.
In addition to the write-byte protocol, the IC can write to
multiple registers as shown in Figure 14b. This protocol
allows the I2C master device to address the slave only
once and then send data to a sequential block of registers starting at the specified register pointer.
Use the following procedure to write to a sequential
block of registers:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends the 8-bit register pointer of the
first register to write.
5) The slave acknowledges the register pointer.
6)
7)
8)
9)
The master sends a data byte.
The slave acknowledges the data byte.
The slave updates with the new data.
Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
10) The master sends a STOP condition.
Read Operations
The method for reading a single register (byte) is
shown in Figure 15a. To read a single register:
SMBus is a trademark of Intel Corp.
18
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
S
7
SLAVE ADDRESS
1
1
8
1
8
1
1
0
A
REGISTER POINTER
A
DATA
A
P
NUMBER OF BITS
R/W
b) WRITING TO MULTIPLE REGISTERS
1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
DATA X+1
A
1
8
1
NUMBER OF BITS
A
DATA X+n
R/W
8
...
DATA X+n-1
NUMBER OF BITS
...
A P
Figures 14a and 14b. Writing to the IC
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the
register).
10) The master asserts a not acknowledge by keeping
SDA high.
11) The master sends a STOP condition.
In addition, the IC can read a block of multiple sequential
registers as shown in Figure 15b. Use the following procedure to read a sequential block of registers:
1) The master sends a START command.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer of the
first register in the block.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the register).
10) The master asserts an acknowledge by pulling SDA
low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
12) The master sends a STOP condition.
2) The master sends the 7-bit slave address followed
by a write bit.
Maxim Integrated
19
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
1
7
S
SLAVE ADDRESS
1
1
8
0
A
REGISTER POINTER
1
1
A Sr
7
1
1
8
SLAVE ADDRESS
1
A
DATA
R/W
1
1
NUMBER OF BITS
NA P
R/W
b) READING MULTIPLE REGISTERS
1
7
S
1
SLAVE ADDRESS
1
8
A
0
1
REGISTER POINTER X
A
1
7
SLAVE ADDRESS
Sr
R/W
8
...
1
A ...
DATA X+1
1 1
8
DATA X+n-1
1
8
A
R/W
1
A
A
DATA X
8
DATA X+n
NUMBER OF BITS
1
1
1
...
NUMBER OF BITS
NA P
Figures 15a and 15b. Reading from the IC
SDA
tSU_STA
tSU_DAT
tLOW
tBUF
tHD_STA
tSU_STO
tHD_DAT
tHIGH
SCL
tHD_STA
tR
START CONDITION
tF
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 16. I2C Timing Diagram
20
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 2. I2C Register Map
POINTER
REGISTER
POR
BIT7
BIT6
0x00
MODE0
0x3F
OPER
MODE
SYNC
MODE
VOUT MODE0[5:0]
0x01
MODE1
0x17
OPER
MODE
SYNC
MODE
VOUT MODE1[5:0]
0x02
MODE2
0x3F
OPER
MODE
SYNC
MODE
VOUT MODE2[5:0]
0x03
MODE3
0x21
OPER
MODE
SYNC
MODE
VOUT MODE3[5:0]
0x04
CONTROL
0xE0
EN_PD
VID0_PD
0x05
SYNC
0x00
SYNC[1:0]
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
VID1_PD
—
—
—
—
—
—
—
—
—
—
—
—
RAMP_DOWN
—
0x06
RAMP
0x01
0x08
CHIP_ID1
0x20
RAMP[2:0]
DIE TYPE[7:4]
FORCE_HYS FORCE_OSC
DIE TYPE[3:0]
0x09
CHIP_ID2
0x1A
DASH[3:0]
MASK REV[3:0]
Table 3. I2C Register: MODE0
This register contains output voltage and operation mode control for MODE0, VID0 = GND, VID1 = GND.
REGISTER NAME
MODE0
Address
0x00h
Reset Value
0x3Fh
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN_ UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
FPWM_EN0
DC-DC Step-Down Converter Operation Mode for MODE0
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE0
B5
B4
B3
B2
B1
B0 (LSB)
Maxim Integrated
OUT_ MODE0[5:0]
Output Voltage Selection for MODE0
000000 = 0.77V
000001 = 0.78V
110011 = 1.28V
110100 = 1.29V
110101 = 1.30V
111110 = 1.39V
111111 = 1.40V
111111
(1.4V)
21
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 4. I2C Register: MODE1
This register contains output voltage and operation mode control for MODE1, VID1 = GND, VID0 = VDD.
REGISTER NAME
MODE1
Address
0x01h
Reset Value
0x17h
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN_ UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
FPWM_EN1
DC-DC Step-Down Converter Operation Mode for MODE1
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE1
B5
B4
B3
B2
B1
B0 (LSB)
22
OUT_MODE1[5:0]
Output Voltage Selection for MODE1
000000 = 0.77V
000001 = 0.78V
010110 = 0.99V
010111 = 1.00V
011000 = 1.01V
111110 = 1.39V
111111 = 1.40V
010111
(1.00V)
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 5. I2C Register: MODE2
This register contains output voltage and operation mode control for MODE2, VID1 = VDD, VID0 = GND.
REGISTER NAME
MODE2
Address
0x02h
Reset Value
0x3Fh
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN_ UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
FPWM_EN2
DC-DC Step-Down Converter Operation Mode for MODE2
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE2
B5
B4
B3
B2
B1
B0 (LSB)
Maxim Integrated
OUT_MODE2[5:0]
Output Voltage Selection for MODE2
000000 = 0.77V
000001 = 0.78V
110011 = 1.28V
110100 = 1.29V
110101 = 1.30V
111110 = 1.39V
111111 = 1.40V
111111
(1.4V)
23
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 6. I2C Register: MODE3
This register contains output voltage and operation mode control for MODE3, VID1 = VDD, VID0 = VDD.
REGISTER NAME
MODE3
Address
0x03h
Reset Value
0x21h
Type
Read/write
Special Features
BIT
B7 (MSB)
B6
Reset upon VDD or IN_ UVLO
NAME
DESCRIPTION
DEFAULT
VALUE
FPWM_EN3
DC-DC Step-Down Converter Operation Mode for MODE3
0 = DC-DC converter automatically changes between hysteretic mode for
light load conditions and PWM mode for medium to heavy load conditions.
1 = DC-DC converter operates in forced-PWM mode.
0
Disable/Enable Synchronization to External Clock
0 = DC-DC converter ignores the external SYNC input regardless of
operation mode.
1 = DC-DC converter synchronizes to external SYNC input when available.
0
SYNC_MODE3
B5
B4
B3
B2
B1
B0 (LSB)
24
OUT_MODE3[5:0]
Output Voltage Selection for MODE3
000000 = 0.77V
000001 = 0.78V
100000 = 1.09V
100001 = 1.10V
100010 = 1.11V
111110 = 1.39V
111111 = 1.40V
100001
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 7. I2C Register: CONTROL
This register enables or disables pulldown resistors.
REGISTER NAME
CONTROL
Address
0x04h
Reset Value
0xE0h
Type
Read/write
Special Features
Reset upon VDD, IN_ UVLO or EN pulled low
BIT
NAME
B7 (MSB)
EN_PD
B6
DESCRIPTION
DEFAULT
VALUE
0 = Pulldown on EN input is disabled.
1 = Pulldown on EN input is enabled.
1
VID0_PD
0 = Pulldown on VID0 input is disabled.
1 = Pulldown on VID0 input is enabled.
1
B5
VID1_PD
0 = Pulldown on VID1 input is disabled.
1 = Pulldown on VID1 input is enabled.
1
B4
—
Reserved for future use.
0
B3
—
Reserved for future use.
0
B2
—
Reserved for future use.
0
B1
—
Reserved for future use.
0
B0 (LSB)
—
Reserved for future use.
0
Maxim Integrated
25
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 8. I2C Register: SYNC
This register specifies the clock frequency of external clock source.
REGISTER NAME
SYNC
Address
0x05h
Reset Value
0x00h
Type
Read
Special Features
BIT
Reset upon VDD or IN_ UVLO
NAME
B7 (MSB)
SYNC[1:0]
B6
26
DESCRIPTION
DEFAULT
VALUE
Sets Clock Frequency of External Clock Present on SYNC Input
00 = 26MHz
01 = 13MHz
10 = 19.2MHz
11 = 19.2MHz
00
B5
—
Reserved for future use.
0
B4
—
Reserved for future use.
0
B3
—
Reserved for future use.
0
B2
—
Reserved for future use.
0
B1
—
Reserved for future use.
0
B0 (LSB)
—
Reserved for future use.
0
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 9. I2C Register: RAMP
This register controls of ramp-up/down function.
REGISTER NAME
RAMP
Address
0x06h
Reset Value
0x01h
Type
Read
Special Features
BIT
Reset upon VDD or IN_ UVLO
NAME
B7 (MSB)
B6
RAMP[2:0]
B5
DESCRIPTION
Control the RAMP Timing
000 = 32mV/µs
001 = 16mV/µs
010 = 8mV/µs
011 = 4mV/µs
100 = 2mV/µs
101 = 1mV/µs
110 = 0.5mV/µs
111 = 0.25mV/µs
DEFAULT
VALUE
000
FORCE_HYS
Only Valid When Converter is Operating with FPWM_EN_ = 0
0 = Automatically change between power-save mode and PWM mode,
depending on load current.
1 = Converter always operates in power-save mode regardless of load
current as long as FPWM_EN_ = 0. If FPWM_EN_ = 1, this setting is
ignored.
0
B3
FORCE_OSC
Force Oscillator While Running in Hysteretic Mode
0 = Internal oscillator is disabled in power save when operating in
hysteretic mode.
1 = Internal oscillator is enabled in power save even when operating in
hysteretic mode.
0
B2
—
Reserved for future use.
0
Active Ramp-Down Control for Power-Save Mode
0 = Active ramp disabled for power-save mode.
1 = During ramp-down, the error crossing detector is disabled allowing
negative current to flow through the nMOS device.
0
Reserved for future use.
0
B4
B1
RAMP_DOWN
B0 (LSB)
—
Maxim Integrated
27
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Table 10. I2C Register: CHIP_ID1
This register contains the die type number (20).
REGISTER NAME
CHIP_ID1
Address
0x08h
Reset Value
0x20h
Type
Read
Special Features
BIT
—
NAME
DEFAULT
VALUE
DESCRIPTION
B7 (MSB)
B6
B5
DIE_TYPE[7:4]
BCD character (2)
0010
DIE_TYPE[3:0]
BCD character (0)
0000
B4
B3
B2
B1
B0 (LSB)
Table 11. I2C Register: CHIP_ID2
This register contains the die type dash number and mask revision level.
REGISTER NAME
CHIP_ID2
Address
0x09h
Reset Value
0x1Ah
Type
Read
Special Features
BIT
—
NAME
DESCRIPTION
DEFAULT
VALUE
B7 (MSB)
B6
B5
DASH[7:4]
BCD character 1 (1)
0001
MASK_REV[3:0]
BCD character A (A)
1010
B4
B3
B2
B1
B0 (LSB)
28
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Applications Information
Inductor Selection
Calculate the inductor value (LIDEAL) using the following formula:
LIDEAL =
4 × VIN × D × (1- D)
IOUT(MAX ) × fOSC
This sets the peak-to-peak inductor current ripple to 1/4
the maximum output current. The oscillator frequency,
fOSC, is 3.25MHz, and the duty cycle, D, is:
V
D = OUT
VIN
Given LIDEAL, the peak-to-peak inductor ripple current
is 0.25 x IOUT(MAX). The peak inductor current is 1.125
x IOUT(MAX). Make sure that the saturation current of
the inductor exceeds the peak inductor current, and
the rated maximum DC inductor current exceeds the
maximum output current (IOUT(MAX)). Inductance values smaller than LIDEAL can be used to reduce inductor size; however, if much smaller values are used,
peak inductor current rises and a larger output capacitance may be required to suppress output ripple.
Larger inductance values than LIDEAL can be used to
obtain higher output current, but typically require a
physically larger inductor size. See Table 12 for recommended inductors.
Table 12. Recommended Inductors
MANUFACTURER
Toko
TDK
Coilcraft
Wurth
Maxim Integrated
SERIES
INDUCTANCE
(µH)
DC RESISTANCE
(Ω typ)
CURRENT RATING
(mA)
DIMENSIONS
L x W x H (mm)
DE2815C
0.47
1.0
0.025
0.033
3800
2700
3.2 x 3.0 x 1.5
3.2 x 3.2 x 1.5
DB3015C
1.0
0.036
2700
VLS252010ET
0.47
0.038
2800
2.5 x 2.0 x 1.0
VLS4012ET
1.0
0.050
2800
4.0 x 4.0 x 1.2
LPS5015
1.0
0.050
3900
5.0 x 5.0 x 1.5
LPS5010
0.47
0.038
3400
5.0 x 5.0 x 1.0
LPS4414
0.7
0.055
3800
4.4 x 4.4 x 1.4
744042001
1.0
0.030
2600
4.8 x 4.8 x 1.8
29
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Input Capacitor Selection
Power Dissipation
The input capacitor in a step-down DC-DC regulator
reduces current peaks drawn from the battery or other
input power source and reduces switching noise in the
controller. 10µF ceramic capacitors in parallel with a
0.1µF ceramic capacitor are recommended for most
applications. The impedance of the input capacitor at the
switching frequency should be less than that of the input
source so that high-frequency switching currents do not
pass through the input source. The input capacitor must
meet the input ripple-current requirement imposed by
the step-down regulator. Ceramic capacitors are preferred due to their resilience to power-up surge currents.
Choose the input capacitor so that the temperature rise
due to input ripple current does not exceed approximately +10°C. For a step-down DC-DC regulator, the
maximum input ripple current is 1/2 of the output current.
This maximum input ripple current occurs when the stepdown regulator operates at 50% duty factor (VIN = 2 x
VOUT). Refer to the MAX8952 Evaluation Kit for specific
input capacitor recommendations.
The IC has a thermal-shutdown feature that protects the
IC from damage when the die temperature exceeds
+160°C. See the Thermal-Overload Protection section
for more information. To prevent thermal overload and
allow the maximum load current on each regulator, it is
important to ensure that the heat generated by the IC
can be dissipated into the PCB.
When properly mounted on a multilayer PCB, the junction-to-ambient thermal resistance (θ JA ) is typically
49°C/W.
Output Capacitor Selection
The step-down DC-DC regulator output capacitor keeps
output ripple small and ensures control-loop
stability. A 10µF ceramic capacitor in parallel with a
0.1µF ceramic capacitor is recommended for most applications. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and
tantalum capacitors are suitable, with ceramic exhibiting
the lowest ESR and lowest high-frequency impedance.
Output ripple due to capacitance (neglecting ESR) is
approximately:
VRIPPLE =
PCB Layout
Due to fast switching waveforms and high current
paths, careful PCB layout is required to achieve optimal
performance. Minimize trace lengths between the IC
and the inductor, the input capacitor, and the output
capacitor; keep these traces short, direct, and wide.
The ground connections of CIN and COUT should be as
close together as possible and connected to PGND.
Connect AGND and PGND directly to the ground plane.
The MAX8952 Evaluation Kit illustrates an example PCB
layout and routing scheme.
Special care should be taken when routing the remote
sense signals. Use a wide SNS+ trace to minimize parasitic inductance in the SNS+ feedback trace. Do not
use vias on the SNS+ trace because these introduce
additional inductance. Connect SNS- to the local AGND
plane for the MAX8952.
Chip Information
PROCESS: BiCMOS
IL (PEAK)
2π × fOSC × COUT
Additional ripple due to capacitor ESR is:
VRIPPLE (ESR) = IL (PEAK) × ESR
Refer to the MAX8952 Evaluation Kit for specific output
capacitor recommendations.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
16 WLP
W162B2+1
21-0200
LAND
PATTERN NO.
Refer to
30
Application Note
1891
Maxim Integrated
MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Revision History
DESCRIPTION
PAGES
CHANGED
6/10
Initial release
6/11
Updated remote sense, Typical Operating Circuit, SNS+ and SNS- impedance entry,
C1 bump description, Figure 1, and PCB Layout section
1, 5, 10,
11, 30
REVISION
NUMBER
REVISION
DATE
0
1
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 31
© 2011 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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