Ultraprecision Operational Amplifier
OP177
Data Sheet
PIN CONFIGURATION
Ultralow offset voltage
TA = 25°C, 25 μV maximum
Outstanding offset voltage drift 0.3 μV/°C maximum
Excellent open-loop gain and gain linearity
12 V/μV typical
CMRR: 130 dB minimum
PSRR: 115 dB minimum
Low supply current 2.0 mA maximum
Fits industry-standard precision operational amplifier
sockets
VOS TRIM 1
OP177
–IN 2
+IN 3
V– 4
8
VOS TRIM
7
V+
6 OUT
TOP VIEW
5 NC
(Not to Scale)
NC = NO CONNECT
00289-001
FEATURES
Figure 1. 8-Lead PDIP (P-Suffix),
8-Lead SOIC (S-Suffix)
GENERAL DESCRIPTION
This low noise, bipolar input operational amplifier is also a cost
effective alternative to chopper-stabilized amplifiers. The OP177
provides chopper-type performance without the usual problems
of high noise, low frequency chopper spikes, large physical size,
limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 features one of the highest precision performance of
any operational amplifier currently available. Offset voltage of the
OP177 is only 25 μV maximum at room temperature. The ultralow
VOS of the OP177 combines with the exceptional offset voltage
drift (TCVOS) of 0.3 μV/°C maximum to eliminate the need for
external VOS adjustment and increases system accuracy over
temperature.
The OP177 is offered in the −40°C to +85°C extended industrial
temperature ranges. This product is available in 8-lead PDIP, as
well as the space saving 8-lead SOIC.
The OP177 open-loop gain of 12 V/μV is maintained over the full
±10 V output range. CMRR of 130 dB minimum, PSRR of 120 dB
minimum, and maximum supply current of 2 mA are just a few
examples of the excellent performance of this operational amplifier.
The combination of outstanding specifications of the OP177
ensures accurate performance in high closed-loop gain
applications.
FUNCTIONAL BLOCK DIAGRAM
V+
(OPTIONAL NULL)
R2A*
R2B*
C1
R7
R1B
R1A
Q19
2B
Q10
Q9
NONINVERTING
INPUT
INVERTING
INPUT
R3
Q3
Q5
Q11
Q8
Q6
Q4
Q1
R4
OUTPUT
Q27
Q21
Q23
Q22
Q24
R9
Q12
Q26
C3
C2
Q17
R10
Q16
R5
Q20
Q25
Q15
Q2
Q18
Q14
Q13
V–
*R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
R6
R8
00289-002
Q7
Figure 2. Simplified Schematic
Rev. H
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OP177
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .................................................................9
Pin Configuration ............................................................................. 1
Gain Linearity ................................................................................9
General Description ......................................................................... 1
Thermocouple Amplifier with Cold-Junction Compensation9
Functional Block Diagram .............................................................. 1
Precision High Gain Differential Amplifier ........................... 10
Revision History ............................................................................... 2
Isolating Large Capacitive Loads.............................................. 10
Specifications..................................................................................... 3
Bilateral Current Source ............................................................ 10
Electrical Characteristics ............................................................. 3
Precision Absolute Value Amplifier ......................................... 10
Test Circuits................................................................................... 4
Precision Positive Peak Detector .............................................. 12
Absolute Maximum Ratings ............................................................ 5
Precision Threshold Detector/Amplifier ................................ 12
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 13
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 14
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
4/16—Rev. G to Rev. H
Changes to Figure 27 ........................................................................ 9
9/12—Rev. F to Rev. G
Changes to Features and General Description Section ............... 1
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
3/09—Rev. E to Rev. F
Added Figure 23, Renumbered Sequentially ................................ 8
Updated Outline Dimensions ....................................................... 13
5/06—Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
Change to Specifications Table 1 .................................................... 3
Changes to Specifications Table 2................................................... 4
Changes to Table 3 ............................................................................ 5
Changes to Figure 23 and Figure 24............................................... 9
Changes to Figure 32 ...................................................................... 12
Updated the Ordering Guide ........................................................ 14
4/06—Rev. C to Rev. D
Change to Pin Configuration Caption ...........................................1
Changes to Features ..........................................................................1
Change to Table 2 ..............................................................................4
Change to Figure 2 ............................................................................4
Changes to Figure 10 and Figure 11 ...............................................6
Changes to Figure 12 through Figure 17 ........................................7
Changes to Figure 18 through Figure 22 ........................................8
Change to Figure 27 ....................................................................... 10
Changes to Figure 30 and Figure 31 ............................................ 11
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
1/05—Rev. B to Rev. C
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits to Pin Connections ..................................................................1
Edits to Electrical Characteristics .............................................. 2, 3
Global deletion of references to OP177E ............................ 3, 4, 10
Edits to Absolute Maximum Ratings ..............................................5
Edits to Package Type .......................................................................5
Edits to Ordering Guide ...................................................................5
Edit to Outline Dimensions .......................................................... 11
11/95—Rev. 0: Initial Version
Rev. H | Page 2 of 16
Data Sheet
OP177
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT OFFSET VOLTAGE
LONG-TERM INPUT OFFSET 1
Voltage Stability
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
INPUT RESISTANCE
Differential Mode 3
INPUT RESISTANCE COMMON MODE
INPUT VOLTAGE RANGE 4
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE SIGNAL VOLTAGE GAIN
OUTPUT VOLTAGE SWING
Symbol
VOS
ΔVOS/time
IOS
IB
en
in
RIN
RINCM
IVR
CMRR
PSRR
AVO
VO
SLEW RATE2
CLOSED-LOOP BANDWIDTH2
OPEN-LOOP OUTPUT RESISTANCE
POWER CONSUMPTION
SR
BW
RO
PD
SUPPLY CURRENT
OFFSET ADJUSTMENT RANGE
ISY
Test Conditions/Comments
Min
OP177F
Typ
10
Max
25
−0.2
0.3
0.3
+1.2
118
3
1.5
+2
150
8
fO = 1 Hz to 100 Hz
fO = 1 Hz to 100 Hz2
2
26
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V 5
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
RL ≥ 2 kΩ
AVCL = 1
VS = ±15 V, no load
VS = ±3 V, no load
VS = ±15 V, no load
RP = 20 kΩ
±13
130
115
5000
±13.5
±12.5
±12.0
0.1
0.4
45
200
±14
140
125
12,000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
1.6
±3
Min
−0.2
18.5
±13
115
110
2000
±13.5
±12.5
±12.0
0.1
0.4
60
4.5
2
OP177G
Typ
Max
20
60
0.4
0.3
+1.2
118
3
45
200
±14
140
120
6000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
1.6
±3
2.8
+2.8
150
8
60
4.5
2
Unit
μV
μV/mo
nA
nA
nV rms
pA rms
MΩ
GΩ
V
dB
dB
V/mV
V
V
V
V/μs
MHz
Ω
mW
mW
mA
mV
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
1
Rev. H | Page 3 of 16
OP177
Data Sheet
At VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
Parameter
INPUT
Input Offset Voltage
Average Input Offset Voltage Drift1
Input Offset Current
Average Input Offset Current Drift2
Input Bias Current
Average Input Bias Current Drift2
Input Voltage Range3
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN4
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
SUPPLY CURRENT
Symbol
VOS
TCVOS
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
VO
PD
ISY
Test Conditions/Comments
OP177F
Typ
Max
Min
−0.2
±13
120
110
2000
±12
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 2 kΩ
VS = ±15 V, no load
VS = ±15 V, no load
15
0.1
0.5
1.5
+2.4
8
±13.5
140
120
6000
±13
60
20
1
Min
40
0.3
2.2
40
+4
40
±13
110
106
1000
±12
75
2.5
OP177G
Typ
Max
20
0.7
0.5
1.5
+2.4
15
±13.5
140
115
4000
±13
60
2
TCVOS is sample tested.
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V.
2
TEST CIRCUITS
200kΩ
50Ω
–
OP177
VOS =
VO
00289-003
+
VO
4000
Figure 3. Typical Offset Voltage Test Circuit
20kΩ
V+
–
–
INPUT
OUTPUT
OP177
VOS TRIM RANGE IS
TYPICALLY ±3.0mV
V–
Figure 4. Optional Offset Nulling Circuit
20kΩ
+20V
–
OP177
+
–20V
Figure 5. Burn-In Circuit
Rev. H | Page 4 of 16
00289-005
PINOUTS SHOWN FOR
P AND Z PACKAGES
00289-004
+
+
100
1.2
4.5
85
±6
60
75
2.5
Unit
μV
μV/°C
nA
pA/°C
nA
pA/°C
V
dB
dB
V/mV
V
mW
mA
Data Sheet
OP177
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Internal Power Dissipation1
Differential Input Voltage
Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 sec)
DICE Junction Temperature (TJ)
1
Ratings
±22 V
500 mW
±30 V
±22 V
Indefinite
−65°C to +125°C
−40°C to +85°C
300°C
−65°C to +150°C
θJA is specified for worst-case mounting conditions, that is, θJA is
specified for device in socket for PDIP; θJA is specified for
device soldered to printed circuit board for SOIC package.
Table 4. Thermal Resistance
Package Type
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
ESD CAUTION
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. H | Page 5 of 16
θJA
103
158
θJC
43
43
Unit
°C/W
°C/W
OP177
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
TA = 25°C
VS = ±15V
RL = 10kΩ
VS = ±15V
ABSOLUTE CHANGE IN
INPUT OFFSET VOLTAGE (µV)
25
1
0
–1
DEVICE IMMERSED IN
70° OIL BATH (20 UNITS)
30
35
40
–2
–10
0
OUTPUT VOLTAGE (V)
–5
50
0
10
5
Figure 6. Gain Linearity (Input Voltage vs. Output Voltage)
30
20
40
TIME (Seconds)
50
60
70
25
TA = 25°C
VS = ±15V
OPEN-LOOP GAIN (V/µV)
20
10
15
10
1
20
10
30
TOTAL SUPPLY VOLTAGE, V+ TO V– (V)
0
0
–55
40
Figure 7. Power Consumption vs. Power Supply
00289-010
5
00289-007
POWER CONSUMPTION (mW)
10
Figure 9. Offset Voltage Change Due to Thermal Shock
100
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 10. Open-Loop Gain vs. Temperature
5
16
TA = 25°C
RL = 2kΩ
4
3
1
OPEN-LOOP GAIN (V/µV)
LOT A
LOT B
LOT C
LOT D
2
0
–1
–2
12
8
4
–4
–5
0
20
40
60
80
100
120
TIME (Seconds)
140
160
00289-011
–3
00289-008
VOS (µV)
00289-009
45
00289-006
INPUT VOLTAGE (µV)
(NULLED TO 0mV @ VOUT = 0V)
2
0
180
0
±10
±5
±15
POWER SUPPLY VOLTAGE (V)
Figure 11. Open-Loop Gain vs. Power Supply Voltage
Figure 8. Warm-Up VOS Drift (Normalized) Z Package
Rev. H | Page 6 of 16
±20
Data Sheet
OP177
4
160
VS = ±15V
TA = 25°C
VS = ±15V
OPEN-LOOP GAIN (dB)
3
2
120
100
80
60
40
1
0
0
50
TEMPERATURE (°C)
–50
0
0.01
100
Figure 12. Input Bias Current vs. Temperature
00289-015
20
00289-012
INPUT BIAS CURRENT (nA)
140
0.1
1
100
10
1k
FREQUENCY (Hz)
100k
10k
1M
Figure 15. Open-Loop Frequency Response
2.0
150
VS = ±15V
TA = 25°C
1.5
CMRR (dB)
130
1.0
110
90
–50
0
50
TEMPERATURE (°C)
00289-016
0
120
100
0.5
00289-013
INPUT OFFSET CURRENT (nA)
140
80
100
1
Figure 13. Input Offset Current vs. Temperature
1k
100
FREQUENCY (Hz)
10k
100k
Figure 16. CMRR vs. Frequency
100
130
TA = 25°C
VS = ±15V
TA = 25°C
120
80
110
60
PSRR (dB)
CLOSED-LOOP GAIN (dB)
10
40
100
90
20
80
0
–20
10
100
1k
100k
10k
FREQUENCY (Hz)
1M
60
0.1
10M
Figure 14. Closed-Loop Response for Various Gain Configurations
00289-017
00289-014
70
1
100
10
FREQUENCY (Hz)
Figure 17. PSRR vs. Frequency
Rev. H | Page 7 of 16
1k
10k
OP177
Data Sheet
20
TA = 25°C
VS = +15V
VIN = ±10mV
RS1 = RS2 = 200kΩ
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
MAXIMUM OUTPUT (V)
100
EXCLUDED
RS = 0
10
POSITIVE SWING
15
NEGATIVE SWING
10
1
1
00289-018
TA = 25°C
VS = ±15V
10
100
00289-021
5
0
100
1k
Figure 21. Maximum Output Voltage vs. Load Resistance
Figure 18. Total Input Noise Voltage vs. Frequency
40
OUTPUT SHORT-CIRCUIT CURRENT (mA)
1
00289-019
RMS NOISE (µV)
TA = 25°C
VS = ±15V
1k
35
+ISC
30
25
–ISC
20
15
0
100k
10k
TA = 25°C
VS = ±15V
00289-022
10
0.1
100
1
2
3
TIME FROM OUTPUT BEING SHORTED (Minutes)
BANDWIDTH (Hz)
Figure 19. Input Wideband Noise vs. Bandwidth
(0.1 Hz to Frequency Indicated)
4
Figure 22. Output Short-Circuit Current vs. Time
32
1.50
TA = 25°C
VS = ±15V
TA = 25°C
VS = ±15V
28
1.25
24
1.00
IB (nA)
20
16
0.75
12
IB1– (nA)
IB2– (nA)
IB3– (nA)
IB1+ (nA)
IB2+ (nA)
IB3+ (nA)
0.50
8
0.25
4
0
1k
00289-020
PEAK-TO-PEAK AMPLITUDE (V)
10k
1k
LOAD RESISTANCE TO GROUND (Ω)
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
0
–16
1M
–14
–10
–6
–2
2
VCM (V)
6
10
00289-033
INPUT NOISE VOLTAGE (nV√Hz)
1000
14
Figure 23. Input Bias (IB) vs. Common-Mode Voltage (VCM)
Figure 20. Maximum Output Swing vs. Frequency
Rev. H | Page 8 of 16
Data Sheet
OP177
APPLICATIONS INFORMATION
GAIN LINEARITY
The actual open-loop gain of most monolithic operational
amplifiers varies at different output voltages. This nonlinearity
causes errors in high closed-loop gain circuits.
It is important to know that the manufacturer’s AVO specification is only a part of the solution because all automated testers
use endpoint testing and, therefore, show only the average gain.
For example, Figure 24 shows a typical precision operational
amplifier with a respectable open-loop gain of 650 V/mV.
However, the gain is not constant through the output voltage
range, causing nonlinear errors. An ideal operational amplifier
shows a horizontal scope trace.
Figure 25 shows the OP177 output gain linearity trace with the
truly impressive average AVO of 12,000 V/mV. The output trace
is virtually horizontal at all points, assuring extremely high gain
accuracy. Analog Devices, Inc., also performs additional testing
to ensure consistent high open-loop gain at various output
voltages. Figure 26 is a simple open-loop gain test circuit.
VX
0V
An example of a precision circuit is a thermocouple amplifier
that must accurately amplify very low level signals without
introducing linearity and offset errors to the circuit. In this
circuit, an S-type thermocouple with a Seebeck coefficient of
10.3 μV/°C produces 10.3 mV of output voltage at a temperature
of 1000°C. The amplifier gain is set at 973.16, thus, it produces
an output voltage of 10.024 V. Extended temperature ranges
beyond 1500°C are accomplished by reducing the amplifier
gain. The circuit uses a low cost diode to sense the temperature
at the terminating junctions and, in turn, compensates for any
ambient temperature change. The OP177, with the high openloop gain plus low offset voltage and drift, combines to yield a
precise temperature sensing circuit. Circuit values for other
thermocouple types are listed in Table 5.
Table 5.
Thermocouple
Type
K
J
S
Seebeck
Coefficient
39.2 μV/°C
50.2 μV/°C
10.3 μV/°C
R2
5.76 kΩ
4.02 kΩ
20.5 kΩ
R7
102 kΩ
80.6 kΩ
392 kΩ
2
REF01
2.2µF
00289-023
AVO ≥ 650V/mV
RL = 2kΩ
10.000V
6
4
R9
1.07MΩ
0.05%
R7
392kΩ
1%
R3
47kΩ
1%
+
Figure 24. Typical Precision Operational amplifier
+15V
10µF
0.1µF
+
VY
–
VX
0V
R2
20.5kΩ
1%
R8
1.0kΩ
0.05%
COPPER
R5
100Ω
(ZERO
ADJUSTMENT)
ISOTHERMAL
COLDJUNCTIONS
TYPES
+
COPPER
+10V
00289-024
ISOTHERMAL
BLOCK
AVO ≥ 12000V/mV
RL = 2kΩ
COLD-JUNCTION
COMPENSATION
R1
100Ω
1%
R4
50Ω
1%
10µF
–
OP177
+
10µF
10µF
0.1µF
–15V ANALOG
GROUND
Figure 25. Output Gain Linearity Trace
VY
10kΩ
VIN = ±10V
ANALOG
GROUND
10kΩ
Figure 27. Thermocouple Amplifier with Cold Junction Compensation
1MΩ
VX
–
10Ω
R9
269 kΩ
200 kΩ
1.07 MΩ
+10V
+15V
–10V
R1
110 Ω
100 Ω
100 Ω
OP177
RL
00289-025
+
Figure 26. Open-Loop Gain Linearity Test Circuit
Rev. H | Page 9 of 16
VOUT
00289-026
–10V
THERMOCOUPLE AMPLIFIER WITH COLDJUNCTION COMPENSATION
OP177
Data Sheet
PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER
ISOLATING LARGE CAPACITIVE LOADS
The high gain, gain linearity, CMRR, and low TCVOS of the
OP177 make it possible to obtain performance not previously
available in single stage, very high gain amplifier applications.
See Figure 28.
The circuit shown in Figure 29 reduces maximum slew rate but
allows driving capacitive loads of any size without instability.
Because the 100 Ω resistor is inside the feedback loop, the effect
on output impedance is reduced to insignificance by the high
open loop gain of the OP177.
R1
R3
must equal
R2
R4
RF
10pF
In this example, with a 10 mV differential signal, the maximum
errors are listed in Table 6.
+15V
R2
1MΩ
0.1µF
+15V
RS
INPUT
2
0.1µF
3
2
R3
1kΩ
3
OP177
+
R4
1MΩ
4
–15V
Figure 29. Isolating Capacitive Loads
0.1µF
–15V
BILATERAL CURRENT SOURCE
The current sources shown in Figure 30 supply both positive
and negative currents into a grounded load.
Figure 28. Precision High Gain Differential Amplifier
Note that
Table 6. High Gain Differential Amplifier Performance
Type
Common-Mode Voltage
Gain Linearity, Worst Case
TCVOS
TCIOS
OUTPUT
CLOAD
6
OP177
+
100Ω
6
4 0.1µF
7
–
00289-027
R1
1kΩ
7
–
00289-028
For best CMR,
Amount
0.1%/V
0.02%
0.0003%/°C
0.008%/°C
R4
R5
1
R2
ZO
R5 R4 R3
R2
R1
and that for ZO to be infinite
R5 R4
R2
must
R3
R1
PRECISION ABSOLUTE VALUE AMPLIFIER
The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the operational amplifiers
(for details, see Figure 31).
BASIC CURRENT SOURCE
100mA CURRENT SOURCE
R3
1kΩ
R3
+15V
R2
100kΩ
2
3
–
OP177
+
R4
990Ω
VIN
6
R1
R2
2
3
R5
10Ω
–
OP177
+
2N2222
2N2907
R4
IOUT ≤ 15mA
6 50Ω
R5
–15V
IOUT ≤ 100mA
IOUT = VIN
R3
R1 × R5
GIVEN R3 = R4 + R5, R1 = R2
Figure 30. Bilateral Current Source
Rev. H | Page 10 of 16
00289-029
VIN
R1
100kΩ
Data Sheet
OP177
1kΩ
1kΩ
+15V
+15V
0.1µF
C1
30pF
D1
1N4148
2
2
VIN
3
7
–
3
6
OP177
7
–
4
R3
2kΩ
4 0.1µF
VOUT
0 < VOUT < 10V
+
2N4393
+
6
OP177
0.1µF
00289-030
0.1µF
–15V
–15V
Figure 31. Precision Absolute Value Amplifier
1kΩ
+15V
+15V
0.1µF
VIN
1kΩ
3
NC
7
2
–
OP177
6
2N930
1kΩ
+
4
0.1µF
CH
–15V
7
–
AD820
3
+
4
6
VOUT
0.1µF
–15V
RESET
1kΩ
00289-031
2
0.1µF
1N4148
Figure 32. Precision Positive Peak Detector
Rev. H | Page 11 of 16
OP177
Data Sheet
CC
PRECISION POSITIVE PEAK DETECTOR
RF
100kΩ
In Figure 32, CH must be polystyrene, Teflon®, or polyethylene
to minimize dielectric absorption and leakage. The droop rate is
determined by the size of CH and the bias current of the AD820.
0.1µF
RS
1kΩ
VTH
In Figure 33, when VIN < VTH, amplifier output swings negative,
reverse biasing diode D1. VOUT = VTH if RL = ∞. When VIN ≥ VTH,
the loop closes.
R
VOUT = VTH + (VIN − VTH )1 + F
RS
VIN
R1
2kΩ
2
3
–
7
OP177
+
6
D1
1N4148
VOUT
4 0.1µF
–15V
Figure 33. Precision Threshold Detector/Amplifier
CC is selected to smooth the response of the loop.
Rev. H | Page 12 of 16
00289-032
PRECISION THRESHOLD DETECTOR/AMPLIFIER
+15V
Data Sheet
OP177
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 34. 8-Lead Plastic Dual In-Line Package (PDIP)
P-Suffix
(N-8)
Dimensions show in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 8-Lead Standard Small Outline Package (SOIC_N)
S-Suffix
(R-8)
Dimensions shown in millimeters and( inches)
Rev. H | Page 13 of 16
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
OP177
Data Sheet
ORDERING GUIDE
Model 1
OP177FPZ
OP177GPZ
OP177FSZ
OP177FSZ-REEL
OP177FSZ-REEL7
OP177GS
OP177GS-REEL
OP177GS-REEL7
OP177GSZ
OP177GSZ-REEL
OP177GSZ-REEL7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. H | Page 14 of 16
Package Option
P-Suffix (N-8)
P-Suffix (N-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
Data Sheet
OP177
NOTES
Rev. H | Page 15 of 16
OP177
Data Sheet
NOTES
©1995–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00289-0-4/16(H)
Rev. H | Page 16 of 16
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