OP177GSZ

Ultraprecision Operational Amplifier OP177 FEATURES Ultralow offset voltage TA = 25°C, 25 μV maximum Outstanding offset voltage drift 0.1 μV/°C maximum Excellent open-loop gain and gain linearity 12 V/μV typical CMRR: 130 dB minimum PSRR: 115 dB minimum Low supply current 2.0 mA maximum Fits industry-standard precision op amp sockets PIN CONFIGURATION VOS TRIM 1 –IN 2 OP177 8 7 VOS TRIM V+ +IN 3 V– 4 NC = NO CONNECT Figure 1. 8-Lead PDIP (P-Suffix), 8-Lead SOIC (S-Suffix) GENERAL DESCRIPTION The OP177 features one of the highest precision performance of any op amp currently available. Offset voltage of the OP177 is only 25 μV maximum at room temperature. The ultralow VOS of the OP177 combines with its exceptional offset voltage drift (TCVOS) of 0.1 μV/°C maximum to eliminate the need for external VOS adjustment and increases system accuracy over temperature. The OP177 open-loop gain of 12 V/μV is maintained over the full ±10 V output range. CMRR of 130 dB minimum, PSRR of 120 dB minimum, and maximum supply current of 2 mA are just a few examples of the excellent performance of this operational amplifier. The combination of outstanding specifications of the OP177 ensures accurate performance in high closed-loop gain applications. This low noise, bipolar input op amp is also a cost effective alternative to chopper-stabilized amplifiers. The OP177 provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. The OP177 is offered in the −40°C to +85°C extended industrial temperature ranges. This product is available in 8-lead PDIP, as well as the space saving 8-lead SOIC. FUNCTIONAL BLOCK DIAGRAM V+ R2A* R1A 2B Q9 Q7 NONINVERTING INPUT R3 Q5 Q3 Q1 Q21 INVERTING INPUT R4 Q22 Q23 Q24 Q2 Q14 Q13 V– *R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY. R6 Q6 Q8 Q4 Q27 Q26 Q25 C3 R5 Q11 C2 Q12 Q17 Q16 Q10 R9 OUTPUT R10 Q20 Q15 Q18 R8 00289-002 (OPTIONAL NULL) R2B* R1B C1 R7 Q19 Figure 2. Simplified Schematic Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 00289-001 6 OUT TOP VIEW 5 NC (Not to Scale) OP177 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration............................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Test Circuits................................................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Application Information.................................................................. 9 Gain Linearity ................................................................................9 Thermocouple Amplifier with Cold-Junction Compensation................................................................................9 Precision High Gain Differential Amplifier ........................... 10 Isolating Large Capacitive Loads.............................................. 10 Bilateral Current Source ............................................................ 10 Precision Absolute Value Amplifier......................................... 10 Precision Positive Peak Detector.............................................. 12 Precision Threshold Detector/Amplifier ................................ 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 14 REVISION HISTORY 5/06—Rev. D to Rev. E Changes to Figure 1.......................................................................... 1 Change to Specifications Table 1 .................................................... 3 Changes to Specifications Table 2................................................... 4 Changes to Table 3............................................................................ 5 Changes to Figure 23 and Figure 24............................................... 9 Changes to Figure 32...................................................................... 12 Updated the Ordering Guide ........................................................ 14 4/06—Rev. C to Rev. D Change to Pin Configuration Caption........................................... 1 Changes to Features.......................................................................... 1 Change to Table 2 ............................................................................. 4 Change to Figure 2 ........................................................................... 4 Changes to Figure 10 and Figure 11............................................... 6 Changes to Figure 12 through Figure 17 ....................................... 7 Changes to Figure 18 through Figure 22 ....................................... 8 Change to Figure 27 ....................................................................... 10 Changes to Figure 30 and Figure 31............................................. 11 Updated Outline Dimensions....................................................... 13 Changes to Ordering Guide .......................................................... 13 1/05—Rev. B to Rev. C Edits to Features.................................................................................1 Edits to General Description ...........................................................1 Edits to Pin Connections..................................................................1 Edits to Electrical Characteristics .............................................. 2, 3 Global deletion of references to OP177E ............................ 3, 4, 10 Edits to Absolute Maximum Ratings ..............................................5 Edits to Package Type .......................................................................5 Edits to Ordering Guide ...................................................................5 Edit to Outline Dimensions .......................................................... 11 11/95—Rev. 0: Initial Version Rev. E | Page 2 of 16 OP177 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ VS = ±15 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT OFFSET VOLTAGE LONG-TERM INPUT OFFSET 1 Voltage Stability INPUT OFFSET CURRENT INPUT BIAS CURRENT INPUT NOISE VOLTAGE INPUT NOISE CURRENT INPUT RESISTANCE Differential Mode 3 INPUT RESISTANCE COMMON MODE INPUT VOLTAGE RANGE 4 COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO LARGE SIGNAL VOLTAGE GAIN OUTPUT VOLTAGE SWING T Symbol VOS ΔVOS/time IOS IB en in RIN RINCM IVR CMRR PSRR AVO VO Conditions Min OP177F Typ 10 0.3 0.3 +1.2 118 3 45 200 ±14 140 125 12,000 ±14.0 ±13.0 ±12.5 0.3 0.6 60 50 3.5 1.6 ±3 Max 25 Min OP177G Typ Max 20 60 0.4 0.3 +1.2 118 3 45 200 ±14 140 120 6000 ±14.0 ±13.0 ±12.5 0.3 0.6 60 50 3.5 1.6 ±3 Unit μV μV/mo nA nA nV rms pA rms MΩ GΩ V dB dB V/mV V V V V/μs MHz Ω mW mW mA mV −0.2 fO = 1 Hz to 100 Hz fO = 1 Hz to 100 Hz2 2 1.5 +2 150 8 −0.2 2.8 +2.8 150 8 26 ±13 130 115 5000 ±13.5 ±12.5 ±12.0 0.1 0.4 18.5 ±13 115 110 2000 ±13.5 ±12.5 ±12.0 0.1 0.4 60 4.5 2 SLEW RATE2 CLOSED-LOOP BANDWIDTH2 OPEN-LOOP OUTPUT RESISTANCE POWER CONSUMPTION SUPPLY CURRENT OFFSET ADJUSTMENT RANGE 1 SR BW RO PD ISY VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V 5 RL ≥ 10 kΩ RL ≥ 2 kΩ RL ≥ 1 kΩ RL ≥ 2 kΩ AVCL = 1 VS = ±15 V, no load VS = ±3 V, no load VS = ±15 V, no load RP = 20 kΩ 60 4.5 2 Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V. Rev. E | Page 3 of 16 OP177 @ VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 2. Parameter INPUT Input Offset Voltage Average Input Offset Voltage Drift 1 Input Offset Current Average Input Offset Current Drift 2 Input Bias Current Average Input Bias Current Drift2 Input Voltage Range 3 COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO LARGE-SIGNAL VOLTAGE GAIN 4 OUTPUT VOLTAGE SWING POWER CONSUMPTION SUPPLY CURRENT 1 2 Symbol VOS TCVOS IOS TCIOS IB TCIB IVR CMRR PSRR AVO VO PD ISY Conditions Min OP177F Typ 15 0.1 0.5 1.5 +2.4 8 ±13.5 140 120 6000 ±13 60 20 Max 40 0.3 2.2 40 +4 40 Min OP177G Typ 20 0.7 0.5 1.5 +2.4 15 ±13.5 140 115 4000 ±13 60 2 Max 100 1.2 4.5 85 ±6 60 Unit μV μV/°C nA pA/°C nA pA/°C V dB dB V/mV V mW mA −0.2 ±13 120 110 2000 ±12 VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V RL ≥ 2 kΩ VS = ±15 V, no load VS = ±15 V, no load ±13 110 106 1000 ±12 75 2.5 75 2.5 TCVOS is sample tested. Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V. TEST CIRCUITS 200kΩ 50Ω – OP177 + VOS = VO 4000 VO 00289-003 Figure 3. Typical Offset Voltage Test Circuit 20kΩ V+ – INPUT + – OP177 + OUTPUT V– Figure 4. Optional Offset Nulling Circuit 20kΩ +20V – OP177 + PINOUTS SHOWN FOR P AND Z PACKAGES –20V 00289-005 Figure 5. Burn-In Circuit Rev. E | Page 4 of 16 00289-004 VOS TRIM RANGE IS TYPICALLY ±3.0mV OP177 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Internal Power Dissipation1 Differential Input Voltage Input Voltage Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 60 sec) DICE Junction Temperature (TJ) 1 Ratings ±22 V 500 mW ±30 V ±22 V Indefinite −65°C to +125°C −40°C to +85°C 300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for worst-case mounting conditions, that is, θJA is specified for device in socket for PDIP; θJA is specified for device soldered to printed circuit board for SOIC package. Table 4. Thermal Resistance Package Type 8-Lead PDIP (P-Suffix) 8-Lead SOIC (S-Suffix) θJA 103 158 θJC 43 43 Unit °C/W °C/W For supply voltages less than ±22 V, the absolute maximum input voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E | Page 5 of 16 OP177 TYPICAL PERFORMANCE CHARACTERISTICS 2 TA = 25°C VS = ±15V RL = 10kΩ 1 20 VS = ±15V 25 ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µV) DEVICE IMMERSED IN 70° OIL BATH (20 UNITS) INPUT VOLTAGE (µV) (NULLED TO 0mV @ VOUT = 0V) 30 0 35 40 –1 00289-006 45 00289-009 –2 –10 –5 0 OUTPUT VOLTAGE (V) 5 10 50 0 10 20 30 40 TIME (Seconds) 50 60 70 Figure 6. Gain Linearity (Input Voltage vs. Output Voltage) 100 TA = 25°C Figure 9. Offset Voltage Change Due to Thermal Shock 25 VS = ±15V 20 POWER CONSUMPTION (mW) OPEN-LOOP GAIN (V/µV) 15 10 10 5 00289-007 1 0 10 20 30 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) 40 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 7. Power Consumption vs. Power Supply 5 4 3 2 VOS (µV) Figure 10. Open-Loop Gain vs. Temperature 16 TA = 25°C RL = 2kΩ 1 0 –1 –2 –3 –4 –5 0 20 40 60 OPEN-LOOP GAIN (V/µV) LOT A LOT B LOT C LOT D 12 8 4 00289-011 00289-008 0 80 100 120 TIME (Seconds) 140 160 180 0 ±5 ±10 ±15 POWER SUPPLY VOLTAGE (V) ±20 Figure 8. Warm-Up VOS Drift (Normalized) Z Package Figure 11. Open-Loop Gain vs. Power Supply Voltage Rev. E | Page 6 of 16 00289-010 OP177 4 VS = ±15V 140 INPUT BIAS CURRENT (nA) 160 TA = 25°C VS = ±15V OPEN-LOOP GAIN (dB) 3 120 100 80 60 40 00289-015 2 1 00289-012 20 0 0.01 0 –50 0 50 TEMPERATURE (°C) 100 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M Figure 12. Input Bias Current vs. Temperature 2.0 VS = ±15V 140 INPUT OFFSET CURRENT (nA) Figure 15. Open-Loop Frequency Response 150 TA = 25°C 1.5 130 CMRR (dB) 00289-013 120 110 100 90 80 1.0 0.5 0 –50 0 50 TEMPERATURE (°C) 100 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 13. Input Offset Current vs. Temperature 100 TA = 25°C VS = ±15V 80 CLOSED-LOOP GAIN (dB) Figure 16. CMRR vs. Frequency 130 TA = 25°C 120 110 60 PSRR (dB) 100 90 80 70 60 0.1 40 20 0 00289-014 –20 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1 10 100 FREQUENCY (Hz) 1k 10k Figure 14. Closed-Loop Response for Various Gain Configurations Figure 17. PSRR vs. Frequency Rev. E | Page 7 of 16 00289-017 00289-016 OP177 1000 RS1 = RS2 = 200kΩ THERMAL NOISE OF SOURCE RESISTORS INCLUDED 100 20 TA = 25°C VS = +15V VIN = ±10mV INPUT NOISE VOLTAGE (nV√Hz) MAXIMUM OUTPUT (V) 15 POSITIVE SWING NEGATIVE SWING EXCLUDED 10 RS = 0 10 5 00289-021 00289-018 TA = 25°C VS = ±15V 1 1 10 FREQUENCY (Hz) 100 1k 0 100 1k LOAD RESISTANCE TO GROUND (Ω) 10k Figure 18. Total Input Noise Voltage vs. Frequency 10 OUTPUT SHORT-CIRCUIT CURRENT (mA) Figure 21. Maximum Output Voltage vs. Load Resistance 40 TA = 25°C VS = ±15V TA = 25°C VS = ±15V 35 RMS NOISE (µV) 30 +ISC 1 25 –ISC 20 00289-022 00289-019 0.1 100 1k BANDWIDTH (Hz) 10k 100k 15 0 1 2 3 TIME FROM OUTPUT BEING SHORTED (Minutes) 4 Figure 19. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency Indicated) 32 28 Figure 22. Output Short-Circuit Current vs. Time TA = 25°C VS = ±15V PEAK-TO-PEAK AMPLITUDE (V) 24 20 16 12 8 00289-020 4 0 1k 10k 100k FREQUENCY (Hz) 1M Figure 20. Maximum Output Swing vs. Frequency Rev. E | Page 8 of 16 OP177 APPLICATION INFORMATION GAIN LINEARITY The actual open-loop gain of most monolithic op amps varies at different output voltages. This nonlinearity causes errors in high closed-loop gain circuits. It is important to know that the manufacturer’s AVO specification is only a part of the solution because all automated testers use endpoint testing and, therefore, show only the average gain. For example, Figure 23 shows a typical precision op amp with a respectable open-loop gain of 650 V/mV. However, the gain is not constant through the output voltage range, causing nonlinear errors. An ideal op amp shows a horizontal scope trace. Figure 24 shows the OP177 output gain linearity trace with its truly impressive average AVO of 12,000 V/mV. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. Analog Devices also performs additional testing to ensure consistent high open-loop gain at various output voltages. Figure 25 is a simple open-loop gain test circuit. THERMOCOUPLE AMPLIFIER WITH COLDJUNCTION COMPENSATION An example of a precision circuit is a thermocouple amplifier that must accurately amplify very low level signals without introducing linearity and offset errors to the circuit. In this circuit, an S-type thermocouple with a Seebeck coefficient of 10.3 μV/°C produces 10.3 mV of output voltage at a temperature of 1000°C. The amplifier gain is set at 973.16, thus, it produces an output voltage of 10.024 V. Extended temperature ranges beyond 1500°C are accomplished by reducing the amplifier gain. The circuit uses a low cost diode to sense the temperature at the terminating junctions and, in turn, compensates for any ambient temperature change. The OP177, with its high openloop gain plus low offset voltage and drift, combines to yield a precise temperature sensing circuit. Circuit values for other thermocouple types are listed in Table 5. Table 5. Thermocouple Type K J S Seebeck Coefficient 39.2 μV/°C 50.2 μV/°C 10.3 μV/°C R1 110 Ω 100 Ω 100 Ω R2 5.76 kΩ 4.02 kΩ 20.5 kΩ R7 102 kΩ 80.6 kΩ 392 kΩ R9 269 kΩ 200 kΩ 1.07 MΩ VX –10V 0V +10V +15V 00289-023 2 REF01 4 6 R3 47kΩ 1% 10.000V R7 392kΩ 1% 10µF + R9 1.07MΩ 0.05% +15V 0.1µF 10µF AVO ≥ 650V/mV RL = 2kΩ 2.2µF + Figure 23. Typical Precision Op Amp VY – TYPES ISOTHERMAL COLDJUNCTIONS R2 20.5kΩ 1% COPPER R8 1.0kΩ 0.05% R5 100Ω (ZERO ADJUSTMENT) R4 50Ω 1% – VX –10V 0V +10V + ISOTHERMAL BLOCK COPPER OP177 + 10µF 10µF 0.1µF VOUT AVO ≥ 12000V/mV RL = 2kΩ 00289-024 COLD-JUNCTION COMPENSATION R1 100Ω 1% Figure 24. Output Gain Linearity Trace VY 10kΩ VIN = ±10V ANALOG GROUND Figure 26. Thermocouple Amplifier with Cold Junction Compensation 10kΩ 1MΩ – 10Ω VX OP177 + RL 00289-025 Figure 25. Open-Loop Gain Linearity Test Circuit Rev. E | Page 9 of 16 00289-026 –15V ANALOG GROUND OP177 PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER The high gain, gain linearity, CMRR, and low TCVOS of the OP177 make it possible to obtain performance not previously available in single stage, very high gain amplifier applications. See Figure 27. For best CMR, ISOLATING LARGE CAPACITIVE LOADS The circuit shown in Figure 28 reduces maximum slew rate but allows driving capacitive loads of any size without instability. Because the 100 Ω resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open loop gain of the OP177. RF 10pF +15V 0.1µF INPUT RS 2 3 R1 R3 must equal R2 R4 In this example, with a 10 mV differential signal, the maximum errors are listed in Table 6. R2 1MΩ +15V 0.1µF R1 1kΩ R3 1kΩ R4 1MΩ 7 – + 7 6 100Ω OUTPUT OP177 4 0.1µF CLOAD 00289-028 2 3 – OP177 + 4 0.1µF 6 –15V Figure 28. Isolating Capacitive Loads BILATERAL CURRENT SOURCE 00289-027 –15V Figure 27. Precision High Gain Differential Amplifier The current sources shown in Figure 29 supply both positive and negative currents into a grounded load. Note that Table 6. High Gain Differential Amp Performance Type Common-Mode Voltage Gain Linearity, Worst Case TCVOS TCIOS Amount 0.1%/V 0.02% 0.0003%/°C 0.008%/°C ⎛ R4 ⎞ + 1⎟ R5⎜ ⎝ R2 ⎠ ZO = R5 + R 4 R3 − R2 R1 and that for ZO to be infinite R5 + R 4 R2 must = R3 R1 PRECISION ABSOLUTE VALUE AMPLIFIER The high gain and low TCVOS assure accurate operation with inputs from microvolts to volts. In this circuit, the signal always appears as a common-mode signal to the op amps (for details, see Figure 30). Rev. E | Page 10 of 16 OP177 BASIC CURRENT SOURCE R3 1kΩ R1 100kΩ R2 100kΩ 100m A CURRENT SOURCE R3 +15V 2 3 VIN – OP177 + R4 990Ω 6 R5 10Ω IOUT ≤ 15mA VIN R1 R2 2 3 – OP177 + R4 6 50Ω 2N2222 2N2907 –15V R5 IOUT ≤ 100mA 00289-029 IOUT = VIN R3 R1 × R5 GIVEN R3 = R4 + R5, R1 = R2 Figure 29. Bilateral Current Source 1kΩ +15V +15V 0.1µF C1 30pF D1 1N4148 0.1µF 7 6 VOUT 0 < VOUT < 10V 0.1µF 1kΩ 2 3 – + 7 6 2N4393 R3 2kΩ 2 3 – + OP177 4 OP177 VIN 4 0.1µF –15V –15V Figure 30. Precision Absolute Value Amplifier 1kΩ +15V 0.1µF 7 6 1N4148 NC 2 2N930 1kΩ CH 7 +15V 0.1µF 2 1kΩ 3 – + OP177 4 0.1µF VIN – AD820 3 + 4 6 VOUT 0.1µF –15V RESET 1kΩ –15V Figure 31. Precision Positive Peak Detector Rev. E | Page 11 of 16 00289-031 00289-030 OP177 PRECISION POSITIVE PEAK DETECTOR In Figure 31, CH must be polystyrene, Teflon®, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the AD820. +15V RS 1kΩ R1 2kΩ 0.1µF 2 3 CC RF 100kΩ PRECISION THRESHOLD DETECTOR/AMPLIFIER In Figure 32, when VIN < VTH, amplifier output swings negative, reverse biasing diode D1. VOUT = VTH if RL = ∞. When VIN ≥ VTH, the loop closes. VTH VIN – + 7 6 D1 1N4148 OP177 VOUT 4 0.1µF 00289-032 ⎛ R⎞ VOUT = VTH + (VIN − VTH ) ⎜1 + F ⎟ ⎜ RS ⎟ ⎝ ⎠ CC is selected to smooth the response of the loop. –15V Figure 32. Precision Threshold Detector/Amplifier Rev. E | Page 12 of 16 OP177 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.005 (0.13) MIN COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 8-Lead Plastic Dual In-Line Package (PDIP) P-Suffix (N-8) Dimensions show in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 4 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) × 45° 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 8-Lead Standard Small Outline Package (SOIC_N) S-Suffix (R-8) Dimensions shown in millimeters and( inches) Rev. E | Page 13 of 16 OP177 ORDERING GUIDE Model OP177FP OP177FPZ 1 OP177GP OP177GPZ1 OP177FS OP177FS-REEL OP177FS-REEL7 OP177FSZ1 OP177FSZ-REEL1 OP177FSZ-REEL71 OP177GS OP177GS-REEL OP177GS-REEL7 OP177GSZ1 OP177GSZ-REEL1 OP177GSZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option P-Suffix (N-8) P-Suffix (N-8) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) Z = Pb-free part. Rev. E | Page 14 of 16 OP177 NOTES Rev. E | Page 15 of 16 OP177 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00289-0-5/06 (E) Rev. E | Page 16 of 16