OP271EZ

a FEATURES Excellent Speed: 8.5 V/ms Typ Fast Settling (0.01%): 2 ms Typ Unity-Gain Stable High-Gain Bandwidth: 5 MHz Typ Low Input Offset Voltage: 200 mV Max Low Offset Voltage Drift: 21 mV/∞C Max High Gain: 400 V/mV Min Outstanding CMR: 106 dB Min Industry Standard 8-Pin Dual Pinout Available in Die Form GENERAL DESCRIPTION High-Speed, Dual Operational Amplifier OP271 PIN CONNECTIONS –IN A 1 +IN A 2 NC 3 V– 4 NC 5 +IN B 6 –IN B 7 NC 8 16 15 14 13 12 11 10 9 OUT A NC NC V+ NC NC OUT B NC NC = NO CONNECT The OP271 is a unity-gain stable monolithic dual op amp featuring excellent speed, 8.5 V/ms typical, and fast settling time, 2 ms typical to 0. 01%. The OP271 has a gain bandwidth of 5 MHz with a high phase margin of 62∞. Input offset voltage of the OP271 is under 200 mV with input offset voltage drift below 2 mV/∞C, guaranteed over the full military temperature range. Open-loop gain exceeds 400,000 into a 10 kW load ensuring outstanding gain accuracy and linearity. The input bias current is under 20 nA limiting errors due to source resistance. The OP271’s outstanding CMR, over 106 dB, and low PSRR, under 5.6 mV/V, reduce errors caused by ground noise and power supply fluctuations. In addition, the OP27l exhibits high CMR and PSRR over a wide frequency range, further improving system accuracy. OUT A 1 –IN A 2 +IN A 3 V– 4 16-Pin SOL (S-Suffix) 8 V+ A –+ B +– 7 OUT B 6 –IN B 5 +IN B Epoxy Mini-DIP (P-Suffix) 8-Pin Hermetic DIP (Z-Suffix) V+ BIAS OUT –IN +IN V– R EV. A Figure 1. Simplified Schematic (One of the two amplifiers is shown.) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP271–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V = ± 15 V, T = 25∞C, unless otherwise noted.) S A Parameter INPUT OFFSET VOLTAGE INPUT OFFSET CURRENT INPUT BIAS CURRENT INPUT NOISE VOLTAGE DENSITY LARGE-SIGNAL VOLTAGE GAIN INPUT VOLTAGE RANGE Symbol VOS IOS IB Conditions OP271A/E Min Typ Max 75 200 10 20 Min OP271F Typ Max 150 4 6 300 15 40 Min OP271G Typ Max 200 7 12 400 20 60 Unit mV nA nA VCM = 0 V VCM = 0 V 1 4 en AVO fO = 1 kHz VO = ± 10 V RL = 10 kW RL = 2 kW 400 300 ± 12 RL ≥ 2 kW VCM = ± 12 V VS = ± 4.5 V to ± 18 V 5.5 AV = +1 No Load ± 12 106 7.6 650 500 ± 12.5 ± 13 120 0.6 8.5 62 45 6.5 3.2 5.5 300 200 ± 12 ± 12 100 7.6 500 300 ± 12.5 ± 13 115 1.8 8.5 62 4.5 6.5 5.6 5.5 250 175 ± 12 ± 12 90 7.6 400 250 ± 12.5 ± 13 105 2.4 8.5 62 4.5 6.5 7.0 nV/Hz V/mV V/mV V V dB mV/V V/ms degrees mA IVR OUTPUT VOLTAGE SWING VO COMMON-MODE REJECTION POWER SUPPLY REJECTION RATIO SLEW RATE PHASE MARGIN CMR PSRR SR um SUPPLY CURRENT (ALL AMPLIFIERS) ISY GAIN BANDWIDTH PRODUCT CHANNEL SEPARATION INPUT CAPACITANCE INPUT RESISTANCE DIFFERENTIALMODE INPUT RESISTANCE COMMON MODE SETTLING TIME GBW CS VO = 20 Vp-p fO = 10 Hz 125 125 5 175 175 3 125 125 5 175 175 3 5 175 175 3 MHz dB dB pF CIN RIN 0.4 0.4 0.4 MW RINCM tS AV = +1, 10 V Step to 0.01% 20 20 20 GW 2 2 2 ms NOTES 1 Guaranteed by CMR test. 2 Guaranteed but not 100% tested. –2– REV. A OP271 ELECTRICAL CHARACTERISTICS (V = ± 15 V, –55∞C £ T £ 125∞C for OP271A, unless otherwise noted.) S A Parameter INPUT OFFSET VOLTAGE AVERAGE INPUT OFFSET VOLTAGE DRIFT INPUT OFFSET CURRENT INPUT BIAS CURRENT LARGE-SIGNAL VOLTAGE GAIN INPUT VOLTAGE RANGE1 OUTPUT VOLTAGE SWING COMMON-MODE REJECTION POWER SUPPLY REJECTION RATIO SUPPLY CURRENT (ALL AMPLIFIERS) NOTE 1 Guaranteed by CMR test. Symbol VOS TCVOS IOS IB AVO Conditions Min OP271A Typ 115 0.4 Max 400 2 30 60 Unit mV mV/∞C nA nA V/mV V/mV V V dB VCM = 0 V VCM = 0 V VO = ± 10 V RL = 10 kW RL = 2 kW RL ≥ 2 kW VCM = ± 12 V VS = ± 4.5 V to ± 18 V No Load 300 200 ± 12 ± 12 100 1.5 7 600 500 ± 12.5 ± 13 120 1.0 5.3 IVR VO CMR PSRR ISY 5.6 75 mV/V mA ELECTRICAL CHARACTERISTICS Parameter INPUT OFFSET VOLTAGE Symbol VOS Conditions (VS = ± 15 V, –40∞C £ TA £ +85∞C, unless otherwise noted.) Min OP271A/E Typ Max 100 330 Min OP271F Typ Max 215 560 Min OP271G Typ Max 300 700 Unit mV AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS INPUT OFFSET CURRENT INPUT BIAS CURRENT LARGE-SIGNAL VOLTAGE GAIN INPUT VOLTAGE RANGE1 IOS IB AVO VCM = 0 V VCM = 0 V V O = ± 10 V RL = 10 kW RL = 2 kW 300 200 ± 12 RL ≥ 2 kW ± 12 0.4 1 6 600 500 ± 12.5 ± 13 120 0.7 2 30 60 200 100 ± 12 ± 12 94 5.6 1 5 10 500 400 ± 12.5 ± 13 115 51.8 4 40 70 150 90 ± 12 ± 12 90 10 2.0 15 15 400 300 ± 12.5 ± 13 100 2.0 5 50 80 mV/∞C nA nA V/mV V/mV V V dB IVR OUTPUT VOLTAGE SWING VO COMMON-MODE REJECTION POWER SUPPLY REJECTION RATIO CMR PSRR VCM = ± 12 V 100 VS = ± 4.5 V to ± 18 V No Load 15 mV/V SUPPLY CURRENT (ALL AMPLIFIERS) ISY NOTE 1 Guaranteed by CMR test. 5.2 7.2 5.2 7.2 5.2 7.2 mA REV. A –3– OP271 (Continued from Page 1) ORDERING GUIDE The OP271 offers outstanding dc and ac matching between channels. This is especially valuable for applications such as multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters. The OP271 conforms to the industry standard, 8-pin dual op amp pinout. It is pin compatible with the TL072, TL082, LF412, and 1458/1558 dual op amps and can be used to significantly improve systems using these devices. For applications requiring lower voltage noise, see the OP270. For a quad version of the OP271, see the OP471. ABSOLUTE MAXIMUM RATINGS 1 TA = 25∞C VOS Max (mV) 200 200 300 400 400 Package CERDIP 8-Pin *OP271AZ *OP271EZ *OP271FZ OP271GP *OP271GS Operating Temperature Range MIL XND XND XND XND Plastic *Not for new design, obsolete April 2002. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 1.0 V Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ± 25 mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Output Short-Circuit Duration . . . . . . . . . . . . . . Continuous Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300∞C Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C Operating Temperature Range OP271A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C OP271E, OP271F, OP271G . . . . . . . . . . . –40∞C to +85∞C Package Type 8-Pin Hermetic DIP (Z) 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 3 jA jC Unit ∞C/W ∞C/W ∞C/W 134 96 92 12 37 27 NOTES 1 Absolute maximum ratings apply to packaged parts, unless otherwise noted. 2 The OP271’s inputs are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low-noise performance. If differential voltage exceeds ± 1.0 V, the input current should be limited to ± 25 mA. 3 jA is specified for worst case mounting conditions, i.e., jA is specified for device in socket for CERDIP and P-DIP packages; jA is specified for device soldered to printed circuit board for SOIC package. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP271 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. A Typical Performance Characteristics– OP271 100 25 0.1 VOLTAGE NOISE DENSITY – nV/ Hz TOTAL HARMONIC DISTORTION – % VOLTAGE NOISE DENSITY – nV/ Hz TA = 25 C VS = 15V 40 20 10 5 4 3 2 1 TA = 25 C 20 AT 10Hz TA = 25 C VS = 15V VO = 10Vp-p RL = 2k AV = 100 15 0.01 AV = 10 1/f CORNER = 40Hz 10 AT 1kHz AV = 1 1 100 10 FREQUENCY – Hz 1k 5 0 5 10 15 SUPPLY VOLTAGE – Volts 20 0.001 10 100 1k FREQUENCY – Hz 10k TPC 1. Voltage Noise Density vs. Frequency TPC 2. Voltage Noise Density vs. Supply Voltage TPC 3. Total Harmonic Distortion vs. Frequency 10.0 CURRENT NOISE DENSITY – pA/ Hz 120 10 INPUT OFFSET VOLTAGE – V CHANGE IN OFFSET VOLTAGE – TA = 25 C VS = 15V VS = 100 80 60 40 20 0 –20 –75 V 15V 9 8 7 6 5 4 3 2 1 0 0 TA = 25 C VS = 15V 1.0 1/f CORNER = 40Hz 0.1 10 100 1k FREQUENCY – Hz 10k –50 –25 0 25 50 75 TEMPERATURE – C 100 125 1 2 3 TIME – Minutes 4 5 TPC 4. Current Noise Density vs. Frequency TPC 5. Input Offset Voltage vs. Temperature TPC 6. Warm-Up Offset Voltage Drift 10 8 6 4 2 0 –2 –75 –50 –25 0 25 50 75 TEMPERATURE – C VS = 15V VCM = 0V 5 4 INPUT OFFSET CURRENT – nA 7 TA = 25 C VS = 15V INPUT BIAS CURRENT – nA INPUT BIAS CURRENT – nA 3 2 1 0 –1 –2 –3 –4 6 5 4 3 100 125 –5 –75 –50 –25 0 25 50 75 TEMPERATURE – C 100 125 2 –12.5 –7.5 –2.5 0 2.5 7.5 COMMON MODE VOLTAGE – Volts 12.5 TPC 7. Input Bias Current vs. Temperature TPC 8. Input Offset Current vs. Temperature TPC 9. Input Bias Current vs. Common-Mode Voltage REV. A –5– OP271 130 120 110 100 90 TOTAL SUPPLY CURRENT – mA TOTAL SUPPLY CURRENT – mA 6 7 7 VS = 15V 6 TA = +125 C 5 CMR – dB 80 70 60 50 40 30 20 10 1 TA = 25 C VS = 15V 10 100 1k 10k FREQUENCY – Hz 100k 1M 5 4 TA = +25 C 4 3 TA = –55 C 0 10 15 5 SUPPLY VOLTAGE – Volts 20 3 –75 –50 –25 0 25 50 75 TEMPERATURE – C 100 125 TPC 10. CMR vs. Frequency TPC 11. Total Supply Current vs. Supply Voltage TPC 12. Total Supply Current vs. Temperature 140 TA = 25 C 120 100 140 120 TA = 25 C VS = 15V 80 TA = 25 C VS = 15V 100 80 60 40 20 0 –PSR CLOSED-LOOP GAIN – dB 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY – Hz 60 OPEN-LOOP GAIN – dB PSR – dB 80 +PSR 60 40 20 0 40 20 0 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY – Hz –20 1k 10k 100k 1M FREQUENCY – Hz 10M TPC 13. PSR vs. Frequency TPC 14. Open-Loop Gain vs. Frequency TPC 15. Closed-Loop Gain vs. Frequency 25 20 PHASE TA = 25 C VS = 15V 100 2000 TA = 25 C RL = 10k 80 VS = 15V 8 GAIN-BANDWIDTH PRODUCT – MHz OPEN-LOOP GAIN – V/mV OPEN-LOOP GAIN – dB GAIN PHASE MARGIN = 62 C PHASE SHIFT – DEG 15 10 5 0 –5 –10 120 140 160 180 PHASE MARGIN – DEG 1500 70 GBW 6 1000 60 m 4 500 50 2 1 2 3 45 FREQUENCY – MHz 6 7 8 10 0 0 5 10 15 SUPPLY VOLTAGE – Volts 20 40 –75 –50 –25 0 0 25 50 75 100 125 150 TEMPERATURE – C TPC 16. Open-Loop Gain, Phase Shift vs. Frequency TPC 17. Open-Loop Gain vs. Supply Voltage TPC 18. Gain-Bandwidth Product, Phase Margin vs. Temperature –6– REV. A OP271 28 PEAK-TO-PEAK AMPLITUDE – Volts 20 TA = 25 C VS = 15V THD = 1% RL = 10k 180 24 20 16 12 8 4 0 1k 18 MAXIMUM OUTPUT – Volts TA = 25 C VS = 15V POSITIVE SWING OUTPUT IMPEDANCE – 160 140 120 100 80 60 40 20 TA = 25 C VS = 15V 16 14 12 10 8 6 4 2 NEGATIVE SWING AV = 1 AV = 100 1k 100k 10k FREQUENCY – Hz 1M 10M 10k 100k 1M FREQUENCY – Hz 10M 0 100 1k LOAD RESISTANCE – 10k 0 100 TPC 19. Maximum Output Swing vs. Frequency TPC 20. Maximum Output Voltage vs. Load Resistance TPC 21. Output Impedance vs. Frequency 12 VS = 11 SLEW RATE – V/ S 190 15V CHANNEL SEPARATION – dB 180 170 160 150 140 130 120 110 100 90 80 TA = 25 C VS = 15V 10 –SR 9 +SR 8 7 6 0 25 50 75 –75 –50 –25 TEMPERATURE – C 100 125 70 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 22. Slew Rate vs. Temperature TPC 23. Channel Separation vs. Frequency TA = 25 C VS = 15V AV = +1 TA = 25 C VS = 15V AV = +1 5V 5s 50mV 200ns TPC 24. Large-Signal Transient Response TPC 25. Small Signal Transient Response REV. A –7– OP271 APPLICATION INFORMATION Capacitive Load Driving and Power Supply Considerations The OP217 is unity-gain stable and is capable of driving large capacitive loads without oscillating. Nonetheless, good supply bypassing is highly recommended. Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the OP271. In the standard feedback amplifier, the op amp’s output resistance combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. A simple circuit to eliminate this effect is shown in Figure 2. The added components, C1 and R3, decouple the amplifier from the load capacitance and provide additional stability. The values of C1 and R3 shown in Figure 8 are for a load capacitance of up to 1000 pF when used with the OP271. When Rf > 3 k , a pole created by Rf and the amplifier’s input capacitance (3 pF) creates additional phase shift and reduces phase margin. A small capacitor in parallel with Rf helps eliminate this problem. Computer Simulations Many electronic design and analysis programs include models for op amps which calculate AC performance from the location of poles and zeros. As an aid to designers utilizing such a program, major poles and zeros of the OP271 are listed below. Their location will vary slightly between production lots. Typically, they will be within 15% of the frequency listed. Use of this data will enable the designer to evaluate gross circuit performance quickly, but should not supplant rigorous characterization of a breadboard circuit. POLES ZEROS V+ C2 10 F + 15Hz 1.2 MHz 2 X 32 MHz 8 X 40 MHz APPLICATIONS R2 2.5 MHz 4 X 23 MHz - C3 0.1 F R1 VIN C1 200pF R3 50 OP271 C4 10 F + VOUT CL 1000pF Low Phase Error Amplifier The simple amplifier depicted in Figure 4, utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared to conventional amplifier designs. At a given gain, the frequency range for a specified phase accuracy is over a decade greater than for a standard single op amp amplifier. The low phase error amplifier performs second-order frequency compensation through the response of op amp A2 in the feedback loop of A1. Both op amps must be extremely well matched in frequency response. At low frequencies, the A1 feedback loop forces V2/(K1 + 1)=VIN. The A2 feedback loop forces VO/VIN=K1 + 1. The DC gain is determined by the resistor divider around A2. Note that, like a conventional single op amp amplifier, the DC gain is set by resistor ratios only. Minimum gain for the low phase error amplifier is 10. R2 R2 K1 R2 = R1 C5 0.1 F V– PLACE SUPPLY DECOUPLING CAPACITORS AT OP271 Figure 2. Driving Large Capacitive Loads Unity-Gain Buffer Applications When Rf 100 and the input is driven with a fast, large-signal pulse (>1 V), the output waveform will look as shown in Figure 3. During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. With Rf 500 , the output is capable of handling the current requirements (IL 20 mA at 10 V); the amplifier will stay in its active mode and a smooth transition will occur. R1 1/2 OP271E A2 V2 1/2 OP271E A1 R1 R1 K1 VIN VO ASSUME: A1 AND A2 ARE MATCHED. OP271 8.5V/ s AO(s) = s VO = (K1+1) VIN Figure 4. Low Phase Error Amplifier Figure 3. Pulsed Operation –8– REV. A OP271 0 –1 PHASE SHIFT – DEG –2 –3 –4 –5 –6 SINGLE OP AMP, CONVENTIONAL DESIGN CASCADED (TWO STAGES) LOW PHASE ERROR AMPLIFIER Dual 12-Bit Voltage Output DAC The dual voltage output DAC shown in Figure 6 will settle to 12-bit accuracy from zero to full scale in 2 s typically. The CMOS DAC-8222 utilizes a 12-bit, double-buffered input structure allowing faster digital throughput and minimizing digital feedback. Fast Current Pump Maximum output current of the fast current pump shown in Figure 7 is 11 mA. Voltage compliance exceeds 10 V with 15 V supplies. The current pump has an output resistance of over 3 M and maintains 12-bit linearity over its entire output range. 0.5 1.0 R3 10k –7 0.001 0.1 0.01 0.005 0.005 FREQUENCY RATIO – 1/ / Figure 5. Phase Error Comparison Figure 5 compares the phase error performance of the low phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. The low phase error amplifier shows a much lower phase error, particularly for frequencies where T