SSM-2122

a FEATURES 0.01% THD at +10 dBV In/Out 100 dB VCA Dynamic Range Low VCA Control Feedthrough 100 dB Level Detection Range Log/Antilog Control Paths Low External Component Count APPLICATIONS Compressors Expanders Limiters AGC Circuits Voltage-Controlled Filters Noise Reduction Systems Stereo Noise Gates Dynamic Range Processors/Dual VCA SSM2120/SSM2122 FUNCTIONAL BLOCK DIAGRAM V+ 36kΩ SIGNAL OUT CURRENT MIRRORS –VC +VC V+ V+ SIGNAL INPUT V+ 36kΩ IREF GENERAL DESCRIPTION V– The SSM2120 is a monolithic integrated circuit designed for the purpose of processing dynamic signals in various analog systems including audio. This “dynamic range processor” consists of two VCAs and two level detectors (the SSM2122 consists of two VCAs only). These circuit blocks allow the user to logarithmically control the gain or attenuation of the signals presented to the level detectors depending on their magnitudes. This allows the compression, expansion or limiting of ac signals, some of the primary applications for the SSM2120. PIN CONNECTIONS 22-Pin Plastic DIP (P Suffix) 16-Pin Plastic DIP (P Suffix) THRESH 1 1 LOG AV 1 2 CONOUT 1 3 SIGOUT 1 4 +VC1 5 CFT 1 6 22 GND 21 V+ 20 SIGOUT 2 19 +VC2 GND 1 SIGOUT 1 2 +VC1 3 CFT 1 4 16 GND 15 V+ 14 SIGOUT 2 SSM2120 18 CFT 2 13 +VC2 TOP VIEW –VC1 5 (Not to Scale) 12 CFT 2 11 –VC2 10 SIGIN 2 9 GND SSM2122 TOP VIEW 17 –VC2 –VC1 7 (Not to Scale) 16 SIGIN 2 15 RECIN 2 14 CONOUT 2 13 LOG AV 2 12 THRESH 2 SIGIN 1 6 IREF 7 V– 8 SIGIN 1 8 RECIN 1 9 IREF 10 V– 11 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM2120/SSM2122–SPECIFICATIONS, I (@V = 15 V, T = +25 C ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter POWER SUPPLY Supply Voltage Range Positive Supply Current Negative Supply Current VCAs Max ISIGNAL (In/Out) Output Offset Control Feedthrough (Trimmed) Gain Control Range Control Sensitivity Gain Scale Factor Drift Frequency Response Off Isolation Current Gain THD (Unity-Gain) Noise (20 kHz Bandwidth) LEVEL DETECTORS (SSM2120 ONLY) Detection Range Input Current Range Rectifier Input Bias Current Output Sensitivity (At LOG AV Pin) Output Offset Voltage Frequency Response IIN = 1 mA p-p IIN = 10 µA p-p IIN = 1 µA p-p CONTROL AMPLIFIERS (SSM2120 ONLY) Input Bias Current Output Drive (Max Sink Current) Input Offset Voltage Specifications are subject to change without notice. S A REF = 200 A, +VC = –VC = GND (AV = 0 dB). 0 dB = 1 V rms SSM2120/SSM2122 Typ Max ± 18 10 –8 ± 350 ±8 +40 6 –3300 250 100 –0.5 0.005 –80 90 0.085 95 2800 4 3 ± 0.5 1000 50 7.5 ± 85 7.5 ± 0.5 ± 175 ± 4.2 ± 3.4 +0.5 0.04 Conditions Min ±5 Units V mA mA µA µA µV dB mV/dB ppm/°C kHz dB dB % dB dB µA p-p nA mV/dB mV 8 –6 ± 300 RIN = ROUT = 36 kΩ, –30 dB ≤ AV ≤ 0 dB Unity-Gain –85 ± 325 ±1 ± 750 Unity Gain or Less At 1 kHz +VC = –VC = 0 V +10 dBV IN/OUT RE: 0 dBV kHz 5.0 nA mA mV ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Operating Temperature Range . . . . . . . . . . . . –10°C to +55°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . 10 mA Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type 16-Pin Plastic DIP (P) 22-Pin Plastic DIP (P) θJA1 86 70 θJC 10 7 Units °C/W °C/W Model SSM2120 SSM2122 Temperature Range –10°C to +50°C –10°C to +50°C Package Description 22-Pin Plastic DIP 16-Pin Plastic DIP Package Option (N-22) (N-16) NOTE 1 θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for P-DIP. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2120/SSM2122 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –2– REV. C SSM2120/SSM2122 +VC1 SSM2122 |I IN | FULL WAVE RECTIFIER 2V V+ RECIN 1 THRESH 1 CONOUT 1 INPUT 1 OUTPUT 1 –VC1 +VC2 CFT 1 LOG AV 1 V– V+ |I IN | INPUT 2 OUTPUT 2 RECIN 2 FULL WAVE RECTIFIER 2V –VC2 CFT 2 THRESH 2 CONOUT 2 LOG AV 2 V– Figure 1. SSM2120 Block Diagram VOLTAGE-CONTROLLED AMPLIFIERS VCA PERFORMANCE The two voltage-controlled amplifiers are full Class A current in/current out devices with complementary dB/V gain control ports. The control sensitivities are +6 mV/dB and –6 mV/dB. A resistor divider (attenuator) is used to adapt the sensitivity of an external control voltage to the range of the control port. It is best to use 200 Ω or less for the attenuator resistor to ground. VCA INPUTS Figures 2a and 2b show the typical THD and noise performance of the VCAs over ± 20 dB gain/attenuation. Full Class A operation provides very low THD. 0.03 REFERENCE PIN THD – % 0.003 –20 The signal inputs behave as virtual grounds. The input current compliance range is determined by the current into the reference current pin. 0.01 The reference current determines the input and output current compliance range of the VCAs. The current into the reference pin is set by connecting a resistor to V+. The voltage at the reference pin is about two volts above V– and the current will be –10 I REF [(V + ) – ((V – ) + 2 V )] = RREF 0 GAIN – dB 10 20 The current consumption of the VCAs will be directly proportional to IREF which is nominally 200 µA. The device will operate at lower current levels which will reduce the effective dynamic range of the VCAs. With a 200 µA reference current, the input and output clip points will be ± 400 µA. In general: ICLIP = ± 2 IREF VCA OUTPUTS NOISE – dBV a. VCA THD Performance vs. Gain (+10 dBV In/Out @ 1 kHz) –70 –80 The VCA outputs are designed to interface directly with the virtual ground inputs of external operational amplifiers configured as current-to-voltage converters. The outputs must operate at virtual ground because of the output stage’s finite output impedance. The power supplies and selected compliance range determines the values of input and output resistors needed. As an example, with ± 15 V supplies and ± 400 µA maximum input and output current, choose RIN = ROUT = 36 kΩ for an output compliance range of ± 14.4 V. Note that the signal path through the VCA including the output current-to-voltage converter is noninverting. –90 –20 –10 0 GAIN – dB 10 20 b. VCA Noise vs. Gain (20 kHz Bandwidth) Figure 2. Typical THD and Noise Performance REV. C –3– SSM2120/SSM2122 TRIMMING THE VCAs The control feedthrough (CFT) pins are optional control feedthrough null points. CFT nulling is usually required in applications such as noise gating and downward expansion. If trimming is not used, leave the CFT pins open. Trim Procedure 1. Apply a 100 Hz sine wave to the control point attenuator. The signal peaks should correspond to the control voltages which induce the VCAs maximum intended gain and at least 30 dB of attenuation. 2. Adjust the 50 kΩ potentiometer for the minimum feedthrough. (Trimmed control feedthrough is typically well under 1 mV rms when the maximum gain is unity using 36 kΩ input and output resistors.) Applications such as compressor/limiters typically do not require control feedthrough trimming because the VCA operates at unity-gain unless the signal is large enough to initiate gain reduction. In this case the signal masks control feedthrough. This trim is ineffective for voltage-controlled filter applications. LEVEL DETECTION CIRCUITS Note: It is natural to assume that with the addition of the averaging capacitor, the LOG AV output would become the average of the log of the absolute value of IIN. However, since the capacitor forces an ac ground at the emitter of the output transistor, the capacitor charging currents are proportional to the antilog of the voltage at the base of the output transistor. Since the base voltage of the output transistor is the log of the absolute value of IIN, the log and antilog terms cancel, so the capacitor becomes a linear integrator with a charging current directly proportional to the absolute value of the input current. This effectively inverts the order of the averaging and logging functions. The signal at the output therefore is the log of the average of the absolute value of IIN. USING DETECTOR PINS REC IN, LOGAV, THRESH AND CONOUT When applying signals to RECIN (rectifier input) an input series resistor should be followed by a low leakage blocking capacitor since RECIN has a dc voltage of approximately 2.1 V above ground. Choose RIN for a ± 1.5 mA peak signal. For ± 15 V operation this corresponds to a value of 10 kΩ. A 1.5 MΩ value of RREF from log average to –15 V will establish a 10 µA reference current in the logging transistor (Q1). This will bias the transistor in the middle of the detector’s dynamic current range in dB to optimize dynamic range and accuracy. The LOG AV outputs are buffered and amplified by unipolar drive op amps. The 39 kΩ, 1 kΩ resistor network at the THRESH pin provides a gain of 40. An attenuator from the CONOUT (control output) to the appropriate VCA control port establishes the control sensitivity. Use 200 Ω for the attenuator resistor to ground and choose RCON for the desired sensitivity. Care should be taken to minimize capacitive loads on the control outputs CONOUT. If long lines or capacitive loads are present, it is best to connect the series resistor RCON as closely to the CONOUT pin as possible. DYNAMIC LEVEL DETECTOR CHARACTERISTICS The SSM2120 contains two independent level detection circuits. Each circuit contains a wide dynamic range full-wave rectifier, logging circuit and a unipolar drive amplifier. These circuits will accurately detect the input signal level over a 100 dB range from 30 nA to 3 mA peak-to-peak. LEVEL DETECTOR THEORY OF OPERATION Referring to the level detector block diagram of Figure 3, the RECIN input is an AC virtual ground. The next block implements the full-wave rectification of the input current. This current is then fed into a logging transistor (Q1) whose pair transistor (Q2) has a fixed collector current of IREF. The LOG AV output is then: V LOG kT  |I IN| AV = ln   q  I REF  With the use of the LOG AV capacitor the output is then the log of the average of the absolute value of IIN. (The unfiltered LOG AV output has broad flat plateaus with sharp negative spikes at the zero crossing. This reduces the “work” that the averaging capacitor must do, particularly at low frequencies.) Figures 4 and 5 show the dynamic performance of the level detector to a change in signal level. The input to the detector (not shown) is a series of 500 ms tone bursts at 1 kHz in successive 10 dBV steps. The tone bursts start at a level of –60 dBV (with RIN = 10 k) and return to –60 dBV after each successive 10 dB step. Tone bursts range from –60 dBV to +10 dBV. Figure 4 shows the logarithmic level detector output. The output of the detector is 3 mV/dB at LOG AV and the amplifier gain is 40 which yields 120 mV/dB. Thus, the output at CONOUT is seen to increase by 1.2 V for each 10 dBV increase in input level. 1kΩ 39kΩ V+ RIN INPUT RECIN |I I N | FULL WAVE RECTIFIER Q1 2V LOG AV CAV Q2 IREF THRESH CONOUT RCON TO VC 200Ω V– RREF V– Figure 3. Level Detector –4– REV. C SSM2120/SSM2122 2V 100 90 1s The decay rates are linear ramps that are dependent on the current out of the LOG AV pin (set by RREF) and the value of CAV. The integration or decay time of the circuit is derived from the formula: Decrementation Rate (in dB/s) = I REF × 333 C AV 10 0% Table I. Settling Time (tS) for CAV = 10 F. tS = tS (CAV = 10 F) 5 dB Figure 4. Detector Output 2V 100 90 3 dB 21.46 26.83 28.33 27.79 2 dB 30.19 35.56 37.06 37.52 (+144 µs) (+46 µs) 1 dB 46.09 51.46 52.96 53.42 10 dB Step 20 dB Step 30 dB Step 40 dB Step 50 dB Step 60 dB Step 11.28 ms 16.65 18.15 18.61 APPLICATIONS 10 0% 50ms The following applications for the SSM2120 use both the VCAs and level detectors in conjunction to assimilate a variety of functions. The first section describes the arrangement of the threshold control in each control circuit configuration. These control circuits form the foundation for the applications to follow which include the downward expander, compressor/limiter and compandor. THRESHOLD CONTROL Figure 5. Overlayed Detector Output DYNAMIC ATTACK AND DECAY RATES Figure 5 shows the output levels overlayed using a storage scope. The attack rate is determined by the step size and the value of CAV. The attack time to final value is a function of the step size increase. Table I shows the values of total settling times to within 5 dB, 3 dB, 2 dB and 1 dB of final value with CAV = 10 µF. When step sizes exceed 40 dB, the increase in settling time for larger steps is negligible. To calculate the attack time to final value for any value of CAV, simply multiply the value in the chart by CAV/10 µF. Figure 6a shows the control circuit for a typical downward expander while Figure 6b shows a typical control curve. Here, the threshold potentiometer adjusts VT to provide a negative unipolar control output. This is typically used in noise gate, downward expander, and dynamic filter applications. This potentiometer is used in all applications to control the signal level versus control voltage characteristics. THRESHOLD RIN L V+ MONO OR R RIN RECIN |I IN | RLL 2V MONO – RIN = 10kΩ STEREO – RIN = 20kΩ LOG AV THRESHOLD CONTROL VT RT TO +VC 200Ω VCON V– 39kΩ CONOUT RCON + 1kΩ – CAV V– 1.5MΩ V– * *LOWER LIMIT CAN BE FIXED BY CONNECTING A RESISTOR RLL FROM RECIN TO GROUND VIN – dB b. Typical Downward Expander Control Curve Figure 6. Noise Gate/Downward Expander Control Circuit and Typical Response a. Control Circuit REV. C –5– SSM2120/SSM2122 In the noise gate, downward expander and compressor/limiter applications, this potentiometer will establish the onset of the control action. The sensitivity of the control action depends on the value of RT. For a positive unipolar control output add two diodes as shown in Figure 7a. This is useful in compressor/limiter applications. Figure 7b shows a typical response. Bipolar control outputs can be realized by adding a resistor from the op amp output to V+. This is useful in compandor circuits THRESHOLD CONTROL RIN L V+ MONO OR R RIN REC IN |I IN | 1kΩ 2V MONO – RIN = 10kΩ STEREO – RIN = 20kΩ LOG AV CAV V– THRESH 1.5MΩ V– VT RT 39kΩ CON OUT V+ as shown in Figure 8a, with its response in Figure 8b. The value of the resistor RPV will determine the maximum output from the control amplifier. STEREO COMPRESSOR/LIMITER The two control circuits of Figures 6 and 7 can be used in conjunction to produce composite control voltages. Figures 9a and 9b show this type of circuit and transfer function for a stereo compressor/limiter which also acts as a downward expander for noise gating. The output noise in the absence of a THRESHOLD RPV RCON TO –VC 200Ω + * VCON – *UPPER LIMIT CAN BE FIXED BY VALUE OF PULL UP RESISTOR (RPV) CONNECTED TO POSITIVE SUPPLY VIN – dB b. Typical Compressor/Limiter Control Curve Figure 7. Compressor/Limiter Control Circuit and Typical Response a. Control Circuit V+ RIN L V+ MONO OR R RIN RECIN |I I N | RLL 2V MONO – RIN = 10kΩ STEREO – RIN = 20kΩ LOG AV CAV V– THRESH 1.5MΩ V– 1kΩ V– GAIN * + VT RT RPV TO +VC OR –VC 39kΩ CONOUT 200Ω VT < 0 VT = 0 VT > 0 VCON – * *UPPER AND LOWER LIMITS CAN BE ESTABLISHED BY VALUES OF RPV AND RLL, RESPECTIVELY VIN – dB a. Control Circuit b. Typical Compandor Control Curves Figure 8. Compandor Control Circuit and Typical Curves EXPANSION THRESHOLD THRESHOLD EXP. FIGURE 6 L MONO OR R 200Ω VOUT – dB COMPRESSION THRESHOLD +VC THRESHOLD COM. FIGURE 7 –VC 200Ω * VIN – dB a. Control Circuit b. Input/Output Curve Figure 9. Control Circuit for Stereo Compressor/Limiter with Noise Gating and Input/Output Curve –6– REV. C SSM2120/SSM2122 +VC 200Ω SIGNAL INPUT 36kΩ 2200pF 47Ω 200Ω –VC V+ 10kΩ RECIN |I I N | 1kΩ RC 39kΩ 10pF –VC 36Ω 200Ω TRANSMISSION OR STORAGE MEDIUM V+ 10kΩ 1µF 10kΩ RECIN |I I N | 1kΩ 200Ω +VC V+ RE 39kΩ V+ 10kΩ 36kΩ 2200pF 47Ω SIGNAL OUTPUT 10pF 36kΩ 1µF 1µF LOG AV 4.7MΩ V– V– V– 1µF LOG AV 4.7MΩ V– Figure 10. Companding Noise Rejection System signal will be dependent on the noise of the current-to-voltage converter amplifier if the expansion ratio is high enough. As discussed in the Threshold Control section, the use of the control circuit of Figure 6, including the RPV to V+ and two diodes, yields positive unipolar control outputs. COMPANDING NOISE REDUCTION SYSTEM being used. As an extreme example, a household tape player would require a higher compression/expansion ratio than a professional stereo system. 20 IREF ≈ 3µA RREF = 4.7MΩ OVERALL RESPONSE 25dB OUTPUT SIGNAL LEVEL – dB 0 A complete companding noise reduction system is shown in Figure 10. Normally, to obtain an overall gain of unity, the value of RC is equal to RE. The values of RC/E will determine the compression/expansion ratio. Table II shows compression/expansion ratios ranging from 1.5:1 to full limiting with the corresponding values of RC/E. An example of a 2:1 compression/expansion ratio is plotted in Figure 11. Note that signal compression increases gain for low level signals and reduces gain for high levels while expansion does the reverse. The net result for the system is the same as the original input signal except that it has been compressed before being sent to a given medium and expanded after recovery. The compression/expansion ratio needed depends on the medium Table II. 2:1 EXPANSION –20 2:1 COMPRESSION –40 –60 –80 –80 –60 –40 –20 INPUT SIGNAL LEVEL – dB 0 20 Figure 11. Companding Noise Reduction with 2:1 Compression/Expansion Ratio Input Signal Increase (dB) 20 20 20 20 20 20 20 20 Gain (Reduction or Increase) (dB) 6.67 10.00 13.33 15.00 16.00 17.33 18.00 20.00 Compressor Only Output Signal Increase (dB) 13.33 10.00 6.67 5.00 4.00 2.67 2.00 0 Expander Only Output Signal Increase (dB) 22.67 30.00 33.33 35.00 36.00 37.33 38.00 40.00 Compression/ Expansion Ratio 1.5:1 2:1 3:1 4:1 5:1 7.5:1 10:1 AGC*/Limiter RC/E 11,800 7,800 5,800 5,133 4,800 4,415 4,244 3,800 VCONTROL – (mV/dB) 2.0 3.0 4.0 4.5 4.8 5.2 5.4 6.0 *AGC for Compression Only. REV. C –7– SSM2120/SSM2122 DYNAMIC FILTER Figure 12 shows a control circuit for a dynamic filter capable of single ended (nonencode/decode) noise reduction. Such circuits usually suffer from a loss of high frequency content at low signal levels because their control circuits detect the absolute amount of highs present in the signal. This circuit, however, measures wideband level as well as high frequency band level to produce a composite control signal combined in a 1:2 ratio respectively. The upper detector senses wideband signals with a cutoff of 20 Hz while the lower detector has a 5 kHz cutoff to sense only high frequency band signals. This approach allows very good noise masking with a minimum loss of “highs” when the signal level goes below the threshold. V+ 2.2µF THRESHOLD CONTROL V– 160kΩ THRESH 1kΩ LOG AV 3.3µF 2 1.5MΩ V– V+ 10kΩ 3300pF REC IN 15 FC = 5kHz (HIGH FREQUENCY) LOG AV 3.3µF 13 1.5MΩ V– 36kΩ 47Ω 2200pF 7 –VC 200Ω V– SIGIN 8 SIGOUT 5 5 +VC 36kΩ 36kΩ 36kΩ AUDIO OUTPUT 100pF THRESH 1kΩ 12 39kΩ CONOUT 5.6kΩ 14 200Ω 160kΩ V– 1 39kΩ CONOUT 12kΩ 3 AUDIO INPUT 10kΩ RECIN 9 |I IN | FC ≤ 20Hz (WIDEBAND) |I IN | Figure 12. Dynamic Noise Filter Circuit –8– REV. C SSM2120/SSM2122 HIGH-FREQUENCY SIGNAL LEVEL – dB Figures 13a–c show the filter’s 3 dB frequency response with the threshold potentiometer at V+, centered, and V–. Data was taken by applying a 300 Hz signal to the wideband detector and a 20 kHz signal to the high-frequency band detector simultaneously. These figures correspond to filter characteristics for 50 dB, 70 dB and 90 dB dynamic range program source material, respectively. The system could thus treat signals from anything ranging from 1/4" magnetic tape to high performance compact disc players. Note that in Figure 13a the control circuit is designed so that the minimum cutoff frequency is about 1 kHz. This occurs as the control circuit detects the noise floor of the source material. Dynamic filtering limits the signal bandwidth to less than 1 kHz unless enough highs are detected in the signal to cover the noise floor in the mid- and high frequency range. In this case the filter opens to pass more of the audio band as more highs are detected. The filter’s bandwidth can extend to 50 kHz with a nominal signal level at the input. At other signal levels with varying high frequency content, the filter will close to the required bandwidth. Here, noise outside the band is removed while the perceived noise is masked by other signals within the band. Even in this system, however, a certain amount of mid- and high frequency components will be lost, especially during transients at very low signal levels. This circuit does not address low frequency noise such as “hum” and “rumble.” 20 10 0 –10 –20 –30 –40 –50 1.0 1.0 1.0 1.9 1.0 1.0 6 2.75 1.2 1.0 17.8 8.3 3.9 1.7 1.0 50.6 26 11.7 5.5 2.4 1.1 50.6 50.6 26 11.7 5.5 2.4 1.1 50.6 50.6 50.6 26 11.7 5.5 2.4 1.1 –50 –40 –30 –20 –10 0 10 WIDEBAND SIGNAL LEVEL – dB 20 a. VTHRESH at V+ HIGH-FREQUENCY SIGNAL LEVEL – dB 20 10 0 –10 –20 –30 –40 –50 1.5 4.9 2.2 15.1 7.1 3.1 48 22 10 4.2 50.6 49.2 22 10 4.2 50.6 50.6 49.2 22 10 4.2 50.6 50.6 50.6 49.2 22 10 4.2 50.6 50.6 50.6 50.6 49.2 22 10 4.2 –50 –40 –30 –20 –10 0 10 WIDEBAND SIGNAL LEVEL – dB 20 b. VTHRESH Centered HIGH-FREQUENCY SIGNAL LEVEL – dB 20 10 0 –10 –20 –30 –40 –50 12.3 40 17.3 50.6 41 17.8 50.6 50.6 41 17.8 50.6 50.6 50.6 41 17.8 50.6 50.6 50.6 50.6 41 17.8 50.6 50.6 50.6 50.6 50.6 41 17.8 50.6 50.6 50.6 50.6 50.6 50.6 41 17.8 –50 –40 –30 –20 –10 0 10 WIDEBAND SIGNAL LEVEL – dB 20 c. VTHRESH at V– Figure 13. 3 dB Filter Response REV. C –9– SSM2120/SSM2122 V+ THRESHOLD V– 160kΩ RECIN IN |I I N | FC ≤ 20Hz LOG AV CAV1 1.5MΩ V– V+ RIN2 RECIN IN |I I N | FC = 5Hz LOG AV CAV2 1.5MΩ V– 36kΩ 47Ω 2200pF –VC 200Ω +VC V– 36kΩ 36kΩ 36kΩ 100pF 36kΩ 1kΩ 160kΩ 39kΩ CONOUT 5.6kΩ 200Ω DOWNWARD EXPANDER V– 1kΩ 12kΩ 39kΩ 12kΩ 200Ω V+ SIGNAL INPUT RIN1 CONOUT +VC 36kΩ 47Ω 2200pF –VC 200Ω SIGNAL OUTPUT Figure 14. Dynamic Filter with Downward Expander DYNAMIC FILTER WITH DOWNWARD EXPANDER –50 Downward expansion uses a VCA controlled by the level detector. This section maintains dynamic range integrity for all levels above the user adjustable threshold level. As the input level decreases below the threshold, gain reduction occurs at an increasing rate (see Figure 15). This technique reduces audible noise in fade outs or low level signal passages by keeping the standing noise floor well below the program material. This technique by itself is less effective for signals with predominantly low frequency content such as a bass solo where wideband frequency noise would be heard at full level. Also, since the level detector has a time constant for signal averaging, percussive material can modulate the noise floor causing a “pumping” or “breathing” effect. –60 –60 –75 Figure 15. Typical Downward Expander I/O Characteristics at –30 dB Threshold Level (1:1.5 Ratio) –10– REV. C OUTPUT – dB A composite single-ended noise reduction system can be realized by a combination of dynamic filtering and a downward expander. As shown in Figure 14, the output from the wideband detector can also be connected to the +VC control port of the second VCA which is connected in series with the sliding filter. This will act as a downward expander with a threshold that tracks that of the filter. Although both of these techniques are used for noise reduction, each alone will pass appreciable amounts of noise under some conditions. When used together, both contribute distinct advantages while compensating for each other’s deficiencies. The dynamic filter and downward expander techniques used together can be employed more subtly to achieve a given level of noise reduction than would be required if used individually. Up to 30 dB of noise reduction can be realized while preserving the crisp highs with a minimum of transient side effects. +20 +20 –30 INPUT – dB –30 –40 –45 SSM2120/SSM2122 FADER AUTOMATION The SSM2120 can be used in fader automation systems to serve two channels. The inverting control port is connected through an attenuator to the VCA control voltage source. The noninverting control port is connected to a control circuit (such as Figure 6) which senses the input signal level to the VCA. Above the threshold voltage, which can be set quite low (for example –60 dBV), the VCA operates at its programmed gain. Below this threshold the VCA will downward expand at a rate determined by the +VC control port attenuator. By keeping the release time constant in the 10 ms to 25 ms range, the modulation of the VCA standing noise floor (–80 dB at unity-gain), can be kept inaudibly low. The SSM2300 8-channel multiplexed sample-and-hold IC makes an excellent controller for VCAs in automation systems. Figure 16 shows the basic connection for the SSM2122 operating as a unity-gain VCA with its noninverting control ports grounded and access to the inverting control ports. This is typical for fader automation applications. Since this device is a pinout option of the SSM2120, the VCAs will behave exactly as described earlier in the VCA section. The SSM2122 can also be used with two or more op amps to implement complex voltage-controlled filter functions. Biquad and state-variable two-pole filters offering low pass, bandpass and high pass outputs can be realized. Higher order filters can also be formed by connecting two or more such stages in series. +15V 0.1µF 10pF 36kΩ 10pF 36kΩ 1 2 16 15 14 200Ω SIGOUT 1 V+ 1/2 TL082 200Ω 3 220kΩ 4 1/2 TL082 V+ 220kΩ 12 200Ω 6 11 10 2000pF 8 –15V 9 47Ω V– 36kΩ 7 0.1µF –VC2 SIGIN 2 50kΩ* SIGOUT 2 50kΩ* V– –VC1 SIGIN 1 36kΩ 2000pF 47Ω V+ 150kΩ 200Ω 13 SSM2122 5 *OPTIONAL CONTROL FEEDTHROUGH TRIM Figure 16. SSM2122 Basic Connection (Control Ports at 0 V) REV. C –11– SSM2120/SSM2122 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 16 1 9 8 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) 22-Pin Plastic DIP (N-22) 1.080 (27.43) 1.020 (25.91) 22 1 12 11 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) PIN 1 0.210 (5.33) MAX 0.060 (1.52) 0.015 (0.38) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) SEATING PLANE 0.045 (1.15) 0.015 (0.381) 0.008 (0.204) –12– REV. C PRINTED IN U.S.A. C2088–2–11/95