SSM-2275

a FEATURES Single or Dual-Supply Operation Excellent Sonic Characteristics Low Noise: 7 nV/√Hz Low THD: 0.0006% Rail-to-Rail Output High Output Current: 50 mA Low Supply Current: 1.7 mA/Amplifier Wide Bandwidth: 8 MHz High Slew Rate: 12 V/ s No Phase Reversal Unity Gain Stable Stable Parameters Over Temperature APPLICATIONS Multimedia Audio Professional Audio Systems High Performance Consumer Audio Microphone Preamplifier MIDI Instruments GENERAL DESCRIPTION OUT A 1 –IN A +IN A V– 2 3 4 Rail-to-Rail Output Audio Amplifiers SSM2275/SSM2475* PIN CONFIGURATIONS 8-Lead Narrow Body SOIC (SO-8) 8 V+ 14-Lead Narrow Body SOIC (R-14) OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 14 OUT D 13 –IN D 12 +IN D SSM2275 (Not to Scale) 7 6 5 OUT B –IN B +IN B SSM2475 (Not to Scale) 11 V– 10 +IN C 9 8 –IN C OUT C 8-Lead microSOIC (RM-8) OUT A –IN A +IN A V– 1 8 V+ OUT B –IN B +IN B OUT A –IN A +IN A V+ +IN B –IN B OUT B 14-Lead TSSOP (RU-14) 1 14 OUT D –IN D +IN D V– +IN C –IN C OUT C SSM2275 4 5 SSM2475 7 8 The SSM2275 and SSM2475 use the Butler Amplifier front end, which combines both bipolar and FET transistors to offer the accuracy and low noise performance of bipolar transistors and the slew rates and sound quality of FETs. This product family includes dual and quad rail-to-rail output audio amplifiers that achieve lower production costs than the industry standard OP275 (the first Butler Amplifier offered by Analog Devices). This lower cost amplifier also offers operation from a single 5 V supply, in addition to conventional ± 15 V supplies. The ac performance meets the needs of the most demanding audio applications, with 8 MHz bandwidth, 12 V/µs slew rate and extremely low distortion. The SSM2275 and SSM2475 are ideal for application in high performance audio amplifiers, recording equipment, synthesizers, MIDI instruments and computer sound cards. Where cascaded stages demand low noise and predictable performance, SSM2275 and SSM2475 are a cost effective solution. Both are stable even when driving capacitive loads. The ability to swing rail-to-rail at the outputs (see Applications section) and operate from low supply voltages enables designers to attain high quality audio performance, even in single supply systems. The SSM2275 and SSM2475 are specified over the extended industrial (–40°C to +85°C) temperature range. The SSM2275 is available in 8-lead plastic DIPs, SOICs, and microSOIC surfacemount packages. The SSM2475 is available in narrow body SOICs and thin shrink small outline (TSSOP) surface-mount packages. *Protected by U.S. Patent No. 5,101,126. 8-Lead Plastic DIP (N-8) OUT A –IN A +IN A V– 1 2 3 4 (Not to Scale) 8 7 6 5 V+ OUT B –IN B +IN B SSM2275 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 SSM2275/SSM2475–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V = S 15 V, T A = Conditions 25 C, VCM = 0 V unless otherwise noted) Min Typ 1 1 250 300 5 15 –14 80 80 100 80 14 14.5 100 100 240 120 14.5 14.7 –14 –14.6 –14.3 ± 50 ± 40 110 105 1.7 1.75 0.0006 12 8 128 8 1 kHz f > 1 kHz AVO OUTPUT CHARACTERISTICS Output Voltage, High Output Voltage, Low VOH VOL ISC Output Short Circuit Current Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Total Harmonic Distortion Slew Rate Gain Bandwidth Product Channel Separation NOISE PERFORMANCE Voltage Noise Spectral Density Current Noise Spectral Density Specifications subject to change without notice. ± 25 ± 17 85 80 –13.5 –14.4 –13.9 ± 75 ± 80 PSRR ISY 2.9 3.0 THD SR GBW CS en in 9 –2– REV. A SSM2275/SSM2475 ELECTRICAL CHARACTERISTICS Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio AVO OUTPUT CHARACTERISTICS Output Voltage, High Output Voltage, Low VOS IB IOS VIN CMRR (VS = 5 V, TA = 25 C, VCM = 2.5 V unless otherwise noted) Min Typ 1 1 250 300 5 15 0.3 85 80 60 50 4.5 4.8 0.6 0.3 0.7 40 1.7 1.75 0.0006 12 6 128 8 1 kHz f > 1 kHz 25 20 4.2 4.5 VOH VOL ISC ISY 1.0 0.5 1.1 Output Short Circuit Current Limit POWER SUPPLY Supply Current/Amplifier DYNAMIC PERFORMANCE Total Harmonic Distortion Slew Rate Gain Bandwidth Product Channel Separation NOISE PERFORMANCE Voltage Noise Spectral Density Current Noise Spectral Density Specifications subject to change without notice. 2.9 3.0 THD SR GBW CS en in REV. A –3– SSM2275/SSM2475 Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 15 V Storage Temperature Range . . . . . . . . . . . . 65° C to 150°C Operating Temperature Range . . . . . . . . . . . 40°C to 85°C Junction Temperature Range . . . . . . . . . . . . 65° C to 150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300°C ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,000 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supplies less than ± 15 V, the input voltage and differential input voltage must be less than ± 15 V. ABSOLUTE MAXIMUM RATINGS 1 Package Type 8-Lead Plastic DIP 8-Lead SOIC 8-Lead microSOIC 14-Lead SOIC 14-Lead TSSOP JA* JC Units °C/W °C/W °C/W °C/W °C/W 103 158 206 120 180 43 43 43 36 35 *θ JA is specified for the worst case conditions, i.e., for device in socket for DIP packages and soldered onto a circuit board for surface mount packages. ORDERING GUIDE Model SSM2275P SSM2275S SSM2275RM SSM2475S SSM2475RU Temperature Range –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C Package Description 8-Lead PDIP 8-Lead SOIC 8-Lead microSOIC 14-Lead SOIC 14-Lead TSSOP Package Options N-8 SO-8 RM-8 R-14 RU-14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2275/SSM2475 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 100 VS = 2.5V RL = 2k CL = 10pF 225 100 80 60 PHASE – Degrees GAIN – dB VS = 2.5V RL = 600 CL = 10pF 225 180 135 PHASE – Degrees 80 60 GAIN – dB 40 180 135 90 40 20 0 90 45 0 20 0 –20 –40 10 45 0 –45 –90 10M 40M –20 –40 10 –45 –90 10M 40M 100 1k 10k 100k FREQUENCY – Hz 1M 100 1k 10k 100k FREQUENCY – Hz 1M Figure 1. Phase/Gain vs. Frequency Figure 2. Phase/Gain vs. Frequency –4– REV. A Typical Characteristics–SSM2275/SSM2475 100 80 60 GAIN – dB VS = 15V RL = 2k CL = 10pF 225 180 135 PHASE – Degrees VOLTAGE NOISE DENSITY – nV/ Hz 60 VS = TA = 50 15V 25 C 40 40 20 0 90 45 0 30 20 –20 –40 10 –45 –90 10M 40M 10 100 1k 10k 100k FREQUENCY – Hz 1M 0 10 100 1k FREQUENCY – Hz 10k 100k Figure 3. Phase/Gain vs. Frequency Figure 6. SSM2275 Voltage Noise Density (Typical) 100 80 60 GAIN – dB VS = 15V RL = 600 CL = 10pF 225 180 135 PHASE – Degrees 140 120 100 VS = TA = 15V 25 C 40 20 0 COMMON MODE REJECTION – dB 90 45 0 80 60 40 –20 –40 10 –45 –90 10M 40M 20 0 100 100 1k 10k 100k FREQUENCY – Hz 1M 1k 10k 1M FREQUENCY – Hz 10M 30M Figure 4. Phase/Gain vs. Frequency Figure 7. Common-Mode Rejection vs. Frequency 2.0 1.8 CURRENT NOISE DENSITY – pA/ Hz 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 10 VS = TA = 15V 25 C POWER SUPPLY REJECTION – dB 140 120 100 VS = TA = 15V 25 C 80 60 40 20 0 100 100 1k FREQUENCY – Hz 10k 1k 10k FREQUENCY – Hz 1M 10M Figure 5. SSM2275 Current Noise Density vs. Frequency Figure 8. Power Supply Rejection vs. Frequency REV. A –5– SSM2275/SSM2475–Typical Characteristics SSM2275/SSM2475 –100 VSY = +5V AV = +1 RL = 100k VIN = 0dBV 1.0 0.9 VOH, VOL (VOLTS-TO-RAIL) – V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –160 0 2 4 6 8 10 12 14 FREQUENCY – kHz 16 18 20 22 0 5 10 15 LOAD CURRENT – mA 20 VOUT – (V–) VOUT – (V+) –110 AMPLITUDE – dBV –120 –130 –140 –150 Figure 9. THD vs. Frequency (FFT) Figure 12. Headroom (VOH and VOL-to-Rails), TA = +25°C 29.5mV 11.0mV 0 0 0 20mV 200ns 20mV 200ns 0 Figure 10. Small Signal Response; R L = 600 Ω, C L = 0 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p Figure 13. Small Signal Response; RL = 600 Ω, CL = 200 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p 35.5mV 22.5mV 0 20mV 200ns 0 0 20mV 200ns 0 Figure 11. Small Signal Response; RL = 600 Ω, CL = 100 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p Figure 14. Small Signal Response; RL = 600 Ω, CL = 300 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p –6– REV. A SSM2275/SSM2475 17.5mV 43.0mV 0 20mV 200ns 0 0 20mV 200ns 0 Figure 15. Small Signal Response; RL = 2 k Ω, CL = 0 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p Figure 18. Small Signal Response; RL = 2 kΩ, C L = 300 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p 31.0mV 10.5mV 0 0 20mV 200ns 0 20mV 100ns 0 Figure 16. Small Signal Response; R L = 2 kΩ, CL = 100 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p Figure 19. Small Signal Response; RL = 600 Ω, C L = 0 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p 38.0mV 22.5mV 0 0 20mV 200ns 0 20mV 100ns 0 Figure 17. Small Signal Response; R L = 2 kΩ, CL = 200 pF, VS = ± 2.5 V, AV = +1, VIN = 100 mV p-p Figure 20. Small Signal Response; RL = 600 Ω, CL = 100 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p REV. A –7– SSM2275/SSM2475–Typical Characteristics 28.0mV 29.0mV 0 0 20mV 200ns 0 20mV 100ns 0 Figure 21. Small Signal Response; RL = 600 Ω, CL = 200 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p Figure 24. Small Signal Response; RL = 2 kΩ, CL = 100 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p 35.5mV 36.5mV 0 20mV 200ns 0 0 20mV 100ns 0 Figure 22. Small Signal Response; RL = 600 Ω, CL = 300 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p Figure 25. Small Signal Response; RL = 2 kΩ, CL = 200 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p 13.0mV 42.0mV 0 0 0 20mV 100ns 20mV 200ns 0 Figure 23. Small Signal Response; RL = 2 kΩ, CL = 0 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p Figure 26. Small Signal Response; RL = 2 kΩ, CL = 300 pF, VS = ± 15 V, AV = +1, VIN = 100 mV p-p –8– REV. A SSM2275/SSM2475 THEORY OF OPERATION The SSM2275 and SSM2475 are low noise and low distortion rail-to-rail output amplifiers that are excellent for audio applications. Based on the OP275 audiophile amplifier, the SSM2275/ SSM2475 offers many similar performance characteristics with the advantage of a rail-to-rail output from a single supply source. Its low input voltage noise figure of 7 nV/√Hz allows the device to be used in applications requiring high gain, such as microphone preamplifiers. Its 11 V/µs slew rate also allows the SSM2275/SSM2475 to produce wide output voltage swings while maintaining low distortion. In addition, its low harmonic distortion figure of 0.0006% makes the SSM2275 and SSM2475 ideal for high quality audio applications. Figure 27 shows the simplified schematic for a single amplifier. The amplifier contains a Butler Amplifier at the input. This front-end design uses both bipolar and MOSFET transistors in the differential input stage. The bipolar devices, Q1 and Q2, improve the offset voltage and achieve the low noise performance, while the MOS devices, M1 and M2, are used to obtain higher slew rates. The bipolar differential pair is biased with a proportional-to-absolute-temperature (PTAT) bias source, IB1, while the MOS differential pair is biased with a non-PTAT source, IB2. This results in the amplifier having a constant gainbandwidth product and a constant slew rate over temperature. The amplifier also contains a rail-to-rail output stage that can sink or source up to 50 mA of current. As with any rail-to-rail output amplifier the gain of the output stage, and consequently the open loop gain of the amplifier, is proportional to the load resistance. With a load resistance of 50 kΩ, the dc gain of the amplifier is over 110 dB. At load currents less than 1 mA, the output of the amplifier can swing to within 30 mV of either supply rail. As load current increases, the maximum voltage swing of the output will decrease. This is due to the collector to emitter saturation voltage of the output transistors increasing with an increasing collector current. Input Overvoltage Protection ± 7 V, then the input current should be limited to less than ± 5 mA. This can be easily done by placing a resistor in series with both inputs. The minimum value of the resistor can be determined by: RIN = VDIFF , MAX − 7 0.01 (1) There are also ESD protection diodes that are connected from each input to each power supply rail. These diodes are normally reversed biased, but will turn on if either input voltage exceeds either supply rail by more than 0.6 V. Again, should this condition occur the input current should be limited to less than ± 5 mA. The minimum resistor value should then be: RIN = VIN , MAX 5 mA (2) In practice, RIN should be placed in series with both inputs to reduce offset voltages caused by input bias current. This is shown in Figure 28. V+ RIN RIN V– Figure 28. Using Resistors for Input Overcurrent Protection Output Voltage Phase Reversal The maximum input differential voltage that can be applied to the SSM2275/SSM2475 is ± 7 V. A pair of internal back-to-back Zener diodes are connected across the input terminals. This prevents emitter-base junction breakdown from occurring to the input transistors, Q1 and Q2, when very large differential voltages are applied. If the device’s differential voltage could exceed The SSM2275/SSM2475 was designed to have a wide commonmode range and is immune to output voltage phase reversal with an input voltage within the supply voltages of the device. However, if either of the device’s inputs exceeds 0.6 V above the positive voltage supply, the output could exhibit phase reversal. This is due to the input transistor’s B–C junction becoming forward biased, causing the polarity of the input terminals of the device to switch. VCC IB2 IN– Q1 Q2 IN+ CFI OUT M1 M2 IB1 VEE Figure 27. Simplified Schematic REV. A –9– SSM2275/SSM2475 This phase reversal can be prevented by limiting the input current to +1 mA. This can be done by placing a resistor in series with the input terminal that is expected to be overdriven. The series resistance should be at least: RIN = VIN , MAX − 0.6 1 mA (3) An equivalent resistor should be placed in series with both inputs to prevent offset voltages due to input bias currents, as shown in Figure 28. Output Short Circuit Protection For example, with the 8-lead SOIC, the calculation gives a maximum internal power dissipation (for all amplifiers, worst case) of PMAX = (150°C – 85°C)/158 °C/W = 0.41 W. For the DIP package, a similar calculation indicates that 0.63 W (approximately 50% more) can be safely dissipated. Note that ambient temperature is defined as the temperature of the PC board to which the device is connected (in the absence of radiated or convected heat loss). It is good practice to place higher power devices away from the more sensitive circuits. When in doubt, measure the temperature in the vicinity of the SSM2275 with a thermocouple thermometer. Maximizing Low Distortion Performance To achieve high quality rail-to-rail performance, the output of the SSM2275/SSM2475 is not short-circuit protected. Shorting the output may damage or destroy the device when excessive voltages or currents are applied. To protect the output stage, the maximum output current should be limited to ± 40 mA. Placing a resistor in series with the output of the amplifier as shown in Figure 29, the output current can be limited. The minimum value for RX can be found from Equation 4. RX = VSY 40 mA (4) Because the SSM2275/SSM2475 is a very low distortion amplifier, careful attention should be given to the use of the device to prevent inadvertently introducing distortion. Source impedances seen by both inputs should be made equal, as shown in Figure 28, with RB = R1 RF for minimum distortion. This eliminates any offset voltages due to varying bias currents. Proper power supply decoupling reduces distortion due to power supply variations. Because the open loop gain of the amplifier is directly dependent on the load resistance, loads of less than 10 kΩ will increase the distortion of the amplifier. This is a trait of any rail-to-rail op amp. Increasing load capacitance will also increase distortion. It is recommended that any unused amplifiers be configured as a unity gain follower with the noninverting input tied to ground. This minimizes the power dissipation and any potential crosstalk from the unused amplifier. As with many FET-type amplifiers, the PMOS devices in the input stage exhibit a gate-to-source capacitance that varies with the common mode voltage. In an inverting configuration, the inverting input is held at a virtual ground and the common-mode voltage does not vary. This eliminates distortion due to input capacitance modulation. In noninverting applications, the gateto-source voltage is not constant, and the resulting capacitance modulation can cause a slight increase in distortion. Figure 30 shows a unity gain inverter and a unity gain follower configuration. Figure 31 shows an FFT of the outputs of these amplifiers with a 1 kHz sine wave. Notice how the largest harmonic amplitude (2nd harmonic) is –120 dB below the fundamental (0.0001%) in the inverting configuration. V+ 10 F 0.1 F RFB R1 VIN RB RL 0.1 F 10 F 0.1 F RFB R1 VOUT VIN 0.1 F 10 F RB RL V+ 10 F For a +5 V single supply application, RX should be at least 125 Ω. Because RX is inside the feedback loop, VOUT is not affected. The trade off in using RX is a slight reduction in output voltage swing under heavy output current loads. RX will also increase the effective output impedance of the amplifier to RO + RX, where RO is the output impedance of the device. RFB RX 125 FEEDBACK VOUT A1 = 1/2 SSM2275 A1 Figure 29. Output Short Circuit Protection Configuration Power Dissipation Considerations While many designers are constrained to use very small and low profile packages, reliable operation demands that the maximum junction temperatures not be exceeded. A simple calculation will ensure that your equipment will enjoy reliable operation over a long lifetime. Modern IC design allows dual and quad amplifiers to be packaged in SOIC and microSOIC packages, but it is the responsibility of the designer to determine what the actual junction temperature will be, and prevent it from exceeding the 150° C. Note that while the θJC is similar between package options, the θJA for the SOIC and TSSOP are nearly double the PDIP. The calculation of maximum ambient temperature is relatively simple to make. PMAX = TI , MAX − TA (5) SSM2275 SSM2275 VOUT V– V– θ JA Figure 30. Basic Inverting and Noninverting Amplifiers –10– REV. A SSM2275/SSM2475 –100 –110 NOISE – dBV –120 –130 –140 –150 –160 0 –100 –110 NOISE – dBV –120 –130 –140 –150 –160 0 10 FREQUENCY – kHz 20 22 VSY = 5V AV = –1 RL = 100k VIN = 0dBV 10 FREQUENCY – kHz 20 22 VSY = 5V AV = 1 RL = 100k VIN = 0dBV STEP SIZE – V 10 8 0.1% 6 4 2 0 –2 –4 –6 –0.01% –8 –10 400 600 800 SETTLING TIME – ns 1000 1200 0.01% Figure 33. Settling Time vs. Step Size Overdrive Recovery Figure 31. Spectral Graph of Amplifier Outputs Settling Time The high slew rate and wide gain-bandwidth product of the SSM2275 and SSM2475 amplifiers result in fast settling times (tS < 1 µs) that are suitable for 16- and 20-bit applications. The test circuit used to measure the settling time of the SSM2275/ SSM2475 is shown in Figure 32. This test method has advantages over false-sum node techniques of measuring settling times in that the actual output of the amplifier is measured, instead of an error voltage at the sum node. Common-mode settling effects are also taken into account in this circuit in addition to slew rate and bandwidth factors. The output waveform of the device under test is clamped by Schottky diodes and buffered by the JFET source follower. The signal is amplified by a factor of ten by the OP260 current feedback amplifier and then Schottky-clamped at the output to the oscilloscope. The 2N2222 transistor sets up the bias current for the JFET and the OP41 is configured as a fast integrator, providing overall dc offset nulling at the output. 9V–15V – + +15V 0.1 F V+ DUT V– 0.1 F + – D1 D2 RL 1k The overdrive, or overload, recovery time of an amplifier is the time required for the output voltage to return to a rated output voltage from a saturated condition. This recovery time can be important in applications where the amplifier must recover quickly after a large transient event, or overload. The circuit in Figure 34 was used to evaluate the recovery time for the SSM2275/SSM2475. Also shown are the input and output voltages. It takes approximately 0.5 µs for the device to recover from output overload. RS 909 VIN 2V p-p 10kHz +5V R1 1k RL 10k –5V RF 10k VOUT Figure 34. Overload Recovery Time Test Circuit 1k D3 D4 OUTPUT (TO SCOPE) 2N4416 1/2 OP260AJ 1F RF 2k 10k 10k IC2 9V–15V 5V RG 222 2N2222A 750 1N4148 15k –15V SCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ IC2 IS PMI OP41EJ Figure 32. Settling Time Test Fixture REV. A –11– SSM2275/SSM2475 Capacitive Loading The output of the SSM2275/SSM2475 can tolerate a degree of capacitive loading. However, under certain conditions, a heavy capacitive load could create excess phase shift at the output and put the device into oscillation. The degree of capacitive loading is dependent on the gain of the amplifier. At unity gain, the amplifier could become unstable at loads greater than 600 pF. At gain greater than unity, the amplifier can handle a higher degree of capacitive load without oscillating. Figure 35 shows how to configure the device to prevent oscillations from occurring. CFB RFB RI VIN VOUT RB 50k CL VIN VOUT RB 50k CL RI CFB RFB For the values given in Figure 36, RIN = 5 kΩ. With C1 omitted the circuit will provide a balanced output down to dc, otherwise the –3 dB corner for the input frequency is set by: f −3dB = 1 2 π RIN CL (8) The circuit can also be configured to provide additional gain if desired. The gain of the circuit is: AV = V OUT 2( R2) = R1 V IN (9) where VOUT = VO1 – VO2 , R 1 = R3 = R5 = R7 and, R2 = R4 = R6 = R8 Figure 37 shows the THD+N versus frequency response of the circuit while driving a 600 Ω load at 1 V rms. C3 33pF R1 10k R2 10k +12V C1* 10 F R11 10k +12V R12 10k +5V R5 10k R9 50 V01 SSM2275 SSM2275 INVERTING GAIN AMPLIFIER NONINVERTING GAIN AMPLIFIER Figure 35. Configurations for Driving Heavy Capacitive Loads RB should be at least 50 kΩ. To minimize offset voltage, the parallel combination of RFB and RI should be equal to RB. Setting a minimum CF of 15 pF bandlimits the amplifier enough to eliminate any oscillation problems from any sized capacitive load. The low-pass frequency is determined by: f −3dB = 1 2 π RFBCF (6) VIN SSM2475-A C4 33pF R7 10k R8 10k +12V R3 10k R10 50 V02 R13 100k C2 10 F R14 100k R6 10k C3 10 F With RFB = 50 kΩ and CF = 15 pF, this results in an amplifier with a 210 kHz bandwidth that can be used with any capacitive load. If the amplifier is being used in a noninverting unity gain configuration and RI is omitted, CFB should be at least 100 pF. If the offset voltage can be tolerated at the output, RFB can be replaced by a short and CFB can be removed entirely. With the typical input bias current of 200 nA and RB = 50 kΩ, the increase in offset voltage would be 10 mV. This configuration will stabilize the amplifier under all capacitive loads. Single Supply Differential Line Driver SSM2475-C C1* IS OPTIONAL SSM2475-B R4 10k C4 10 F R13 and R14 set up the common-mode output voltage equal to half of the supply voltage. C1 is used to couple the input signal and can be omitted if the input’s dc voltage is equal to half of the supply voltage. The minimum input impedance of the circuit as seen from VIN is: RIN = R1 + R5 || R3 + R7 || R11 THD + N – % Figure 36 shows a single supply differential line driver circuit that can drive a 600 Ω load with less than 0.001% distortion. The design mimics the performance of a fully balanced transformer based solution. However, this design occupies much less board space while maintaining low distortion and can operate down to dc. Like the transformer based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Figure 36. A Low Noise, Single Supply Differential Line Driver 0.1 VSY = 12V RL = 600 0.01 0.001 ( )( ) (7) 0.0001 20 100 1k FREQUENCY – Hz 10k 20k Figure 37. THD+N vs. Frequency of Differential Line Driver –12– REV. A SSM2275/SSM2475 Multimedia Soundcard Microphone Preamplifier The low distortion and low noise figures of the SSM2275 make it an excellent device for amplifying low level audio signals. Figure 38 shows how the SSM2275 can be configured as a stereo microphone preamplifier driving the input to a multimedia sound codec, the AD1848. The SSM2275 can be powered from the same +5 V single supply as the AD1848. The VREF pin on the AD1848 provides a bias voltage of 2.25 V for the SSM2275. This voltage can also be used to provide phantom power to a condenser microphone through a 2N4124 transistor buffer and 2 kΩ resistors. The phantom power circuitry can be omitted for dynamic microphones. The gain of SSM2275 amplifiers is set by R2/R1 which is 100 (40 dB) as shown. Figure 39 shows the device’s THD+N performance with a 1 VRMS output. R2 10k +5V 10 F L CHANNEL MIC IN R1 100 10 F 3 2k 10k +5V 2N4124 R CHANNEL MIC IN 10 F 2k 10k 5 10 F R1 100 7 6 28 RMIC 0.1 F 2 8 The AD1862 has a built in 3 kΩ resistor that is connected from the inverting input to the output of the amplifier. The full-scale output current of the AD1862 is ± 1 mA, resulting in a maximum output voltage of ± 3 V. Additional feedback resistance can be added in the feedback loop to increase the output voltage. With RFB connected the maximum output voltage will be: VOUT ,MAX = 1 mA × 3 kΩ + RFB +12V VCC 16 12 11 10 TO LPF 100pF RFB (OPTIONAL) ( ) (10) AD1862 ACOM IOUT RF SSM2275-A NOTE: ADDITIONAL PIN CONNECTIONS OMITTED FOR CLARITY 1 29 35/36 34/37 32 1/2 4 SSM2275 +5V 0.1 F LMIC VCC GND VREF Figure 40. A High Performance I-V Converter for a 20-Bit DAC AD1848 1/2 SSM2275 R2 10k Figure 38. Low Noise Microphone Preamplifier for Multimedia Soundcard Codec 1 AV = +40dB VSY = ±2.5V VIN = –40dBV RL > 10k BW = 22kHz In Figure 41, the SSM2275 is used as a low-pass filter for one channel of the AD1855, a 24-bit 96 kHz stereo sigma-delta DAC, which uses a complementary voltage output. The filter is configured as a second order low-pass Bessel filter with a cutoff frequency of 50 kHz. This provides a phase linear response from dc to 24 kHz, which is ideal for high quality audio applications. The SSM2275 can be connected to the same +5 V power supply source, that the AD1855 is connected to, eliminating the need for extra power circuitry. The FILT output (Pin 14) from the AD1855 provides a common reference voltage equal to half of the supply voltage for the SSM2275. Amplifier A1 is used as a unity-gain inverter for the positive output of the AD1855. The output of A1 is combined with a negative output of the AD1855 into the active low pass filter around A2. The output impedance of each output of the AD1855 is 100 Ω which must be taken into account to achieve proper dc gain, which in Figure 41 is unity gain. In this configuration the SSM2275 can drive reasonable capacitive loads, making the device suitable for the RCA jack line outputs found in most consumer audio equipment. +5V VDD VDD OUT– 28 18 13 OR 18 1.05k 1.15k 12 OR 17 1.05k A1 FILT GND GND 14 1 15 +5V NOTE: ADDITIONAL PIN CONNECTIONS OMITTED FOR CLARITY 0.1 F 10 F A1 AND A2 ARE SSM2275 OR 1/2 SSM2475 1.15k 10 F 562 237 A2 OUT 4.7nF 0.1 THD + N – % 0.01 0.001 20 100 1k FREQUENCY – Hz 10k 20k AD1855 OUT+ Figure 39. THD+N vs. Frequency (VSY = +5 V, AV = 40 dB, VOUT = 1 V rms) High Performance I-V Converters and Filters for 20-Bit DACs Because of the increasing resolution and lower harmonic distortions required by more audio applications, the need for high quality amplifiers at the output of D/A converters becomes critical. The SSM2275 and SSM2475 can be used as current-tovoltage converters and smoothing filters for 18- and 20-bit DACs, achieving 0.0006% THD+N figures while running from the same +5 V or +12 V source used to power the D/A converter. Figure 40 shows how the SSM2275 can be used with the AD1862, a current output 20-bit DAC. Figure 41. Low-Pass Filter for a 24-Bit Stereo SigmaDelta DAC REV. A –13– SSM2275/SSM2475 SPICE Macro-model The SPICE macro-model for the SSM2275 is shown in Listing 1 on the following page. This model is based on typical values for the device and can be downloaded from Analog Devices’ Internet site at www.analog.com. The model uses a common emitter output stage to provide rail-to-rail performance. A resistor and dc voltage source, in series with the collector, accurately portray output dropout voltage versus output current. The VCMH and VCML sources set the upper and lower limits of the input common mode voltage range. Both are set up as a function of the supply voltage to mimic the varying common mode range with supply voltage. The EOS voltage source establishes the offset voltage and is also used to create the commonmode rejection and power supply rejection characteristics for the model. A secondary pole section is also set up to vary the gain bandwidth product and phase margin of the model based on the supply voltage. The H1 and VR1 sources set up an equivalent resistor that is linearly varied with supply voltage. This equivalent resistance, in parallel with C2, creates the secondary pole. G2 is also linearly varied to increase the GBW at higher supply voltages. With a supply voltage of 5 V, the gain bandwidth product is 6.3 MHz with a 47 degree phase margin. At a 30 V supply voltage, the GBW product moves out to 7.5 MHz with 48° phase margin. The broadband input referred voltage noise for the model is 6.8 nV/√Hz. Flicker noise characteristics are also accurately modeled with the 1/f corner frequency set through the KF and AF terms in the input stage transistors. Finally, a voltage-controlled current source, GSY, is used to model the amplifier’s supply current versus supply voltage characteristics. +5V SUPPLY 1 2 3 4 5 6 7 8 VL LL 18-BIT DAC VBL 16 15 1/2 SSM2275 3 7.68k 9.76k 2 330pF 4 47kΩ 8 1 220 F LEFT CHANNEL OUTPUT DL CK DR LR 18-BIT SERIAL REG. VREF VOL 14 13 AD1868 18-BIT SERIAL REG. VREF 7.68k AGND 12 11 VOR 7.68k 10 100pF DGND VBR 18-BIT DAC VS 7.68k 9 330pF 9.76k 6 100pF 1/2 SSM2275 220 F 7 47k RIGHT CHANNEL OUTPUT 5 Figure 42. A Smoothing Filter for an 18-Bit Stereo DAC –14– REV. A SSM2275/SSM2475 Listing 1: SSM2275 SPICE Macro-Model * SSM2275 SPICE Macro-Model Typical Values * 8/97, Ver. 1 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT SSM2275 1 2 99 50 45 * * INPUT STAGE * Q1 4 3 5 QNIX Q2 6 2 7 QNIX RC1 99 11 15E3 RC2 99 12 15E3 RE1 5 8 1E3 RE2 7 8 1E3 EOS 3 1 POLY(2) (61,98) (73,98) 1.5E-3 1.78E-5 1 IOS 1 2 5E-9 ECMH1 4 11 POLY(1) (99,50) 0.9 -30E-3 ECMH2 6 12 POLY(1) (99,50) 0.9 -30E-3 ECML1 9 50 POLY(1) (99,50) 0.1 30E-3 ECML2 10 50 POLY(1) (99,50) 0.1 30E-3 D1 9 5 DX D2 10 7 DX D3 13 1 DZ D4 2 13 DZ IBIAS 8 50 200E-6 * * CMRR=115 dB, ZERO AT 1kHz, POLE AT 10kHz * ECM1 60 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 60 61 159.2E3 RCM2 61 98 17.66E3 CCM1 60 61 1E-9 * * PSRR=120dB, ZERO AT 1kHz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 1.59E6 CPS3 72 73 1E-10 RPS4 73 98 1.59 * * INTERNAL VOLTAGE REFERENCE * RSY1 99 91 100E3 RSY2 50 90 100E3 VSN1 91 90 DC 0 EREF 98 0 (90,0) 1 GSY 99 50 POLY(1) (99,50) 0.97E-3 -7E-6 * * ADAPTIVE POLE AND GAIN STAGE * AT Vsy= 5, fp=12.50MHz,Av=1 * AT Vsy=30, fp=18.75MHz,Av=1.16 * G2 98 20 POLY(2) (4,6) (99,50) 0 80.3E-6 0 0 2.79E-6 VR1 20 21 DC 0 H1 21 98 POLY(2) VR1 VSN1 0 11.317E3 0 0 -28.29E6 C2 20 98 1.2E-12 * * POLE AT 90MHz * G3 98 23 (20,98) 565.5E-6 R5 23 98 1.768E3 C3 23 98 1E-12 * * GAIN STAGE * G1 98 30 (23,98) 733.3E-6 R1 30 98 9.993E3 CF 30 45 200E-12 D5 31 99 DX D6 50 32 DX V1 31 30 0.6 V2 30 32 0.6 * * OUTPUT STAGE * Q3 46 42 99 QPOX Q4 47 44 50 QNOX RO1 46 48 30 RO2 47 49 30 VO1 45 48 15E-3 VO2 49 45 10E-3 RB1 41 42 200 RB2 43 44 200 EO1 99 41 POLY(1) (98,30) 0.7528 1 EO2 43 50 POLY(1) (30,98) 0.7528 1 * * MODELS * .MODEL QNIX NPN(IS=1E-16,BF=400,KF=1.96E-14,AF=1) .MODEL QNOX NPN(IS=1E-16,BF=100,VAF=130) .MODEL QPOX PNP(IS=1E-16,BF=100,VAF=130) .MODEL DX D(IS=1E-16) .MODEL DZ D(IS=1E-14,BV=6.6) .ENDS SSM2275 REV. A –15– SSM2275/SSM2475 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 14 1 14-Lead SOIC (R-14) 0.3444 (8.75) 0.3367 (8.55) 8 7 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) SEATING PLANE 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 14-Lead TSSOP (RU-14) 0.201 (5.10) 0.193 (4.90) 0.280 (7.11) 0.240 (6.10) 1 4 0.177 (4.50) 0.169 (4.30) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE 0.195 (4.95) 0.115 (2.93) 1 7 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 0.006 (0.15) 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.256 (6.50) 0.246 (6.25) 0.325 (8.25) 0.300 (7.62) 14 8 8-Lead microSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) SEATING PLANE 8° 0° 0.028 (0.70) 0.020 (0.50) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33° 27° 0.028 (0.71) 0.016 (0.41) –16– REV. A PRINTED IN U.S.A. C3239a–0–4/99