SSM2402P

a Dual Audio Analog Switches SSM2402/SSM2412 FUNCTIONAL BLOCK DIAGRAM TE FEATURES “Clickless” Bilateral Audio Switching Guaranteed “Break-Before-Make” Switching Low Distortion: 0.003% typ Low Noise: 1 nV/√Hz Superb OFF-Isolation: 120 dB typ Low ON-Resistance: 60 V typ Wide Signal Range: VS = 618 V; 10 V rms Wide Power Supply Range: 620 V max Available in Dice Form GENERAL DESCRIPTION O B SO LE The SSM2402/SSM2412 are dual analog switches designed specifically for high performance audio applications. Distortion and noise are negligible over the full audio operating range of 20 Hz to 20 kHz at signal levels of up to 10 V rms. The SSM2402/ SSM2412 offer a monolithic integrated alternative to expensive and noisy relays or complex discrete JFET circuits. Unlike conventional general-purpose CMOS switches, the SSM2402/SSM2412 provide superb fidelity without audio “clicks” during switching. Conventional TTL or CMOS logic can be used to control the switch state. No external pull-up resistors are needed. A “T” configuration provides superb OFF-isolation and true bilateral operation. The analog inputs and outputs are protected against overload and overvoltage. An important feature is the guaranteed “break-before-make” for all units, even IC-to-IC. In large systems with multiple switching channels, all separate switching units must open before any switch goes into the ON-state. With the SSM2402/ SSM2412, you can be certain that multiple circuits will all break-before-make. The SSM2402/SSM2412 represent a significant step forward in audio switching technology. Distortion and switching noise are significantly reduced in the new SSM2402/SSM2412 bipolarJFET switches relative to CMOS switching technology. Based on a new circuit topology that optimizes audio performance, the SSM2402/SSM2412 make use of a proprietary bipolarJFET process with thin-film resistor network capability. Nitride capacitors, which are very area efficient, are used for the proprietary ramp generator that controls the switch resistance transition. Very wide bandwidth amplifiers control the gate-to-source voltage over the full audio operating range for each switch. The ON-resistance remains constant with changes in signal amplitude and frequency, thus distortion is very low, less than 0.01% max. The SSM2402 is the first analog switch truly optimized for high-performance audio applications. For broadcasting and other switching applications which require a faster switching time, we recommend the SSM2412—a dual analog switch with one-third of the switching time of the SSM2402. PIN CONNECTIONS 14-Pin Epoxy DIP (P-Suffix) 16-Pin SOL (S-Suffix) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 SSM2402/SSM2412–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ VS = 618 V, RL = OPEN, and –408C ≤ TA ≤ +858C unless otherwise noted. All specifications, tables, graphs, and application data apply to both the SSM2402 and SSM2412, unless otherwise noted.) SSM2402/SSM2412 Min Typ Max Units Parameter Symbol Conditions POSITIVE SUPPLY CURRENT +ISY VIL = 0.8 V, 2.0 V1 6.0 7.5 mA NEGATIVE SUPPLY CURRENT –ISY VIL = 0.8 V, 2.0 V 1 4.8 6.0 mA GROUND CURRENT IGND VIL = 0.8 V, 2.0 V1 0.6 1.5 mA DIGITAL INPUT HIGH VINH TA = Full Temperature Range DIGITAL INPUT LOW VINL TA = Full Temperature Range LOGIC INPUT CURRENT ILOGIC VIN = 0 V to 15 V2 VANALOG 3 IANALOG ANALOG CURRENT RANGE 1.0 –14.2 RON 0.8 V 5.0 µA +14.2 V –10 VIN = ± VSUPPLY OVERVOLTAGE INPUT CURRENT SWITCH ON RESISTANCE V +10 TE ANALOG VOLTAGE RANGE 3 20 ± 40 –14.2 V ≤ VA ≤ +14.2 V IA = ± 10 mA, VIL = 2.0 V TA = +25°C TA = Full Temperature Range Tempco (∆RON/∆T) 60 mA mA 85 115 Ω Ω Ω/°C 1 5 % 0.2 RON MATCH –14.2 V ≤ VA ≤ +14.2 V IA = ± 10 mA, VIL = 2.0 V SWITCH ON LEAKAGE CURRENT IS(ON) VIL = 2.0 V –14.2 V ≤ VA ≤ +14.2 V VA = 0 V 0.05 0.05 1.0 10.0 µA nA VIL = 0.8 V –14.2 V ≤ VA ≤ +14.2 V VA = 0 V 0.05 0.05 1.0 10.0 µA nA B SO SWITCH OFF LEAKAGE CURRENT IS(OFF) LE RON MATCH tON VA = +10 V, RL = 2 kΩ TA = +25°C, See Test Circuit SSM2402 SSM2412 10.0 3.5 ms TURN-OFF TIME5 tOFF VA = +10 V, RL = 2 kΩ TA = +25°C, See Test Circuit SSM2402 SSM2412 4.0 1.5 ms BREAK-BEFORE-MAKE TIME DELAY6 tOFF–tON TA = +25°C SSM2402 SSM2412 6.0 2.0 ms CHARGE INJECTION Q TA = +25°C SSM2402 SSM2412 50 150 pC ON-STATE INPUT CAPACITANCE CS(ON) VA = 1 V rms f = 5 kHz, TA = +25°C 12 pF OFF-STATE INPUT CAPACITANCE CS(OFF) VA = 1 V rms f = 5 kHz, TA = +25°C 4 pF OFF ISOLATION ISO(OFF) VA = 10 V rms, 20 Hz to 20 kHz TA = +25°C, See Test Circuit 120 dB CHANNEL-TO-CHANNEL CROSSTALK CT VA = 10 V rms, 20 Hz to 20 kHz TA = +25°C 96 dB TOTAL HARMONIC DISTORTION7 THD 0 V to 10 V rms, 20 Hz to 20 kHz TA = +25°C, RL = 5 kΩ 0.003 0.01 % SPECTRAL NOISE DENSITY en 20 Hz to 20 kHz, TA = +25°C 1 nV/√Hz WIDEBAND NOISE DENSITY en p-p 20 Hz to 20 kHz, TA = +25°C 0.2 µV p-p O TURN-ON TIME4 NOTES 1 “VIL” is the Logic Control Input. 2 Current tested at V IN = 0 V. This is the worst case condition. 3 Guaranteed by RON test condition. 4 Turn-ON time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the final value. 5 Turn-OFF time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the initial value. 6 Switch is guaranteed by design to provide break-before-make operation. 7 THD guaranteed by design and dynamic R ON testing. Specifications subject to change without notice. –2– REV. A SSM2402/SSM2412 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Operating Supply Voltage Range . . . . . . . . . . . . . . . . . ± 20 V Analog Input Voltage Range Continuous . . . . . . . . . . . . . . V– +3.5 V ≤ VA ≤ V+ –3.5 V Maximum Current Through Switch . . . . . . . . . . . . . . 20 mA Logic Input Voltage Range . . . . . . . . . . . . V+ Supply to –2 V V+ Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V V– Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 V VA to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V Package Type uJA* uJC Units 14-Pin Plastic DIP (P) 16-Pin SOL (S) 76 92 33 27 °C/W °C/W Model Temperature Range Package Description SSM2402P SSM2402S –40°C to +85°C –40°C to +85°C 14-Pin Plastic DIP 16-Pin SOL SSM2412P SSM2412S –40°C to +85°C –40°C to +85°C 14-Pin Plastic DIP 16-Pin SOL DICE CHARACTERISTICS Die Size 0.105 × 0.097 Inch, 10,185 sq. mils (2.667 × 2.464 mm, 6.57 sq. mm) B SO LE TE *θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for P-DIP package; θJA is specified for device soldered to printed circuit board for SOL package. Timing Diagram WAFER TEST LIMITS Symbol Conditions1 Limit Units POSITIVE SUPPLY CURRENT +ISY VIL = 0.8 V 7.5 mA max NEGATIVE SUPPLY CURRENT –ISY VIL = 0.8 V 6.0 mA max GROUND CURRENT IGND VIL = 0.8 V 1.5 mA max LOGIC INPUT CURRENT ILOGIC VIN = 0 V2 5.0 µA max SWITCH ON RESISTANCE RON –14.2 V ≤ VA ≤ +14.2 V IA = ± 10 mA, VIL = 2.0 V 85 Ω max RON MATCH BETWEEN SWITCHES RON MATCH –14.2 V ≤ VA ≤ +14.2 V IA = ± 10 mA, VIL = 2.0 V 5 % max SWITCH ON LEAKAGE CURRENT IS(ON) –14.2 V ≤ VA ≤ +14.2 V, VIL = 2.0 V 1.0 µA max SWITCH OFF LEAKAGE CURRENT IS(OFF) –14.2 V ≤ VA ≤ +14.2 V, VIL = 0.8 V 1.0 µA max O Parameter NOTES 1 VIL = Logic Control Input; V A = Applied Analog Input Voltage; I A = Applied Analog Input Current. 2 Worst Case Condition. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. REV. A –3– SSM2402/SSM2412–Typical Performance Characteristics “ON” Resistance vs. Analog Voltage TE “OFF” Isolation vs. Frequency B SO LE Total Harmonic Distortion vs. Frequency SSM2412 Switching Time vs. Temperature Channel Separation vs. Frequency Overvoltage Characteristics Leakage Current vs. Analog Voltage O SSM2402 Switching Time vs. Temperature Supply Current vs. Temperature –4– REV. A SSM2402/SSM2412 SSM2402 TON/TOFF Switching Response LE TE TON/TOFF Switching Response Test Circuit Switch ON/OFF Transition Test Circuit O B SO SSM 2412 TON/TOFF Switching Response “OFF” Isolation Test Circuit Switching ON/OFF Transition REV. A –5– SSM2402/SSM2412 O B SO LE TE Switching Time Test Circuit Simplified Schematic –6– REV. A SSM2402/SSM2412 APPLICATIONS INFORMATION FUNCTIONAL SECTIONS Each half of the SSM2402/SSM2412 are made up of three major functional blocks: 1. “T” Switch Consists of JFET switches S1 and S2 in series as the main switches and switch S3 as a shunt. 2. Ramp Generator TE Generates a ramp voltage on command of the Control Input (see Figure 1). A LOW-to-HIGH TTL input at Control Input initiates a ramp that goes from approximately –7 V to +7 V in 12 ms. Conversely, a HIGH-to-LOW TTL transition at Control Input will cause a downward ramp from approximately +7 V to –7 V in 12 ms for the SSM2402, and 4 ms for the SSM2412. The Ramp Generator also supplies the +3 V and –3 V reference levels for Switch Control. 3. Switch Control The ramp from the Ramp Generator section is applied to two differential amplifiers (DA1 and DA2) in the Switch Control block. (See Simplified Schematic). One amplifier is referenced to –3 V and the other is referenced to +3 V. Switch Control Outputs are: LE Figure 1. Ramp Generator B SO —Main Switch Control—Drives two 0.25 mA current sources that control the inverting inputs of each op amp. When ON, the current sources cause a gate-to-source voltage of approximately 2.5 V which is sufficient to turn off S1 and S2. When the current sources from Main Switch Control are OFF, each op amp acts as a unity-gain follower (VGS = 0) and both switches (S1 and S2) will be ON. —Shunt Switch Control—Controls the Shunt Switch of the “T” configuration. SWITCH OPERATION Unlike conventional analog switches, the SSM2402/SSM2412 are designed to ramp on and off gradually over several milliseconds. The soft transition prevents popping or clicking in audio systems. Transients are minimized in active filters when the SSM2402/SSM2412 are used to switch component values. O To see how the SSM2402/SSM2412 switches work, first consider an OFF-to-ON transition. The Control Input is initially LOW and the Ramp Output is at approximately –7 V. The Main Switch Control is HIGH which drives current sources Q3 and Q4 to 0.25 mA each. These currents generate 2.5 V gateto-source back bias for each JFET switch (S1 and S2) which holds them OFF. When the Control Input goes from LOW to HIGH, the Ramp Generator slews in the positive direction as shown in Figure 2. When the ramp goes more positive than –3 V, the Shunt Switch Control is pulled positive by differential amplifier DA2 which thereby puts shunt switch S3 into the OFF state. Note that S1 and S2 are still OFF, so at this time all three switches in the “T” are OFF. The Shunt Switch Control is negative which holds the shunt JFET S3 ON. Undesired feedthrough signals in the series JFET switches S1 and S2 are shunted to the negative supply rail through S3. REV. A Figure 2. Switch Control –7– SSM2402/SSM2412 In systems using a large number of separate switches, there are advantages to having faster switching into OFF state than into the ON state. Break-before-make can be maintained at the system level. To see how the SSM2402/SSM2412 guarantee break-before-make, consider the ON-to-OFF transition. The SSM2402/SSM2412 are designed to guarantee correct operation with inputs of up to ± 14.2 V with ± 18 V supplies. The switch input should never be forced to go beyond the supply rails. In the OFF condition, if the inputs exceeds +14.2 V, there is a risk of turning the respective input pass FET “ON.” When the input voltage rises to within 3.8 V of the positive supply, the op amp follower saturates and will not be able to maintain the full 2.5 V of back bias on the gate-to-source junction. Under this condition, current will flow from the input through the shunt FET to the negative supply. This current is substantial, but is limited by the FET IDSS. Although this current will not damage the device, there is a danger of also turning on the output pass FET, especially if the output is close to the negative rail. This risk of signal “breakthrough” for inputs above +14.2 V can be eliminated by using a source resistor of 100 Ω–500 Ω in series with the analog input to provide additional current limiting. Near the negative supply, transistors Q3 and Q4 saturate and can no longer keep the switch OFF. Signal breakthrough cannot happen, but the danger here is latch-up via a path to V– through the shunt FET. Additional circuitry (not shown) has been incorporated to turn OFF the shunt FET under these conditions, and the potential for latch-up is thereby eliminated. O B SO LE A Control Input LOW initiates the ON-to-OFF transition. The Ramp Generator integrates down from approximately +7 V towards –7 V. As the ramp goes through +3 V, the comparator controlling the Main Switches (S1 and S2) goes HIGH and turns on current sources Q3 and Q4 which thereby puts S1 and S2 into the OFF state. At this time, all switches in the “T” are OFF. When the ramp integrates down to –3 V, the Shunt Switch Control changes state and pulls shunt switch S3 into the ON state. This completes the ON-to-OFF transition; S1 and S2 are OFF, and S3 is ON to shunt away any undesired feedthrough. Note though that the ON-to-OFF time for main switches S1 and S2 is only the time interval required for the ramp to go from +7 V to +3 V, about 4 ms for the SSM2402, and 1.5 ms for the SSM2412. The time to turn on is about 2.5 times as long as the time to turn off. OVERVOLTAGE PROTECTION TE When the Ramp Output reaches +3 V, and the drive for the Main Switch Control output is gated OFF by differential amplifier DA1, current sources Q3 and Q4 go to the OFF state and the VGS of each main switch goes to zero. The high speed op amp followers provide essentially zero gate-to-source voltage over the full audio signal range; this in turn assures a constant low impedance in the ON state over the full audio signal range. Total time to turn on the SSM2402 switch is approximately 10.0 ms and 3.5 ms for the SSM2412. Typical Configuration The SSM2402/SSM2412 are much more than simple single solid state switches. The “T” configuration provides superb OFF-isolation through shunting of feedthrough via shunt switch S3. Break-before-make is inherent in the design. The ramp provides a controlled gating action that softens the ON/OFF transitions. Distortion is minimized by holding zero gate-to-source voltage for the two main FET switches, S1 and S2, using the two op amp followers. Figure 3 shows a distortion comparison between the SSM2402 and a typical CMOS switch. In summary, the SSM2402/SSM2412 are designed specifically for high performance audio system usage. Figure 3. Comparison of the SSM2402 and Typical CMOS Switch for Distortion –8– REV. A SSM2402/SSM2412 DIGITALLY-CONTROLLED ATTENUATOR HIGH PERFORMANCE STEREO ROUTING SWITCHER Figure 4 shows the usual approach to digitally-controlled attenuation. With S1 closed, the signal passes unattenuated to the output. With S1 open and S2 closed, the signal is attenuated by R1 and R2. The advantage of this configuration is that the attenuator current does not have to flow through the switches. The disadvantage is that the output is undefined during the switching period, which can be several milliseconds. The SSM2402 Dual Audio Switch comprises the nucleus for this 16 channels-to-one high performance stereo audio routing switcher, which features negligible noise and low distortion over the frequency range of 20 Hz to 20 kHz. This performance is achieved even while driving 600 Ω loads at signal levels up to +30 dBu. The SSM2402 affords a much simplified electrical design and printed circuit board layout, along with reduced manufacturing cost, when compared with discrete JFET circuits of similar performance. The electrical performance of the design described is vastly superior to CMOS switch designs, which are more prone to failure resulting from electrical static discharge. The low distortion characteristics of the SSM2402/SSM2412 enable the alternate arrangement of Figure 5 to be used. Now only one switch is required to change between two gains, and there is always a signal path to the output. Values for R2 will typically be in the low kilohm range. The switching control of the SSM2402 may be activated by conventional mechanical switches or 5 volt TTL or CMOS logic circuits. The application shown utilizes a simple mechanical control switch for illustration purposes only. Many diverse X/Y control schemes, destination control, or computer controlled designs can be utilized. LE The “T” configuration of the SSM2402 switch provides excellent ON-OFF isolation. The SSM2402 also features ms ramped turn on and ms ramped turn off for click-free switching. Additionally, the switch has a break-before-make switching sequence. Both features become significant in large audio switching systems where the audio path can pass through multiple switching elements. Such controlled switching is very important in large systems used in broadcast program switching or in production work. The application circuit design also employs the SSM2015 balanced input amplifier (Figure 7). The input impedance is high (≈100 kΩ), balanced or unbalanced. The input circuit incorporates a single pole RFI filter with a cutoff frequency set at 145 kHz. In addition, the input circuit attenuates the signal by 25 dB and extends the common-mode input voltage range to ± 98 volts peak, with common-mode rejection greater than 70 dB from 20 Hz to 20 kHz. The SSM2015 is set to produce a 15 dB gain. The signal drive level into the SSM2402 switch is then +10 dBu with a +20 dBu input level and +14 dBu peak, well within ideal operating range. Good signal-to-noise is maintained, with generous head-room available by electing to use ± 18 V dc power supply voltages. B SO Figure 4. TE For more gain steps and higher attenuation, the ladder arrangement of Figure 6 can be used. This enables a wide dynamic range to be achieved without the need for large value resistors, which would result in degradation of the noise performance. O Figure 5. Figure 6. REV. A –9– B SO LE TE SSM2402/SSM2412 O Figure 7. Switcher Schematic –10– REV. A B SO LE TE SSM2402/SSM2412 Figure 8. Switcher Functional Block Diagram O The routing switcher bus carries high level unbalanced audio, but is driven with low impedance sources. With the output impedance of the SSM2015 at virtually 0 Ω and the SSM2402 switch ON, resistance is typically 60 Ω. Bus-to-bus crosstalk is exceptionally low. For example, assuming 14 pF coupling between buses and 20 kHz signal, the crosstalk (isolation) exceeds 80 dB. The 14 pF would be representative for the 16 × 1 stereo design shown. Shielding of the buses with a printed circuit board ground plane and physically isolating the input and output circuits will reduce the crosstalk even further. The “T” configuration of the SSM2402 switch virtually eliminates crosstalk between the various input signal sources. The output amplifier incorporates a buffer amplifier that provides 4 dB of gain (nominally), with adjustable output level trim control. The buffer also isolates the switching bus from the balanced output amplifier circuit. The balanced output is designed to drive 600 Ω loads and utilizes two SSM2134 IC amplifiers. The differential design increases drive capability, yet increases the heat dissipation surface area, and keeps IC package temperature well within safe operating limits, even when driving 600 Ω loads. The SSM2134 is recommended due to its low noise, wide frequency response, and output drive current capabilities. REV. A Overall performance of the 16 × 1 stereo switcher is noteworthy. Input-to-output frequency response is flat to within 1 dB over a 10 Hz to 50 kHz band. Total harmonic distortion plus noise is less than 0.03%, from 20 Hz to 20 kHz. SMPTE intermodulation distortion is less than 0.02%. The use of ± 18 V dc power supplies produces a +30 dBm clip level, even when driving 600 Ω loads. Table I. Circuit Performance Specifications Max Input Level Input Impedance, Unbalanced Input Impedance, Balanced Common-Mode Rejection (20 Hz to 20 kHz) Common-Mode Voltage Limit Max Output Level Output Impedance Gain Control Range Output Voltage Slew Rate Frequency Response (± 0.05 dB) Frequency Response (± 0.5 dB) THD + Noise (20 Hz to 20 kHz, +8 dBu) THD + Noise (20 Hz to 20 kHz, +24 dBu) IMD (SMPTE 60 Hz & 4 kHz, 4:1, +24 dBu) Crosstalk (20 Hz to 20 kHz) S/N Ratio @ 0 dB Gain –11– +30 dBu 100 kΩ 200 kΩ >70 dB ± 98 V Peak +30 dBu/dBm 67 Ω ± 2 dB 6 V/µs 20 Hz to 20 kHz 10 Hz to 50 kHz 0.005% 0.03% 0.02% >80 dB 135 dB SSM2402/SSM2412 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Pin Epoxy DIP (P-Suffix) 0.795 (20.19) 0.725 (18.42) 14 8 1 7 PIN 1 0.130 (3.30) MIN 0.4193 (10.65) 0.3937 (10.00) B SO 0.2992 (7.60) 0.2914 (7.40) 9 8 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) PRINTED IN U.S.A. O 0.0500 (1.27) BSC TE LE 0.4133 (10.50) 0.3977 (10.00) 1 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC 16-Pin SOL (S-Suffix) 16 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.280 (7.11) 0.240 (6.10) –12– REV. A