AIC1573

AIC1573 5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller n FEATURES l l n DESCRIPTION The AIC1573 combines two PWM voltage mode controllers and two linear controllers as well as the monitoring and protection functions in this chip. One PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. The second PWM controller provides AGP bus 1.5V or 3.3V power with a standard buck converter. Two linear controllers regulate power for the 1.5V GTL bus and 1.8V power for the chip set core voltage and/or cache memory circuits. An integrated 5 bit D/A converter that adjusts the microprocessor core voltage from 2.1V to 3.5V in 0.1V increments and from 1.3V to 2.05V in 0.05V increments. The second PWM controller for AGP bus power is selectable by means of SELECT pin status for 1.5V or 3.3V with 3% accuracy. Two linear controllers drive with external N-channel MOSFETs to provide 1.5V±3% and fixed output voltage 1.8V±3%. This chip monitors all the output voltages. Power Good signal is issued when the core voltage is within ±10% of the DAC setting and the other levels are above their under-voltage levels. Over-voltage protection for the core output uses the lower Nchannel MOSFET to prevent output voltage above 116% of the DAC setting. The PWM over-current function monitors the output current by using the voltage drop across the upper MOSFET’s RDS(ON), eliminating the need for a current sensing resistor. Compatible with HIP6020. Provides 4 Regulated Voltages for Microprocessor Core, AGP Bus, Memory and GTL Bus Power. TTL Compatible 5-bit Digital-to-Analog Core Output Voltage Selection. Range from 1.3V to 3.5V. 0.1V Steps from 2.1V to 3.5V. 0.05V Steps from 1.3V to 2.05V. l l l l ±1.0% PWM Output Voltage for VCORE. ± 3% PWM Output Voltage for AGP Bus. ±3.0% Reference Voltage for Chipset and/or C ache Memory and VGTL. Simple Voltage-Mode PWM Control with Built in Internal Compensation Networks. N-Channel MOSFET Driver for PWM buck converters. Linear Controller Drives Compatible with both N – Chanel MOSFET and NPN Bipolar Series Pass Transistor. l l l l l l l Operates from +3.3V, +5V and +12V Inputs. Fast Transient Response. Full 0% to 100% Duty Ratios. Adjustable Current Limit without External Sense Resistor. Microprocessor Core Voltage Protection against Upper MOSFET shorted to +5V. Power Good Output Voltage Monitor. Over-Voltage and Over-Current Fault Monitors. 200KHz Free-Running Oscillator Programmable up to 700KHz. l l l l n APPLICATIONS l Full Motherboard Power Regulation for Computers. Analog Integrations Corporation www.analog.com.tw DS-1573-01 Sep 10, 01 TEL: 886-3-5772500 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC FAX: 886-3-5772510 1 AIC1573 n APPLICATION CIRCUIT +12V IN + 4.7µF C7 VCC 28 C5 1nF L3 +5V IN 1nF 9 23 OCSET2 OCSET1 UGATE1 PHASE1 R3 Q1 + CIN 10V 680µF*7 1 µH GND V OUT2 3.3V or 1.5V + COUT2 1000µF*3 Q3 L2 7µH UGATE2 PHASE2 1 2 27 26 V OUT1 Q2 R1 10K L1 3µH + COUT1 1000µF*7 25 LGATE1 VSEN2 24 10 PGND 21 FB1 C6 0.22µF SELECT 11 20 NC R2 680K +3.3V IN VAUX 16 22 VSEN1 Q4 V OUT3 1.5V COUT3 + DRIVE3 18 7 19 6 5 4 3 VID0 VID1 VID2 VID3 VID4 VSEN3 Q5 VOUT4 1.8V + COUT4 DRIVE4 15 8 13 PGOOD FAULT/RT SS VESN4 14 17 GND 12 Css 2 AIC1573 n ORDERING INFORMATION AIC1573-CX PACKAGING TYPE S: SMALL OUTLINE ORDER NUMBER AIC157 3CS (SO28) PIN CONFIGURATION UGATE2 1 28 V C C 27 UGATE1 26 PHASE1 25 LGATE1 24 PGND 23 OCSET1 22 VSEN1 21 FB1 20 NC 1 9 VSEN 3 1 8 DRIVE3 17 GND 1 6 VAUX 15 DRIVE4 PHASE2 2 VID 4 3 VID 3 4 VID 2 5 VID 1 6 VID0 7 PGOOD 8 OCSET2 9 VSEN2 10 SELECT 11 S S 12 FAULT/RT 13 VSEN4 14 n ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC ...............… … … … … .....… … … … .........… ..… … ..................... +15V PGOOD, FAULT and GATE Voltage .....… … … .....… … … ..… .... GND -0.3V to VCC +0.3V Input, Output , or I/O Voltage ......… ...… … … … … … … … … ..… … ............ GND -0.3V to 7V Recommended Operating Conditions Supply Voltage; VCC… … ..… … … … ...........… ................... +12V±10% Ambient Temperature Range … … ..… … ..… … … ................. 0°C~70°C Junction Temperature Range … … ....… .… … … .................. 0°C~125°C Thermal Information Thermal Resistance, θJA SOIC package … … … … … … … … … … … … … ..… ..… .............. 70°C/W SOIC package (with 3in2 of copper) … ...… ..… … .......… ......... 50°C/W Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range Maximum Lead Temperature (Soldering 10 sec) … … … … … … … ..… … ...... 150°C … … … … … … … … … … ..… ... 300°C … … … … … … … … ..… … … .... -65°C ~ 150°C 3 AIC1573 n ELECTRICAL CHARACTERISTICS PARAMETER VCC SUPPLY CURRENT Supply Current POWER ON RESET Rising VCC Threshold Falling VCC Threshold Rising VAUX Threshold VAUX Threshold Hysteresis Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp. Amplitude RT=Open 6k Ω 0.6V VREG3 VREG4 VSENUV 3 1.5 1.8 75 5 20 30 % V V % % mA 4 AIC1573 n ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS SYNCHRONOUS PWM CONTROLLER AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate (G.B.D.) (G.B.D.) (G.B.D.) note 1. (Continued) SYMBOL MIN. TYP. MAX. UNIT 80 GBWP SR 13 6 dB MHz V/µs PWM CONTROLLER GATE DRIVERS UGATE1,2 Upper Drive Source UGATE1,2 Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION VSEN1 Over-Voltage ( VSEN1 /DACOUT) FAULT Sourcing Current OCSET1,2 Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold ( VSEN1 /DACOUT ) VSEN1 Under-Voltage ( VSEN1/DACOUT ) VSEN1 Hysteresis (VSEN1/DACOUT) PGOOD Voltage Low Upper and Lower Threshold IPGOOD=-4mA VPGOOD 2 0.4 0.8 % V VSEN1 Falling 92 95 % VSEN1 Rising 108 111 % VSEN1 Rising VCC-VFAULT/RT =2.0V VOCSET =4.5VDC OVP IOVP IOCSET ISS 170 116 20 200 25 230 120 % mA µA µA VCC=12V, VUGATE = 6V VUGATE=1V VCC=12V, VLGATE =1V VLGATE=1V IUGH RUGL ILGH RLGL 0.9 2.8 1 2.2 3.0 3.5 A Ω A Ω Note 1. Without internal compensation network, the gain bandwidth product is 13MHz. Being associated with internal compensation networks, the Bode Plot is shown in Fig. 3, “Internal Compensation Gain of PWM Error Amplifier”. 5 AIC1573 n TYPICAL PERFORMANCE CHARACTERISTICS PGOOD SS SS VDAC=3.5V VOUT4 VOUT3 VDAC=2V VOUT2 VOUT1 VDAC=1.3V Fig. 1 Soft Start Interval with 4 Outputs and P GOOD 30 Fig. 2 10M Soft Start Initiates PWM Output 90 °C 25 RT Pull Up to 12V 1M 20 15 22°C Resistance (Ω) -40 °C Gain (dB) 100k RT Pull Down to GND 10 5 10k 0 -5 1k 10k 100k 1M 1k 10k 100k 1M Frequency (Hz) Fig 3. Internal Compensation Gain of PWM Error Amplifier Switching Frequency (Hz) Fig. 4 R T Resistance vs. Frequency 160 140 120 100 80 Over Load VCC=12V CUG1=CLG1=C UG2=C C=4.7nF C=3.3nF Applied Inductor Current 5A/div I CC (mA) C=1.5nF 60 40 20 C=650pF SS C=0 0 200k Fault 900k 300k 400k 500k 600k 700k 80 0k 1M Switching Frequency (Hz) Fig. 5 Supply Current vs. Frequency Fig. 6 Over Current ON Inductor 6 AIC1573 n TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 4 3 2 FSW =200KHz Switching Frequency Drift (%) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -40 -20 0 20 40 60 80 100 120 Fig. 7 6 5 Load Transient of Linear Controller 0.4 Temperature (°C) Fig. 8 Temperature vs. Switching Frequency Drift OCSET Current = 200 µA 0.3 0.2 OCSET Current Drift (%) 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -40 -20 0 20 40 60 80 100 120 VSEN2 Voltage Drift (%) 4 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -40 VREG2=3.3V -20 0 20 40 60 80 100 120 Fig. 9 0.4 0.3 Temperature (°C) Temperature vs. OCSET Current Drift 0.4 0.3 Fig. 10 Temperature (° C) Temperature Drift of 9 Different Parts PWM Output Voltage Drift (%) 0.1 0.0 -0. 1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 -20 0 20 40 60 80 100 120 VSEN4 Voltage Drift (%) 0. 2 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 DACOUT=1.6 V VREG4=1.8V -20 Fig. 11 Temperature (° C) Temperature Drift of 13 Different Parts Fig. 12 Temperature (°C) Temperature Drift of 9 Different Parts 0 20 40 60 80 100 120 7 AIC1573 n TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 0 to 20A Load Step V OUT1 0 to 20A Load Step VOUT1 Fig. 13 Load Transient of PWM Output Fig. 14 Stringent Load Transient of PWM Output 70 80 Mean= -0.006% 60 DACOUT=1.6V Ta=25 °C Mean = 0.16% 70 60 3 std.=0.56% 3 std.=1% Ta = 25°C 50 Number of Parts Number of Parts 50 40 30 20 10 0 40 30 20 10 0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 -1.0 -0.5 0.0 0.5 1.0 Fig. 15 Accuracy (%) FB Voltage Accuracy Accuracy (%) Fig. 16 VSEN3 Voltage Accuracy 8 VSEN3 VSEN1 PGOOD INHB LUV OVER UP 4V OC1 SS OC1 x 110% VCC OV 0.2V COUNTER (3) R x 115% FAULT LATCH CURRENT LATCH R X 90% VAUX DRIVE3 n BLOCK DIAGRAM X 75% VAUX DRIVE4 R RESET 200uA POR RAMP2 RAMP1 SOFT START LOGIC 200uA DACOUT TTL D/A CONVERTER VID3 SS OFF VCC VID4 25uA VID0 VID1 VID2 OSCILLATOR INHB FAULT / RT VSEN4 OCSET2 OCSET1 VAUX VCC POWER ON RESET POR PHASE2 VSEN1 VCC SS INHB x 75% DRV-H VCC GATE VCC 1.5V or 3.3V D RV-L ERROR AMP2 CONTROL COMP1 ERROR AMP1 Comp. 3 P, 2 Z 4.5V UGATE2 DRV2 GATE CONTROL RAMP2 GND COMP2 VSEN2 SELECT PHASE1 UGATE1 LGATE1 PGND NC FB1 AIC1573 9 AIC1573 n PIN DESCRIPTIONS Pin 1: UGATE2: External high-side N-MOSFET gate drive pin. Connect UGATE2 to gate of the external high-side N-MOSFET . Pin 2: PHASE2: Over-current detection pin. Connect the PHASE2 pin to source of the external high-side NMOSFET. This pin detects the voltage drop across the high-side N-MOSFET Pin 7: Pin 6: Pin 5: Pin 4: Pin 3: VID4: VID3: VID2: VID1: VID0: 5bit DAC voltage select pin. TTLcompatible inputs used to set the internal voltage reference VDAC. When left open, these pins are internally pulled up to 5V and provide logic ones. The level of VDAC sets the converter output voltage as well as the PGOOD and OVP thresholds. Table 1 specifies the VDAC voltage for the 32 combinations of DAC inputs. Pin 8: PGOOD: Power good indicator pin. PGOOD is an open drain output. This pin is pulled low when the converter output is ±10% out of the VDAC reference voltage or the other outputs are below their under-voltage thresholds. The PGOOD output is open for VID codes that inhibit operation. See Pin 12: SS: RDS(ON) for overcurrent protection. Pin 9: Table 1. OCSET2: Current limit sense pin. Connect a resistor R OCSET from this pin to the drain of the external high-side N-MOSFET. ROCSET, an internal 200µA current source (IOCSET), and the upper N-MOSFET onresistance (RDS(ON)) set the overcurrent trip point according to the following equation: IOCSET × ROCSET IPEAK = RDS(ON) Pin 10: VSEN2: Connect this pin to the output of the standard buck PWM regulator. The voltage at this pin is regulated to the 1.5V/3.3V predetermined by the logic Low/High level status of the SELECT pin. This pin is also monitored by the PGOOD comparator circuit. Pin 11: SELECT: This pin determines the output voltage of the AGP bus switching regulator. A low TTL input sets the output voltage to 1.5V, while a high input sets the output voltage to 3.3V. Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 25µA (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Pin 13: FAULT/RT: Frequency adjustment pin. Connecting a resistor (RT) from this pin to GND, increasing the frequency. Connecting a resistor (RT) from this pin to VCC, de- 10 AIC1573 creasing the frequency by the following figure (Fig.3). This pin is 1.26V during normal operation, but it is pulled to VCC in the event of an over-voltage or over-current condition. Pin 21: FB1: nected to FB1 in to compensate the voltage control feedback loop of the converter. The error amplifier inverting input pin of the synchronous PWM converter. The FB1 pin and COMP1 pin are used to compensate the voltage-control feedback loop.  25 .2K  , f = f0 1 +  RT    RT pulled to GND  VCC − 1.26V f = f0 1 −  5 × RT  RT pulled to VCC,  ,   Pin 22: VSEN1: Synchronous PWM converter’s output voltage sense pin. Connect this pin to the converter output. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection function. Pin 23: OCSET1: Current limit sense pin. Connect a resistor ROCSET from this pin to the drain of the external high-side N-MOSFET. ROCSET, an internal 200µA current source (IOCSET ), and the upper N-MOSFET onresistance (RDS(ON)) set the overcurrent trip point according to the following equation: IOCSET × ROCSET IPEAK = RDS(ON) The voltage at this pin is also moni tored for power-on reset (POR) purpose. Pin 24: PGND: Driver power GND pin. PGND should be connected to a low impedance ground plane in close to lower N-MOSFET source. Pin 25: LGATE1: Lower N-MOSFET gate drive pin of the synchronous PWM converter. Pin 26: PHASE1: Over-current detection pin. Con- where f0 is free run frequency. Pin14: VSEN4: Connect this pin to the 1.8V linear regulator’s output. This pin is monitored for under-voltage events. Pin15: DRIVE4: Connect this pin to the gate of the external N-MOS to supply 1.8V power for Memorey requirement. Pin 16: VAUX: The +3.3V input voltage at this pin is monitored for power-on – reset (POR) purpose. Connect to +5V provides boost current for the linear regulator’s output. Pin 17: GND: Signal GND for IC. All voltage levels are measured with respect to this pin. Pin 18: DRIVE3: Connect this pin to the Gate of the external N-MOS for providing 1.5V power to GTL bus. Pin 19: VSEN3: Connect this pin to the 1.5V linear regulator’s output. This pin is monitored for under-voltage events. Pin 20: COMP1: External compensation pin of the synchronous PWM converter. This pin is connected to error amplifier output and PWM comparator. A RC network is con- 11 AIC1573 nect the PHASE1 pin to source of the external high-side NPin 28: VCC: MOSFET. This pin detects the voltage drop across the high-side N-MOSFET Pin 27: UGATE1:External RDS(ON) for overcurrent protection. high-side N-MOSFET gate drive pin. Connect UGATE1 to the synchronous PWM converter’s gate of the external highside N-MOSFET . The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. The voltage at this pin is monitored for Power-OnReset purpose. n APPLICATIONS INFORMATION The AIC1573 is designed for microprocessor computer applications with 3.3V and 5V power, and 12V bias input. This IC has two PWM controller and two linear controllers. The first PWM (PWM1) controller is designed to regulate the microprocessor core voltage (VOUT1) by driving 2 MOSFETs (Q1 and Q2) in a synchronous rectified buck converter configuration. The core voltage is regulated to a level programmed by the 5 bit D/A converter. The second PWM (PWM2) controller is designed to regulate the advanced graphics port (AGP) bus voltage (VOUT2). PWM2 One of the linear controllers is designed to regulate the advanced graphic port (AGP) bus voltage (VOUT2). PWM2 controller drives a MOSFET (Q3) in a standard buck converter and regulates the output voltage to a digitallyprogrammable level of 1.5V or 3.3V.Selection of either output voltage is achieved by applying the proper logic level at the SELECT pin. The two linear controllers supply the 1.5V GTL bus power (VOUT3) and 1.8V memory power (VOUT4). The Power-On-Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VAUX pin. The POR function initiates softstart operation after all three input supply voltage exceeds their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. An internal 25µA current source charges an external capacitor (CSS) on the SS pin to 4.5V. The PWM error amplifier reference input (Non-inverting terminal) and output (COMP1 pin) is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. After the output voltage increases to approximately 70% of the set value, the reference-input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. Additionally, all linear regulator’s reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Fig.1 and Fig.2 show the soft-start sequence for the typical application. The internal oscillator’s triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. 12 AIC1573 Each linear output initially follows a ramp. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. The PGOOD signal toggles ‘high’ when all output voltage levels have exceeded their under-voltage levels. Fault Protection All four outputs are monitored and protected against extreme overload. A sustained overload on any output or over-voltage on PWM1 output disables all outputs and drive the FAULT/RT pin to VCC. Over Current Latch LUV OC1 OC2 0.15V SS + 4.0V OV POR + S R Q INHIBIT S Counter R Fault Latch S R Q Fault VCC Fig. 17 Simplified Schematic of Fault Logic A simplified schematic is shown in figure 1 An 7. over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. The overcurrent latch is set dependent on the status of the over-current (OC1 and OC2), linear under-voltage (LUV) and the soft-start signal. An under-voltage event on either linear output (VSEN3, VSEN4) is ignored until the soft-start interval. Cycling the bias input voltage (+12V off then on) resets the counter and the fault latch. Over-Voltage Protection During operation, a short on the upper PWM1 MOSFET (Q1) causes VOUT1 to increase. When the output exceed the over-voltage threshold of 116% of DACOUT, the FAULT pin is set to fault latch and turns Q2 on as required in order to regulate VOUT1 to 116% of DACOUT. The fault latch raises the FAULT/RT pin close to VCC potential. A separate over-voltage circuit provides protection during the initial application of power. For voltage on VCC pin below the power-on reset (and above ~4V), Should VSEN1 exceed 1.0V, the lower MOSFET (Q2) is driven on as needed to regulate VOUT1 to 1.0V. Gate Drive Overlap Protection The Overlap Protection circuit ensures that the Bottom MOSFET does not turn on until the Upper MOSFET source has reached a voltage low enough to ensure that shoot-through will not occur. 13 AIC1573 Over-Current Protection All outputs are protected against excessive overcurrent. Both PWM controller uses upper MOSFET’s on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. All linear controllers monitor VSEN for under-voltage to protect against excessive current. When the voltage across Q1 (ID•RDS(ON)) exceeds the level (200µA • ROCSET ), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 28µA current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 6 illustrates the over-current protection until an over load on OUT1. Should excessive current cause VSEN to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power (off then on reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by: The status of the SELECT pin can not be changed during operation of the IC without immediatelly causing a fault condition. (DACOUT) through a TTL compatible 5 bit digital to analog converter. The VID pins can be left open for a logic 1 input, because they are internally pulled up to 5V by a 70k Ω resistor. Changing the VID inputs during operation is not recommended. ‘11111’ VID pin combinations disable the IC and open the PGOOD pin. OUT2 Voltage Selection The AGP regulator output voltage is internally set to one of two discrete levels, based on the SELECT pin status. Left SELECT pin open, internal pulled high, the output voltage is 3.3V. Grounding SELECT pin will get the 1.5V output voltage. Shutdown Neither PWM output switches until the soft-start voltage exceeds the oscillator’s vally voltage. Additional, the reference on each linear’s amplifier is clamped to the soft-start voltage. Holding the SS pin low turns of all four regulators. The VID codes resulting in an INHIBIT as shown in Table 1 also shut down the IC. IPEAK IOCSET × R OCSET = R DS(ON) The OC trip point varies with MOSFET’s temperature. To avoid over-current tripping in the normal operating load range, determine the R OCSET resistor from the equation above with: 1. The maximum RDS(ON) at the highest junction. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK > IOUT(MAX) + (inductor ripple current) /2. Oscillator Synchronization The AIC1573 avoids the problem of cross talk b etween the converters by way of phase control method. Therefore, for both output voltage settings less than 2.4V or both greater than 2.4V, PWM1 operates out of phase with PWM2. For one PWM output voltage setting below 2.4V and the other PWM output voltage setting of 2.4V and above, PWM1 operates in phase with PWM2. OUT1 Voltage Program The output voltage of the PWM1 converter is programmed to discrete levels between 1.3V to 3.5V. The VID pins program an internal voltage reference 14 AIC1573 @VOUT1=1.7V UGATE1 @VOUT1=1.7V UGATE1 @ V OUT2=3.3V UGATE2 @VOUT2=1.5V UGATE2 Fig. 18 PWM1 operates in phase with PWM2 Fig. 19 PWM1 operates out of phase with PWM2 Table 1 VOUT1 Voltage Program ( 0=connected to GND, 1=open or connected to 5V ) For all package version PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DACOUT VOLTAGE 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80 V 1.85 V 1.90 V 1.95 V 2.00 V 2.05 V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PIN NAME VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DACOUT VOLTAGE INHIBIT 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V 2.6 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V 15 AIC1573 Layout Considerations Any inductance in the switched current path generates a large voltage spike during the switching interval. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component selection and tight layout of critical components, and short, wide metal trace minimize the voltage spike. A ground plane should be used. Locate the input capacitors (CIN) close to the power switches. Minimize the loop formed by CIN, the upper MOSFET (Q1) and the lower MOSFET (Q2) as possible. Connections should be as wide as short as possible to minimize loop inductance. The connection between Q1, Q2 and output inductor should be as wide as short as practical. Since this connection has fast voltage transitions will e asily induce EMI. The output capacitor (COUT ) should be located as close the load as possible. Because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board The AIC1573 is best placed over a quiet ground plane area. The GND pin should be connected to the groundside of the output capacitors. Under no circumstances should GND be returned to a ground inside the C , Q1, Q2 loop. The GND and PGND IN pins should be shorted right at the IC. This help to minimize internal ground disturbances in the IC and prevents differences in ground potential from disrupting internal circuit operation. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 1A current. The traces for OUT2 need only be sized for 0.5A. Locate COUT2 close to the AIC1573. The Vcc pin should be decoupled directly to GND by a 2.2µF ceramic capacitor, trace lengths should be as short as possible. A multi-layer-printed circuit board is recommended. Figure 11 shows the connections of the critical components in the converter. The C and COUT IN could each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. PWM Output Capacitors The load transient for the microprocessor core r equires high quality capacitors to supply the high slew rate (di/dt) current demand. The ESR (equivalent series resistance) and ESL (equivalent series inductance) parameters rather than actual capacitance determine the buck capacitor values. For a given transient load magnitude, the output voltage transient change due to the output capacitor can be note by the following equation: ∆VOUT = ESR × ∆IOUT + ESL × ∆IOUT is transient load current step. ∆IOUT ∆T , where After the initial transient, the ESL dependent term drops off. Because the strong relationship between output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. In most case, multiple electrolytic capacitors of small case size are better than a single large case c apacitor. 16 AIC1573 Output Inductor Selection Inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1573 will provide either 0% or 100% duty cycle in response to a load transient. The response time to a transient is different for the application of load and remove of load. of input bulk capacitors to control the voltage overshoot across the upper MOSFET. The ceramic capacitance for the high frequency decoupling should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current is approximate equal to: L × ∆IOUT VIN − VOUT , L × ∆IOUT tFALL = VOUT . tRISE = load current step. IRMS = (1− D) × D × I2 OUT + 1  VIN × D ×  12  f × L  2 D= Where ∆IOUT is transient , where VOUT VIN The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. In a typical 5V input, 2V output application, a 3 H µ inductor has a 1A/µS rise time, resulting in a 5 S µ delay in responding to a 5A load current step. To optimize performance, different combinations of input and output voltage and expected loads may require different inductor value. A smaller value of inductor will improve the transient response at the expense of increase output ripple voltage and ni ductor core saturation rating. Peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to: PWM MOSFET Selection In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are dissipated by the AIC1573. However, the gate charge increases the switching interval, tSW, which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. (V IN − VOUT) × VOUT I RIPPLE = f × L × VIN ; f = AIC1573 oscillator frequency. The inductor must be able to withstand peak current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss PUPPER = IOUT 2 × RDS(ON) × D + IOUT × VIN × tSW × f 2 PLOWER = IOUT 2 × RDS(ON) × (1 − D) The equations above do not model power loss due to the reverse recovery of the lower MOSFET’s body diode. The RDS(ON) is different for the two previous equations even if the type devices is used for both. This Input Capacitor Selection Most of the input supply current is supplied by the input bypass capacitor, the resulting RMS current flow in the input capacitor will heat it up. Use a mix 17 AIC1573 is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Logic level MOSFETs should be selected based on on-resistance considerations, RDS(ON) should be chosen base on input and output voltage, allowable power dissipation and maximum required output current. Power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode’s rated reverse breakdown voltage must be greater than twice the maximum input voltage. Linear Controller MOSFET Selection The power dissipated in a linear regulator is: PLINEAR = IOUT × (V IN − VOUT ) Select a package and heatsink that maintains junction temperature below the maximum rating while operation at the highest expected ambient temperature. Linear Output Capacitor The output capacitors for the linear regulator and linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. COUT3 and COUT4 should be selected for transient load regulation. The output capacitor for the linear regulator provides loop stability. PWM Feedback Analysis VIN ∆VOSC Q1 VDAC VEA PWM COMP. ERROR AMP. Compensation Networks Q2 LO CO RESR VOUT + Modulation Gain Fig 20. Control Loop Closed Loop Gain(dB) = Modulation Gain(dB) + Compensation Gain (dB) Modulation Gain(dB) The compensation network consists of the error amplifier and built in compensation networks. The goal of the compensation network is to provide for fast response and adequate phase margin. Phase Margin is the difference between the closed loop phase at 0dB and 180 degree.  VIN ≈ 20 log  ∆V  OSC 2   F   + 10 log 1 +     F   ESR       18 AIC1573   F − 10 log  1 −      FLC   where 1 FLC = 2π LO CO     2   F  +   F ×Q    LC   2 2  60     FZ1 40 F Z2 FP1 Gain (dB ) Compensation Gain F P2 20log(VIN/δVOSC) 0 20 ; ; FOdB FESR = 1 = Q 1 2π × RESR × CO × R ESR + CO LO LO CO × 1 R LOAD -20 100 Modulation Gain FLC F 1k F ESR 10k 100k Closed Loop Gain 1M 10M Frequency (KHz) Fig. 21 Bode Plot of Converter Gain The break frequency of Internal Compensation Gain are given by Bode Plot of Converter Gain Sampling theory shows that F0dB must be less that half the switching frequency for the loop stables. But it must be considerably less than that, or there will be large amplitude switching frequency ripple at the output. Thus, the usual practices is to fix F0dB at 1/4 to 1/5 the switching frequency. FZ 1 = 2.6KHz ; FZ 2 = 24 KHz ; FP1 = 30 KHz ; FP 2 = 400 KHz n PHYSICAL DIMENSIONS l 28 LEAD PLASTIC SO (unit: mm) SYMBOL D MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 1.27 A A1 B E H C D E e H L e A 1.27 (TYP) A1 B C L 19