AK4324VF

ASAHI KASEI [AK4324] AK4324 96kHz Sampling 24Bit ∆Σ DAC General Description The AK4324 is a high performance 1bit stereo DAC for the 96kHz sampling mode of DAT,DVD including a 24bit digital filter. A 1bit DAC can achieve monotonicity and low distortion with no adjustment and is superior to traditional R-2R ladder based DACs. In the AK4324, the analog outputs are filtered in the analog domain by switched-capacitor filter(SCF) with high tolerance to clock jitter. The digital I/F can correspond to TTL levels. Features † High Performance Stereo 1bit DAC † 128x Oversampling † Sampling Rate up to 96kHz † 24Bit 8 times Digital Filter Ripple: ±0.005dB, Attenuation: 75dB † 2nd Order SCF(LPF) with High Tolerance to Clock Jitter † Low Distortion Differential Output † Digital de-emphasis for 32, 44.1, 48kHz, 96kHz sampling † Soft Mute † I/F format : MSB justified, LSB justified, I2S † Dynamic Range: 105dB † Master Clock Normal speed: 256fs or 384fs, Double speed: 128fs or 198fs † Power Supply: 4.5 to 5.5V † Small Package: 24pin VSOP 0168-E-01 1997/5 -1- ASAHI KASEI [AK4324] „ Ordering Guide AK4324-VF AKD4324 -40∼+85°C 24pin VSOP(0.65mm pitch) Evaluation Board „ Pin Layout 0168-E-01 1997/5 -2- ASAHI KASEI [AK4324] PIN/FUNCTION No. Pin Name I/O Function 1 DVSS - Digital Ground Pin 2 DVDD - Digital Power Supply 3 CKS I Master Clock Select Pin (Internal Pull-down pin) Normal Speed #"L": MCLK=256fs, #"H": MCLK=384fs Double Speed #"L": MCLK=128fs, #"H": MCLK=192fs 4 MCLK I Master Clock Input Pin 5 PD I Power-Down Mode Pin When at "L", the AK4324 is in power-down mode and is held in reset. The AK4324 should always be reset upon power-up. 6 BICK I Audio Serial Data Clock Pin 64fs clock is recommended to be input on this pin. 7 SDATA I Audio Serial Data Input Pin 2's complement MSB-first data is input on this pin. 8 LRCK I L/R Clock Pin 9 SMUTE I Soft Mute Pin When this pin goes "H", soft mute cycle is initiated. When returning "L", the output mute releases. 10 DFS I Double speed sampling mode Pin (Internal Pull-down pin) "L": Normal Speed, "H": Double Speed 11 DEM0 I De-emphasis Frequency Select Pin 12 DEM1 I De-emphasis Frequency Select Pin 13 DIF0 I Digital Input Format Pin 14 DIF1 I Digital Input Format Pin 15 DIF2 I Digital Input Format Pin 16 AOUTR- O Rch Negative analog output pin 17 AOUTR+ O Rch Positive analog output pin 18 AOUTL- O Lch Negative analog output pin 19 AOUTL+ O Lch Positive analog output pin 20 AVSS - Analog Ground pin 21 VREF I Voltage Reference Input Pin 22 AVDD - Analog Power Supply Pin 23 DZFR O Rch Zero Input Detect Pin 24 DZFL O Lch Zero Input Detect Pin Note: All input pins except internal pull-down pins should not be left floating. 0168-E-01 1997/5 -3- ASAHI KASEI [AK4324] ABSOLUTE MAXIMUM RATINGS (AVSS,DVSS=0V; Note 1 ) Parameter Power Supplies: Analog Digital DVDD-AVDD Symbol min max Units AVDD DVDD VDA -0.3 -0.3 - 6.0 6.0 0.3 V V V - ±10 mA Input Current, Any Pin Except Supplies IIN Input Voltage VIND -0.3 AVDD+0.3 V Ambient Operating Temperature Ta -40 85 Storage Temperature Tstg -65 150 °C V Note: 1 . All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS,DVSS=0V; Note 1 ) Parameter Power Supplies: Voltage Reference Analog Digital (Note 2 ) (Note 3 ) Symbol min typ max Units AVDD DVDD VREF 4.5 4.5 2.5 5.0 5.0 - 5.5 AVDD AVDD V V V Notes:2. AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. 3. Analog output voltage scales with the voltage of VREF. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=±2.8Vpp*VREF/5. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 0168-E-01 1997/5 -4- ASAHI KASEI [AK4324] ANALOG CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD,DVDD=5.0V; VREF=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement Bandwidth=10Hz∼20kHz; RL≥5kΩ; unless otherwise specified) Parameter min typ Resolution max Units 24 Bits Dynamic Characteristics (Note 4 ) THD+N 0dB Output -20dB Output -60dB Output Dynamic Range (-60dB Output, A weight) S/N (A weight) -94 -81 -41 -88 - dB dB dB (Note5 ) 100 105 dB (Note 6 ) 100 105 dB 100 110 dB Interchannel Isolation(1kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift (Note 7 ) 0.15 0.3 dB 20 - ppm/°C ±2.8 ±2.94 Vpp DC Accuracy Output Voltage (Note 8 ) Load Resistance ±2.66 5 kΩ Output Current 300 uA 43 6 64 9 mA mA (Note 9 ) 10 50 uA (Note 9 ) (Note 10 ) 245 50 50 365 250 mW uW dB Power Supplies Power Supply Current Normal Operation (PD="H") AVDD DVDD Power-Down-Mode (PD="L") AVDD+DVDD Power Dissipation (AVDD+DVDD) Normal Operation Power-Down-Mode Power Supply Rejection Notes: 4. 5. 6. 7. 8. Measured by AD725C(SHIBASOKU). Averaging mode. Refer to the eva board manual. 100dB at 16bit data and 105dB at 20bit data. S/N does not depend on input bit length. 101dB at CCIR-ARM weighted. The voltage on VREF pin is held +5V externally. Full-scale voltage(0dB). Output voltage scales with the voltage of VREF pin. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=±2.8Vpp*VREF/5. 9. Power Dissipation in the power-down mode is applied with no external clocks (MCLK,BICK,LRCK held "H" or "L"). 10. PSR is applied to AVDD,DVDD with 1kHz, 100mVpp. VREF pin is held +5V. 0168-E-01 1997/5 -5- ASAHI KASEI [AK4324] ANALOG CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD,DVDD=5.0V; VREF=AVDD; fs=96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement Bandwidth=20Hz∼40kHz; RL≥5kΩ; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits -86 - dB dB dB Dynamic Characteristics (Note 11 ) THD+N -92 -78 -38 0dB Output -20dB Output -60dB Output Dynamic Range (-60dB Output) (Note 12 ) S/N (Note 12 ) Interchannel Isolation(1kHz) 98 dB 93 98 dB 100 110 dB DC Accuracy Interchannel Gain Mismatch Gain Drift (Note 13 ) 0.15 0.3 dB 20 - ppm/°C ±2.8 ±2.94 Vpp DC Accuracy Output Voltage (Note 14 ) ±2.66 Load Resistance 5 kΩ Output Current 300 uA 43 9 64 13 mA mA Power Supplies Power Supply Current Normal Operation (PD="H") AVDD DVDD Power-Down-Mode (PD="L") AVDD+DVDD (Note 15 ) 10 50 uA Power Dissipation (AVDD+DVDD) Normal Operation Power-Down-Mode Power Supply Rejection (Note 15 ) (Note 16 ) 260 50 50 385 250 mW uW dB Notes: 11. 12. 13. 14. Measured by UPD(ROHDE&SCHWARZ). Refer to the eva board manual. 105dB at 20kHz LPF & A-weighted The voltage on VREF pin is held +5V externally. Full-scale voltage(0dB). Output voltage scales with the voltage of VREF pin. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=±2.8Vpp*VREF/5. 15. Power Dissipation in the power-down mode is applied with no external clocks (MCLK,BICK,LRCK held "H" or "L"). 16. PSR is applied to AVDD,DVDD with 1kHz, 100mVpp. VREF pin is held +5V. 0168-E-01 1997/5 -6- ASAHI KASEI [AK4324] FILTER CHARACTERISTICS(fs=44.1kHz) (Ta=25°C; AVDD,DVDD=4.5V∼5.5V; fs=44.1kHz; DFS="0"; DEM0="1",DEM1="0") Parameter Digital Filter Passband ±0.01dB (Note 17 ) -6.0dB Stopband (Note 17 ) Passband Ripple Stopband Attenuation Group Delay (Note 18 ) Digital Filter + SCF Frequency Response 0∼20.0kHz Symbol min typ max Units PB 0 24.1 22.05 20.0 - SB PR SA GD 75 - 27.2 - kHz kHz kHz dB dB 1/fs - ±0.2 - dB ±0.005 Note: 17. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs. 18. The calculating delay time which occurred by digital filtering. This time is from setting the data of both channels to input register to the output of analog signal. FILTER CHARACTERISTICS(fs=96kHz) (Ta=25°C; AVDD,DVDD=4.5V∼5.5V; fs=96kHz; DFS="1"; DEM0="1",DEM1="0") Parameter Digital Filter Passband ±0.01dB (Note 19 ) -6.0dB Stopband (Note 19 ) Passband Ripple Stopband Attenuation Group Delay (Note 20 ) Digital Filter + SCF Frequency Response 0∼40.0kHz Symbol min typ max Units PB 0 52.5 48.0 43.5 - SB PR SA GD 75 - 27.2 - kHz kHz kHz dB dB 1/fs - ±0.3 - dB ±0.005 Note: 19. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs. 20. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal. DIGITAL CHARACTERISTICS (Ta=25°C; AVDD,DVDD=4.5∼5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-100uA) Low-Level Output Voltage (Iout=100uA) Input Leakage Current (Note 21 ) Symbol VIH VIL VOH VOL Iin min 2.2 DVDD-0.5 - typ - max 0.8 0.5 ±10 Units V V V V uA Notes: 21 . DFS,CKS pins have internal pull-down devices, nominally 160kΩ. 0168-E-01 1997/5 -7- ASAHI KASEI [AK4324] SWITCHING CHARACTERISTICS (Ta=25°C; AVDD,DVDD=4.5∼5.5V; CL=20pF) Parameter Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High LRCK Frequency (Note 22 ) Normal Speed Mode (DFS="L") Double Speed Mode (DFS="H") Duty Cycle Serial Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK rising to LRCK edge LRCK Edge to BICK rising SDATA Hold Time SDATA Setup Time Reset Timing PD Pulse Width (Note 23 ) (Note 23 ) (Note 24 ) Symbol min fCLK tCLKL tCLKH fCLK tCLKL tCLKH 7.7 28 28 11.5 20 20 typ max Unit 13.824 MHz ns ns MHz ns ns 20.736 44.1 88.2 54 108 55 kHz kHz kHz % fsn fsd Duty 30 60 45 tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 140 60 60 20 20 20 20 ns ns ns ns ns ns ns tPW 150 ns Notes: 22. When the normal speed mode and the double speed mode are switched, AK4324 should be reset by PD pin. 23. BICK rising edge must not occur at the same time as LRCK edge. 24. The AK4324 can be reset by bringing PD "L" to "H" only upon power up. 0168-E-01 1997/5 -8- ASAHI KASEI [AK4324] „ Timing Diagram Reset Timing 0168-E-01 1997/5 -9- ASAHI KASEI [AK4324] OPERATION OVERVIEW „ System Clock The external clocks which are required to operate the AK4324 are MCLK, LRCK, BICK. The master clock(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is determined by the sampling rate (LRCK), CKS pin and DFS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs or 192fs is selected, the internal master clock becomes 256fs(=384fs*2/3) or 128fs(=192fs*2/3). Refer to Figure 1. All external clocks(MCLK,BICK,LRCK) should always be present whenever the AK4324 is in normal operation mode(PD="H"). If these clocks are not provided, the AK4324 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4324 should be reset by PD="L" after these clocks are provided. If the external clocks are not present, the AK4324 should be in the power-down mode(PD="L"). After exiting reset at power-up etc., the AK4324 is in power-down mode until MCLK and LRCK are input. Speed LRCK (fs) BICK CKS="L" MCLK CKS="H" Normal(DFS="L") 32k∼48kHz ∼64fs 256fs 384fs Double(DFS="H") 64k∼96kHz ∼64fs 128fs 192fs Table 1 . System Clocks Figure 1 . MCLK divider at normal speed mode „ Audio Serial Interface Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five serial data modes are supported and selected by the DIF0, DIF1 and DIF2 pins as shown in Table 2 . In all modes the serial data is MSBfirst, 2's compliment format and is clocked on the falling edge of BICK. Modes 0-3 are compatible with AK4321. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs. DIF2 DIF1 DIF0 Mode 0 0 0 0: 16bit LSB Justified 0 0 1 1: 20bit LSB Justified 0 1 0 2: 24bit MSB Justified 2 0 1 1 3: I S Compatible 1 0 0 4: 24bit LSB Justified Test Mode 1 0 1 DZF output is invalid. 1 1 1 1 1 1 BICK ≥32fs ≥40fs ≥48fs ≥48fs ≥48fs Figure Figure 2 Figure 3 Figure 4 Figure 5 Figure 3 Table 2 . Serial Data Modes *The use of 64fs clock is recommended as BICK. 0168-E-01 1997/5 - 10 - ASAHI KASEI [AK4324] Figure 2 . Mode 0 Timing Figure 3 . Mode 1,4 Timing Figure 4 . Mode 2 Timing Figure 5 . Mode 3 Timing 0168-E-01 1997/5 - 11 - ASAHI KASEI [AK4324] „ De-emphasis filter A digital de-emphasis filter is available for 32, 44.1, 48kHz or 96kHz sampling rates(tc=50/15us) and is enabled or disabled with the DEM0, DEM1 and DFS input pins. DEM1 DEM0 DFS Mode 0 0 0 44.1kHz 0 1 0 OFF 1 0 0 48kHz 1 1 0 32kHz 0 0 1 OFF 0 1 1 OFF 1 0 1 96kHz 1 1 1 OFF Table 3 . De-emphasis filter control „ Zero detection The AK4324 has a channel separated zero detecting function. When the input data at left channel are continuously zeros for 8192 LRCK cycles, DZFL goes to "H". When the input data at right channel are continuously zeros for 8192 LRCK cycles, DZFR goes to "H". Each DZF immediately goes to "L" if input data are not zero after each DZF "H". When the test mode in serial interface mode is enabled, the zero detection function is invalid. „ Soft mute operation Soft mute operation is performed at digital domain. When SMUTE goes to "H", the output signal is attenuated by -∞during 1024 LRCK cycles. When SMUTE is returned to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. Figure 6 . Soft mute and zero detection Notes: 1 { 2 { 3 { 4 { The output signal is attenuated by -∞ during 1024 LRCK cycles(1024/fs). Analog output corresponding to digital input have the group delay(GD). If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. As the input data at both channels are continuously zeros for 8192 LRCK cycles, both DZFs go to "H". Both DZFs immediately go to "L" if input data are not zero after both DZFs "H". 0168-E-01 1997/5 - 12 - ASAHI KASEI [AK4324] „ Power-Down The AK4324 are placed in the power-down mode by bringing PD pin "L" and the analog outputs are floating(Hi-Z). Figure 7 shows an example of the system timing at the power-down and power-up. Figure 7 . Power-down/up sequence example Notes: 1 { 2 { 3 { 4 { 5 { Analog output corresponding to digital input have the group delay(GD). Analog outputs are floating(Hi-Z) at the power-down mode. Click noise about -50dB occurs at the edges("↑↓") of PD signal. This noise is output even if "0" data is input. When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4324 should be in the powerdown mode. 3 ) influences system application. Please mute the analog output externally if the click noise({ The timing example is shown in this figure. „ System Reset The AK4324 should be reset once by bringing PD "L" upon power-up. The internal timing starts clocking by LRCK "↑" upon exiting reset by MCLK. „ Click Noise from analog output Click noise occurs from analog output in the following cases. 1 When switching de-empahsis mode by DEM0,DEM1,DFS pins, { 2 When switching serial data mode by DIF0,DIF1,DIF2 pins, { 3 When going and exiting power down mode by PD pin, { 4 When switching normal speed and double speed by DFS pin, { 1 &{ 2 , If the input data is "0" or the soft mute is enabled (after 1024 LRCK cycles However in case of { from SMUTE="H"), no click noise occur except for switching DFS pin. 0168-E-01 1997/5 - 13 - ASAHI KASEI [AK4324] SYSTEM DESIGN Figure 8 shows the system connection diagram. An evaluation board[AKD4324] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Figure 8 . Typical Connection Diagram Notes: - LRCK=fs, BICK=64fs. - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down pins(DFS,CKS) should not be left floating. 0168-E-01 1997/5 - 14 - ASAHI KASEI [AK4324] 1. Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from AVDD via 10Ω resistor. Alternatively if AVDD and DVDD are supplied separately, AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible. 2. Voltage reference The differential Voltage between VREF and AVSS set the analog output range. VREF pin is normally connected to AVDD with a 0.1uF ceramic capacitor. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the AK4324. 3. Analog Outputs The analog outputs are full differential outputs and ±1.4Vpp(typ@VREF=5V) centered around AVDD/2. The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is ±2.8Vpp(typ@VREF=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage(VAOUT) is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal VAOUT is 0V for 000000H(@24bit). The internal switched-capacitor filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. However, as the outband noise more than 40kHz is not so small in case of double sampling mode, some application may require external filter. DC offset on analog outputs is eliminated by AC coupling since the differential outputs have DC offset of AVDD/2 + a few mV. Figure 9 shows the example of external op-amp circuit summing the differential outputs. Figure 9 . External LPF Circuit Example 0168-E-01 1997/5 - 15 - ASAHI KASEI [AK4324] PACKAGE z 24pin VSOP (Unit: mm) NOTE: Dimension “*” does not include mold flash. „ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: 0168-E-01 Epoxy Cu Solder plate 1997/5 - 16 - ASAHI KASEI [AK4324] MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code 0168-E-01 1997/5 - 17 - IMPORTANT NOTICE zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. zAKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. zAny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. zAKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. 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(b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. zIt is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.