A3987

A3987 DMOS Microstepping Driver with Translator Features and Benefits ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Low RDS(on) outputs Short-to-ground protection Shorted load protection Automatic current decay mode detection/selection Mixed and slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Description The A3987 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes, with output drive capability of 50 V and ±1.5 A. The A3987 includes a fixed off-time current regulator, which has the ability to operate in slow or mixed decay modes. The translator is the key to the easy implementation of the A3987. Simply inputting one pulse on the step input drives the motor to take one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3987 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. The A3987 chopping control automatically selects the current decay mode (slow or mixed). When a STEP signal occurs, the translator determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to slow decay. If the change is to a lower current, then the decay mode is set to 30.1% fast decay. This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Continued on the next page… Package: 24 pin TSSOP with exposed thermal pad (suffix LP) Approximate scale Typical Application Diagram 0.22 μF VREG 10 μF 5 kΩ Microcontroller or Controller Logic ROSC STEP DIR SLEEP/RESET ENABLE MS1 MS2 REF VDD CP1 0.1 μF X7R CP2 VCP 0.1 μF X7R VBB1 A3987 VBB2 OUT1A OUT1B SENSE1 100 μF OUT2A OUT2B SENSE2 3987DS, Rev.1 A3987 DMOS Microstepping Driver with Translator protection. Special power-up sequencing is not required. The A3987 is supplied in a thin profile (1.2 mm maximum height) 24-lead TSSOP (suffix LP) with exposed thermal tab. The package is lead (Pb) free with 100% matte tin leadframe plating. Description (continued) Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover current Selection Guide Part Number A3987SLP-T A3987SLPTR-T Package 24-pin TSSOP with exposed thermal pad 24-pin TSSOP with exposed thermal pad Packing 62 pieces / tube 3000 pieces / reel Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Supply Voltage Logic Input Voltage Range VBBx to OUTx Sense Voltage Reference Voltage Nominal Operating Temperature Maximum Junction Temperature Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VDD VIN Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Notes Rating 50 ±1.5 7.0 –0.3 to VDD + 0.3 50 0.5 0 to 4 –20 to 85 150 –55 to 150 Units V A V V V V V ºC ºC ºC Thermal Characteristics* Characteristic Package Thermal Resistance *Additional thermal data available on the Allegro website. Maximum Power Dissipation, PD(max) 5.5 5.0 4.5 4.0 Symbol RθJA 2-layer PCB with 3.8 Notes 4-layer PCB based on JEDEC standard in.2 2 oz. copper each side Rating 28 32 Units °C/W °C/W Power Dissipation, PD (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 (R θJ (R θJ A = 28 ºC A = /W 32 ) ºC /W ) 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A3987 DMOS Microstepping Driver with Translator Functional Block Diagram 0.22 µF 0.1 µF CP1 CP2 VCP VREG VDD Regulator Charge Pump 0.1 µF To VDD DAC VREG VCP PWM Latch Blanking Mixed Decay DMOS Full Bridge 1 VBB1 OSC ROSC OUT1A OUT1B To VDD STEP DIR Translator SLEEP/RESET MS1 MS2 OUT2A ENABLE PWM Latch Blanking Mixed Decay OUT2B Gate Drive SENSE1 Control Logic OCP DMOS Full Bridge 2 VBB2 SENSE2 DAC Buffer REF GND GND Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A3987 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 50 V, unless noted otherwise Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage VBB VDD RDS(on) VF Operating During sleep mode Operating Source driver, IOUT = –1.5 A Sink driver, IOUT = 1.5 A Source diode, IF = –1.5 A Sink diode, IF = 1.5 A fPWM < 50 kHz Motor Supply Current IBB Operating, outputs disabled Sleep (idle) mode fPWM < 50 kHz Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Input Hysteresis Blank Time Fixed Offtime Reference Input Voltage Range Reference Input Current GM Error3 IREF VREF = 4 V, DAC = 37.5% Err tDT tRP tS VUVLO VUVHYS VDD rising VREF = 4 V, DAC = 70.31% VREF = 4 V, DAC = 100% Crossover Dead Time Reset Pulse Width Sleep Pulse Width UVLO Enable Threshold UVLO Hysteresis Continued on the next page… tBLANK tOFF fosc = 4 MHz ROSC tied to ground ROSC = 59 KΩ VIN(1) VIN(0) IIN(1) IIN(0) VIN = VDD × 0.7 VIN = VDD × 0.3 VDD × 0.7 – –20 –20 150 0.7 15 23 0.8 –3 – – – 300 0.2 >2.5 2.35 0.05 – –