A4402_1

A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Features and Benefits ▪ 2 MHz switching frequency ▪ Adjustable soft start timer ▪ Watchdog input ▪ Power-on reset output ▪ Adjustable 2% buck regulator ▪ Adjustable 2% linear regulator ▪ Enable input ▪ 6 to 50 V supply voltage range ▪ Overcurrent protection ▪ Undervoltage lockout (UVLO) ▪ Thermal shutdown protection Description The A4402 is a power management IC that combines a 2% constant on-time buck regulator and a 2% linear regulator. Ideal for applications that require two regulated voltages. The buck regulator output supplies the adjustable linear regulator to reduce power dissipation and increase overall efficiency. The switching regulator is capable of operating above 2 MHz. A greater than 2 MHz switching frequency enables the customer to select low value inductors and capacitors while avoiding EMI. Protection features include undervoltage lockout and thermal shutdown. In case of a shorted load, each regulator features overcurrent protection. The A4402 also features a power-on reset with adjustable delay for the microprocessor output. The A4402 is provided in a 16-pin, ≤1.20 mm nominal overall height TSSOP, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Applications: ▪ Photo and inkjet printers ▪ Industrial controls ▪ Distributed power systems ▪ Network applications Package: 16-pin TSSOP with exposed thermal pad (suffix LP) Not to scale Typical Application TON VIN1 CTSET TSET 0.15 μF CPOR POR 0.33 μF 0.1 μF 10 μF Switching Regulator Output VSW 5V Rton 750 kΩ VBAT BOOT 0.01 μF LX ISEN RSENSE GND GND R1 31.6 kΩ R2 9.76 kΩ L1 33 μH 4.7 μF A 4402 VO2 20 kΩ NPOR ENB WDI 4.7 kΩ GND FB1 VIN2 VO2 R3 10 kΩ FB2 R4 5.62 kΩ Linear Regulator Output VLIN 3.3 V 300 mA 1 μF 4402-DS, Rev. 2 A4402 Selection Guide Part Number A4402ELPTR-T Constant On-Time Buck Converter with Integrated Linear Regulator Packing 4000 pieces per 13-in. reel Package 16-pin TSSOP with exposed thermal pad Absolute Maximum Ratings Characteristic VIN1 Pin VIN2 Pin LX Pin ISEN Pin ENB Pin VO2 Pin WDI Pin TON Pin FB1 and FB2 Pins NPOR Ambient Operating Temperature Junction Temperature Storage Temperature Range Symbol VIN1 VIN2 VLX VISEN VENB VO2 VWDI VTON VFBx VNPOR TA Tj(max) Tstg Range E Notes Rating –0.3 to 50 –0.3 to 7 –1 to 50 –0.5 to 1 –0.3 to 7 –0.3 to 7 –0.3 to 6 –0.3 to 7 –0.3 to 7 –0.3 to 6.5 –40 to 85 150 –40 to 150 Units V V V V V V V V V V °C °C °C Thermal Characteristics Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Units 34 ºC/W *Additional thermal information available on the Allegro website. Terminal List Table Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 – Name TON GND FB2 VIN2 VO2 WDI TSET NPOR FB1 POR ISEN BOOT LX GND VIN1 ENB PAD Function On time setting terminal Ground Feedback for VLIN Input voltage 2 Regulator 2 output Watchdog input Soft start and watchdog timing capacitor terminal Fault output Feedback for VSW POR delay Current sense, limit setting for switching regulator, connect to GND through series resistor Boot node for LX Switching regulator output Ground Input voltage 1 Enable input Exposed thermal pad Pin-out Diagram TON 1 GND 2 FB2 3 VIN2 4 VO2 5 WDI 6 TSET 7 NPOR 8 PAD 16 ENB 15 VIN1 14 GND 13 LX 12 BOOT 11 ISEN 10 POR 9 FB1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Functional Block Diagram BOOT VREF CTSET TSET 0.15 μF WDI CPOR POR 0.33 μF Soft Start Ramp Generator Watchdog Timer TON 0.01 μF VIN1 Rton 750 kΩ VBAT Boot Charge 0.1 μF 10 μF LX ISEN L1 33 μH 4.7 μF RSENSE VSW 5V Switch PWM Control ENB VO2 VFB2 20 kΩ NPOR FAULT TSD Switch Disable GND GND FB1 R2 9.76 kΩ R1 31.6 kΩ VIN2 VSW VO2 ENB WDI 4.7 kΩ Internal Regulator VREG VREF VREG VREF FB2 R4 5.62 kΩ VIN1 R3 10 kΩ 1 μF VLIN 3.3 V 300 mA Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator ELECTRICAL CHARACTERISTICS1,2 valid at TJ = 25°C, VIN = 13.5 V (unless otherwise noted) Characteristics Input Voltage Supply 1 Input Voltage Supply 2 Supply Quiescent Current ENB Logic Input Voltage ENB Hysteresis ENB Logic Input Current Linear Regulator Output Voltage Range Feedback Voltage VO2 Undervoltage Lockout Threshold VO2 Undervoltage Lockout Hysteresis Feedback Input Bias Current Current Limit Dropout Voltage Switching Regulator Output Voltage Range Feedback Voltage Feedback Input Bias Current Switcher On Time ton Low Voltage Threshold ton High Voltage Threshold Changeover Hysteresis On-time Accuracy Minimum On-time Minimum Off-time Buck Switch On-Resistance ISEN Voltage Valley Current Limit Threshold VSW VFB1 IFB1 VIN = 19.25 V, Rton = 750 kΩ ton VPL VPH VHYS errton tonmin toffmin RDS(on) VISEN Ilim RSENSE = 0.27 Ω 6 V < VIN < 8 V TJ = 25°C, ILOAD = 1 A TJ = 125°C, ILOAD = 1 A VIN = 13.5 V, Rton = 750 kΩ VIN = 8 V, Rton = 750 kΩ VIN rising VIN rising IOUT = ISW+ ILIN = 1 mA to 1.0 A, 8 V < VIN < 18 V 3.3 1.156 –400 – 185 – 8.1 15.75 – –30 80 130 – – – – – – 1.180 –100 670 235 1.4 9 17.5 250 – – – 400 650 –200 740 – 5 1.204 100 – 285 – 9.9 19.25 – 30 – – – – – – 550 V V nA ns ns μs V V mV % ns ns mΩ mΩ mV mA mA VO2 VFB2 VO2UVLO VO2UVHYS IFB2 IO2 VDROP IOUT = ISW+ ILIN = 250 mA 1 mA < IO2 < 250 mA, 3.3 V < VIN2 < 5 V VO2 rising based on FB voltage 1.8 1.156 0.896 30 –100 250 – – 1.180 0.944 50 100 – – 3.3 1.204 0.990 70 400 350 1.2 V V V mV nA mA V Symbol VIN1 VIN2 IIN(Q) VENB VENBHYS IENB High input level, VENB = 3 V Low input level, VENB < 0.4 V VIN2 = VSW ENB = 5 V, IOUT = ISW+ ILIN = 0 mA, VIN = 13.5 V VIN1 = 13.5 V, ENB = 0 V, IOUT = ISW+ ILIN = 0 mA VENB rising Test Conditions Min. 6 3.3 – – 2.0 – – –2 Typ. 13.5 – 10 – 2.28 100 – – Max. 50 5 – 1 2.56 – 100 2 Units V V mA μA V mV μA μA Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator ELECTRICAL CHARACTERISTICS1,2 (continued) valid at TJ = 25°C, VIN = 13.5 V (unless otherwise noted) Characteristics Protection Circuitry NPOR Output Voltage NPOR Leakage Current NPOR Reset Thermal Shutdown Threshold Thermal Shutdown Hysteresis Timing Circuitry TSET Current, Watchdog Mode TSET Valley Voltage, Watchdog Mode TSET Reset Voltage, Watchdog Mode WDI Frequency WDI Duty Cycle WDI Logic Input WDI Logic Input Current WDI Input Hysteresis TSET Current, Soft Start Mode POR Current 1For Symbol VNPOR INPOR VNPORRESET TJTSD TJTSDHYS ITSETWDI VTRIP VRESET fWDI DCWDI VWDI(0) IWDI VWDIHYS ITSETSS IPOR NPOR = low VWDI = 0 to 5 V NPOR = high INPOR = 1 mA VNPOR = 5 V Test Conditions Min. – – – – – 7 – – – 10 VIN2 × 0.55 –20 – 14 3.92 Typ. – – – 170 15 10 1.2 0.48 – – – < 1.0 300 20 5.60 Max. 400 1 0.7 – – 14 – – 100 90 – 20 – 26 7.28 Units mV μA V ºC ºC μA V V kHz % V μA mV μA μA 20 kΩ pullup connected to VOUT2, VIN < TJ rising input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. 2Performance in the range –40°C to 85°C guaranteed by design and characterization. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Power-Up and Power-Down Timing Diagrams Using ENB ENB 18 V VIN1 t ss 6V V SW V LIN UVLO Rising UVLO Falling UVLO Rising t por NPOR t por Using VIN1 VIN1 t ss t ss V SW V LIN UVLO Rising UVLO Falling UVLO Rising NPOR VPOR VCTSET t por t por Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Watchdog Timing Diagram ENB t ss V SW VO2 NPOR UVLO Rising t por t por WDI t wait V trip t wait V TSET V reset Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Functional Description Basic Operation The A4402 contains a fixed on-time, adjustable voltage buck switching regulator with valley sensing current mode control, and an adjustable linear regulator designed to run off the buck regulator output. The constant on-time converter maintains a constant output frequency because the on-time is inversely proportional to the supply voltage. As the input voltage decreases, the on-time is increased, maintaining a relatively constant period. Valley mode current control allows the converter to achieve very short on-times because current is measured during the off-time. The device is enabled via the ENB input. When the ENB pin is pulled high, the converter starts-up under the control of an adjustable soft start routine whose ramp time is controlled by an external capacitor. Under light load conditions, the switch enters pulse-skipping mode to ensure regulation is maintained. This effectively changes the switcher frequency. The frequency also is affected when the switcher is operating in discontinuous mode. In order to maintain a wide input voltage range, the switcher period is extended when either the minimum off-time at low VIN, is reached or the minimum on-time at high VIN. Switcher Overcurrent Protection The converter utilizes pulse-by-pulse valley current limiting, which operates when the current through the sense resistor creates a voltage on the sense pin (ISEN) that equals –0.2 V. During an overload condition, the switch is turned on for a period determined by the constant ontime circuitry. The switch off-time is extended until the current decays to the current limit value set by the selection of the sense resistor, at which point the switch turns on again. Because no slope compensation is required in this control scheme, the current limit is maintained at a reasonably constant level across the input voltage range. Figure 1 illustrates how the current is limited during an overload condition. The current decay (period with switch off) is proportional to the output voltage. As the overload is increased, the output voltage tends to decrease and the switching period increases. VIN1 and VIN2 VIN1 is a high voltage input, designed to withstand 50 V. Bulk capacitance of at least 10 μF should be used to decouple input supply VIN1. The VIN2 input is used to supply the linear regulator and should be connected directly to the output of the switching regulator. Output Voltage Selection The output voltage on each of the two regulators is set by a voltage divider off the regulator output, as follows: ⎛ R1 + R2 ⎞ ⎟ VSW = VFB1 ⎜ , ⎜ R2 ⎟ ⎝ ⎠ ⎛ R1 + R2 ⎞ ⎟ (1) VLIN = VFB2 ⎜ . ⎜ R2 ⎟ ⎝ ⎠ In order to maintain accuracy on the regulators the equivalent impedance on the FB node (R1 parallel with R2) should be approximately 10 kΩ. Inductor current operating at maximum load Current Limit level Maximum load Current Constant On-Time Constant period Time Inductor current operating in a “soft” overload Overload Current Limit level Current Constant On-Time Extended period Time Figure 1. Current limiting during overload Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator TSET The TSET pin serves a dual function by controlling the timing for both the soft start ramp and the WDI input. The current sourced from the TSET pin is dependant on the state of NPOR. There are two formulas for calculating the time constants. CTSET must be selected so that both the WDI frequency and soft start requirements are met. The formulas for calculating WDI and soft start timing are: (2) tWDI = 7.2 × 9.6 × 104 × CTSET , and tSS = 6.0 × 6.0 × 104 × CTSET , where CTSET is the value of the capacitor and the results, tx, are in s. Watchdog The WDI input is used to monitor the state of a DSP or microcontroller. A constant current is driven into the capacitor on TSET, causing the voltage on the TSET pin to ramp upward until, at each rising edge on the WDI input, the ramp is pulled down to VRESET. If no edge is seen on the WDI pin before the ramp reaches VTRIP , the NPOR pin is pulled low. The watchdog timer is not activated until the WDI input sees one rising edge. The WDI pin should be pulled to ground with a 4.7 kΩ resistor. Soft Start During soft start, an internal ramp generator and the external capacitor on TSET are used to ramp the output voltage in a controlled fashion. This reduces the demand on the external power supply by limiting the current that charges the output capacitor and any DC load at startup. Either of the following conditions are required to trigger a soft start: • ENB pin input rising edge • Reset of a TSD event When a soft start event occurs, VO2 is held in the off state until the soft start ramp timer expires. Then the regulator will power up normally. Refer to timing diagrams for details. BOOT A bootstrap capacitor is used to provide adequate charge to the NMOS switch. The boot capacitor is referenced to LX and supplies the gate drive with a voltage larger than the supply voltage. The size of the capacitor must be 0.01 μF, X7R type, and rated for at least 25 V. (3) TON A resistor from the TON input to VIN1 sets the on-time of the converter for a given input voltage. The formula to calculate the on-time is: R ton = ton VIN1 3.12–12 + 30 × 10–9 . (4) When the supply voltage is between 9 and 17.5 V, the switcher period remains constant, at a level based on the selected value of Rton . At voltages lower than 9 V and higher than 17.5 V, the period is reduced by a factor of 3.5. If a constant period is desired over varying input voltages, it is important to select an on-time that under worst case conditions will not exceed the minimum off-time or minimum on-time of the converter. For reasonable input voltage ranges, the period of the converter can be held constant, resulting in a constant operating frequency over the input supply range. More information on how to choose Rton can be found in the Application Information section. ISEN The sense input is used to sense the current in the diode during the off-time cycle. The value for RSENSE is obtained by the formula: RSENSE = 0.2 / IVALLEY , tor during the off-time cycle. It is recommended that the current sense resistor be sized so that, at peak output current, the voltage on ISEN does not exceed –0.5 V. Because the diode current is measured when the inductor current is at the valley, the average output current is greater than the IVALLEY value. The value for IVALLEY should be: IVALLEY = IOUT(av) – 0.5 IRIPPLE + K , where: IOUT(av) is the average of both output currents, IRIPPLE is the inductor ripple current, and K is a guardband margin. The peak current in the switch is then: IPEAK = IVALLEY + IRIPPLE . (7) (6) (5) where IVALLEY is the lowest current measured through the induc- Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator The valley current must be calculated so that, at the worst-case ripple, the converter can still supply the required current to the load. Further information on how to calculate the ripple current is included in the Application Information section. ENB An active high input enables the device. When set low, the device enters sleep mode; all internal circuitry is disabled, and the part draws a maximum of 1 μA. Thermal Shutdown When the device junction temperature, TJ , is sensed to be at TJTSD, a thermal shutdown circuit disables the regulator output, protecting the A4402 from damage. Power-on Reset Delay The POR function monitors the VFB2 voltage and provides a signal that can be used to reset a DSP or microcontroller. A POR event is triggered by either of the following conditions: • VFB2 falls below its UVLO threshold. This occurs if the current limit on either regulator is exceeded, or if the switcher voltage falls due to TSD. • After a rising edge on the WDI input, the voltage on TSET reaches VTRIP. An open drain output, through the NPOR pin, is provided to signal a POR event to the DSP or microcontroller. The reset occurs after an adjustable delay, tPOR, set by an external capacitor connected to the POR pin. The value of tPOR is calculated using the following formula: tPOR = 2.4 × 102 × CPOR , (8) where CPOR is the value of the capacitor and tPOR is in s. Shutdown The buck regulator will shutdown if one of the following conditions is present: • TSD • ENB falling edge Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Application Information Switcher On-Time and Switching Frequency In order for the switcher to maintain regulation, the energy that is transferred to the inductor during the on-time must be transferred to the capacitor during the off-time. Because of this relationship, the load current, IR drops, as well as input and output voltages, affect the on-time of the converter. The equation that governs switcher on-time is: ton = TSW × (VSW+ RLOAD× IPEAK + Vf + RSENSE× IPEAK ) VIN1+ RDS(on)× IPEAK + Vf . (9) After the resistor is selected and a suitable ton is found, it must be demonstrated that ton does not, under worst-case conditions, exceed the minimum on-time or minimum off-time of the converter. The minimum on-time occurs at maximum input voltage and minimum load. The maximum off time is occurs at minimum supply voltage and maximum load. For supply voltages below 9.5 V and above 7 V, refer to the Low Voltage Operation section. Low Voltage Operation The converter can run at very low input voltages. With a 5 V output, the minimum input supply can be as low as 6 V. When operating at high frequencies, the on-time of the converter must be very short because the available period is short. At high input voltages the converter must maintain very short on-times, while at low input voltages the converter must maintain long off-times. Rather than limit the supply voltage range, the converter solves this problem by automatically increasing the period by a factor of 3.5. With the period extended, the converter will not violate the minimum on-time or off-time. If the input voltage is between 9.5 V and 17 V, the converter will maintain a constant period. When calculating worst-case on-times and off-times, make sure to use the multiplier if the supply voltage is between those values. When operating at voltages below 8 V, additional care must be taken when selecting the inductor and diode. At low voltages the maximum current may be limited due to the IR drops in the current path. When selecting external components for low voltage operation, the IR drops must be considered when determining on-time, so the complete formula should be used to make sure the converter does not violate the timing specification. Inductor Selection Choosing the right inductor is critical to the correct operation of the switcher. The converter is capable of running at frequencies above 2 MHz. This makes it possible to use small inductor values, which reduces cost and board area. The inductor value is what determines the ripple current. It is important to size the inductor so that under worst-case conditions IVALLEY equals IAV minus half the ripple current plus reasonable margin. If the ripple current is too large, the converter will be current limited. Typically peak-to-peak ripple current should be limited to 20% to 25% of the maximum average load current. The effects of the voltage drop on the inductor and trace resistance affect the switching frequency. However, the frequency variation due to these factors is small and is covered in the variation of the switcher period, TSW , which is ±25% of the target. Removing these current dependant terms simplifies the equation: 1 V + V + (VSENSE× IPEAK ) ton = SW f VIN1+ Vf + (VSENSE× IPEAK ) × fSW . (10) Be sure to use worst-case sense voltage and forward voltage of the diode, including any effects due to temperature. For example, given a 1 A converter with a supply voltage of 13.5 V, output voltage is 5 V, Vf is 0.5 V, VSENSE is 0.15 V and the desired frequency is 2.0 MHz. We can solve for ton as follows: 1 5 + 0.5 + 0.15 ton = 199 ns 13.5 + 0.5 + 0.15 × 2×106 = . The formulas above describe how ton changes based on input and load conditions. Because load changes are minimal, and the output voltage is fixed, the dominant factor that affects the on-time is the input voltage. The converter is able to maintain a constant period over a varying supply voltage because the on-time change is based on the input voltage. The current into the TON terminal is derived from a resistor tied to VIN1, which sets the on-time proportional to the supply voltage. Selecting the resistor value, based on the ton calculated above, is done using the following formula: RTON = VIN1× (ton+ 10 ns) 3.12 × 10–12 . (11) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4402 Worst-case ripple current occurs at maximum supply voltage. After calculating the duty cycle, DC, for this condition, the ripple current can be calculated. First to calculate DC: VSW+ Vf + (VSENSE× IPEAK ) DC = VIN1(max) + Vf + (VSENSE× IPEAK ) . (12) Constant On-Time Buck Converter with Integrated Linear Regulator further filtering is needed it, is recommended that two ceramic capacitors be used in parallel to further reduce emissions. Rectification Diode The diode conducts the current during the off-cycle. A Schottky diode is needed to minimize the forward drop and switching losses. In order to size the diode correctly, it is necessary to find the average diode conduction current using the formula below: (15) ID(av) = ILOAD × (1 – DC(min)) , where DC (min) is defined as: DC (min) = VSW+Vf VIN1+Vf , (16) Using the duty cycle, a ripple current can be calculated using the following formula: L= VIN1– VSW IRIPPLE × DC × 1 fSW(min) , (13) where IRIPPLE is 25% of the maximum load current, and fSW(min) is the minimum switching frequency (nominal frequency minus 25%). For the example used above, a 1 A converter with a supply voltage of 13.5 V was the design objective. The supply voltage can vary by ±10%. The output voltage is 5 V, Vf is 0.5 V, VSENSE is 0.15, and the desired frequency is 2.0 MHz. The duty cycle is calculated to be 36.45%. The worst-case frequency is 2 MHz minus 20% or 1.6 MHz. Using these numbers in the above formula shows that the minimum inductance for this converter is 9.6 μH. Output Capacitor The converter is designed to operate with a low-value ceramic output capacitor. When choosing a ceramic capacitor, make sure the rated voltage is at least 3 times the maximum output voltage of the converter. This is because the capacitance of a ceramic decreases as they operate closer to their rated voltage. It is recommended that the output be decoupled with a 10 μF, X7R ceramic capacitor. Larger capacitance may be required on the outputs if load surges dramatically influence the output voltage. Output ripple is determined by the output capacitance and the effects of ESR and ESL can be ignored assuming recommended layout techniques are followed. The output voltage ripple is approximated by: where VIN1 is the maximum input voltage and Vf is the maximum forward voltage of the diode. Average power dissipation in the diode is: PD(diode) = ILOAD(av) × DC(min) × Vf , (17) The power dissipation in the sense resistor must also be considered using I2R and the minimum duty cycle. PCB Layout The board layout has a large impact on the performance of the device. It is important to isolate high current ground returns, to minimize ground bounce that could produce reference errors in the device. The method used to isolate power ground from noise sensitive circuitry is to use a star ground. This approach makes sure the high current components such as the input capacitor, output capacitor, and diode have very low impedance paths to each other. Figure 2 illustrates the technique. L Q1 CIN RSENSE D COUT RLOAD VRIPPLE = IRIPPLE 4 × fSW × COUT . (14) Input Capacitor The value of the input capacitance affects the amount of current ripple on the input. This current ripple is usually the source of supply side EMI. The amount of interference depends on the impedance from the input capacitor and the bulk capacitance located on the supply bus. Adding a small value, 0.1 μF , ceramic capacitor as close to the input supply pin as possible can reduce EMI effects. The small capacitor will help reduce high frequency transient currents on the supply line. If Current path (on-cycle ) Star Ground Current path (off-cycle ) Figure 2. Star Ground Connection Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4402 The ground from each of the components should be very close to each other and be connected on the same surface as the components. Internal ground planes should not be used for the star ground connection, as vias add impedance to the current path. In order to further reduce noise effects on the PCB, noise sensitive traces should not be connected to internal ground planes. The feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. The exposed pad should be connected to internal ground planes and to any exposed copper used for heat dissipation. If the grounds from the device are also connected Constant On-Time Buck Converter with Integrated Linear Regulator directly to the exposed pad the ground reference from the feedback network will be less susceptible to noise injection or ground bounce. To reduce radiated emissions from the high frequency switching nodes it is important to have an internal ground plane directly under the LX node. The plane should not be broken directly under the node as the lowest impedance path back to the star ground would be directly under the signal trace. If another trace does break the return path, the energy will have to find another path, which is through radiated emissions. PCB Layout Diagram C5 VIN1 GND R5 GND U1 VIN2 R6 C2 C3 VLIN VSW C6 C4 R1 L1 C1 C8 C7 GND R7 Star Ground R4 GND R3 GND R2 D1 R5 C5 C1 TON GND ENB VIN1 C8 C2 R1 C3 D1 PCB R7 VLIN R6 FB2 VIN2 VO2 WDI A4402 PAD VIN1 GND LX BOOT ISEN POR FB1 C7 A4402 Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.) L1 C6 R4 VSW TSET NPOR R2 R3 C4 Thermal Vias Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Pin Circuit Diagrams Power Terminals VIN1 LX TON Logic Terminals VIN2 FB1 FB2 WDI TSET NPOR POR ISEN ENB 54 V GND GND GND 7V GND GND VIN1 BOOT 10 V 10 V GND VIN2 VO2 VIN1 54 V GND GND Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4402 Constant On-Time Buck Converter with Integrated Linear Regulator Package LP, 16-Pin TSSOP 5.00 ±0.10 16 4° ±4 +0.05 0.15 –0.06 1.70 0.45 16 0.65 B 3.00 A 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 (1.00) 3.00 6.10 1 2 3.00 0.25 SEATING PLANE 0.65 1.20 MAX 0.15 MAX C SEATING PLANE GAUGE PLANE 12 3.00 C PCB Layout Reference View 16X 0.10 C +0.05 0.25 –0.06 All dimensions nominal, not for tooling use (reference JEDEC MO-153 ABT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright ©2008-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15