A4490EESTR-T

A4490 Triple Output Step-Down Switching Regulator Features and Benefits ▪ Three buck converters ▪ 4.5 to 34 V input voltage range ▪ 550 kHz fixed frequency ▪ Multiphase switching ▪ Independent control of each converter ▪ Power-on-reset flag ▪ Internal compensation ▪ 4 × 4 mm QFN Package, small PCB footprint Description Designed to provide the power supply requirements of printers, office automation, industrial, and portable equipment, the A4490 provides three high current, high performance, switching regulator outputs with independent soft start. High frequency switching allows selection of inexpensive inductors and small ceramic output capacitors. The turn-on cycles of the regulators are interleaved to minimize stresses on the input capacitors and to reduce EMI. A charge pump is used to provide the supply for driving the power switches, ensuring operation at very wide operating duty cycles and avoiding the need for power-draining clamp circuits. A power-on-reset circuit with user configurable delay indicates when enabled regulators are in specification. The power-onreset flag also indicates when the input voltage drops below specification, giving the system controller advance warning while the switchers continue to operate down to the shutdown level. Internal diagnostics provide comprehensive protection against overloads, input undervoltages, and overtemperatures. Continued on the next page… Package: 20-contact QFN (suffix ES) Approximate size Typical Application VBB VDD PORZ CPOR Microcontroller or Controller Logic CP1 CP2 VCP VBB1 LX1 VREG1 FB1 VBB2 LX2 FB2 A4490 ENB1 ENB2 ENB3 VREG2 PGND VBB3 LX3 VREG3 FB3 GND 4490-DS, Rev. 9 A4490 Triple Output Step-Down Switching Regulator Description (continued) The A4490 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number A4490EESTR-T Applications include the following: ▪ Photo, inkjet, and portable printers ▪ Industrial ▪ Hand-held devices ▪ Portable applications Operating Temperature Range (°C) –40 to 85 Packing 1500 pieces per 7-in. reel Absolute Maximum Ratings (reference to GND) Characteristic Load Supply Voltage LX1, LX2, and LX3 Pins PORZ and VDD Pins ENBx Pin Input Current Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VBB VLXn VIN IENBx TA TJ(max) Tstg Driven by a current-limited voltage source Range E Notes Rating 36 –1 to 36 –0.3 to 7 1 –40 to 85 150 –55 to 150 Units V V V mA ºC ºC ºC Recommended Operating Conditions Characteristic Load Supply Voltage LX1, LX2, and LX3 Pins Operating Ambient Temperature Junction Temperature Symbol VBB VLXn TA TJ Conditions To operate at VBB < 6 V, connect VDD supply to the VBB supply. See Powering Configurations section. Min. 4.5 –0.7 –40 –40 Typ. – – – – Max. 34 34 85 125 Units V V ºC ºC Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Units 37 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4490 Triple Output Step-Down Switching Regulator Functional Block Diagram C2 47 nF CP1 CP2 V BB C1 100 nF V BB VDD Regulator Charge Pump VCP C3 Switch 47 nF VBB1 C4 VCP 10 μ F L1 LX1 Switcher #1 PWM Control D1 R1 FB1 R2 10 μ F 15 μ H C5 V REG1 5 V / 1.5 A V BB Bias Supply 100 kΩ ENB1 SS VBB2 C6 VCP LX2 ENB2 V DD SS Switcher #2 PWM Control D2 10 μ F R3 FB2 PORZ POR Block C14 470 nF ENB3 SS CPOR VCP LX3 Switcher #3 PWM Control FB3 PGND GND R6 D3 10 μ F R5 10 μ F 10 μ F 10 μ F L3 4.7 μ H C10 C11 C12 VBB3 C9 10 μ F V REG3 1.0 V / 1.5 A C13 R4 10 μ F 10 μ F C7 V REG2 3.3 V / 1.5 A C8 L2 10 μ H Note: All capacitors ceramic X5R. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4490 Triple Output Step-Down Switching Regulator Pin-out Diagram 20 ENB1 18 VBB1 17 VBB3 19 LX1 16 LX3 FB1 VDD GND FB2 ENB2 1 2 3 4 5 VCP 10 6 7 8 9 PAD 15 14 13 12 11 ENB3 FB3 PGND CP1 CP2 CPOR VBB2 Terminal List Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 – 1GND Name FB1 VDD GND1 FB2 ENB2 LX2 VBB22 CPOR PORZ VCP CP2 CP1 PGND1 FB3 ENB3 LX3 VBB32 VBB12 LX1 ENB1 PAD3 Feedback REG1 Bias supply Ground Feedback REG2 PORZ LX2 Function Enable REG2, logic input, active high Switch node REG2 Input supply for REG2 POR delay adjustment Power on reset output, active low Charge pump reservoir Charge pump capacitor terminal Charge pump capacitor terminal Ground for charge pump circuitry Feedback REG3 Enable REG3, logic input, active high Switch node REG3 Input supply for REG3 Input supply for REG1 Switch node REG1 Enable REG1, logic input, active high Exposed pad for enhanced thermal dissipation and PGND should be connected externally. 2The three VBBx pins should be connected together externally. 3Thermal pad should be connected to the ground (0 V) plane using thermal vias. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4490 Triple Output Step-Down Switching Regulator ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics General VBB Quiescent Current VDD Supply Range VDD Quiescent Current REG1, REG2, and REG3 Feedback Input Bias Current Feedback Voltage Output Voltage Regulation3 PWM Frequency Maximum Duty Cycle Minimum Duty Cycle IBIAS VFB VOUT fSW Dmax Dmin TJ = 25°C, ILOAD = 1.5 A, VBB = 6.0 V Buck Switch On-Resistance RDS(on) TJ = 125°C, ILOAD = 1.5 A, VBB = 6.0 V TJ = 25°C, ILOAD = 1.5 A, VBB = 4.5 V TJ = 125°C, ILOAD = 1.5 A, VBB = 4.5 V Current Limit Threshold Soft Start Duration Logic Inputs and Outputs ENBx Input Voltage ENBx Input Hysteresis ENBx Input Current PORZ Output (Open Drain) PORZ Output Leakage Current Power-On Reset Duration VIL VIH VI(hys) IIL VPORZL IPORZH tPOR VIH ≤ 5 V IPORZL = 1 mA, fault asserted VPORZ = 5 V, fault not asserted CPOR = 470 nF – 2.0 300 –1 – –1 75 – – 500 – – – 115 0.8 – – 1 0.4 1 155 V V mV μA V μA ms ILIM tss Peak current through switch with D = 0.9 With respect to 0.8 V target voltage VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –20°C to 85°C VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –40°C to 85°C –400 – –2.5 –3.5 470 90 – – – – – 2.0 0.625 1.25 1.875 –100 ±1.5 – – 550 – 5 450 700 560 870 100 – 2.5 3.5 630 – – – – – – nA % % % kHz % % mΩ mΩ mΩ mΩ A ms IBBON IBBOFF VDD IDD ENBx = high ENBx = 0 V ENBx = high, ILOAD = 0 mA, VBB = 12 V, current drawn by feedback resistors ignored ENBx = 0 V – – 3.3 – – 1 1 – – 1 2 – 5.5 5 – mA μA V mA μA Symbol Test Conditions Min. Typ. Max. Unit Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4490 Triple Output Step-Down Switching Regulator ELECTRICAL CHARACTERISTICS1,2 (continued) at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics Protection VREGx Undervoltage Lockout Startup VREGx Undervoltage Lockout Shutdown VREGx Undervoltage Lockout Startup Hysteresis VBB Undervoltage Lockout Startup VBB Undervoltage Lockout Shutdown VBB Undervoltage Lockout Shutdown Hysteresis VBB Undervoltage Warning Threshold Junction Overtemperature Shutdown Junction Overtemperature Shutdown Hysteresis 1For 2Specifications Symbol VREGUV(su) VREGUV(sd) VREGUV(suhys) VBBUV(su) VBBCPUV(su) VBBUV(sd) VBBCPUV(sd) VBBUV(sdhys) Test Conditions FB1, FB2, and FB3 rising FB1, FB2, and FB3 falling Min. – – – Typ. 85 80 5 4.3 4.2 4.1 3.5 500 600 3.6 165 15 Max. – – – 4.6 4.4 4.5 4.1 – – – – – Unit %VFB %VFB % V V V V mV mV V °C °C No external VDD supply, VBB rising External VDD supply, VBB rising No external VDD supply, VBB falling External VDD supply, VBB falling No external VDD supply VBB falling (forces PORZ low); switchers continue to operate Temperature rising Recovery = TJTSD –TJTSD(hys) 3.9 3.9 3.7 3.0 – – – – – VBBCPUV(sdhys) External VDD supply VBBUV(por) TJTSD TJTSD(hys) input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. over the junction temperature range of –40°C to 125°C are assured by design and characterization. 3Average value of V OUT relative to target voltage. The effects of the feedback resistors are not taken into account. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4490 Triple Output Step-Down Switching Regulator Functional Description Basic Operation The A4490 contains three fixed frequency, buck switching converters with peak current-mode control, including slope compensation. Each converter can be independently turned on and off via the enable inputs (EN1, EN2, and EN3), which are active high. When enabled, the corresponding output is brought-up under the control of a soft start routine, which avoids output voltage overshoot and minimizes input inrush current. The output voltage is typically divided down by an external potential divider, and is compared against an internal reference voltage to produce an error signal, also known as the current demand signal. The current signal through the buck switch is converted into a voltage. This signal is then compared against the current demand signal to create the required duty cycle. At the beginning of each switching cycle, the buck switch is turned on. When the current signal through the switch reaches the level of the current demand signal, the on-time of the switch is terminated. On the next switching cycle, the switch is turned on again and the cycle is repeated. One shared clock is used to define the switching frequency for each regulator. Each of the three switching cycles (REG1, REG2, and REG3) are phase shifted with respect to one another by 120° in an attempt to minimize the pulsed current drawn from the input filter capacitors. Under certain conditions, for example at low VBB conditions and relatively high user-set output voltages, switching overlap between channels is inevitable. Under conditions, such as light loads or high VBB voltages, that cause duty cycles (DC) of less than the minimum value, the converter enters a pulse-skipping mode to ensure regulation is maintained. A charge pump regulator is provided to ensure a sufficient gate drive is available for all three power switches across the full input voltage range. This regulator allows operation even at very wide operating duty cycles. On initial power-up, an internal regulator is used to provide the bias supply for on-chip control functions. Each regulator channel utilizes pulse-by-pulse current limiting in the event of either a short circuit or an overload. If the overload is applied long enough, the IC temperature may rise sufficiently to cause the thermal shutdown circuit to operate. The part will auto-restart under control of the soft start circuit after the thermal disable condition is removed, and assuming all other conditions are met. See the Shutdown section for more information. Power Configuration The A4490 supports alternative schemes for providing logic supply voltage on the VDD pin. In addition, the IC can be powered up and down using either the VBB or ENB pins. Powering VDD To minimize power dissipation, especially at high input voltages, it is recommended that an external supply be applied to the VDD input pin. Typically, this voltage is derived from one of the three regulated outputs that are set-up for between 3.3 and 5 V (VREGx). Another advantage of powering the VDD externally is that the VBB undervoltage lockout level is lowered. To maximize the run time of the switchers during a VBB power-down condition, two alternative undervoltage shutdown conditions are supported, depending on which VDD-powering configuration has been implemented. When no external VDD is applied, the minimum VBB, VBBUV(sd) , is 4.1 V typical. When an external VDD is applied, the minimum VBB, VBBCPUV(sd) , is 3.5 V typical. One note of caution when deriving VDD from a VREG output: during initial application of VBB, the internal bias supply automatically starts from the internal regulator because VREG has not yet reached regulation. This means the startup threshold is determined by VBBUV(su) (4.3 V typical) because there is no external VDD. When VREG has begun to supply VDD externally, the shutdown threshold reduces to VBBCPUV(sd) (3.5 V typical). This assumes that VREG is present. Powering Up and Down with VBB Referring to figure 1, each of the enable inputs (ENBx) are held high by being tied to the VBB rail via a 100 kΩ resistor and the VDD is supplied from one of the regulator outputs. When the VBB voltage reaches the minimum threshold, VBBUV(su) , the charge pump supply (VCP) ramps up. When VBB + VCP has reached the minimum threshold VBBCPUV(su), the soft start routines are initiated (tSS) for all three regulator channels (VREGx). When all three regulators have reached the 85% FBx threshold, the power-on-reset timer is initiated. After the power-on-reset period, tPOR , has elapsed, PORZ goes high, indicating that all the regulators and VBB are in specification. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4490 Triple Output Step-Down Switching Regulator V BBUV(su) 0V VBB V BBUV(por) VBB+VCP V BBCPUV(su) V BB+5.5 V V BBCPUV(sd) VREG1 VREG2 VREG3 85%FB1 85%FB2 85%FB3 PORZ t SS t POR Figure 1. Timing diagram for powering up and down using the VBB pin VBB 0V ENB1 ENB2 ENB3 VREG1 VREG2 VREG3 85%FB1 85%FB2 80%FB2 85%FB2 85%FB3 PORZ tSS tSS tPOR tSS tPOR tPOR Figure 2. Timing diagram for powering up and down using the ENB pin Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4490 Triple Output Step-Down Switching Regulator When the VBB voltage starts to fall below the undervoltage warning level, VBBUV(por) , of 3.6 V typical, the PORZ flag resets. This gives advance warning to the system controller that the VBB voltage is falling. Note that this feature is only guaranteed when VDD is supplied externally. During this interval, the three switchers continue to operate. While VBB falls further, the VCP supply also tends to fall, which degrades the drive voltage to the series switches. In addition, the higher voltage rails start to fall out of regulation first, as the corresponding maximum duty cycle (Dmax) for these particular converters is reached. The regulators that have the lower output voltages achieve some level of steady state, before the A4490 powers down when all of the corresponding VBB undervoltage thresholds have been reached. For example, it may be possible for a 1 V output to continue to operate down to a VBB of 3.4 V typical, if the VDD supply is derived externally. The extent of this effect depends on a myriad of factors, including input and output filter capacitance, output loads, gate drive amplitude, MOSFET RDS(on), and so forth. Powering Up and Down with Enable Referring to figure 2, VBB is present and the UVLO start-up thresholds, VBBUV(su) and VBBCPUV(su) have been reached. Each of the regulators are enabled in turn. Initially, VREG1 is enabled and is brought-up under the control of the soft start circuit (tSS). Before VREG1 reaches 85% FB1, VREG2 is enabled and is brought-up under a separate soft start control. When both regulators have reached their respective 85% FB thresholds, the power-on-reset (POR) timer is initiated. Note that the POR timer is only enabled after all of the enabled regulators reach their corresponding 85% FB levels. After the power-onreset time, tPOR , has elapsed, if the FB levels of VREG1 and VREG2 are not below their respective 80% FB levels, then the PORZ signal will go high. At some point later, if VREG3 is enabled, then the PORZ is reset and VREG3 is brought-up under the control of the soft start circuit. When the 85% FB3 threshold is reached, the POR timer is initiated. After tPOR has elapsed, if all the FB levels are above their respective 80% FB levels, then the PORZ signal will go high. Note that if any regulator channel is not enabled, the channel will not influence PORZ. To avoid multiple signal changes of the PORZ signal, it is recommended that the system be designed such that all three regulator channels are within specification before tPOR has elapsed. If any regulator channel drops below 80% FB, the PORZ signal will be reset. If the voltage then recovers to within 85% FB, the POR timer is initiated again. Note that a soft start is not initiated when the feedback voltage drops below the 80% FB level. This is to allow a rapid auto-restart in the event of an overload or similar fault. If a soft start is required, it is recommended that on receipt of the PORZ reset signal, the system controller disables and then re-enables the relevant regulator channels again. As soon as the last regulator is disabled the PORZ signal is reset. Power on Reset The power-on-reset duration, tPOR , is determined by selecting an appropriate capacitor connected to the CPOR pin. The value of tPOR can be determined by the following formula: tPOR = 2.131 ×105 × CPOR . (1) The PORZ output goes high when both VBB is above the undervoltage warning levels, and the FB pins of the regulators that are enabled are > 85% of the VREG voltage. Because the external capacitor is charged via a 5 μA current source, care must be taken in the layout to avoid additional leakage paths. The capacitor should be positioned adjacent to the CPOR pin, and the ground connection to the A4490 GND pin should be as short as possible. It is recommended that the tPOR period be set to exceed the start-up phases of all three regulators, to avoid the possibility of multiple triggerings of the PORZ output. Output Voltage Selection The output voltage on each of the three regulators is set by the following relationship, shown here for the VREG1 channel: ⎛V ⎞ R1 = R2 ⎜ REG1 – 1 ⎟ , (2) ⎜V ⎟ ⎝ FB ⎠ where R2 (connected between GND and the FB1 pin) should be a value between 4.7 and 12 kΩ. R1 is connected between the output rail and the FB1 pin. VREG1 is the set output regulator voltage. VFB is the reference voltage. The tolerances of the feedback resistors influence the voltage setpoint. It is therefore important to consider the tolerance selection when targeting an overall regulation figure. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4490 Triple Output Step-Down Switching Regulator The bias current, IBIAS , flowing out of the FB1 node into R2, will introduce a small voltage offset to the output. Enable Each regulator channel can be individually enabled via the corresponding ENBx pin. If any channel is required to startup automatically after the VBB voltage is applied, that particular channel should have the ENB pin tied to the VBB rail via a pullup resistor. This resistor should be selected to limit the current to less than the maximum specified value, 1 mA. This prevents the internal protection clamps from turning on. It is recommended that a 100 kΩ pull-up resistor be used. This would ensure the current remains below the maximum value when VBB = 36 V. Soft Start Each regulator channel contains a soft start circuit. A soft start cycle is initiated when the appropriate regulator enable input is set to high; the VBB, charge pump, and bias supply voltages are above the minimum values; and no thermal shutdown condition exists. Note that an overload or short circuit will not cause a soft start cycle, unless a thermal shutdown event occurs. During a soft start cycle, the reference voltage is ramped from 0 to 0.8 V typical, which in turn forces the current demand signal to increase in a linear fashion. Shutdown All converter channels are disabled in the event of either a thermal shutdown event or an undervoltage on VBB (VBBUV(sd) or VBBCPUV(sd)). As soon as the above fault conditions have been removed, and assuming the ENB inputs are enabled, the appropriate channels will auto-restart under control of the soft start. Current Limit The typical peak current limit for each channel is specified as 2.5 A minimum, with a duty cycle of 0.9. The minimum current limit occurs at maximum duty cycle (0.9), because the slope compensation has a maximum effect under this condition. As the duty cycle reduces, the current limit increases. This means for applications that operate with a narrow duty cycle, it is possible to operate with a load current greater than 2.0 A. Figure 3 illustrates the typical peak current limit versus duty cycle. For example, it is possible to operate with a peak current limit of 3.75 A with a duty cycle of 0.3. As well as ensuring the peak current limit is not exceeded, under worst case load and input voltage conditions, it is also important to check the implications on the thermal performance. See the Thermal Considerations section. Component Selection Inductor The inductance value, L, determines the ripple current. It is important to ensure that the minimum current limit is not exceeded under worst-case conditions: VBB(min), ILOAD(max), fSW(min), and L(min). It is recommended that gapped ferrite solutions be used as opposed to powdered iron solutions, the latter of which exhibit relatively high core losses that can have a large impact on long term reliability. Inductors are typically specified at two current levels, rms current and saturation current. With regard to the rms current, it is important to understand how the rms current level is specified, in terms of ambient temperature. Some manufacturers quote an ambient only, whilst others quote a temperature that includes a self-induced temperature rise. For example, if an inductor is rated for 85°C and includes a self-induced temperature rise of 25°C at maximum load, then the inductor cannot be safely operated beyond an ambient temperature of 60°C at full load. The rms current can be assumed to be simply the maximum load current, with perhaps some margin to allow for overloads, and so forth. The first stage of determining the inductor value is to specify a peak-to-peak ripple current of typically about 20% to 25% of the maximum load. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0.5 1.0 0.5 0 0 20 40 60 80 100 Duty Cycle (%) Figure 3. Current limit versus duty cycle Current Limit (A) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4490 Triple Output Step-Down Switching Regulator The maximum peak-to-peak ripple current, IRIPPLE , occurs at the maximum input voltage. Therefore the duty cycle, D, should be found under these conditions (for the VREG1 channel): D(min) = VREG1+Vf VBB(max)+Vf . (3) The output capacitor determines the output voltage ripple and is used to close the control loop. To guarantee stability, the capacitance has to increase as the output voltage is reduced. This is actually reasonable from a ripple voltage point of view, as the ripple voltage is typically specified as a percentage of output voltage. The following table outlines what the minimum output capacitance should be for a given output voltage: Output Voltage (V) Minimum Output Capacitance (μF) 3.3 4.7 10 20 30 40 where Vf is the forward voltage drop of the recirculation diode. The required inductance can be found: L (min) = VBB(max) – VREG1 × D(min) × IRIPPLE 1 fSW(min) , (4) 15 12 5 3.3 1.8 to 2.5