A6272
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
FEATURES AND BENEFITS
DESCRIPTION
• AEC-Q100 qualified
• 5.3 to 40 V supply; operates down to 5.1 V, when enabled
• LED current programmed independently with two
external MOSFETs
• Flexible LED dimming options
□□ Integrated PWM dimming set by resistors
□□ External PWM dimming set by microcontroller
□□ Analog voltage control for PWM dimming
□□ Current slew rate limit during PWM dimming
• Adjustable LED current derating for elevated VIN
• LED current derating for elevated junction temperature
• Low regulation voltage for low power dissipation
• Extensive fault detection and protection
□□ Drain short-to-ground detection
□□ Drain short-to-VIN, LED open, and thermal protection
The A6272 is a linear programmable current controller capable
of accurately regulating LED current in two strings with
external MOSFETs. The LED current can be switched between
high current and low current for stop/tail or DRL/position
applications. The two LED current levels from each output
are set by two sense resistors. Current reference accuracy for
each string current is better than ±4%.
PACKAGES:
A temperature monitor is included to reduce the LED drive
current if the chip temperature exceeds a thermal threshold.
An input voltage monitor is included to reduce LED current
if VIN rises enough to exceed the set level.
16-pin TSSOP with
exposed thermal pad
(suffix LP)
Driving LEDs with constant current ensures safe operation
with maximum possible light output. ICs can be connected in
parallel for larger lighting applications.
Drain short-to-ground detection is provided for both external
MOSFETs. A6272 also offers MOSFET drain short-to-VIN
and open-LED fault protection. The MODE pin controls the
action of the IC in the case of a fault.
The device is available in a 16-pin TSSOP (LP) and a 16-pin
wettable flank TQFN (ES), both with exposed pad for enhanced
thermal dissipation. Both packages are lead (Pb) free, with
100% matte-tin leadframe plating.
16-pin TQFN with
wettable flank and
exposed thermal pad
(suffix ES)
Not to scale
TAIL
S1
D1
STOP
S2
D2
R10
C1
R1
FULL
R9
VIN
VTHTH
D1
DR
D2
D4
D5
D6
D7
D8
R3
MODE
C2
To MCU
External PWM
A6272
VBIAS
GATE1
Q1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
NC
Typical Application Diagram
A6272-DS
D3
GND
R6
R7
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
SELECTION GUIDE
Part Number
Packing1
A6272KLPTR-T
4000 pieces per reel
A6272KESTR-J2
1500 pieces per reel
1 Contact Allegro™
2
Contact factory.
for additional packing options.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Characteristic
Symbol
VIN, D1, D2 Pins
Notes
–
Unit
V
FULL Pin
–
–1 to 42
V
GATE1, GATE2 Pins
–
–0.3 to 10
V
DR Pin
–
–0.3 to VVBIAS + 0.7
V
All Other Pins
–
–0.3 to 7
V
TJ(max)
150
ºC
Maximum Continuous Junction
Temperature
Through 10 kΩ resistor
Rating
–0.3 to 42
Transient Junction Temperature
TTJ
175
ºC
Storage Temperature Range
Tstg
–55 to 150
ºC
*With respect to GND.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Package Thermal Resistance
(Junction to Ambient)
RθJA
Package Thermal Resistance
(Junction to Pad)
RθJP
Package
LP
ES
Test Conditions*
On 4-layer PCB based on JEDEC standard
On 2-layer PCB with 3.8
in.2
copper area each side
On 4-layer PCB based on JEDEC standard
Value
Unit
34
ºC/W
43
ºC/W
47
ºC/W
2
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
PWM_IN
4
10 GATE2
FF 7
9
GND 8
D2
Package LP, 16-Pin TSSOP with Exposed Thermal Pad
Pinout Diagram
13 FULL
10 SENSE1
9
8
11 SENSE2
PWM_IN 6
11 GATE1
PAD
GATE2
3
7
NC
12 SENSE1
12 D1
D2
2
6
1
5
PAD
FF
VBIAS
MODE
13 GATE1
MODE 4
GND
14 D1
VBIAS 3
NC 5
16 DR
15 FULL
DR 2
14 VIN
16 VIN
VTHTH 1
15 VTHTH
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
SENSE2
Package ES, 16-Pin TQFN with Exposed Thermal Pad
Pinout Diagram
Terminal List Table
Name
Pin Number
Function
LP Package
ES Package
D1
14
12
Drain sensing for channel 1 faults: drain short-to-VIN, and LED open- or drain short-to-GND. If this
channel is not used, connect the D1 pin to GND through 10 kΩ resistor.
D2
9
7
Drain sensing for channel 2 faults: drain short-to-VIN, and LED open- or drain short-to-GND. If this
channel is not used, connect D2 pin to GND through 10 kΩ resistor.
DR
2
16
Connect to external DC voltage to adjust operating duty cycle in internal PWM mode only. In external
PWM mode, connect DR pin to VBIAS. When DR connected to VBIAS , PWM duty cycle is controlled by
PWM_IN.
FF
7
5
Fault flag output. Also used as fault input when MODE is connected to VBIAS.
FULL
15
13
Full (Stop) mode current-select 100% duty cycle operation. While FULL pin is high, the DR pin, PWM_IN
pin, and external PWM information is overridden.
GATE1
13
11
Gate driver for external N-channel MOSFET1.
GATE2
10
8
Gate driver for external N-channel MOSFET2.
GND
8
6
Ground. Connect separate signal and power GND planes to this pin.
MODE
4
2
MODE pin decides the fault mode. Refer to Table 1 for details.
PAD
–
–
Exposed thermal pad. Connect to external ground pad for better thermal performance.
PWM_IN
6
4
In internal PWM mode (DR pin voltage < 3.7 V), PWM frequency is set by a resistor to GND. If DR pin
connected to VBIAS , PWM frequency and duty cycle are determined by external signal.
NC
5
3
No connect pin. Connect it to GND or leave it open.
SENSE1
12
10
Current sense for channel 1. Connect sense resistor to set peak current level for channel 1.
SENSE2
11
9
Current sense for channel 2. Connect sense resistor to set peak current level for channel 2.
VBIAS
3
1
Internal bias supply. Connect to GND through a 0.1 µF capacitor.
VIN
16
14
Input supply.
VTHTH
1
15
Voltage at this pin sets the VIN derating threshold and the VIN threshold for open-LED detect fault.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
VBIAS
A6272
Bias
FULL
DR
OSC
PWM and Duty
Generator
Thermal
Derating
PWM_IN
VIN
VTHTH
+
VREF Ramp
Generator
Voltage
Derating
–
X5
Driver
– EN
+
SENSE1
+
Open LED
Disable
Driver
– EN
GATE2
PWM_IN
MODE
GATE1
SENSE2
Fault
Logic
Short to
VIN
FF
D1
Short to
GND,LED
Open
TSD
Fault
D2
Open LED
Disable
PAD
GND
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
ELECTRICAL CHARACTERISTICS: Valid at VIN = 7 to 19 V, indicates specifications across the full operating
temperature range with TA = TJ = –40ºC to 125ºC; other specifications are at TA = TJ = 25ºC, unless noted otherwise. Refer to Figure A1 in Application Information section for typical application circuit.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
5.3
−
40
V
Input Supply
Operating Input Voltage Range
VIN
VIN Operational Current
IINQ
FULL = VIHF
Startup Time
tON
VIN > 7 V, CVBIAS = 0.1 µF, VREF = 20 mV
●
●
−
−
10
mA
−
100
–
μs
192
200
208
mV
Current Regulation
Reference Voltage on SENSE1 and SENSE2
VREF
Maximum VIN Derating for Reference Voltage
VREF1
Matching Between SENSE1 and SENSE2
Reference1
VBIAS Pin Voltage
ErrVREF
VVBIAS
VVTHTH = VVBIAS (no VIN derating)
●
VVTHTH = VVBIAS (no VIN derating, TJ = 125°C)
194
200
206
mV
VVTHTH = 2 V, VIN ≥ 26 V
−
50
−
%
No VIN derating
−
−
2
%
5.15
5.3
5.45
V
VBIAS Undervoltage Release
VVBIASUV
IVBIAS = 0 to 3 mA
VIN rising
●
−
4.5
−
V
VBIAS Undervoltage Lockout Hysteresis
VVBIASHYS
IC disabled
−
0.2
−
V
Gate Driver
GATE1 and GATE2 High-Level Output
VGATEH
VIN = 12 V, PWM_IN = high, VREF = 150 mV,
DR = VBIAS
6
−
9
V
GATE1 and GATE2 Low-Level Output
VGATEL
PWM_IN = low
−
−
0.7
V
GATE Driver Dropout
VGATE_drop
VIN = 7 V, VREF = 150 mV, measured as
( VIN – VGATE )
−
−
1
V
Gate Pull-Up Current
IGPU
VSENSE = 180 mV, VGATE = 0 V, VIN = 7 V
−
−360
−
µA
IGPD
VSENSE = 220 mV, VGATE = 7 V, VIN = 7 V
Gate Pull-Down Current
External FET Gate Capacitance Range
CGISS
PWM Dimming Frequency
fPWM
For stable operation
External RFPWM = 30.9 kΩ, across PWM_IN
to GND
●
−
360
−
µA
250
−
2000
pF
180
200
220
Hz
DPWML
VDR driven by resistor divider from VBIAS,
VVBIAS / VDR = 18.7 V/V, fPWM = 200 Hz
7
7.7
8.4
%
DPWMH
VDR driven by resistor divider from VBIAS,
VVBIAS / VDR = 1.62 V/V, fPWM = 200 Hz
88
90
92
%
tSR
Rising or falling between 20% and 90%
levels, for internal reference ramp
43
70
97
µs
Rise Time to Fall Time Matching2
tSRM
Rising or falling between 20% and 90%
levels, for internal reference ramp
−
20
−
µs
Rise Time and Fall Time Mismatch Between
Two Strings3, 4
tSRMS
Rise and fall time mismatch between 20%
and 90% levels in two strings
−
–
2
%
PWM Duty
Cycle5
Current Slew Time
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
ELECTRICAL CHARACTERISTICS (continued): Valid at VIN = 7 to 19 V, indicates specifications across the full
operating temperature range with TA = TJ = –40ºC to 125ºC; other specifications are at TA = TJ = 25ºC, unless noted
otherwise. Refer to Figure A1 in Application Information section for typical application circuit.
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Logic Pins
MODE, PWM_IN Pins Input Low Voltage
VIL
Below VIL level, input voltage considered as
logic LOW
●
–
–
0.8
V
MODE, PWM_IN Pins Input High Voltage
VIH
Above VIH level, input voltage considered as
●
logic HIGH
2
–
–
V
FF Pins Output Low Voltage
VOL
IOL = 1 mA
●
–
–
0.4
V
FULL Pin Input Low Voltage
VILF
Below VILF level, input voltage on FULL pin
will disable FULL mode
●
0.85
–
1.15
V
FULL Pin Input High Voltage
VIHF
Above VIHF level, input voltage on FULL pin
will enable FULL mode
●
1.06
–
1.44
V
MODE Pin Pull-Down Current
Ilkg
−
10
−
µA
19.7
20.7
21.7
V
−
2.16
−
V
MODE connected to VBIAS
Protection
Input Voltage Required to Derate VREF by 10%
VINth(L)
VVTHTH = 2 V
VIN Derating Range (VINth(H) to VINth(L) )
VINthd
VREF drops from 180 to 120 mV
VIN-to-Drain Short Detect Voltage
VSCV
Measured as VIN – VDx, GATEx = high
●
0.5
0.8
1.1
V
Measured at Dx, GATEx = low, VIN >
VOLED_dis
●
0.19
0.24
0.29
V
Open-LED Fault Detect Voltage
Open-LED Disable Voltage
Thermal Monitor Activation Temperature4
VOLED
VOLED_dis
TJM
VVTHTH = 2 V
−
10
−
V
TJ with ISENSEx , VREF = 180 mV
−
TJF – 21
−
°C
Thermal Monitor Low-Current Temperature4
TJL
TJ with ISENSEx , VREF = 70 mV
–
TJF – 7
–
°C
Overtemperature Shutdown4
TJF
Temperature increasing
−
170
−
°C
Overtemperature Hysteresis4
TJhys
Recovery = TJF – TJhys
−
30
−
°C
1 Reference
matching is defined as: ( VSENSE1 – VSENSE2 ) / VSENSE(AVG) , where VSENSE(AVG) is the average of VSENSE1 and VSENSE2 .
2 Rise Time to Fall Time Matching is defined as the maximum difference between the rise time and the fall time of the same string.
3 Rise Time to Fall Time Mismatch Between Two Strings is defined as the maximum ratio of the difference between either the rise time or the fall time to the average of the
rise time or fall times between two strings.
4 Ensured by design and characterization.
5 Measured at 50% level of LED current.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
FUNCTIONAL DESCRIPTION
Protection Functions
DRAIN SHORT-TO-VIN (FIGURE 1A, FIGURE 2A, AND FIGURE 2B)
Various short-circuit faults handled by the A6272 are shown in
Figure 1.
This fault is detected when VIN – VD2 < 0.8 V and both GATEs
are asserted high and after completion of reference ramp. When
detected, the FF flag remains low, independent of GATE status. Once the fault detected, GATE2 is pulled high to detect the
removal of the fault and restore operation. As the GATE2 remains
continuously high, Q2 will dissipate significant power. Current
through Q2 is regulated to set level.
VIN
VIN
VIN
Short
Short
Short
(1A)
(1B)
(1C)
Figure 1: Short-Circuit Protection
For the fault description below, it is assumed (for a simpler explanation) that the fault is applied on the D2 string and the D1 string
is assumed to be a healthy string. The IC will respond similarly in
the case of a fault on D1.
When MODE = VBIAS, GATE2 remains high with 100% duty
cycle, regardless of FULL or TAIL mode. GATE1 and FF are
pulled low once the fault is detected but they are not latched. The
IC returns to normal operation (FF = HIGH and GATE1 active)
when the fault is removed. As the drain is shorted to VIN, current
through LED2 string is zero and GATE1 is pulled low to keep
LED1 current low. ICs connected in parallel turn off as FF is
pulled low.
When MODE = LOW, both gates switch at 100% duty cycle
(FULL mode) or desired PWM duty cycle (TAIL mode). Only
LED2 Current is Zero
SENSE2
C2
C3
SENSE1
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 2A: Drain Short-to-VIN Fault on D2 with MODE = HIGH and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
LED2 Current is Zero
SENSE2
C2
C3
SENSE1
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 2B: Drain Short-to-VIN Fault on D2 with MODE = LOW and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
the FF pin is pulled low continuously. The IC returns to normal
operation (FF = HIGH) when the fault is removed and GATE2 is
asserted high. In this mode, the IC will operate normally except
the FF pin is pulled low. The current in the LED1 string and the
current in parallel-connected ICs will be normal. The current in
the LED2 string is zero as D2 is shorted to VIN. The FF pin does
not affect the operation of parallel-connected ICs.
The symmetrical action applies if the fault is in string 1
(i.e., VIN – VD1 < 0.8 V).
As the LED2 string is open, current through the LED2 string
is zero and GATE1 is pulled low to keep LED1 current off.
Parallel-connected ICs turn off the LED string current as FF is
pulled low.
When MODE = LOW, both gates run at 100% duty cycle (FULL
mode) or desired PWM duty cycle (TAIL mode). Only the FF pin
is pulled low as long as VD2 < 0.24 V. The IC returns to normal
VIN
Open
OPEN LED (FIGURE 3, FIGURE 4A, AND FIGURE 4B)
This fault is detected when VIN > VOLED_dis and VD2 < 0.24 V.
When MODE = VBIAS, GATE2 remains on with 100% duty
cycle, regardless of FULL or TAIL mode. GATE1 and FF are
pulled low once the fault is detected, but they are not latched. The
IC returns to normal operation (FF = HIGH and GATEs active)
when the fault is removed.
Figure 3: Open-LED Protection
SENSE2
C2
C3
SENSE1
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 4A: Open-LED Fault on D2 with MODE = HIGH and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
SENSE2
C2
C3
SENSE1
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 4B: Open-LED Fault on D2 with MODE = LOW and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
operation (FF = HIGH) when the fault is removed. In this mode,
the IC will operate normally except the FF pin is pulled low.
LED1 and current in parallel-connected ICs will be normal. Current in the LED2 string is zero as the LED2 string is open. The FF
pin does not affect the operation of parallel-connected ICs.
The symmetrical action applies if the fault is in string 1 (i.e.,
VIN > VOLED_dis and VD1 < 0.24 V).
DRAIN SHORT-TO-GND (FIGURE 1B, FIGURE 5, AND
FIGURE 6)
This fault is detected when VIN > VOLED_dis and VDx < 0.24 V
(same as open-LED fault).
When MODE = VBIAS, GATE2 remains on with 100% duty
cycle, regardless of FULL or TAIL mode. GATE1 and FF are
pulled low once the fault is detected, but they are not latched. The
IC returns to normal operation (FF = HIGH and GATEs active)
when the fault is removed.
As the LED2 string is shorted to GND, a large current will flow
through the LED2 string. GATE1 will be pulled low to keep
LED1 current off. Parallel-connected ICs turn the LED string
current off as FF is pulled low.
When MODE = LOW, both gates run at 100% duty cycle (FULL
mode) or desired PWM duty cycle (TAIL mode). Only the FF pin
is pulled low as long as VD2 < 0.24 V. The IC returns to normal
operation (FF = HIGH) when the fault is removed. In this mode,
the IC will operate normally except the FF pin is pulled low. The
current in LED1 and the current in parallel-connected ICs will
be normal. As the LED2 string is shorted to GND, a large current
will flow through the LED2 string. The FF pin does not affect the
operation of parallel-connected ICs.
The symmetrical action applies if the fault is in string 1 (i.e.,
VIN > VOLED_dis and VD1 < 0.24 V).
SINGLE LED SHORT (FIGURE 1C)
In the case where a few LEDs are shorted, the IC continues to
work normally.
Uncontrolled LED2 Current
SENSE2
C2
SENSE1
C3
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 5: Drain Short-to-GND Fault on D2 with MODE = HIGH and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
Uncontrolled LED2 Current
SENSE2
C2
SENSE1
C3
D2
C4
Fault Applied
Fault Released
FF
M1
GATE2
M3
GATE1
M4
Figure 6: Drain Short-to-GND Fault on D2 with MODE = LOW and PWM Dimming
C4: 5 V/div; C2-C3: 200 mV/div; M1, M3 & M4: 5 V/div; Time: 5 ms/div.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
OPEN-LED DISABLE THRESHOLD
THERMAL DERATING AND PROTECTION SHUTDOWN
When input voltage, VIN , is below VOLED_dis, defined by voltage
on the VTHTH pin, drain short-to-GND and open-LED faults are
disabled. Select a VOLED_dis level higher than the LED forward
voltage. The IC will continue to operate normally in cases where
these faults exist. VOLED_dis value is given by:
This feature takes effect at higher temperatures, limiting power
dissipation in the external MOSFETs. At higher temperatures, the
reference voltage drops with increasing TJ as shown in Figure 9.
Thermal shutdown (TSD) completely disables the outputs under
extreme overtemperature ( >170°C) conditions, and FF goes low.
The IC restarts when the temperature drops by 30°C.
VOLED_dis = 5 × VVTHTH (1)
VREF (mV)
Voltage on VTHTH sets the input voltage derating threshold
(VINth(L)) as well as the open-LED disable level (VOLED_dis).
Select a VTHTH voltage suitable to avoid an open-LED fault due
to insufficient input voltage. This also sets VINth(L).
INPUT OVERVOLTAGE DERATING
This feature takes effect at higher VIN levels, limiting power
dissipation in the external MOSFETs. At higher input voltages,
output current drops, corresponding with increasing VIN. Output
current is controlled with peak current (see Figure 8). The VIN
threshold can be set with an external resistor divider from VBIAS
connected to VTHTH. The reference voltage drops to 90% at the
VINth(L) level and to 60% at VINth(H) level. Reference level drops
to 50% and stays at this level for higher input voltages. Voltage
on the VTHTH pin sets the VINth(L) level, and the VINth(H) level
is typically higher than VINth(L) by VINthd (2.16 V ). The range for
VINth(L) is from 16 to 36 V, determined by:
VINth(L) = 10 × VVTHTH + 0.7 V
40
VINth(L) = 20.7 V
VINthd = 2.16 V
VINth(H)
6
11
16
21
26
Figure 8: Output Current Foldback Based on VIN
Output current changed by DC current control (VINth(L) determined by
voltage on VTHTH pin). VREF drops to the 90% level when VIN exceeds
VINth(L), which is 20.7 V when VVTHTH = 2 V.
(2)
where VINth(L) is the supply voltage level where VREF drops to the
90% level, and VVTHTH is the voltage on VTHTH pin. Figure 7 shows
the relationship between voltage on the VTHTH pin and VINth(L).
3.6 V
VIN (V)
200
TSD
180
Ri
sin
g
VREF (mV)
200
180
160
140
120
100
80
60
40
20
0
Falling
70
35
VINth(L) (V)
50
30
0
125
25
140
149
TJM
163 166
TJL
170
TJF
TJ (ºC)
20
15
Figure 9: Output Current Foldback Based on Rising TJ
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VVTHTH (V)
Output current changed by DC current control; when temperature
exceeds 170°C (typ), the gates turn off due to TSD function, and
turns on again at 140°C (30°C (typ) hysteresis).
Figure 7: VTHTH Voltage versus VIN Derating Threshold
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10
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
Internal Dimming Frequency and Duty Cycle
LED CURRENT SETTING
Dimming frequency can be set using the PWM_IN pin. This
PWM frequency can be set in the range from 200 Hz to 1 kHz,
either by using an external resistor, or by using an external clock
signal, on the PWM_IN pin. The equation for frequency setting
with the PWM_IN pin resistor is as follows:
LED peak current (100%) level can be set independently for each
channel by selecting a proper resistor value from the SENSEx pin
to GND, as follows:
where LED peak current is in mA and RSENSE is in Ω .
fPWM = 5400 / RFPWM + 25
(3)
LED Peak Current = 200 / RSENSE (5)
When frequency is set through an external resistor (for internal
PWM), the voltage on the DR pin determines the operating duty
cycle. For better accuracy, derive this voltage from VBIAS using a
voltage divider. The PWM duty cycle depends on ratio of the DR
and VBIAS pin voltages. The IC works with 100% duty cycle in
STOP mode ( FULL = HIGH ). In TAIL mode, the duty cycle can
be programmed by controlling the analog voltage on the DR pin.
The duty cycle can be changed from 5% to 90% (see Figure 10),
as:
PWM (%) = [146 × (VDR / VVBIAS)] – 0.1
(4)
where VDR and VVBIAS are in volts.
If the DR pin is connected to VBIAS , an external clock pulse on
the PWM_IN pin controls dimming frequency and duty cycle.
Duty Cycle, D (%)
where fPWM is in Hz and RFPWM is in kΩ. For example, with a
30.9 kΩ resistor, fPWM = 200 Hz.
100
80
60
40
20
0
0
1.08
2.16
VDR (V)
3.24
Figure 10: Relationship of External Voltage Input on DR
Pin and Dimming Duty Cycle
VDR can be varied from 0 to 3.6 V.
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11
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
Table 1: Fault Operation and Derating
FF
Drain
Shorted
to VIN
Low
Operation
MODE = VBIAS
MODE = LOW
Detected when VIN – VDx < 0.8 V. The faulty string remains on
with 100% duty cycle regardless of FULL or TAIL mode.
Other string and FF pull low once fault is detected but is not
latched. Faulty MOSFET drops full VIN voltage. IC recovers to
normal operation when fault removed.
Detected when VIN – VDx < 0.8 V. IC operates normally except
FF pin pulled low. Faulty MOSFET drops full VIN voltage
when enabled.
FF pin goes high when fault is removed.
Fault is detected when both GATEs are asserted high and after completion of reference ramp. When detected, the fault remains active
independent of GATE status.
Low
Detected when VIN > VOLED_dis and VDx < 0.24 V. The faulty
string remains on with 100% duty cycle regardless of FULL or
TAIL mode. Other GATEx is turned off. IC recovers to normal
operation when fault is removed.
Detected when VIN > VOLED_dis and VDx < 0.24 V.
IC operates normally except FF pin is pulled low.
FF pin goes high when fault is removed.
Drain
Shorted
to GND
Low
Detected when VIN > VOLED_dis and VDx < 0.24 V. The faulty
string remains on with 100% duty cycle regardless of FULL or
TAIL mode. Other GATEx is turned off. IC recovers to normal
operation when fault is removed. LEDs in faulty string may be
damaged due to excessive LED current.
Detected when VIN > VOLED_dis and VDx < 0.24 V.
IC operates normally except FF pin pulled low.
LEDs in faulty string may be damaged due to excessive LED
current.
FF pin goes high when fault is removed.
Thermal
Derating
Normal
LED current derates based on junction temperature.
Same operation as MODE = VBIAS.
VIN
Derating
Normal
LED current derates based on supply voltage and VTHTH
setting.
Same operation as MODE = VBIAS.
TSD
Low
LEDs turn off when TJ exceeds 170ºC. Auto-recover when TJ
drops below 140ºC.
LEDs turn off when TJ exceeds 170ºC. Auto-recover when TJ
drops below 140ºC.
Open
LED
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12
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
APPLICATION INFORMATION
Figure 11: VIN vs. VREF (VVTHTH = 3.6 V)
Figure 12: Temperature vs. VREF
Figure 13: Temperature vs. fPWM (RFPWM = 30.9 kΩ)
Figure 14: Temperature vs. Duty Cycle
(VVBIAS/VDR = 28.6 V/V)
7.5
7.0
VGATE (V)
6.5
6.0
5.5
5.0
4.5
4.0
5
10
15
20
25
VIN (V)
30
35
40
Figure 15: GATE Voltage vs. VIN
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A6272
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
Figure 16: Rise Time and Fall Time During PWM Dimming.
IOUT (Total LED Current) (200 mA/div), PWM_IN and VGATE (2 V/div), Time (20 µs/div)
Figure 17: Reference Matching During PWM Dimming
VREF1, VREF2 (100 mV/div), IOUT (Total LED Current)(200 mA/div), VREF1-VREF2 (2 mV/div), Time (100 µs/div).
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14
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
Modes of Operation
A. SINGLE IC, INTERNAL PWM MODE
The IC can operate in one of the following modes:
In TAIL mode, the IC generates its PWM frequency based on a
resistor connected from the PWM_IN pin to GND, and the duty
cycle is controlled by voltage at the DR pin (which can be generated by a resistor divider, or driven by an external DC signal). In
FULL (STOP) mode, the duty cycle is always 100%. Overtemperature or input overvoltage conditions derate LED current by
controlling peak current in both STOP and TAIL modes. Voltage
on the VTHTH pin controls the input voltage derating threshold.
A. Single IC, internal PWM mode
B. Single IC, external PWM mode
C. Multiple ICs, in parallel mode
These are each described in the remainder of this section.
TAIL
S1
D1
STOP
S2
D2
C1
R1
R10
FULL
R8
VIN
VTHTH
D1
DR
D2
R2
D4
D5
D6
D7
D8
MODE
R3
R9
D3
A6272
VBIAS
C2
Q1
GATE1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
To MCU
R6
R7
R5
NC
GND
Typical Application Circuit A1: Single IC Operation with Internal Reference to DR and MODE Pulled High.
TAIL
S1
D1
STOP
S2
D2
C1
R1
R10
FULL
VIN
VTHTH
R2
R9
R3
MODE
VBIAS
C2
D4
D5
D6
D7
D8
D1
DR
R8
D3
D2
A6272
GATE1
Q1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
To MCU
R6
R7
R5
NC
GND
Typical Application Circuit A2: Single IC Operation with Internal Reference to DR and MODE Shorted to GND.
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Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
TAIL
S1
D1
STOP
S2
D2
C1
R1
R10
FULL
External DC
Voltage
R2
R9
VIN
VTHTH
D1
DR
D2
D3
D4
D5
D6
D7
D8
R3
D9
MODE
A6272
VBIAS
C2
Q1
GATE1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
To MCU
R6
R7
R5
NC
GND
Typical Application Circuit A3a: Single IC Operation with External Analog Reference to DR and MODE Pulled High
External DC voltage can be applied on DR pin to control PWM dimming. Voltage on DR pin should be 0 < VDR < 3.6 V for duty cycle control.
Voltage on DR pin must be lower than VVBIAS under all conditions. Optional R2-D9 clamp used to ensure DR pin voltage limited to VVBIAS.
TAIL
S1
D1
STOP
S2
D2
C1
R1
R10
FULL
External DC
Voltage
DAC
or
uC
R9
VIN
VTHTH
D1
DR
D2
D3
D4
D5
D6
D7
D8
R3
MODE
REF
VBIAS
C2
A6272
GATE1
Q1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
To MCU
R6
R7
R5
NC
GND
Typical Application Circuit A3b: Using DAC to Microcontroller to Control PWM Duty Cycle
The PWM duty cycle is ratiometric to VVBIAS. Using VBIAS as reference to DAC improves accuracy with external DC voltage. DR pin voltage
should be lower than VVBIAS under all conditions. Apply voltage on DR pin after VBIAS powers up.
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16
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
B. SINGLE IC, EXTERNAL PWM MODE
When the DR pin is connected to VBIAS, in TAIL mode, the IC
disables internal PWM generation and replicates the frequency
and duty cycle of the signal at the PWM_IN pin onto GATEx. In
TAIL
S1
D1
STOP
S2
D2
R10
FULL mode, the duty cycle is always 100%. Overtemperature
or input overvoltage conditions derate LED current by controlling peak current in both STOP and TAIL modes. Voltage on the
VTHTH pin controls the input voltage derating threshold.
C1
R1
FULL
R8
VIN
VTHTH
D1
DR
D2
D3
D4
D5
D6
D7
D8
R2
MODE
C2
VBIAS
A6272
GATE1
Q1
Q2
GATE2
R4
FF
SENSE1
PWM_IN
SENSE2
To MCU
External PWM
NC
R6
R7
GND
Typical Application Circuit B1: Single IC Operation with External PWM to PWM_IN Pin and MODE Pulled High.
For the above configuration, DR pin voltage is always connected to the VBIAS pin.
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17
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
C. MULTIPLE ICS, IN PARALLEL MODE
In STOP mode, duty cycle is always 100%.
All the ICs are configured for external PWM mode. PWM input
from the MCU controls frequency and duty cycle in TAIL mode.
Each IC derates LED current independently, based on VIN pin
voltage and junction temperature of the respective IC.
TAIL
S1
D1
STOP
S2
D2
C1
R1
R10
FULL
VIN
VTHTH
D1
DR
D2
D3
D4
D5
D6
D7
D8
R3
R8
MODE
C2
A6272
VBIAS
Q1
GATE1
Q2
GATE2
R4
External
PWM
FF
SENSE1
PWM_IN
SENSE2
NC
R6
R7
GND
To MCU
C3
FULL
VTHTH
D1
DR
D2
MODE
C4
VIN
VBIAS
A6272
GATE1
D10
D11
D12
D13
D14
Q3
Q4
GATE2
FF
SENSE1
PWM_IN
SENSE2
NC
D9
R12
R13
GND
Typical Application Circuit C1: Parallel Operation with External PWM and MODE Pulled High
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18
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
TAIL
S1
D1
STOP
S2
D2
C1
D3
D5
R1
R10
FULL
R8
R2
R9
R3
VTHTH
D1
DR
D2
MODE
A6272
VBIAS
C2
R4
To MCU
R5
D7
VIN
R11
10 kΩ
Q1
GATE1
GATE2
FF
SENSE1
PWM_IN
SENSE2
NC
R6
GND
Typical Application Circuit D1: Single LED String Driven by a MOSFET (MODE = HIGH).
Connect unused Dx pin to GND through 10 kΩ resistor.
Keep unused GATEx and SENSEx pins open.
TAIL
S1
D1
STOP
S2
D2
C1
D5
R1
R10
FULL
R8
R2
R9
R3
VTHTH
D1
DR
D2
A6272
VBIAS
R4
To MCU
R5
GATE1
R11
10 kΩ
Q1
Q2
GATE2
FF
SENSE1
PWM_IN
SENSE2
NC
D7
VIN
MODE
C2
D3
R6
R7
GND
Typical Application Circuit E1: Single LED String Driven by Two MOSFETs for Higher Current Applications
(MODE = HIGH).
Drains of Q1 and Q2 can be connected together for driving single high-current LED string. To avoid interaction of fault sensing on D1 and D2,
connect one of Dx pin to GND through 10 kΩ resistor.
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19
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.65
0.45
8º
0º
5.00±0.10
16
16
1.70
0.20
0.09
B
3 NOM
4.40±0.10
3.00
6.40±0.20
6.10
A
0.60 ±0.15
1
1.00 REF
2
3 NOM
C
SEATING
PLANE
0.30
0.19
0.65 BSC
0.15
0.00
3.00
GAUGE PLANE
1.20 MAX
C
2
SEATING PLANE
C
16X
0.10
1
0.25 BSC
Branded Face
PCB Layout Reference View
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface)
C
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Figure 18: Package LP, 16-Pin TSSOP with Exposed Thermal Pad
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20
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
0.30
3.00 ±0.05
16
1
2
0.90
0.0-0.05
A
0.50
16
1
3.00 ±0.05
Branded Face
16X
DETAIL A
D
0.10 REF
0.22±0.05
0.40 ±0.10
B
2
1.70 ±0.10
3.10
C
PCB Layout Reference View
0.40 ±0.10
0.10 REF
0.203 REF
0.05 REF
Detail A
1
0.05 REF
C
0.75 ±0.05
0.50 BSC
3.10
1.70
SEATING
PLANE
0.05 C
0.20 REF
1.70
16
1.70 ±0.10
0.14 REF
For reference only
(reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Figure 19: Package ES, 16-Pin TQFN with Exposed Thermal Pad and Wettable Flank
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21
Automotive Two-Channel Linear LED Controller
with Internal PWM Dimming
A6272
Revision History
Revision
Revision Date
–
June 1, 2016
Description of Revision
Initial release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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22
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