A6850KLTR-T

A6850 Dual Channel Switch Interface IC Not for New Design These parts are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Date of status change: October 1, 2022 Recommended Substitutions: For existing customer transition, and for new customers or new applications, contact factory. NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. A6850 Dual Channel Switch Interface IC FEATURES AND BENEFITS ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ DESCRIPTION 4.75 to 26.5 V operation Low VIN-to-VOUT voltage drop 1/ current sense feedback 10 Survive short-to-battery and short-to-ground faults Survive 40 V load dump >4 kV ESD rating on the output pins, >2 kV on all other pins Output current limiting Low operating and Sleep mode currents Integrates with Allegro A114x and A118x Hall effect two-wire sensor ICs The Allegro™ A6850 is designed to interface between a microprocessor and a pair of 2-wire Hall effect sensor ICs. The A6850 uses protected high-side low resistance DMOS MOSFETs to switch the supply voltage to the two Hall effect devices. Each switch can be controlled independently via individual ENABLE pins and both switches are protected with current-limiting circuitry. The output switches are rated to operate to 26.5 V and will source at least 25 mA per channel before current limiting. Typical two-wire Hall device applications require the user to measure the supply current to determine whether the Hall IC is switched on (magnetic field present) or switched off (no magnetic field present). This is usually accomplished by using an external series shunt resistor and protection circuits for the microprocessor. In many systems, the sensed voltage is used as the input to a microprocessor analog-to-digital (A-to-D) input. This provides the system with an indication of the status of the two-wire switch as well as provides the capability for diagnostic information if there is an open or shorted Hall device. PACKAGE: 8-pin SOIC (suffix L) Approximate Footprint Continued on the next page… Functional Block Diagram VIN ENABLE1 Control Block ENABLE2 SENSE1 × IOUTPUT1 1/ 10 Fault Detection OUTPUT1 Fault Detection OUTPUT2 SENSE2 × IOUTPUT2 1/ 10 GROUND 6850-DS, Rev. 8 MCO-0000882 October 1, 2022 A6850 Dual Channel Switch Interface IC Description (continued) The A6850 eliminates the need for the external series shunt resistor in Hall device applications by incorporating an integrated current mirror which reports the Hall IC supply current as a 1/10 value on the SENSE1 or SENSE2 output pin. A low current Sleep mode is Selection Guide Part Number available ( 7 V VIN < 7 V – 4.0 7.5 µs – – – – 35 –20 Ω µA –100 – 100 µA – 0 0 2.0 – 125 – – –25.0 – – – – – – 40 8.0 –35.0 10 6 VIN – 1 – 0.4 375 100 20 –45.0 µA V V V V mV µA µA mA – 500 750 µA 27.0 – – – – 2.0 175 15 33.0 – – – V V °C °C Enable Delay Time2 tENdlyLH Disable Delay Time2 tENdlyHL OUTPUTx Source Resistance OUTPUTx Leakage Current SENSEx Output Current Offset3 SENSEx Voltage4 ENABLEx Input Voltage Range ENABLEx Input Hysteresis ENABLEx Current OUTPUT Current Limit OUTPUT Reverse Bias Current Overvoltage Protection Threshold Overvoltage Protection Hysteresis Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1Delay 2R ISENSE(ofs) ISENSEQ VSENSEx VENABLEH VENABLEL VENABLEhys IENABLE IOUTPUTM IOUTPUT(rvrs) VOVP VOVPhys TTSD TTSDhys At least one output enabled ENABLEx = 2.0 V ENABLEx = 0.4 V Reverse bias blocking: VIN = 4.75 V, VOUTPUT = 26.5 V Rising VIN Temperature Increasing from end of Sleep mode to outputs enabled. SENSEx 3For RDS(on) IOUTPUTQ = 1.5 kΩ. input and output current specifications, negative current is defined as coming out of (sourced from) the specified device pin. 4User to ensure that V SENSEx remains within the specified range. If VSENSEx exceeds the maximum value, the device is self-protected by an internal clamp, but not all parameters perform as specified. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A6850 Dual Channel Switch Interface IC Characteristic Performance 0 mA OUTPUTx current 10% 90% – 10 mA trLH tfHL 90% SENSEx voltage 10% 0V Figure 1. Signal Channel Timing, ENABLE1 = ENABLE1 = High, RSENSE = 1.5 kΩ 50% ENABLEx Voltage 0V 0 mA OUTPUTx Current tENdlyHL tENdlyLH 50% SENSEx Voltage 0V Figure 2. Enable Delays, one ENABLE input held high to prevent the IC going into Sleep mode Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A6850 Dual Channel Switch Interface IC Functional Description SENSE Pin Outputs The A6850 divides the OUTPUTx pin current by 10 and mirrors it onto the corresponding SENSEx pin. Putting sense resistors, RSENSE , from these pins to ground will create a voltage that can be read by an ADC (analog-to-digital converter). The value of RSENSE should be chosen so that the voltage drop across the sense resistor (VRSENSE) does not exceed the maximum voltage rating of the ADC. For further protection of the ADC, an external clamping circuit, such as a Zener diode, can be used to clamp any transient current spikes that may occur on the output that would be translated onto the SENSE pins. Overvoltage Protection The A6850 has built-in overvoltage protection against a load dump on the supply bus. In the case of a load dump, or when VIN is connected to the battery supply bus and VIN rises above the overvoltage threshold, VOVP , the A6850 will shut off the outputs. The sense current is one tenth of the output current, plus an offset current. This offset current is consistent across the whole range of the output current. The sense current can be calculated by the following formula: When enabling an output, the part must first come out of sleep mode. Consequently, the wake-up time amounts to a propagation delay before the outputs turn on. Also, the ENABLE pins do not switch with hysteresis until the regulators stabilize. ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) . (1) The sense resistor must also be chosen to meet the voltage limits on the sense pin (see Electrical Characteristics table). Sleep Mode Low-leakage or sleep modes are required in automotive applications to minimize battery drain when the vehicle is parked. The A6850 enters sleep mode when both ENABLE pins are low. In sleep mode, the internal regulators and all other internal circuitry are disabled. After the internal regulators stabilize, internal circuitry is enabled and the outputs turn on, as shown in figure 3. As long as one ENABLE pin is held high, the A6850 operates with hysteresis. Output Current Limit The A6850 limits the output current to a maximum current of IOUTPUTM. The output current will remain at the current limit until the output load is reduced or the A6850 goes into thermal shutdown. The high output current limit allows the bypass capacitor, CBYP , on the Hall sensor IC to charge up quickly. This allows a high slew rate on the VCC pin of the Hall sensor IC, ensuring that the sensor IC Power-On State will be correct. See the Applications Information section for schematic diagrams and power calculations. Output Faults The A6850 withstands short-to-ground or short-to-battery of the OUTPUTx pins. In the case of short-to-ground, current is held to the current limit (IOUTPUTM). If VOUTPUTx > (VIN + 0.7 V) during a short-to-battery event, the A6850 monitors VOUTPUTx and disables the outputs. Because the protection circuitry requires a finite amount of time to disable the outputs, a bypass capacitor of 1 µF is necessary on VIN. Although OUTPUTx sinks current into the A6850 in this state, the reverse current is shunted to ground and does not appear on the VIN pin. ENABLE VENABLEL > tON RegOk VREG OUTPUT Figure 3. Activation Timing Diagram. Exiting Sleep mode via ENABLE signal to output waveform. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A6850 Dual Channel Switch Interface IC Signal and Enable delays When ENABLEx = 1, current signals applied to the OUTPUTx pins will appear scaled and delayed on the SENSEx pins. The transfer characteristic can be considered that of a low pass filter. The response time definitions are given in figures 1 and 2, in the Characteristic Performance section. The rise time response is dependent on the effective capacitance loading on the SENSEx pin. The RC time constant, τ, can be estimated using: τ = RSENSEx (90 + CSENSE) (2) where RSENSEx is in kΩ and CSENSE is in pF; the result will be in ns. The 10% to 90% rise time, trLH , may be estimated from: trLH = 2.2 × τ (3) When a capacitor is added in parallel with the signal source connected to an OUTPUTx pin, additional allowance must be made for settling time caused by the inrush current needed to recharge a partially, or fully discharged, capacitor which has decayed during the disabled period. During this time the current required may reach IOUTPUTM, the current limit value for the OUTPUTx pins. The effects will be most noticeable on a SENSEx pin and will usually cause a signal overshoot as shown as tENsettle in figure 4. Thermal Shutdown (TSD) The A6850 protects itself from excessive heat damage by disabling both outputs when the junction temperature, TJ , rises above the TSD threshold (TTSD). The outputs will remain off until the junction temperature falls below the TTSD level minus the TSD hysteresis, TTSDhys. The small signal low pass filter bandwidth based on a single pole response may be estimated using: BW = 350 / trLH (4) The result is in MHz when trLH is in ns. If the values of trLH and tfHL are significantly different then a better estimate may be given by: BW = 700 / (trLH + tfHL ) (5) The result is in MHz when trLH and tfHL are in ns. Each signal channel may be enabled or disabled individually via their respective ENABLEx pins, as shown in table 1. ENABLEx 50% 0 mA OUTPUTx tENdlyLH Table 1. Enable/Disable Signal Channel Truth Table EN1 EN2 IOU1 IOU2 SEN1 SEN2 L* L* 0 0 0 0 H L I1 0 I1 / 10 0 L H 0 I2 0 I2 / 10 H H I1 I2 I1 / 10 I2 / 10 *Sleep mode SENSEx tENsettle 0V Figure 4. Overshoot resulting from additional capacitance. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A6850 Dual Channel Switch Interface IC TJ can be estimated by calculating the power dissipation (PD) of the A6850. To calculate PD: Example: Calculating the power dissipation and temperature rise, given: TA = 25°C , PD = VIN IINQ (6) – VOUTPUT1 IOUTPUT1 – VOUTPUT2 IOUTPUT2 IINQ = 5 mA , – VSENSE1 ISENSE1 – VSENSE2 ISENSE2 . PD = VIN IINQ VIN = 5 V , (7) IOUTPUT1 = IOUTPUT2 = 15 mA , ISENSEx = IOUTPUTx /10 = 1.5 mA , + (VIN – VOUTPUT1 ) IOUTPUT1 RSENSE1 = RSENSE2 = 2 kΩ , and + (VIN – VOUTPUT2 ) IOUTPUT2 + (VIN – VSENSE1) ISENSE1 + (VIN – VSENSE2) ISENSE2 . Then: PD = 5 V × 5 mA When IOUTPUTx × RDS(on) < approximately 700 mV, then: + 0.525 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5 mA (VIN – VOUTPUTx ) = IOUTPUTx × RDS(on) . + 0.525 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5 mA When IOUTPUTx × RDS(on) > approximately 700 mV, then: IOUTPUTx = IOUTPUT (max) , and VOUTPUTx is set by the loading on the OUTPUTx pin. The temperature rise of the A6850 can be calculated by multiplying PD and the thermal resistance from junction to ambient, RθJA . The formula for temperature rise, ∆T, is:  ∆T = PD × RθJA . IOUTPUTx × RDS(on) = 15 × 35 = 525 mV = VIN – VOUTPUTx . (8) The RθJA for an 8-pin SOIC (Allegro L package) on a one-layer board with minimum copper area is 140 °C/W. (More thermal data is available on the Allegro MicroSystems website.) = 46.75 mW . Substituting in equation 8: ∆T = 46.75 mW × 140 °C/W = 6.5°C . Substituting in equation 9: TJ = 25°C + 6.5°C = 31.5°C . The total junction temperature can be calculated by: TJ = TA + ∆T , (9) where TA is the ambient air temperature. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A6850 Dual Channel Switch Interface IC Applications Information Two-Wire Hall IC Interfacing When voltage is applied to two-wire Hall effect ICs, current flows within one of two narrow ranges. Any current level not within these ranges indicates a fault condition. The following table describes some of the possible output conditions that can be monitored through the SENSE pins. Figure 5 is a typical application using the A6850 with dual Hall effect ICs. Signal and Fault Table Output Pin Current (mA) Sense Pin Current (mA) Sense Pin Voltage, Rsense= 1.5 kΩ (V) OUTPUT Pin Short-to-Ground 25 to 45 2.5 to 4.5 3.75 to 6.75 Logic High from Hall IC 12 to 17 1.2 to 1.7 1.8 to 2.55 0.0 0.0 0 2 to 6.9 0.2 to 0.69 0.3 to 1.04 Thermal Shutdown 0.0 0.0 0 OUTPUT Pin Open 0.0 0.0 0 Condition Short-to-Battery Logic Low from Hall *This IC* current range includes all A114x and A118x devices. VCC or VBAT VCC VIN Digital Output Digital Output 1 µF 1 ENABLE1 3 ENABLE2 5 VIN OUTPUT1 8 CBYP 0.01 µF A6850 Controller ADC ADC 2 SENSE1 4 SENSE2 Wiring Harness OUTPUT2 6 A114x or A118x GROUND RSENSE1 1.5 kΩ RSENSE2 1.5 kΩ CBYP 0.01 µF 7 A114x or A118x Figure 5. Typical Application with 2-Wire Hall Effect ICs Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A6850 Dual Channel Switch Interface IC Mechanical Switch Interfacing A series resistor included in the circuit reduces power dis- The A6850 can be used as an interface between mechanical switches, set in a switch-to-ground configuration, and a low voltage microprocessor. A series resistor must be placed in the circuit to limit current when the mechanical switch is closed, in order to prevent excessive power dissipation in the A6850. sipation in the OUTPUTx section of the A6850. For example, to calculate the power dissipation in the A6850 driving two mechanical switches with 1 kΩ series resistors, with VIN = 12 V, assume that the current limit for each of the outputs is set to the maximum value, IOUTPUTM (max) = 45 mA. When the mechanical switch is closed without a series resistor, the A6850 will be at the current limit. The full 12 V of the power supply will drop across the A6850 at 45mA The power dissipation for one mechanical switch closed would be: PD1 = VDrop1 × IOUTPUT1 = 12 V × 45 mA = 540 mW (6) VCC or VBAT VCC VIN Digital Output Digital Output The current is then limited to: IOUTPUT1 = VIN / (35 + RSERIES) = 12 V / 1035 Ω = 11.59 mA (7) VDrop1 = 35 × IOUTPUT1 (8) = 405.7 mV The power dissipation in the A6850 from this switch is much lower: PD1 = VDrop1 × IOUTPUT1 = 0.4057 V × 11.3 mA = 4.58 mW 1 µF 1 ENABLE1 3 ENABLE2 5 VIN OUTPUT1 8 (9) Wiring Harness RSERIES A6850 Controller Input1 Input2 2 SENSE1 4 SENSE2 OUTPUT2 GROUND RSENSE1 RSENSE2 6 RSERIES 7 Figure 6. Typical Application with Mechanical Switches Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A6850 Dual Channel Switch Interface IC Ganging SENSE1 and SENSE2 and ENABLE2 may be activated simultaneously, with the In certain applications both outputs may be read with a single ADC channel. The OUTPUTx loads are enabled by alternatively activating ENABLEx. In fact, both ENABLE1 SENSE1 and SENSE2 currents added together. For valid measurements the load resistor need only be selected so that VSENSEx remain within specification. Vin Digital Output Digital Output 1 µF Enable 1 Enable 2 Controller Vin Output 1 LOAD1 Vcc or Vbat Vcc A6850 Sense 1 Sense 2 ADC Output 2 LOAD2 R Figure 7. Outline of ganged configuration VENABLE1 VENABLE2 IOUTPUT1 ILOAD1 ILOAD2 IOUTPUT2 VADC ILOAD1 R×ILOAD1/10 ILOAD2 R×ILOAD2/10 R× (ILOAD1/10 + ILOAD2/10) Figure 8. Functional response in ganged configuration Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A6850 Dual Channel Switch Interface IC Protection from EMI Transients generated by electromagnetic interference (EMI) can disturb operation of the A6850 or add unwanted noise to the signals being processed. The scheme shown in figure 9 illustrates possible supply decoupling and signal filtering options. The selection of protection and filtering component values will depend on the details of the final application. The A6850 must be protected with a suitable bypass capacitor to prevent transients entering VIN. The capacitor should be as close to the VIN and GND pins as feasible. A pi-filter placed between the OUTPUTx pins and the sensor IC has been shown to demonstrate excellent performance in normal automotive Bulk Cable Injection (BCI) testing. However, component selection and layout as well as cable specification and placement must be tailored to the individual application. EMC results should be validated. 1 µF VIN OUTPUT1 ENABLE1 1000 pF ENABLE2 VBAT A6850 SENSE1 SENSE2 100 Ω 1 0.1 µF Hall Device 2 OUTPUT2 GROUND Figure 9. Decoupling and filtering suggestions Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A6850 Dual Channel Switch Interface IC L Package, 8-Pin SOIC For Reference Only; not for tooling use (reference Allegro DWG-0000385, Rev. 2 or JEDEC MS-012AA) Dimensions in millimeters – Not to scale Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.90 BSC 8° 0° 8 0.65 1.27 8 0.21 ±0.04 3.90 BSC Pin 1 Mark Area 1 6.00 BSC 1.75 2 0.84 +0.43 –0.44 Branded Face C 8× 0.10 C 0.41 ±0.10 1.27 BSC 5.60 SEATING PLANE +0.13 1.62 –0.27 0.15 +0.10 –0.05 0.25 BSC SEATING PLANE GAUGE PLANE 1 2 PCB Layout Reference View Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A6850 Dual Channel Switch Interface IC Revision Table Number Date 6 May 29, 2020 Description Minor editorial updates 7 June 4, 2021 Updated Package Outline Drawing 8 October 1, 2022 Changed product status: Not for new design Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13