APS12205, APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
FEATURES AND BENEFITS
DESCRIPTION
The APS12205, APS12215, and APS12235 Hall-effect sensor
ICs are extremely temperature-stable and stress-resistant
devices especially suited for operation over extended junction
temperature ranges up to 175°C. Superior high-temperature
performance is made possible through dynamic offset
cancellation, which reduces the residual offset voltage normally
caused by device overmolding, temperature dependencies, and
thermal stress.
• Optimized for applications with regulated power rails
□ Operation from 2.8 to 5.5 V
• AEC-Q100 automotive qualified
• Operation up to 175°C junction temperature
• Dynamic offset cancellation
□ Resistant to physical stress
□ Superior temperature stability
• Symmetrical latch switchpoints
• Output short-circuit protection
• Solid-state reliability
• Industry-standard packages and pinouts
The single silicon chip includes: a Hall plate, small signal
amplifier, chopper stabilization, Schmitt trigger, and a shortcircuit-protected open-drain output. A south pole of sufficient
strength turns the output on; a north pole of sufficient strength
is necessary to turn the output off. For applications requiring
operation from greater than 5.5 V or operation directly from
a battery, refer to the A1220, A1221, or A1223.
PACKAGES:
Not to scale
Two package styles provide a choice of through-hole or surface
mounting. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultramini SIP
for through-hole mounting. Both packages are lead (Pb) free,
with 100% matte-tin-plated leadframes.
3-pin SOT23W
(suffix LH)
3-pin SIP
(suffix UA)
Functional Block Diagram
VCC
Amp
Sample and Hold
Dynamic Offset
Cancellation
To All Subcircuits
VOUT
Low-Pass
Filter
Control
Current Limit
GND
APS12205-15-35-DS, Rev. 5
MCO-0000479
September 10, 2021
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
SELECTION GUIDE
Part Number
Packing [1]
Mounting
Branding
APS12205ELHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A04
APS12205ELHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A04
APS12205LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A04
APS12205LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A04
APS12205LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A18
APS12215LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A01
APS12215LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A01
APS12215LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A03
APS12235LLHALX
13-in. reel, 10000 pieces/reel
3-pin SOT23W surface mount
A35
APS12235LLHALT [2]
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A35
APS12235LUAA
Bulk, 500 pieces/bag
3-pin SIP through hole
A36
Ambient, TA
BRP (Min)
BOP (Max)
–40 G
40 G
–40°C to 150°C
–90 G
90 G
–40°C to 150°C
–180 G
180 G
–40°C to 85°C
–40°C to 150°C
[1] Contact Allegro
[2] Available
for additional packing options.
through authorized Allegro distributors only.
RoHS
COMPLIANT
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
Units
Forward Supply Voltage
VCC
6
V
Reverse Supply Voltage
VRCC
–0.3
V
Output Off Voltage
VOUT
Output Current
IOUT
Maximum Junction Temperature
Storage Temperature
TJ(max)
Tstg
Through short-circuit current limiting device.
For 1000 hours.
6
V
60
mA
165
°C
175
°C
–65 to 170
°C
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
2
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
GND
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
2
3
VOUT
VOUT
1
GND
2
VCC
1
VCC
3
Package UA
Package LH
Terminal List
Number
Name
Description
Package
LH
Package
UA
Connects power supply to chip
1
1
VOUT
Output from circuit
2
3
GND
Ground
3
2
VCC
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
3
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature range, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.[1]
Max.
Unit [2]
2.8
–
5.5
V
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage
Supply Current
Output Leakage Current
Output Saturation Voltage
VCC
Operating, TJ < 175°C
ICC
VCC = 5.5 V
–
2
3
mA
IOUTOFF
VOUT = 5.5 V, B < BRP
–
–
10
µA
VOUT(SAT)
IOUT = 5 mA, B > BOP
–
50
500
mV
Output Current
IOUT
Recommended value used during characterization
–
5
–
mA
Output Short-Circuit Current Limit
IOM
B > BOP
30
–
60
mA
Power-On Time [3]
tON
VCC ≥ 2.8 V, B < BRP(min) – 10 G,
B > BOP(max) + 10 G
–
–
25
µs
Power-On State, Output [3]
POS
Chopping Frequency
fC
Output Rise Time [3][4]
tr
Output Fall Time [3][4]
tf
VCC ≥ VCC(min), t < tON
Low
–
–
800
–
kHz
RPULL-UP = 1 kΩ, CL = 20 pF
–
0.2
2
µs
RPULL-UP = 1 kΩ, CL = 20 pF
–
0.1
2
µs
APS12205
5
22
40
G
APS12215
15
50
90
G
APS12235
100
150
180
G
APS12205
–40
–22
–5
G
MAGNETIC CHARACTERISTICS
Operate Point
Release Point
BOP
BRP
APS12215
–90
–50
–15
G
APS12235
–180
–150
–100
G
APS12205
Hysteresis
BHYS
APS12215
(BOP – BRP)
APS12235
10
45
80
G
30
100
180
G
200
300
360
G
[1] Typical
data are are at TA = 25°C and VCC = 5 V, and are for initial design estimations only.
G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] C = oscilloscope probe capacitance.
L
[2] 1
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
4
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions
RθJA
Package Thermal Resistance
Value
Units
Package LH, 1-layer PCB with copper limited to solder pads
228
°C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each
side connected by thermal vias
110
°C/W
Package UA, 1-layer PCB with copper limited to solder pads
165
°C/W
Power Derating Curve
TJ(max) = 175°C; ICC = ICC(max), IOUT = 0 mA (Output Off)
6
Maximum Allowable VCC (V)
VCC(max)
5
Package LH, 2-layer PCB
(RθJA = 110 °C/W) (Right)
Package UA, 1-layer PCB
(RθJA = 165 °C/W) (Center)
Package LH, 1-layer PCB
(RθJA = 228 °C/W) (Left)
4
3
2
VCC(min)
25
45
65
85 105 125 145
Temperature (°C)
165
185
TJ(max)
Power Dissipation, PD (mW)
Package Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Package LH, 2-layer PCB
(RθJA = 110°C/W)
Package UA, 1-layer PCB
(RθJA = 165°C/W)
Package LH, 1-layer PCB
(RθJA = 228°C/W)
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
5
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
CHARACTERISTIC PERFORMANCE
Electrical Characteristics
Average Supply Current versus Ambient Temperature
Average Supply Current versus Supply Voltage
4.0
4.0
3.5
3.5
TA (°C)
2.5
-40
2.0
25
1.5
3.0
ICC (mA)
ICC (mA)
3.0
150
1.0
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
0.0
6
Average Low Output Voltage versus Supply Voltage for IOUT = 5 mA
5.5
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Low Output Voltage versus Ambient Temperature for IOUT = 5 mA
500
450
450
400
400
350
TA (°C)
300
-40
250
25
200
150
150
100
VOUT(SAT) (mV)
VOUT(SAT) (mV)
5
1.5
0.5
500
VCC (V)
350
300
2.8
250
200
5
150
5.5
100
50
0
2.8
2.0
1.0
0.5
0.0
VCC (V)
2.5
50
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
0
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
6
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
CHARACTERISTIC PERFORMANCE (continued)
APS12205 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
Average Operate Point versus Supply Voltage
40
40
35
35
TA (°C)
-40
25
25
20
30
BOP (G)
BOP (G)
30
150
15
2.8
20
5
15
5.5
10
10
5
VCC (V)
25
5
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
-60
-40
40
60
TA (°C)
80
100
120
140
160
-20
-25
25
-30
150
-15
BRP (G)
BRP (G)
20
-10
TA (°C)
-15
VCC (V)
-20
2.8
-25
5
-30
5.5
-35
-35
-40
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
-60
Average Switchpoint Hysteresis versus Supply Voltage
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
80
80
70
70
60
TA (°C)
50
-40
40
25
30
150
VCC (V)
60
BHYS (G)
BHYS (G)
0
-5
-10
2.8
50
5
40
5.5
30
20
20
10
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-5
-40
-40
10
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
CHARACTERISTIC PERFORMANCE (continued)
APS12215 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
TA (°C)
-40
25
BOP (G)
BOP (G)
Average Operate Point versus Supply Voltage
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
150
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
6
VCC (V)
2.8
5
5.5
-60
-40
25
BRP (G)
BRP (G)
TA (°C)
150
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
6
25
150
3.5
4
4.5
VCC (V)
5
5.5
6
BHYS (G)
BHYS (G)
-40
3
20
40
60
TA (°C)
80
100
120
140
160
2.8
5
5.5
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
TA (°C)
2.5
0
VCC (V)
Average Switchpoint Hysteresis versus Supply Voltage
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
VCC (V)
2.8
5
5.5
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
8
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
CHARACTERISTIC PERFORMANCE (continued)
APS12235 Magnetic Characteristics
Average Operate Point versus Ambient Temperature
Average Operate Point versus Supply Voltage
180
180
170
160
TA (°C)
160
150
-40
150
140
25
130
BOP (G)
BOP (G)
170
150
120
2.8
5
130
5.5
120
110
110
100
VCC (V)
140
100
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
-60
40
60
TA (°C)
80
100
120
140
160
-120
TA (°C)
-120
-130
-40
-130
-140
25
-150
2.8
-140
5
-150
150
-160
VCC (V)
BRP (G)
BRP (G)
20
-110
-110
5.5
-160
-170
-170
-180
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
6
-60
Average Switchpoint Hysteresis versus Supply Voltage
TA (°C)
-40
25
150
2.5
3
3.5
4
4.5
VCC (V)
5
5.5
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Average Switchpoint Hysteresis versus Ambient Temperature
6
BHYS (G)
BHYS (G)
0
-100
-100
360
350
340
330
320
310
300
290
280
270
260
250
240
230
220
210
200
-20
Average Release Point versus Ambient Temperature
Average Release Point versus Supply Voltage
-180
-40
360
350
340
330
320
310
300
290
280
270
260
250
240
230
220
210
200
VCC (V)
2.8
5
5.5
-60
-40
-20
0
20
40
60
TA (°C)
80
100
120
140
160
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
9
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
FUNCTIONAL DESCRIPTION
OPERATION
The output of these devices switches low (turns on) when a magnetic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see Figure 1). After turn-on, the output voltage is VOUT(SAT) . The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off).
The difference in the magnetic operate and release points is the
hysteresis, BHYS , of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Device power-on occurs once tON has elapsed. During the
time prior to tON, and after VCC ≥ VCC(min), the output state is
VOUT(SAT) (Low). After tON has elapsed, the output will correspond with the applied magnetic field for B > BOP or B < BRP.
See Figure 2 for an example.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an output state of VOUT(SAT). The correct state is attained after the first excursion beyond BOP or BRP .
POS
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switch point is BRP.
POWER-ON BEHAVIOR
BOP
BRP
VOUT
POS
t
V
VOUT(SAT)
0
Output State
Undefined for
VCC< VCC(min)
VOUT(SAT )
B+
BHYS
VCC
VOUT
Switch to Low
Switch to High
VOUTOFF
B–
B < BRP
VOUTOFF
V+
0
B > BOP, BRP < B < BOP
V
VCC (min)
0
t ON
t
Figure 2: Power-On Timing Diagram
Figure 1: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates decreasing south polarity field strength (including the
case of increasing north polarity.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
10
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
APPLICATIONS
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from
internal circuitry. As is shown in Figure 3, a 0.1 µF capacitor is
typical.
Extensive applications information on magnets and Hall-effect
sensors is available in:
VS
VCC
CBYP
0.1 µF
APS122xx
VOUT
RPULL-UP
Output
GND
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009
Figure 3: Typical Application Circuit
All are provided on the Allegro website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
11
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 4 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its original spectrum at baseband while the DC offset becomes a highfrequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
the APS12205, APS12215, and APS12235 that use this approach
have an extremely stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low offset and
low noise amplifiers in combination with high-density logic and
sample-and-hold circuits.
Hall Element
Amp
Sample and
Hold
Clock/Logic
Low-Pass
Filter
Figure 4: Model of Chopper Stabilization
(Dynamic Offset Cancellation)
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
12
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
POWER DERATING
The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating conditions. The junction temperature mission profile specified in the
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions,
where TJ may reach 175°C.
The silicon IC is heated internally when current is flowing into
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the
junction temperature, TJ, above the surrounding ambient temperature. The APS12205, APS12215, and APS12235 are permitted
to operate up to TJ = 175°C. As mentioned above, an operating
device will increase TJ according to equations 1, 2, and 3 below.
This allows an estimation of the maximum ambient operating
temperature.
For example, given common conditions such as: TA= 25°C,
VCC = 5 V, ICC = 2.5 mA, VOUT = 185 mV, IOUT = 2 mA (output
on), and RθJA = 165°C/W, then:
PD = (VCC × ICC) + (VOUT × IOUT) =
(5 V × 2.5 mA) + (185 mV × 2 mA) =
12.5 mW + 0.4 mW = 12.9 mW
ΔT = PD × RθJA = 12.9 mW × 165°C/W = 2.1°C
TJ = TA + ΔT = 25°C + 2.1°C = 27.1°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RθJA.
For example, given the conditions RθJA = 228°C/W, TJ(max) =
175°C, VCC(max) = 5.5 V, ICC(max) = 4 mA, VOUT = 500 mV,
and IOUT = 5 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The power dissipation required for the output is shown below:
PD(VOUT) = VOUT × IOUT = 500 mV × 5 mA = 2.5 mW
The power dissipation required for the IC supply is shown below:
PD(VCC) = VCC × ICC = 5.5 V × 4 mA = 22 mW
Next, by inverting using equation 2:
ΔT = PD × RθJA = [PD(VOUT) + PD(VCC)] × 228°C/W =
(2.5 mW + 22 mW) × 228°C/W =
24.5 mW × 228°C/W = 5.6°C
Finally, by inverting equation 3 with respect to voltage:
TA(est) = TJ(max) – ΔT = 175°C – 5.6°C = 169.4°C
In the above case there is only sufficient power dissipation
PD = VIN × IIN
(1) capability to operate up to TA(est). This particular result indicates
that, at TJ(max), the application and device can only dissipate
ΔT = PD × RθJA
(2) adequate amounts of heat at ambient temperatures ≤ TA(est);
the APS12205, APS12215, and APS12235 performance is not
TJ = TA + ΔT (3) guaranteed above T = 150°C for the “L” temperature variant and
A
TA = 85°C for the “E” temperature variant.
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
13
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
Package LH, 3-Pin (SOT-23W)
For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000628, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.125
2.975 –0.075
4°±4°
Active Area Depth
0.28 ±0.04 mm
3
+0.020
0.180–0.053
Die Rotation
Error 4° Max
+0.10
2.90 –0.20
+0.19
1.91 –0.06
Hall Element
(not to scale)
0.25 MIN
0.38 NOM
Package Centerline
to Die Centerline ±0.20
8× 10° ±5°
0.25 BSC
0.95 BSC
Lead Foot Centerline
To Package Centerline ±0.18
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Seating Plane
Gauge Plane
Branded Face
Standard Branding Reference View
0.41 ±0.04
C
0.95
PCB Layout Reference View
0.55 REF
0.57 ±0.04
3×
1.00
Package Centerline
to Die Centerline ±0.15
2
1
0.10
2.40
0.70
+0.10
0.05 –0.05
1.00 ±0.13
C
A04
SEATING
PLANE
1
APS12205ELHA and APS12205LLHA
0.40 ±0.10
A01
1
A35
APS12215LLHA
1
APS12235LLHA
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
14
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
Package UA, 3-Pin SIP
For Reference Only – Not For Tooling Use
(Reference DWG-0000404, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
Mold gate and tie bar
protrusion zone
Ejector pin flash
protrusion
R0.25 MAX (2×)
5° (2×)
0.56 MAX
45° (2×)
0.10 MAX
1.52 ±0.05
1.68 MAX
5° (2×)
+0.08
4.09 –0.05
3.00 ±0.05
2.04
Sensor element location tolerance
Standard ±0.20
Mold gate and tie bar
protrusion zone
0.50 ±0.08 Active Area Depth
+0.05
0.08 –0.00
Ejector pin flash
protrusion
Sensor element location tolerance
Standard ±0.20
1.44
+0.08
3.02 –0.05
3.10 MAX
0.15 MAX
Ejector pin
(far side)
Including gate and
tie bar burrs
Hall Element
(not to scale)
10° (3×)
1.02 MAX
45°
0.79 REF
0.51 REF
0.05 NOM
0.05 NOM
14.99 ±0.25
+0.03
0.41 –0.06
0.10 MAX
0.10 MAX
Dambar Trim Detail
+0.05
0.43 –0.07 (3×)
1.27 NOM (2×)
Standard Branding Reference View
Branding scale and appearance at supplier discretion.
A18
1
1
APS12205LUAA
A36
A03
1
APS12215LUAA
APS12235LUAA
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
15
APS12205,
APS12215,
and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications
Revision History
Number
Date
Description
–
June 3, 2016
Initial release
1
June 20, 2016
Updated Functional Block Diagram (page 1);
Updated Selection Guide (page 2) and package outline drawing brand information (pages 1415).
2
September 23, 2016
3
July 5, 2018
4
June 18, 2019
5
September 10, 2021
Updated Title (all pages), Selection Guide (page 2), Absolute Maximum Ratings (page 2);
Electrical Characteristics (page 4); added Characteristic Performance Data (pages 6-9);
updated Functional Description (page 6), Chopper Stabilization (page 12), and Power
Derating sections (page 13).
Updated TJ(max) notes (page 2), Typical Application Circuit (page 11), Power Derating section
(page 13), Package Outline Drawings (pages 14-15), and other minor editorial updates.
Updated Selection Guide (page 2), Power Derating section (page 13), and Package Outline
Drawing branding (page 14).
Updated Supply Current maximum value (page 4) and package drawings (page 14-15)
Copyright 2021, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
16
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