AS6C4016-55ZINTR

MARCH January 2008 2007 AS6C4016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER FEATURES GENERAL DESCRIPTION Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 4 A (TYP.) LL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage :1.5V(MIN.) Lead free and green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. is well designed for low power The application, and particularly well suited for battery back-up nonvolatile memory application. operates from a single power The supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family (I) Operating Temperature -40 ~ 85 Vcc Range 2.7 ~ 5.5V FUNCTIONAL BLOCK DIAGRAM C C R YY2 c/2 I SYMBOL DESCRIPTION A0 - A17 Address Inputs DQ0 – DQ15 Data Inputs/Outputs O C c/2 55ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 4µA(LL) 30mA PIN DESCRIPTION L WW L AA C M7 2 Speed T O RT V OU OO U CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground R TO O RT R MARCH/2008, V 1.0 Alliance Memory Inc. Page 1 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM PIN CONFIGURATION A4 A5 A3 A6 A2 A7 A1 OE# A0 UB# CE# LB# DQ0 DQ15 DQ1 DQ14 DQ2 DQ13 DQ3 DQ12 Vcc Vss Vss Vcc DQ4 DQ11 DQ5 DQ10 DQ6 DQ9 C C C C L AA C C L WW L WW C C L AA C C C C DQ7 DQ8 WE# NC A17 A8 A16 A9 A15 A10 A14 A11 A13 A12 C R C C TSOP II C T ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 RATING -0.5 to 6.5 -0.5 to VCC+0.5 Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) TA TSTG PD IOUT TSOLDER -40 to 85(I grade) -65 to 150 1 50 260 UNIT V V W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. MARCH/2008, V 1.0 Alliance Memory Inc. Page 2 of 12 MARCH January 2008 2007 AS6C4016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H X L L L L L L L L X X H H L L L X X X H = VIH, L = VIL, X = Don't care. WE# LB# X X H H H H H L L L UB# X H L X L H L L H L X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z DOUT DOUT DOUT High – Z DIN High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *1 Input Low Voltage VIL Input Leakage Current ILI VCC VIN VSS Output Leakage VCC VOUT VSS ILO Output Disabled Current Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL, ICC - 55 II/O = 0mA Average Operating Other pins at VIL or VIH Power supply Current Cycle time = 1µs ICC1 CE# 0.2V, II/O = 0mA Other pins at 0.2V or VCC-0.2V Standby Power CE# VCC-0.2V LLI ISB1 Supply Current Others at 0.2V or VCC-0.2V MIN. 2.7 2.4 - 0.2 -1 TYP. 3.0 - *3 MAX. 5.5 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 30 60 mA - 4 10 mA - 4 50 *4 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 2. Over/Undershoot specifications are characterized, not 100% tested. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = VCC(TYP.) and TA = 25 4. 25µA for special request CAPACITANCE (TA = 25 , f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. MARCH/2008, V 1.0 Alliance Memory Inc. Page 3 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW AS6C4016-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - UNIT AS6C4016-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. MARCH/2008, V 1.0 Alliance Memory Inc. Page 4 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. MARCH/2008, V 1.0 Alliance Memory Inc. Page 5 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) MARCH/2008, V 1.0 Alliance Memory Inc. Page 6 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. MARCH/2008, V 1.0 Alliance Memory Inc. Page 7 of 12 MARCH January 2008 2007 AS6C4016 X 8 BITCMOS LOW SRAM POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE# VCC - 0.2V VCC = 1.5V, CE# VCC-0.2V Data Retention Current IDR Others at 0.2V or VCC-0.2V Chip Disable to Data See Data Retention tCDR Retention Time Waveforms (below) Recovery Time tR tRC* = Read Cycle Time MIN. 1.5 TYP. - MAX. 5.5 UNIT V - 2 30 µA 0 - - ns tRC* - - ns LLI DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR Vcc 1.5V Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (LB#, UB# controlled) VDR Vcc 1.5V Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH MARCH/2008, V 1.0 tR LB#,UB# Vcc-0.2V Alliance Memory Inc. VIH Page 8 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP- SYMBOLS A A1 A2 b c D E E1 e L ZD y Package Outline Dimension DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 MARCH/2008, V 1.0 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Alliance Memory Inc. Page 9 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM 48-ball 6mm 8mm TFBGA Package Outline Dimension MARCH/2008, V 1.0 Alliance Memory Inc. Page 10 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM Alliance Organization VCC Range Package Operating Temp Speed ns AS6C4016-55ZIN 256K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 C - 85 C 55 AS6C4016-55BIN 256K x 16 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 C - 85 C 55 Part Numbering System AS6C 4016 -55 Device Number low power S RAM prefix 40 = 4M 16 =x16 MARCH/2008, V 1.0 Access Time X X Package Option Temperature Range 44pin TSOP II I = Industrial 48ball TFBGA (-40 to + 85 C) Alliance Memory Inc. N N = Lead Free RoHS compliant part Page 11 of 12 MARCH January 2008 2007 AS6C4016 X 8 BIT LOW POWER CMOS SRAM 256K X 16 BIT SUPER 512K LOW POWER CMOS SRAM ® Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2008 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use. MARCH/2008, V 1.0 Alliance Memory Inc. Page 12 of 12