AS7C256B

September 2006 Advance Information ® AS7C256B 5V 32K X 8 CMOS SRAM (Common I/O) Features • Industrial (-40o to 85oC) temperature • Organization: 32,768 words × 8 bits • High speed - 12 ns address access time - 6 ns output enable access time • 28-pin JEDEC standard packages - 300 mil SOJ - 8 × 13.4 mm TSOP - 300 mil PDIP • ESD protection ≥ 2000 volts • Low power consumption via chip deselect • One chip select plus one Output Enable pin • Bidirectional data inputs and outputs • TTL-compatible Logic block diagram Pin arrangement 28-pin DIP, SOJ (300 mil) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 Address decoder I/O7 Sense amp 32,768 X 8 Array (262,144) I/O0 28-pin TSOP 1 (8×13.4mm) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (21) 28 (22) (20) 27 (23) (19) 26 (24) (18) 25 (25) (17) 24 (26) (16) 23 (27) (28) AS7C256B (15) 22 (14) 21 (1) (13) 20 (2) (12) 19 (3) (11) 18 (4) (10) 17 (5) (9) 16 (6) (8) 15 (7) A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Address decoder WE Control circuit OE CE AAAAAAA 8 9 10 11 12 13 14 Note: This part is compatible with both pin numbering conventions used by various manufacturers. 12/5/06; V.1.0 Alliance Memory AS7C256B P. 1 of 8 Copyright © Alliance Memory. All rights reserved. AS7C256B ® Functional description The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min –0.5 –0.5 – –55 –55 – Max +7.0 VCC + 0.5 1.25 +125 +125 50 Unit V V W oC o C mA Truth table CE WE OE Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) H L L L Notes: H = VIH, L = VIL, x = Don’t care. VLC = 0.2V, VHC = VCC - 0.2V. Other inputs ≥ VHC or VLC. X H H L X H L X 12/5/06; V.1.0 Alliance Memory P. 2 of 8 AS7C256B ® Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature (Industrial) Note: 1 VIL min = –1.5V for pulse width less than 10ns, once per cycle. Symbol VCC VIH VIL(1) TA Min 4.5 2.2 -0.5(1) –40 Typical 5.0 – – – Max 5.5 VCC+0.5 0.8 85 Unit V V V o C DC operating characteristics (over the operating range)1 AS7C256B-12 Parameter Input leakage current Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC ISB Standby power supply current ISB1 VOL VOH Test conditions VCC = Max, Vin = GND to VCC VCC = Max, CS = VIH, VOUT = GND to VCC VCC = Max, CE ≤ VIL f = fMax, IOUT = 0mA VCC = Max, CE > VIH f = fMax, IOUT = 0mA VCC = Max, CE > VCC–0.2V VIN < GND + 0.2V or VIN > VCC–0.2V, f = 0(2) IOL = 8 mA, VCC = Min IOH = –4 mA, VCC = Min Min – – – – Max 5 5 160 50 Unit µA µA mA mA – – 2.4 15 0.4 – mA V V Output voltage Notes: All values are maximum guaranteed values. fMax = 1/tRC, only address inputs cycling at fMax, f = 0 means that no inputs are cycling. Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Note: This parameter is guaranteed by device characterization, but is not production tested. Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions Vin = 3dV Vout = 3dV Max 7 7 Unit pF pF 12/5/06; V.1.0 Alliance Memory P. 3 of 8 AS7C256B ® Read cycle (over the operating range)3,9 AS7C256B-12 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE LOW to output in low Z CE HIGH to output in high Z OE LOW to output in low Z OE HIGH to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 12 – – – 3 4 0 0 0 0 – Max – 12 12 6 – – 6 – 6 – 12 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA Dout Data valid tOH Read waveform 2 (CE controlled)3,6,8,9 tRC CE tOE OE tOLZ tACE Dout tCLZ Supply current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ 12/5/06; V.1.0 Alliance Memory P. 4 of 8 AS7C256B ® Write cycle (over the operating range)11 AS7C256B-12 Parameter Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Shaded areas contain advance information. Symbol tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min 12 9 9 0 8 0 0 6 0 0 4 Max – – – – – – – – – 6 – Unit ns ns ns ns ns ns ns ns ns ns ns Notes 4, 5 4, 5 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW Address tWP WE tAS Din tWZ Dout tDW Data valid tOW tDH tAH tWR Write waveform 2 (CE controlled)10,11 tWC tAW Address tAS CE tWP WE tWZ Din Dout tDW Data valid tDH tCW tAH tWR 12/5/06; V.1.0 Alliance Memory P. 5 of 8 AS7C256B ® AC test conditions Output load: see Figure B. Input pulse level: GND to VCC. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent 168Ω Dout +1.72V (5V) VCC 480Ω VCC GND 90% 10% 3 ns 90% 10% Dout 255Ω C(13) Figure A: Input pulse GND Figure B: Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±200mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except on High Z and Low Z parameters, where C=5pF. 12/5/06; V.1.0 Alliance Memory P. 6 of 8 AS7C256B ® Package diagrams 28-pin SOJ Min Max in mils B A E1 E2 A1 b Pin 1 A2 E2 e D Seating Plane c A A1 A2 B b c D E E1 E2 e 0.025 0.095 0.140 0.105 0.028 TYP 0.018 TYP 0.010 TYP 0.245 0.295 0.327 0.730 0.285 0.305 0.347 0.050 BSC b e c L A2 A A1 28-pin TSOP 8×13.4 mm Min Max A A1 A2 – 0.10 0.95 0.15 0.10 11.60 1.20 0.20 1.05 0.25 0.20 11.80 D Hd pin 1(22) pin 8(21) α pin 1(7) 28-pin E pin 5(8) b c D e E Hd L α 0.55 nominal 8.0 nominal 13.30 0.50 0° 13.50 0.70 5° 28-pin PDIP Min Max in mils D A S E1 E B α e Pin 1 b A1 Seating Plane Note: This part is compatible with both pin numbering conventions used by various manufacturers. L c eA A A1 B b c D E E1 e eA L a S 0.010 0.040 0.014 0.008 0.295 0.278 0.180 0.065 0.022 0.014 1.400 0.320 0.298 0.100 BSC 0.330 0.120 0° 0.380 0.140 15° 0.055 12/5/06; V.1.0 Alliance Memory P. 7 of 8 AS7C256B ® Ordering information Package Plastic DIP, 300 mil Plastic SOJ, 300 mil TSOP 8x13.4 mm Volt/Temp 5V industrial 5V industrial 5V industrial 12 ns AS7C256B-12PIN AS7C256B-12JIN AS7C256B-12TIN Part numbering system AS7C 256B –XX X I X Package: P=DIP 300 mil Temperature range: J=SOJ 300 mil I = -40C to 85C T=TSOP 8x13.4 mm SRAM prefix Device number Access time N=Lead Free Part ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved Part Number: AS7C256B Document Version: v.1.0 © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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