ASM2I9942C-32-ET

May 2005 rev 0.2 Low Voltage 1:18 Clock Distribution Chip Features LVCMOS/LVTTL Clock Input 2.5V LVCMOS Outputs for Pentium IITM* ASM2I9942C device ideal for supplying clocks for a high performance Pentium II TM microprocessor based design. With a low output impedance (≈12Ω), in both the HIGH and LOW logic states, the output buffers of the ASM2I9942C are ideal for driving series terminated transmission lines. With an output impedance of 12Ω, the ASM2I9942C can drive two series terminated transmission lines from each output. This capability gives the ASM2I9942C an effective fanout of 1:36. The ASM2I9942C provides enough copies of low skew clocks for most high performance synchronous systems. The LVCMOS/LVTTL input of the ASM2I9942C provides a more standard LVCMOS interface. The OE pins will place the outputs into a high impedance state. The OE pin has an internal pullup resistor. The ASM2I9942C is a single supply device. The VCC power pins require either 2.5V or 3.3V. The 32–lead TQFP and LQFP package is chosen to optimize performance, board space and cost of the device. The 32–lead TQFP has a 7x7mm2 body size with a conservative 0.8mm pin spacing. Microprocessor Support 150pS Maximum Targeted Output–to–Output Skew Maximum Output Frequency of 250MHz @ 3.3 VCC 32–Lead TQFP and LQFP Packaging Single 3.3V or 2.5V Supply. Pin and Function compatible to MPC942C. Functional Description The ASM2I9942C is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the ASM2I9942C has an LVCMOS input clock while the ASM2I9942P has an LVPECL input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output–to–output skews of 200pS, the ASM2I9942C is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V outputs also make the *Pentium II is a trademark of Intel Corporation Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. May 2005 rev 0.2 Block Diagram Q0 LVCMOS_CLK Q1:Q16 Q17 OE (Int. Pullup) ASM2I9942C Table 1. Function Table OE 0 1 Output HIGH IMPEDANCE OUTPUTS ENABLED 24 GND Q5 Q4 Q3 VCC Q2 Q1 Q0 25 26 27 28 29 30 31 32 1 23 22 21 20 19 18 GND 17 16 15 14 VCC Q12 Q13 Q14 GND Q15 Q16 Q17 13 12 11 10 9 8 VCC VCC Q10 6 NC ASM2I9942C 2 3 4 5 LVCMOS_CLK GND GND OE NC Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. VCC Q11 7 Pin Diagram Q6 Q7 Q8 Q9 2 of 10 May 2005 rev 0.2 Table 2. Pin Configuration Pin # 1,2,12,17,25 3 4,6 5 7,8,16,21,29 9-11 13-15 18-20 22-24 26-28 30-32 ASM2I9942C Pin Name GND LVCMOS_CLK NC OE VCC Q17-Q15 Q14-Q12 Q11-Q9 Q8-Q6 Q5-Q3 Q2-Q0 I/O Supply Input Input Supply Output Output Output Output Output Output Type Ground LVCMOS LVCMOS VCC LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Function LVCMOS Clock Input No Connect Outputs are enabled, when OE is high and are tri-stated, when OE is made low. Positive power supply Clock outputs Clock outputs Clock outputs Clock outputs Clock outputs Clock outputs Table 3. Absolute Maximum Rating1 Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range Parameter Min –0.3 –0.3 –40 Max 3.6 VCC + 0.3 ±20 125 Unit V V mA °C Note: 1These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 4. DC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%) Symbol VIH VIL VOH VOL IIN CIN CPD ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current Min 2.0 2.0 Typ Max VCCI 0.8 0.5 ±200 Unit V V V V µA pF pF Ω mA Condition IOH = –16 mA IOL = 16 mA 4.0 14 12 0.5 Per Output Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 3 of 10 May 2005 rev 0.2 Table 5. AC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%) Symbol Fmax tPLH ASM2I9942C Characteristic Maximum Frequency Propagation Delay1 Output-to-output Skew Within one bank Min 1.5 Typ Max 200 2.8 150 Unit MHz nS Condition pS 350 1.3 600 45 0.2 55 1.0 nS pS % nS tsk(o) tsk(pr) tsk(pr) dt tr, tf Any output, Any Bank Part–to–Part Skew1, 2 Part–to–Part Skew1, 3 Duty Cycle Output Rise/Fall Time Note: 1.Tested using standard input levels, production tested @ 133 MHz. 2.Across temperature and voltage ranges, includes output skew. 3.For a specific temperature and voltage, includes output skew. Table 6. DC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%) Symbol VIH VIL VOH VOL IIN CIN CPD ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current Min 2.4 2.4 Typ Max VCCI 0.8 0.5 ±200 Unit V V V V µA pF pF Ω mA Condition IOH = –20 mA IOL = 20 mA 4.0 14 12 0.5 Per Output Table 7. AC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%) Symbol Fmax tPLH Characteristic Maximum Frequency Propagation Delay1 Output-to-output Skew Within one bank Any Output, Any Bank Min 1.3 Typ Max 250 2.3 150 Unit MHz nS Condition tsk(o) pS 350 1.0 500 45 0.2 55 1.0 nS pS % nS tsk(pr) tsk(pr) dt tr, tf Part–to–Part Skew Part–to–Part Skew Duty Cycle 1,2 1,3 Output Rise/Fall Time Note: 1.Tested using standard input levels, production tested @ 133 MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 4 of 10 May 2005 rev 0.2 Power Consumption of the ASM2I9942C and Thermal Management The ASM2I9942C AC specification is guaranteed for the entire operating frequency range up to 250MHz. The ASM2I9942C power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the ASM2I9942C die junction temperature and the associated device reliability. ASM2I9942C Where ICCQ is the static current consumption of the ASM2I9942C, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the ASM2I9942C). The ASM2I9942C supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination. VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used Table 8. Die junction temperature and MTBF Junction temperature (°C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 8, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the ASM2I9942C in a series terminated transmission line system, equation 4. Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the ASM2I9942C needs to be controlled and the thermal impedance of the board/package dissipated equation1. in should the be optimized. is The power in ASM2I9942C represented    PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅VCC M       PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DCQ ⋅ I OH (VCC − VOH ) + (1 − DCQ )⋅ I OL ⋅VOL M   P  TJ = TA + PTOT ⋅ Rthja Equation 1 [ ] Equation 2 Equation 3 Equation 4 f CLOCKMAX =  T − TA 1 ⋅  J , MAX − (I CCQ ⋅VCC ) 2 C PD ⋅ N ⋅ VCC  Rthja    Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 5 of 10 May 2005 rev 0.2 TJ,MAX should be selected according to the MTBF system requirements and Table 8. Rthja can be derived from Table 9. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. ASM2I9942C If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the ASM2I9942C. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Table 9. Thermal package impedance of the 32LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), °C/W 86 76 71 68 66 60 Rthja (2P2S board), °C/W 61 56 54 53 52 49 Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 6 of 10 May 2005 rev 0.2 Package Information 32-lead LQFP Package ASM2I9942C SECTION A-A Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Dimensions Inches Millimeters Min Max Min Max …. 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° … 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7° 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 7 of 10 May 2005 rev 0.2 ASM2I9942C 32-lead TQFP Package SECTION A-A Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Dimensions Inches Millimeters Min Max Min Max …. 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0° 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7° … 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0° 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7° 0.03937 REF 1.00 REF 0.031 BASE Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 8 of 10 May 2005 rev 0.2 Ordering Information Ordering Code ASM2I9942C-32-LT ASM2I9942C-32-LR ASM2I9942CG-32-LT ASM2I9942CG-32-LR ASM2I9942C-32-ET ASM2I9942C-32-ER ASM2I9942CG-32-ET ASM2I9942CG-32-ER ASM2I9942C Top Mark ASM2I9942CL ASM2I9942CL ASM2I9942CGL ASM2I9942CGL ASM2I9942CE ASM2I9942CE ASM2I9942CGE ASM2I9942CGE Package Type 32-pin LQFP, Tray 32-pin LQFP –Tape and Reel 32-pin LQFP, Tray, Green 32-pin LQFP –Tape and Reel, Green 32-pin TQFP, Tray 32-pin TQFP –Tape and Reel 32-pin TQFP, Tray, Green 32-pin TQFP –Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Device Ordering Information ASM2I9942CG-32-LR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 9 of 10 May 2005 rev 0.2 ASM2I9942C Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2I9942C Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. 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