405EX

Part Number 405EX Revision 1.09 - August 21, 2007 405EX PowerPC 405EX Embedded Processor Features • AMCC PowerPC® 405 32-bit RISC processor core operating from 333MHz to 667MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus (PLB) operating up to 200MHz • On-chip 32-bit peripheral bus (OPB) operating up to 100 MHz • External 8-,16-, or 32-bit peripheral bus (EBC) operating up to 100MHz • External bus master (EBM) operating up to 100MHz • On-chip Security feature with True Random Number generation • Eight- and 16-bit NAND Flash interface • Inter-chip connectivity (SCP and IIC) • Boot from NOR Flash on the external peripheral bus or NAND Flash on the NAND Flash interface • DMA (4-channel) support for all on-chip slaves and external bus, UARTs, and devices on the EBC • DDR1/2 SDRAM interface operating up to 400 Mbps Preliminary Data Sheet • Two one-lane PCI Express interfaces operating up to 2.5 Gbps • Two Gigabit Ethernet interfaces (half- and fullduplex) to external PHY (GMII/RGMII) • USB 2.0 OTG port configurable as either Host or Device • Programmable universal interrupt controller (UIC) • General Purpose Timer (GPT) • Up to two serial ports (16750 compatible UART) • Two IIC interfaces operating up to 400kHz and supporting all standard IIC EEPROMs • One SCP (SPI) synchronous full-duplex channel operating up to 25 MHz • General purpose I/Os (GPIOs), each with programmable interrupts and outputs • Supports JTAG for board-level testing • System power management, low power dissipation and small form factor • Available in a RoHS compliant (lead-free) package Description With speeds up to 667MHz, a flexible off-chip memory architecture, and a diverse communications package that includes PCI Express, USB 2.0 OTG, and 10/100/1000 Ethernet, the PowerPC 405EX embedded processor provides a low power and small footprint system-on-a-chip (SOC) solution for a wide range of high performance, cost-constrained embedded applications. This includes wireless LAN applications, security appliances, internet appliances, line cards, and intelligent USB peripherals. It is an easily programmable general purpose, 32-bit RISC controller that offers an upgrade path for applications in need of performance and connectivity improvements. Technology: Cu-08 CMOS, 90nm Package: 388-ball, 27mm × 27mm, enhanced plastic ball grid array (EPBGA), 1mm ball pitch Power consumption (est.): less than 2W, typical Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM only), and 1.2V AMCC Proprietary 1 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power PC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Security Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DDR 1/2 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet List of Figures Figure 1. PPC405EX Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 6. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 7. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 8. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 9. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 10. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 List of Tables Table 1. System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 10. I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 13. DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 14. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 15. System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 16. Peripheral Interface I/O Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 17. I/O Specifications—All CPU Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 18. I/O Specifications—333 MHz to 667 MHz CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 19. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 20. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 21. I/O Timing—DDR SDRAM TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 22. I/O Timing—DDR SDRAM TSK, TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 23. I/O Timing—DDR SDRAM Write TimingTSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 24. I/O Timing—DDR SDRAM Read Timing TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 25. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 AMCC Proprietary 3 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Ordering, PVR, and JTAG Information This section provides the part number nomenclature. For availability, contact your local AMCC sales office. Order Part Number (see Notes:) PPC405EX-SpAfffTx PPC405EX-NpAfffTx Rev Level A A Product Name PPC405EX PPC405EX Notes: 1. 2. 3. 4. Package 27mm, 388-ball, EPBGA 27mm, 388-ball, EPBGA PVR Value 0x12911477 0x12911475 JTAG ID 0x1405B1E1 0x1405B1E1 S = security feature present, N = security feature not present p = Package: S = lead-free (RoHS compliant), P = leaded A = Chip revision level A fff = Processor frequency 333 = 333MHz 400 = 400MHz 533 = 533MHz 666 = 667MHz 5. T = Case temperature range, -40°C to +85°C 6. x = Shipping package type Z = tape-and-reel blank = tray The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC405EX Embedded Processor User’s Manual for details about accessing these registers. Order Part Number Key PPC405EX-SSA667TZ Shipping Package AMCC Part Number Case Temperature Range Processor Speed (MHz) Security Chip Package Revision Level Note: The example P/N above has the security feature, is lead-free, capable of running at 667MHz, and is shipped in tape-and-reel packaging. 4 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Block Diagram Figure 1. PPC405EX Embedded Controller Functional Block Diagram Universal Interrupt Controller x3 Clock Control Reset Power Mgmt Timers MMU Power PC 405 Processor JTAG Trace DCRs UART x2 IICx2/ BSC SCP (SPI) NAND Flash Controller EBC EBM DCR Bus GPIO Arbiter On-chip Peripheral Bus (OPB) 16KB D-Cache 16KB I-Cache OPB/PLB Bridges GPT PKA TRNG Arbiter Processor Local Bus (PLB4)—128 bits DDR1/2 SDRAM Controller EIP-94 Security Feature PCI-E PCI-E 1-lane 1-lane DMA Controller (4-Channel) MAL/w Interrupt Coalescing AHB-PLB Bridge HSS HSS Ethernet MAC 1Gbit x2 USB 2.0 OTG Controller ULPI The PPC405EX is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. AMCC Proprietary 5 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Address Maps The PPC405EX incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EX processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory) Function Local Memory EBC PCI Express GPT UART 0 Reserved UART 1 Reserved IIC 0 Reserved IIC 1 Reserved OPB Peripherals SCP Reserved OPB Arbiter Reserved GPIO Reserved Ethernet 0 Ethernet 1 RGMII Bridge Reserved PKA +TRNG PCI Express Interrupt Handler PLB/AHB Peripherals Reserved USB OTG Security Reserved EBC Notes: 1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory regions for other uses. 3. PCI Express can use PLB address range 1 0000 0000 to FFFF FFFF FFFF FFFF even though the CPU can not access it. EBC Memory EBC Memory—Boot ROM Subfunction DDR 1/2 SDRAM Start Address (Hex) 0 0000 0000 0 8000 0000 0 9000 0000 0 EF60 0000 0 EF60 0200 0 EF60 0208 0 EF60 0300 0 EF60 0308 0 EF60 0400 0 EF60 0420 0 EF60 0500 0 EF60 0520 0 EF60 0600 0 EF60 0606 0 EF60 0700 0 EF60 0740 0 EF60 0800 0 EF60 0880 0 EF60 0900 0 EF60 0A00 0 EF60 0B00 0 EF60 0C04 0 EF61 0000 0 EF62 0000 0 EF62 0100 0 EF6C 0000 0 EF70 0000 0 EF78 0000 0 F000 0000 0 FFE0 0000 End Address (Hex) 0 7FFF FFFF 0 8FFF FFFF 0 EF5F 00FF 0 EF60 01FF 0 EF60 0207 0 EF60 02FF 0 EF60 0307 0 EF60 03FF 0 EF60 041F 0 EF60 04FF 0 EF60 051F 0 EF60 05FF 0 EF60 0605 0 EF60 06FF 0 EF60 073F 0 EF60 07FF 0 EF60 087F 0 EF60 08FF 0 EF60 09FF 0 EF60 0AFF 0 EF60 0C03 0 EF60 FFFF 0 EF61 FFFF 0 EF62 00FF 0 EF6B FFFF 0 EF6F FFFF 0 EF77 FFFF 0 EFFF FFFF 0 FFDF FFFF 0 FFFF FFFF Size 2GB 256MB 1.5GB 512B 8B 248B 8B 248B 32B 224B 32B 224B 6B 250B 64B 192B 128B 128B 256B 256B 260B 62KB 64KB 256B 640KB 256KB 512KB 8.9MB 254MB 2MB 6 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 2. DCR Address Map Function Total DCR Address Space Reserved CPR (Clocking, Power-on Reset) System DCRs DDR 1/2 SDRAM Controller External Bus Controller (EBC) External Bus Master (EBM) Reserved PLB4XAHB Bridge Reserved PCI Express 0 PCI Express 1 PLB4 Arbiter PLB-to-OPB Bridge OPB-to-PLB Bridge Reserved Power Management Reserved UIC 0 UIC 1 UIC 2 Reserved DMA Reserved Ethernet MAL Reserved 1 Start Address (Hex) 0x000 000 00C 00E 010 012 014 016 020 030 040 060 080 090 0A0 0A8 0B0 0B3 0C0 0D0 0E0 0F0 100 140 180 200 End Address (Hex) 0x3FF 00B 00D 00F 011 013 015 01F 02F 03F 05F 07F 08F 09F 0A7 0AF 0B2 0BF 0CF 0DF 0EF 0FF 13F 17F 1FF 3FF Size 1KW (4KB)1 2W 2W 2W 2W 2W 16W 32W 32W 16W 16W 8W 3W 16W 16W 16W 64W 128W Notes: 1. A DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or one kiloword (KW) (which equals 4KB). AMCC Proprietary 7 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Power PC 405 Processor The PPC405 processor is a fixed-point, 32-bit RISC unit. Features include: • Five-stage pipeline with single-cycle execution of most instructions, including loads and stores • Separate, configurable 16 KB D- and I-caches, both two-way set associative • Thirty-two 32-bit general purpose registers (GPRs) • Unaligned load/store support • Hardware multiply/divide • Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB) • Double word instruction fetch from cache • Translation of the four GB logical address space into physical addresses • Built-in timer and debug support • Power management • DCR interface is 32 bits wide • Selectable processor vs. bus clock ratios (N:1 ratio only, where N =1, 2, 3,or 4 ) Internal Buses The PPC405EX contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus (AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. The daisychained DCR bus provides a lower bandwidth path for passing status and control information between the processor and the other on-chip peripheral functions. PLB The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and slave devices to the PPC405 CPU. It provides a 128-bit data path with 64-bit addressing and operates up to 200MHz. There are bridges between the PLB and the OPB. Features include: • Separate and simultaneous 6.4GB/s read and write data paths • Decoupled address and data buses • Address pipelining • Late master request abort capability • Hidden (overlapped) bus request/grant protocol • Bus arbitration-locking mechanism • Byte-enable capability allows for unaligned half word transfers and 3-B transfers • Support for 32- and 64-B burst transfers • Read word address capability • Sequential burst protocol • Guarded and unguarded memory transfers • Simultaneous control, address, and data phases • DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations AHB The Advanced High-Performance Bus (AHB) is dedicated to the USB OTG 2.0. Features include: • 32-bit data path • 32-bit address • Synchronous to the PLB • From 60MHz to 100MHz. 8 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet OPB The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the OPB and the PLB. Features include: • Pipelined read support • Dynamic bus sizing • Single-cycle data transfer between masters and slaves DCR Bus The daisy-chained DCR bus provides a path for passing status and control information between the processor core and the other on-chip cores. All DCRs are 32 bits in width with 10-bit addressing. External Bus Controller The external bus controller (EBC and EBM ) transfers data between the PLB and external memory or peripheral devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices. Features include: • From 60MHz to 100 MHz speed • Data bus is 8, 16, or 32 bits with a 27-bit address bus • Up to four chip selects • Arbitration and multi-master supported • Flash ROM interface • Boot from EBC (including NAND Flash interface) support • Direct support for 8-,16-, or 32-bit SRAM and external peripherals • External bus master support NAND Flash Controller The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a variety of NAND Flash-based storage devices. Features include: • Attachment as internal EBC slave device • Eight- and 16-bit NAND Flash interface • Up to four banks of NAND Flash supported • Device sizes of 4MB to 256MB (32Mb to 2Gb) supported • 512B + 16B or 2kB + 64B device page sizes supported • ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED) • Eight-bit command write, address write, and data read/write • Interrupt on device ready (after long page write or block erase operations) • Boot from NAND – Executes up to 4KB of boot code out of first block – Automatic page read accesses performed based on device configuration and read address DMA Controller The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an independent set of registers needed for data transfer: a control register, a source address register, a destination address register, and a transfer count register. AMCC Proprietary 9 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Features include: • Memory-to-memory transfers • Buffered memory-to-peripheral transfers • Buffered peripheral-to-memory transfers • Four independent DMA channels • Scatter/gather capability for dynamically programming multiple DMA transfers • Programmable address increment or decrement • Internal data buffering • Can transfer data to/from any PLB slave, including the external bus USB 2.0 OTG Interface One USB 2.0 On-the-Go (OTG) controller that can be configured as either a Host or Device port. Features include: • Low- (Host only), Full- and High-Speed support • Internal DMA to optimize performance and offload the CPU • Up to two IN/OUT Endpoints in Device mode (one can be isochronous) • Supports maximum packet size of 1024B (isochronous) and 512B (bulk) • Support for isochronous traffic • Three packets per microframe (24MB/s throughput) • Eight KB buffer • ULPI SDR interface DDR1/2 SDRAM Controller The Double Data Rate 1/2 (DDR1/2) SDRAM memory controller supports industry standard discrete devices that are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: • 16- or 32-bit memory interface • Optional 8-bit error checking and correcting (ECC) • 1.6-GB/s peak data rate • Two memory banks of up to 1 GB each • Maximum capacity of 2GB • Support for one memory bank of 2GB with CAS latencies of 2, 2.5, or 3 • Clock frequencies from 133MHz (266Mbps) to 200MHz (400Mbps) supported (Faster parts may be used, but must be clocked no faster than 200MHz) • Page mode accesses (up to 16 open pages) with configurable paging policy • Programmable address mapping and timing • Software initiated self-refresh • Power management (self-refresh, suspend) • Two regions (two chip selects, one clock driver) PCI Express The PCI Express single-lane interfaces include the following features: Features include: • Compliant with PCI Express base specification 1.1 • Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream) – Applications compliant with MSI rules are limited to one End Point port per PPC405EX 10 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet • • • • • • PCI-Express to PCI-Express opaque (Non-Transparent) bridge Power Management Supports one virtual channel (VC0) with no Traffic Class (TC) filtering Maximum Payload block size 256B Supports up to 512B maximum Read request size Requests supported: – Up to two posted outbound Write requests (memory and messages) – Up to two posted inbound Write requests – Up to two outbound Read requests outstanding on PCI Express – Up to two inbound Read requests outstanding on PCI Express – Outbound I/O request as a PCI Express Root Port – Inbound I/O request as a PCI Express End Point Buffering in each PCI Express Port for the following transaction types: – 1KB Replay buffer: up to eight in flight transactions – 512B for Outbound posted Writes – 512B for Outbound Reads completion – 512B for Inbound posted Writes – 512B for Inbound Reads completion Parity checking on each buffer POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM INTx Interrupts support (PCI legacy): – Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC – A/B/C/D INTx types Generation for Endpoints MSI - Message Signaled Interrupts – MSI Generation for End Point – MSI Termination for Root Ports – MSI_X Termination for Root Ports • • • • • • Security Function The built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt controllers. Features include: • Federal Information Processing Standard (FIPS) 140-2 design • Support for an unlimited number of Security Associations (SA) • Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP) • Internet Protocol Security (IPSec) features – Full packet transforms (ESP & AH) – Complete header and trailer processing (IPv4 and IPv6) – Multi-mode automatic padding – "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers • Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS) – Packet transforms – One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4 Stream Cipher • Secure Real-Time Protocol (sRTP) features – Packet transforms – ROC removal and TAG insertion – Variable bypass offset of header length per packet AMCC Proprietary 11 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet • Media Access Control Security (MACSec) features – Cipher suite GCM-AES-128 – Header insertion and removal – Integrity and confidentiality with MSDU • SGT L2 supported features: – GCM-AES with 128-bit key. – Integrity only and with confidentiality of MSDU • ICV generation and validation SGT L3 supported features – AES-GCM, AES-GMAC with 128, 192 and 256 bit key. • IPsec/SSL security acceleration engine • DES, 3DES, AES, ARC-4, AES-GCM, and GMAC-AES encryption/decryption • MD-5, SHA-1, and SHA-256 hashing • Public key acceleration for RSA, DSA and Diffie-Hellman • Combined encryption-hash and hash-decryption with the AES-CCM algorithm. • True or pseudo random number generators – Non-deterministic true random numbers – Pseudo random numbers with lengths of 8B or 16B – ANSI X9.17 Annex C compliant using a DES algorithm • Interrupt controller – Fifteen programmable, maskable interrupts – Initiate commands via an input interrupt – Sixteen programmable interrupts indicating completion of certain operations – All interrupts mapped to one level- or edge-sensitive programmable interrupt output • DMA controller – Autonomous, 4-channel – 1024-words (32 bits/word) per DMA transfer – Scatter/gather capability with byte aligned addressing – Byte reverse capability on SA and descriptors UART The Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations: • One 8-signal port • Two 4-signal ports. • Two 2-signal ports • One 4-signal port and one 2-signal port The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. Features include: • Compatible with the16750 • All six software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART0 • Programmable auto flow (data flow controlled by RTS and CTS signals) • Characters can be 5, 6, 7, or 8 bits • Programmable start, stop, parity bit insertion • Sixty-four byte FIFOs for buffering Tx and Rx data • LIN sub-bus specification compliant - line break generation/detection and false start bit detection • Programmable internal/external loopback capabilities • Low Power and Sleep mode • Register conformance (after reset) to configuration of the NS16450 register set • Hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) • Complete status reporting • Full prioritized interrupt system controls 12 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet • Independently controlled transmit, receive, line status, and data set interrupts • Programmable baud generator (divides serial clock input and generates 16x clock) • Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data • Even, odd, or no-parity bit generation and detection • Stop bit generation of 1, 1.5, or 2 bits • Variable baud rate • Internal diagnostic capability • Loopback controls for isolating communications link faults • Break, parity, overrun, framing error simulation • OPB interface with optional DMA support IIC Bus Interface The Inter-Integrated Circuit (IIC) interface provides a Philips I2C® compatible interface operating up to 400kHz either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be used to replace the default configuration settings provided by the chip. Features include: • Two IIC channels • Compliant with Philips Semiconductors I2C Specification, dated 1995 • Operation at 100kHz or 400kHz • Byte (8-bit) data • Addresses are 10 or 7 bits • Slave Transmit and Receive • Master Transmit and Receive • Multiple bus masters supported • Programmable as master, slave, or master/slave • Boot parameters read from IIC attached memory (Port 0) with IIC bootstrap controller • OPB slave interface is 32 bits wide Serial Communication Port Interface (SCP/SPI) The Serial Communication Port (SCP) (also known as the Serial Peripheral Interface or SPI) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a three-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include: • One SCP channel, full duplex synchronous • SCP master • Up to 25MHz • Programmable internal loopback capabilities • Multi-master protocol supported • Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow) • Dynamic control of serial bit rate of data transfer (serial-master mode only) • Data Item size for each data transfer under programmer control (4-to-16 bits) • OPB slave interface is 32 bits wide AMCC Proprietary 13 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet General Purpose I/O (GPIO) Controller The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I/O groups. Features include: • Up to 32 GPIOs available – GPIOs are multiplexed with alternate functions – If not in use for dedicated functions, I/Os are available as GPIOs • Direct control of all functions from registers programmed by means of OPB bus master accesses • Time multiplexing of controller outputs to module outputs • Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs externally) • Time multiplexing of module inputs to controller inputs Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the PPC405 processor. Features include: • Ten external interrupt sources supported • Generate interrupt on level (high or low) or edge (rising or falling) • Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive triggering) • Each interrupt source/bit programmable as critical or non critical • DCR bus interface is 32 bits wide • Optional interrupt handler vector generation – Programmable vector base address – Programmable vector offset size – Programmable interrupt priority ordering • Programmable polarity for all interrupt types • Interrupts of the same type do not need to be in contiguous bit positions • Status registers provide: current state of all interrupts, current state of enabled interrupts Gigabit Ethernet The Ethernet support provides two Gigabit (10/100/1000 Mbps) interfaces (GMII/RGMII ). Features include: • ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant • Half-duplex and full-duplex supported • Receive FIFOs are 512 bytes with programmable thresholds • FCS control for transmit/receive packets • Multiple packet handling in transmit and receive FIFOs • Unicast, multicast, broadcast, and promiscuous address filtering • Two 256-bit hash filters for unicast and multicast frames • Automatic retransmission of collided frames • Runt frame rejection • Programmable inter-frame gap • IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame transmitting) • Wake-on-LAN and Power-over-Internet supported 14 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet • • • • • • • • • • • Programmable internal/external loopback capabilities OPB slave (MAC) and PLB master (MAL) interfaces are 32 bits wide Extensive error/status vector generation for each processed packet VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard) Programmable automatic source address inclusion/replacement for transmit packets Programmable automatic Pad/FCS stripping for receive packets Programmable VLAN Tag inclusion/replacement for transmit packets Half- or full-duplex GMII/RGMII Jumbo frames support Memory Access Layer (MAL) provides DMA capability to Ethernet channel Interrupt coalescence support for two transmit and two receive channels General Purpose Timer (GPT) The GPT provides a time base counter and system timers in addition to those defined in the processor. Features include: • 32-bit time base counter driven by the OPB clock • Seven 32-bit compare timers JTAG Features include: • IEEE 1149.1 test access port • JTAG Boundary Scan Description Language (BSDL) Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the JTAG interface. AMCC Proprietary 15 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Figure 2. Package 27mm, 388-Ball EPBGA Gold Gate Release Corresponds to A01 Ball Location Top View Logo View ® Part Number Lot Number PPC405EX 1YWWBZZZZZ Side View PCB Substrate Epoxy Mold Compound 2.65 max 0.3 min 27.0 Bottom View AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 25.0 1.0 Basic 27.0 01 03 05 07 09 11 13 15 17 19 21 23 25 02 04 06 08 10 12 14 16 18 20 22 24 26 0.60 ± 0.1 SOLDERBALL x 388 Notes: 1. All dimensions are in mm. 2. Package conforms to JEDEC MS-034C 3. Package available in leaded or lead-free versions 16 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Signals that have different functions for different modes with the same function are separated by commas. Shared signals appear alphabetically multiple times in the list—once for each signal name on the ball. The Page column indicates the page within the table “Signal Functional Description” on page 38 on which the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 13) Signal Name AGND AGND AGND AGND AHVDD AHVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD BA0 BA1 BA2 BankSel0 BankSel1 [BusReq]GPIO27[DMAEOT3][IRQ5] CAS DM0 DM1 DM2 DM3 DM4 [DMAAck0]PerAddr07[TS1] [DMAAck1]GPIO31[IRQ0] [DMAAck2][HoldReq]GPIO22 [DMAAck3][ExtAck]GPIO25[IRQ3] [DMAEOT0][PerAddr05]GPIO26[TS3] [DMAEOT1]GPIO29[IRQ2] [DMAEOT2][ExtReq]GPIO24[IRQ4] [DMAEOT3][BusReq]GPIO27[IRQ5] [DMAReq0]PerAddr06[TS2] [DMAReq1]GPIO30[IRQ1] [DMAReq2][HoldAck]GPIO23 [DMAReq3]PerAddr08[TS0] AMCC Proprietary Ball K01 L04 P04 R01 M04 R04 J03 K04 M01 N03 N04 P01 T01 AD22 AF24 AE24 AF21 AE20 B03 AF20 M25 T26 AD16 AD13 Y26 J26 D01 B05 C04 K26 D03 A03 B03 K25 D02 C05 J25 17 DMA 41 DMA 41 DMA 41 DDR 1/2 SDRAM 42 DDR 1/2 SDRAM External Bus Master DDR 1/2 SDRAM 42 41 42 DDR 1/2 SDRAM 42 Power 44 Power 44 Power 44 Interface Group Page PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 2 of 13) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 EAGND EAVDD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD [ExtAck]GPIO25[DMAAck3][IRQ3] [ExtReq]GPIO24[DMAEOT2][IRQ4] ExtReset Ball M26 T25 AE16 AE12 Y25 AE07 AE08 V24 W24 AB26 AB25 V25 W25 AA26 AA25 D12 T12 AC05 AB04 AC07 AC08 C04 A03 B19 External Bus Master 41 Power 44 DDR 1/2 SDRAM 42 Power 44 DDR 1/2 SDRAM 42 Interface Group Page 18 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 3 of 13) Signal Name GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0, GMC0RxD0 GMCRxD1, GMC0RxD1 GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 GMCRxD5, GMC1RxD1 GMCRxD6, GMC1RxD2 GMCRxD7, GMC1RxD3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0, GMC0TxD0 GMCTxD1, GMC0TxD1 GMCTxD2, GMC0TxD2 GMCTxD3, GMC0TxD3 GMCTxD4, GMC1TxD0 GMCTxD5, GMC1TxD1 GMCTxD6, GMC1TxD2 GMCTxD7, GMC1TxD3 GMCTxEn, GMC0TxCtl GMCTxEr, GMC1TxCtl Ball AD04 AF04 AE04 AE03 AF02 AD07 AD09 AC11 AE10 AD10 AF09 AE09 AF07 AF06 AE06 AE05 AF05 AC06 AE01 AD02 AD01 AC03 AC02 AC01 AB03 AB02 AD05 AF03 Ethernet 38 Interface Group Page AMCC Proprietary 19 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 4 of 13) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A08 A13 A19 A26 B01 B02 B25 C01 C02 C03 C24 D04 D09 D14 D18 D23 E01 E03 H01 H26 J04 J23 K24 L11 L13 L16 M12 M13 M14 M15 N12 N13 N14 N15 N16 N26 P11 P12 P13 P14 P15 P23 Power 44 Interface Group Page 20 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 5 of 13) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball R12 R13 R14 R15 T11 T14 T16 U01 U02 V04 V23 W01 W26 AB01 AC04 AC09 AC13 AC18 AC23 AD03 AD24 AE02 AE25 AF01 AF08 AF14 AF19 AF26 Power 44 Interface Group Page AMCC Proprietary 21 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 6 of 13) Signal Name GPIO00[PerDataPar0] GPIO01[PerDataPar1] GPIO02[PerDataPar2] GPIO03[PerDataPar3] GPIO04[PerData20][USB2Data4] GPIO05[PerData21][USB2Data5] GPIO06[PerData22][USB2Data6] GPIO07[PerData23][USB2Data7] GPIO08[PerCS1][NFCE1][IRQ7] GPIO09[PerCS2][NFCE2][IRQ8] GPIO10[PerCS3][NFCE3][IRQ9] GPIO11[IRQ6] GPIO12[PerData16][USB2Data0] GPIO13[PerData17][USB2Data1] GPIO14[PerData18][USB2Data2] GPIO15[PerData19][USB2Data3] GPIO16[UART0DCD][UART1CTS] GPIO17[UART0DSR][UART1RTS] GPIO18[UART0CTS] GPIO19[UART0RTS] GPIO20[UART0DTR][UART1Tx] GPIO21[UART0RI][UART1Rx] GPIO22[HoldReq][DMAAck2] GPIO23[HoldAck][DMAReq2] GPIO24[ExtReq][DMAEOT2][IRQ4] GPIO25[ExtAck][DMAAck3][IRQ3] GPIO26[PerAddr05][DMAEOT0][TS3] GPIO27[BusReq][DMAEOT3][IRQ5] GPIO28 GPIO29[IRQ2][DMAEOT1] GPIO30[IRQ1][DMAReq1] GPIO31[IRQ0][DMAAck1] Halt [HoldAck]GPIO23[DMAReq2] [HoldReq]GPIO22[DMAAck2] IIC0SData IIC0SClk IIC1SData[SCPDO] IIC1SClk[SCPClkOut] Ball A16 B12 C09 B04 C13 B09 C12 D11 C20 A21 B20 H03 C11 B08 A10 B10 F04 F02 G02 G01 F03 F01 B05 C05 A03 C04 K26 B03 U03 D03 D02 D01 A02 C05 B05 AA01 Y03 AA04 AA02 IIC 38 System External Bus Master 40 41 System 40 Interface Group Page 22 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 7 of 13) Signal Name [IRQ0]GPIO31[DMAAck1] [IRQ1]GPIO30[DMAReq1] [IRQ2]GPIO29[DMAEOT1] [IRQ3][ExtAck]GPIO25[DMAAck3] [IRQ4][ExtReq]GPIO24[DMAEOT2] [IRQ5][BusReq]GPIO27[DMAEOT3] [IRQ6]GPIO11 [IRQ7][PerCS1][NFCE1]GPIO08 [IRQ8][PerCS2][NFCE2]GPIO09 [IRQ9][PerCS3][NFCE3]GPIO10 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemAddr14 MemClkEn MemClkOut0 MemClkOut0 Ball D01 D02 D03 C04 A03 B03 H03 C20 A21 B20 AE21 AD20 AF22 AE22 AF23 AD21 AC21 AE23 AE26 AD25 AD26 AC24 AB24 AC25 AC26 Y24 AA23 AA24 DDR1/2 SDRAM 42 DDR1/2 SDRAM 42 Interrupts 39 Interface Group Page AMCC Proprietary 23 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 8 of 13) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 MemFBD MemFBR MemODT0 MemODT1 Ball M24 N24 P25 P24 L25 L26 N25 P26 R24 T24 V26 U24 R25 R26 U26 U25 AE17 AF17 AE15 AF15 AF18 AD17 AF16 AD15 AE13 AF12 AF10 AD11 AE14 AF13 AF11 AE11 AD23 AF25 AD18 AE18 DDR1/2 SDRAM 42 DDR1/2 SDRAM 42 Interface Group Page 24 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 9 of 13) Signal Name [NFALE]PerData30 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO08[IRQ7] [NFCE2][PerCS2]GPIO09[IRQ8] [NFCE3][PerCS3]GPIO10[IRQ9] [NFCLE]PerData29 [NFData00]PerData00 [NFData01]PerData01 [NFData02]PerData02 [NFData03]PerData03 [NFData04]PerData04 [NFData05]PerData05 [NFData06]PerData06 [NFData07]PerData07 [NFData08]PerData08 [NFData09]PerData09 [NFData10]PerData10 [NFData11]PerData11 [NFData12]PerData12 [NFData13]PerData13 [NFData14]PerData14 [NFData15]PerData15 [NFRdyBusy]PerData31 [NFREn]PerData27 [NFWEn]PerData28 OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball C06 B21 C20 A21 B20 A06 C18 B18 C17 A18 D16 B17 C16 B16 A17 B15 C15 A15 B14 A14 C14 B13 A04 A05 C08 D05 D07 D08 D13 D19 D20 D22 E04 E23 G04 G23 H23 L12 L15 M11 M16 R11 V03 W04 Y04 Power 44 NAND Flash 42 Interface Group Page AMCC Proprietary 25 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 10 of 13) Signal Name PCIE0ATB PCIE0ClkC PCIE0ClkT PCIE0RExt PCIE0RExtG PCIE0Rx PCIE0Rx PCIE0Tx PCIE0Tx PCIE1ATB PCIE1ClkC PCIE1ClkT PCIE1RExt PCIE1RExtG PCIE1Rx PCIE1Rx PCIE1Tx PCIE1Tx [PerAddr05]GPIO26[TS3][DMAEOT0] PerAddr06[TS2][DMAReq0] PerAddr07[TS1][DMAAck0] PerAddr08[TS0][DMAReq3] PerAddr09[TS1E] PerAddr10[TS0E] PerAddr11[TS1O] PerAddr12[TS0O] PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk Ball L03 L01 L02 M03 M02 J01 J02 K02 K03 R02 T02 R03 T03 T04 N01 N02 P02 P03 K26 K25 J26 J25 H25 J24 G26 H24 G25 F26 E26 F25 G24 E25 D26 F24 C26 D25 F23 E24 C25 D24 B26 A25 B24 C23 C22 D21 A20 External Peripheral 41 External Peripheral 41 PCI Express 1 39 PCI Express 0 39 Interface Group Page 26 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 11 of 13) Signal Name PerCS0[NFCE0] [PerCS1][NFCE1]GPIO08[IRQ7] [PerCS2][NFCE2]GPIO09[IRQ8] [PerCS3][NFCE3]GPIO10[IRQ9] PerData00[NFData00] PerData01[NFData01] PerData02[NFData02] PerData03[NFData03] PerData04[NFData04] PerData05[NFData05] PerData06[NFData06] PerData07[NFData07] PerData08[NFData08] PerData09[NFData09] PerData10[NFData10] PerData11[NFData11] PerData12[NFData12] PerData13[NFData13] PerData14[NFData14] PerData15[NFData15] [PerData16]GPIO12[USB2Data0] [PerData17]GPIO13[USB2Data1] [PerData18]GPIO14[USB2Data2] [PerData19]GPIO15[USB2Data3] [PerData20]GPIO04[USB2Data4] [PerData21]GPIO05[USB2Data5] [PerData22]GPIO06[USB2Data6] [PerData23]GPIO07[USB2Data7] PerData24[USB2Dir] PerData25[USB2Stop] PerData26[USB2Next] PerData27[NFREn] PerData28[NFWEn] PerData29[NFCLE] PerData30[NFALE] PerData31[NFRdyBusy] [PerDataPar0]GPIO00 [PerDataPar1]GPIO01 [PerDataPar2]GPIO02 [PerDataPar3]GPIO03 PerErr PerOE PerReady PerRW PerWBE0 PerWBE1 PerWBE2 PerWBE3 AMCC Proprietary Ball B21 C20 A21 B20 C18 B18 C17 A18 D16 B17 C16 B16 A17 B15 C15 A15 B14 A14 C14 B13 C11 B08 A10 B10 C13 B09 C12 D11 A07 B07 B06 A05 C08 A06 C06 A04 A16 B12 C09 B04 C19 A24 B11 B23 A23 C21 B22 A22 27 External Peripheral 41 External Peripheral 41 External Peripheral 41 External Peripheral 41 External Peripheral 41 Interface Group Page PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 12 of 13) Signal Name PSROUser RAS Reserved SAGND SAVDD [SCPClkOut]IIC1SClk SCPDI [SCPDO]IIC1SData SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVREF1A SVREF1B SVREF2A SVREF2B SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS TrcClk TRST [TS0]PerAddr08[DMAReq3] [TS1]PerAddr07[DMAAck0] [TS2]PerAddr06[DMAReq0] [TS3][PerAddr05]GPIO26[DMAEOT0] [TS0E]PerAddr10 [TS0O]PerAddr12 [TS1E]PerAddr09 [TS1O]PerAddr11 Ball A09 AD19 AD12 A11 A12 AA02 AA03 AA04 N23 R16 T15 W23 Y23 AB23 AC19 AC20 AC22 AD14 AC14 T23 AC16 L23 C10 AD06 AD08 V02 W02 W03 Y02 D06 V01 L24 Y01 J25 J26 K25 K26 J24 H24 H25 G26 Trace 40 Trace 40 System JTAG Trace JTAG 40 39 40 39 JTAG 39 System 40 DDR1/2 SDRAM 42 Power 44 Serial Communication Port 43 System DDR 1/2 SDRAM Other Power Interface Group Page 40 42 44 44 28 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 3. Signals Listed Alphabetically (Sheet 13 of 13) Signal Name [UART0CTS]GPIO18 [UART0DCD][UART1CTS]GPIO16 [UART0DSR][UART1RTS]GPIO17 [UART0DTR][UART1Tx]GPIO20 [UART0RI][UART1Rx]GPIO21 [UART0RTS]GPIO19 UART0Rx UART0Tx [UART1CTS][UART0DCD]GPIO16 [UART1RTS][UART0DSR]GPIO17 [UART1Rx][UART0RI]GPIO21 [UART1Tx][UART0DTR]GPIO20 UARTSerClk USB2Clk [USB2Data0][PerData16]GPIO12 [USB2Data1][PerData17]GPIO13 [USB2Data2][PerData18]GPIO14 [USB2Data3][PerData19]GPIO15 [USB2Data4][PerData20]GPIO04 [USB2Data5][PerData21]GPIO05 [USB2Data6][PerData22]GPIO06 [USB2Data7][PerData23]GPIO07 [USB2Dir]PerData24 [USB2Next]PerData26 [USB2Stop]PerData25 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE Ball G02 F04 F02 F03 F01 G01 G03 H02 F04 F02 F01 F03 E02 C07 C11 B08 A10 B10 C13 B09 C12 D11 A07 B06 B07 D10 D15 D17 H04 K23 L14 M23 N11 P16 R23 T13 U04 U23 AC10 AC12 AC15 AC17 AE19 DDR1/2 SDRAM 42 Power 44 USB 2.0 43 USB 2.0 43 UART Peripheral USB 2.0 43 43 UART Peripheral 43 UART Peripheral 43 Interface Group Page AMCC Proprietary 29 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet In the following table, only the default signal name is shown for each ball. Shared balls are marked with an asterisk (*). To determine what signals or functions are shared on those balls, look up the default signal name in “Signals Listed Alphabetically” on page 17. The following table lists the signals by ball assignment. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7) Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 GND Halt GPIO24 * PerData31 * PerData27 * PerData29 * PerData24 * GND PSROUser GPIO14 * SAGND SAVDD GND PerData13 * PerData11 * GPIO00 * PerData08 * PerData03 * GND PerClk GPIO09 * PerWBE3 PerWBE0 PerOE PerAddr28 GND Signal Name Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 GND GND GPIO27 * GPIO03 * GPIO22 * PerData26 * PerData25 * GPIO13 * GPIO05 * GPIO15 * PerReady GPIO01 * PerData15 * PerData12 * PerData09 * PerData07 * PerData05 * PerData01 * ExtReset GPIO10 * PerCS0 * PerWBE2 PerRW PerAddr29 GND PerAddr27 Signal Name Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 GND GND GND GPIO25 * GPIO23 * PerData30 * USB2Clk PerData28 * GPIO02 * SysClk GPIO12 * GPIO06 * GPIO04 * PerData14 * PerData10 * PerData06 * PerData02 * PerData00 * PerErr GPIO08 * PerWBE1 PerAddr31 PerAddr30 GND PerAddr25 PerAddr21 Signal Name Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Signal Name GPIO31 * GPIO30 * GPIO29 * GND OVDD TmrClk OVDD OVDD GND VDD GPIO07 * EOVDD OVDD GND VDD PerData04 * VDD GND OVDD OVDD PerBLast OVDD GND PerAddr26 PerAddr22 PerAddr19 30 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7) Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 GND UARTSerClk GND OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PerAddr24 PerAddr18 PerAddr15 Signal Name Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 Signal Name GPIO21 * GPIO17 * GPIO20 * GPIO16 * No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball PerAddr23 PerAddr20 PerAddr16 PerAddr14 Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 Signal Name GPIO19 * GPIO18 * UART0Rx * OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PerAddr17 PerAddr13 PerAddr11 * Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 GND UART0Tx * GPIO11 * VDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PerAddr12 * PerAddr09 * GND Signal Name AMCC Proprietary 31 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7) Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 Signal Name PCIE0Rx PCIE0Rx AVDD GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND PerAddr10 * PerAddr08 * PerAddr07 * Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 Signal Name AGND PCIE0Tx PCIE0Tx AVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball VDD GND PerAddr06 * GPIO26 * Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 Signal Name PCIE0ClkC PCIE0ClkT PCIE0ATB AGND No ball No ball No ball No ball No ball No ball GND OVDD GND VDD OVDD GND No ball No ball No ball No ball No ball No ball SVREF2B TrcClk MemData04 MemData05 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 AVDD PCIE0RExtG PCIE0RExt AHVDD No ball No ball No ball No ball No ball No ball OVDD GND GND GND GND OVDD No ball No ball No ball No ball No ball No ball VDD MemData00 DM0 DQS0 Signal Name 32 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7) Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 Signal Name PCIE1Rx PCIE1Rx AVDD AVDD No ball No ball No ball No ball No ball No ball VDD GND GND GND GND GND No ball No ball No ball No ball No ball No ball SVDD MemData01 MemData06 GND Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 Signal Name AVDD PCIE1Tx PCIE1Tx AGND No ball No ball No ball No ball No ball No ball GND GND GND GND GND VDD No ball No ball No ball No ball No ball No ball GND MemData03 MemData02 MemData07 Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 Signal Name AGND PCIE1ATB PCIE1ClkT AHVDD No ball No ball No ball No ball No ball No ball OVDD GND GND GND GND SVDD No ball No ball No ball No ball No ball No ball VDD MemData08 MemData12 MemData13 Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 AVDD PCIE1ClkC PCIE1RExt PCIE1RExtG No ball No ball No ball No ball No ball No ball GND EOVDD VDD GND SVDD GND No ball No ball No ball No ball No ball No ball SVREF1B MemData09 DQS1 DM1 Signal Name AMCC Proprietary 33 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7) Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 GND GND GPIO28 VDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball VDD MemData11 MemData15 MemData14 Signal Name Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 TMS TCK OVDD GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND ECC0 ECC4 MemData10 Signal Name Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 GND TDI TDO OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD ECC1 ECC5 GND Signal Name Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Signal Name TRST TestEn IIC0SClk OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD MemClkEn DQS4 DM4 34 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7) Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 Signal Name IIC0SData IIC1SClk * SCPDI IIC1SData * No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball MemClkOut0 MemClkOut0 ECC7 ECC6 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 GND GMCTxD7 * GMCTxD6 * EOVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD MemAddr12 ECC3 ECC2 Signal Name Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 Signal Name GMCTxD5 * GMCTxD4 * GMCTxD3 * GND EOVDD GMCTxClk EOVDD EOVDD GND VDD GMCRxD0 * VDD GND SVREF1A VDD SVREF2A VDD GND SVDD SVDD MemAddr06 SVDD GND MemAddr11 MemAddr13 MemAddr14 Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Signal Name GMCTxD2 * GMCTxD1 * GND GMCCD * GMCTxEn * SysErr GMCRefClk SysReset GMCRxClk * GMCRxD2 * MemData27 Reserved DM3 SVDD MemData23 DM2 MemData21 MemODT0 RAS MemAddr01 MemAddr05 BA0 MemFBD GND MemAddr09 MemAddr10 AMCC Proprietary 35 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7) Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 Signal Name GMCTxD0 * GND GMCMDClk GMCGTxClk * GMCRxDV * GMCRxD7 * EAGND EAVDD GMCRxD4 * GMCRxD1 * MemData31 DQS3 MemData24 MemData28 MemData18 DQS2 MemData16 MemODT1 WE BankSel1 MemAddr00 MemAddr03 MemAddr07 BA2 GND MemAddr08 Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 GND GMCMDIO GMCTxEr * GMCCrS * GMCRxEr * GMCRxD6 * GMCRxD5 * GND GMCRxD3 * MemData26 MemData30 MemData25 MemData29 GND MemData19 MemData22 MemData17 MemData20 GND CAS BankSel0 MemAddr02 MemAddr04 BA1 MemFBR GND Signal Name Ball Signal Name Ball Signal Name 36 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Pin Group List The following table provides a summary of the number of package pins (balls) associated with each functional interface group. Table 5. Pin Groups Group Total Signal Pins VDD OVDD EOVDD SVDD GND AVDD AHVDD SAVDD SAGND EAVDD EAGND AGND Total Power Pins Reserved Total Pins No. of Pins 246 17 20 6 10 71 7 2 1 1 1 1 4 141 1 388 In the table “Signal Functional Description” on page 38, each external signal is listed along with a short description of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table, “Signals Listed Alphabetically” on page 17, for the pin (ball) number to which each signal is assigned. Shared Pins Some signals are shared on the same package pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that might share the same pin. If you need to know what, if any, signals are shared with a particular signal, look up the name in “Signals Listed Alphabetically” on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of sharing allows a single chip to offer a richer pin selection than would otherwise be possible. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Initialization” on page 65). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3kΩ to +3.3V and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logical zero or logical one state when accounting for the total input current into the PPC405EX. AMCC Proprietary 37 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Signal Functional Descriptions The following table provides a description of the I/O signals on the PPC405EX. Table 6. Signal Functional Description (Sheet 1 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes Ethernet Interface GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMII: Collision detect. RGMII 1: Receive clock. GMII: Carrier sense. RGMII 1: Transmit clock. GMII: Transmit clock for GMII 1000Mbps. RGMII 0: Transmit clock. Management data clock. Management data I/O. I I/O O O I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS receiver 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 1, 5 1, 5 1 GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0:3, GMC0RxD0:3 GMCRxD4:7, GMC1RxD0:3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0:3, GMC0TxD0:3 GMCTxD4:7, GMC1TxD0:3 GMCTxEn, GMC0TxCtl GMCTxEr, GMC1TxCtl GMII, RGMII: Reference clock for 1000Mbps. GMII: Receive clock. RGMII 0: Receive clock. GMII: Receive data. RGMII 0: Receive data. GMII: Receive data. RGMII 1: Receive data. GMII: Receive data valid. RGMII 0: Receive control. GMII: Receive error. RGMII 1: Receive control. GMII: Transmit clock for 10/100Mbps. GMII: Transmit data. RGMII 0: Transmit data. GMII: Transmit data. RGMII 1: Transmit data. GMII: Transmit enable. RGMII 0: Transmit control. GMII: Transmit error. RGMII 1: Transmit control. I I I I I I I O O O O 1, 5 1 1 1 1 1, 5 IIC Interface IIC0SClk IIC0SData IIC1SClk IIC1SData IIC Serial Clock. IIC Serial Data. IIC Serial Clock. IIC Serial Data. I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 2 2 1 1 38 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 2 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes PCI Express Interface (n = 0 and 1) PCIEnATB PCIEnClkC PCIEnClkT PCIEnRExt PCIEnRExtG PCIEnRx PCIEnRx PCIEnTx PCIEnTx Analog Test Bus for manufacturing test. Differential input for external reference clock. External reference resistor. Attach a 1.37 kΩ, 1% resistor between RExt and RExtG to provide the reference for both the bias currents and the impedance calibration circuitry. Differential receiver for received serial data. Differential driver for transmitted serial data. O I CML CML I/O CML I O LVDS receiver LVDS driver Interrupts Interface IRQ0:2 IRQ3:5 IRQ6 IRQ7:9 External interrupt requests. External interrupt requests. External interrupt requests. External interrupt requests. I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 1, 5 5 1, 5 JTAG Interface TCK TDI TDO TMS TRST Test clock. Test data in. Test data out. Test mode select. Test reset. Must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EX. I I O I I 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 1 1, 5 1 1, 4 AMCC Proprietary 39 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 3 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes System Interface SysClk System input clock. I 3.3V tolerant 2.5V CMOS receiver 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL receiver w/pull-down 3.3V LVTTL receiver w/pull-up 3.3V LVTTL receiver w/pull-up 3.3V LVTTL 1, 2 1 SysErr SysReset Machine check exception has occurred. Main system reset. This signal may be driven by the PPC405EX to cause a board level reset to occur. Test enable. Reserved for manufacturing LSSD test. O I/O TestEn I 3 Halt External request to stop the processor. I TmrClk Processor timer external input. General purpose I/O. Most of the GPIO signals are multiplexed with other signals. Which signal is connected to the external pin depends on the setting of bits in the GPIO registers. General purpose I/O. Most of the GPIO signals are multiplexed with other signals. Which signal is connected to the external pin depends on the setting of bits in the GPIO registers. Performance screen ring output. Use for module characterization and screening only. I GPIO00:27 GPIO29:31 I/O GPIO28 I/O 3.3V tolerant 2.5V CMOS 3 PSROUser O Trace Interface TrcClk TS0E TS1E TS0O TS1O TS0:3 Trace interface clock. Operates at half the CPU core frequency. Even trace execution status. Odd trace execution status. Trace status. O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 40 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 4 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes External Peripheral Interface PerAddr05:31 PerClk PerCS0 PerCS1:3 PerData00:31 PerDataPar0:3 PerOE PerReady PerBLast PerErr PerRW PerWBE0:3 ExtReset Address bus 5:31. Clock output. Chip selects 0. Chip selects 1:3. Data bus 0:31. Data bus parity 0:3. Output enable. Slave is ready to trasfer data. Last transfer of burst access. External bus error. Read/Write. Write Byte enable 0:3. External reset. I/O O O I/O I/O I/O O I I/O I/O I/O I/O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL receiver 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 4 1, 5 1, 2 1, 2 2 2 1, 2 External Bus Master Interface BusReq ExtAck ExtReq HoldReq HoldAck External bus request. External data transfer complete. External data transfer request. External request for bus access. External request acknowledge. I/O I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1 1 1, 4 1, 5 1 DMA Interface DMAAck0:1 DMAAck2:3 DMAReq0:1 DMAReq2 DMAReq3 DMAEOT0:1 DMAEOT2:3 External peripheral DMA acknowledge. External peripheral DMA acknowledge. External peripheral DMA request. External peripheral DMA request. External peripheral DMA request. External DMA peripheral end-of-transmission. External DMA peripheral end-of-transmission. I/O I/O I/O I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1 5 1, 5 5 5 1, 5 AMCC Proprietary 41 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 5 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes NAND Flash Interface NFALE NFCE0 NFCE1:3 NFCLE NFData00:15 NFRdyBusy NFRE NFWE Address latch enable. Chip select 0. Chip selects 1:3. Command latch enable. Data Bus Read/Busy. If low, indicates that Read/Erase command is in process. If high, indicates that the command is complete. Read enable. Write enable. I/O O I/O I/O I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 2 DDR1/2 SDRAM Interface MemData00:31 MemAddr00:14 RAS CAS MemClkEn MemClkOut0 MemClkOut0 MemFBD MemFBR MemODT0:1 DM0:4 DQS0:4 BA0:2 BankSel0:1 ECC0:7 WE Memory data. Memory address. Row address strobe. Column address strobe. Clock enable. Differential DDR SDRAM clock output. Feedback driver. Feedback receiver. Connect externally to MemFBD. On-die termination. Write data byte lane mask. DM4 is the byte lane mask for the ECC byte lane. Byte lane strobe. DQS4 is the strobe for the ECC lane. Bank address for up to eight banks. Bank select for up to two SDRAM memory banks. ECC check bit byte. Write enable. I/O O O O O O O I O O I/O O O I/O O 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 42 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 6 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name SVREF1A:B SVREF2A:B Description DDR 1 (DDR2) Reference voltage 1 and 2 inputs: Min. +1.15 (+0.825)V Nom. +1.25 (+0.9)V Max. +1.35 (0.975)V I/O Type 1.25V (0.9V) Volt ref receiver Notes I Serial Communication Port (SCP) Interface SCPClkOut SCPDI SCPDO Output clock. Data input. Data output. I/O I O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL UART Peripheral Interface The UART interface can be configured as follows: 1. One 8-pin 2. Two 4-pin 3. Two 2-pin (pull up DCD, DSR, CTS and RTS) 4. One 4-pin and one 2-pin UARTSerClk UARTnCTS UARTnDCD UARTnDSR UARTnDTR UARTnRI UARTnRTS UARTnRx UARTnTx Serial clock input. Clear to send. Data carrier detect. Data set ready. Data terminal ready. Ring indicator. Request to send. Receive data. Transmit data. I I/O I/O I/O I/O I/O I/O I O 3.3V LVTTL receiver w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL receiver w/pull-down 3.3V LVTTL 1, 6 1, 6 1, 6 1 1 1 USB 2.0 Interface USB2Clk USB2Data0:7 USB2Dir USB2Next USB2Stop USB clock. Parallel data bus. Data bus direction control. Next data byte control. When data is being transferred to the PHY, the next byte should be sent. When data is being received from the PHY, the next byte is available. Stop output control. I I/O I/O I/O I/O 3.3V LVTTL receiver 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 AMCC Proprietary 43 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 6. Signal Functional Description (Sheet 7 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes Power VDD OVDD SVDD EOVDD GND AVDD SAVDD SAGND EAVDD EAGND AHVDD AGND Logic supply (+1.2V). I/O supply (+3.3V). DDR1/2 SDRAM supply (+2.5 V or +1.8V) CMOS supply (+2.5V) System ground. Logic Analog supply (+1.2V) System analog supply (+2.5V). System analog ground. Ethernet analog supply (+2.5V). Ethernet analog ground. SerDes analog supply (+2.5V). Analog ground. na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na Other Reserved Do not connect voltages, grounds, or signals to these pins. na na na 44 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Ratings and Specifications Table 7. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings. Characteristic Supply Voltage (Internal Logic) Core SerDes Analog Supply Voltage PLL SerDes Analog Supply Voltage I/O Supply Voltage SDRAM DDR1(2) Supply Voltage CMOS Supply Voltage System PLL Analog Supply Voltage Ethernet PLL Analog Supply Voltage Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case Temperature Range under bias Junction Temperature Range Symbol VDD AVDD AHVDD OVDD SVDD EOVDD SAVDD EAVDD VIN TSTG TC TJMax Value 0 to +1.6 0 to +1.6 0 to +2.6 0 to +3.6 0 to +2.6 (+1.9) 0 to +2.6 0 to +2.6 0 to +2.6 0 to +3.6 −55 to +150 −40 to +120 −40 to +125 Unit V V V V V V V V V °C °C °C 1 1 1 1 Notes 1. The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering the PPC405EX. Use a separate filter for each voltage. This circuit can be used for AVDD, AHVDD , SAVDD, and EAVDD. Use AGND with AVDD and AHVDD. Use SAGND with SAVDD. Use EAGND with EAVDD. These analog grounds must be brought out and connected to the digital ground plane at the filter capacitor. Keep all wire lengths as short as possible. VDD L1 C1 AVDD L1 – Murata BLM18AG121SN1D C1 – 0.1 μF ceramic AGND GND AMCC Proprietary 45 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Thermal Management Table 8. Package Thermal Specifications The PPC405EX is designed to operate within a case temperature range TC defined in “Recommended DC Operating Conditions” on page 47. Thermal resistance values for the EPBGA packages in a convection environment are as follows: Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: 1. Values in the table are achieved with the following JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC – PxθCA, where TA is ambient temperature and P is power consumption. c. TC Max = TJ Max – PxθJC, where TJMax is maximum junction temperature and P is power consumption. Symbol 0 (0) 100 (0.51) 16.6 200 (1.02) 15.8 Airflow ft/min (m/sec) 300 (1.52) 15.4 400 (2.02) 15.0 500 (2.53) 14.7 600 (3.03) 14.4 °C/W Unit θJA θJA 18.9 15.5 12.5 11.4 10.9 Resistance Value 10.7 10.5 10.3 °C/W θJC θJB 8.96 13.74 °C/W °C/W The following heat sink was used in the above thermal analysis: 26.92mm x 27mm x 11.43mm The heat sink is manufactured by: Aavid Thermalloy, P/N 62925 46 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 9. Recommended DC Operating Conditions (Sheet 1 of 2) Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage SDRAM DDR1(2) Supply Voltage CMOS Supply Voltage Symbol VDD OVDD SVDD EOVDD AHVDD PLL Analog Supply Voltage SAVDD EAVDD Analog Supply Voltage I/O Input Low (3.3V LVTTL) I/O Input High (3.3V LVTTL) I/O Output Low (3.3V LVTTL) I/O Output High (3.3V LVTTL) I/O Input Low (3.3V tol, 2.5V CMOS) I/O Input High (3.3V tol, 2.5V CMOS) I/O Output Low (3.3V tol, 2.5V CMOS) I/O Output High (3.3V tol, 2.5V CMOS) I/O Input Low DDR1 (DDR2) (SSTL2) I/O Input High DDR1 (DDR2) (SSTL2) I/O Output Low DDR1 (DDR2) (SSTL2) I/O Output High DDR1 (DDR2) (SSTL2) I/O Input Common-Mode I/O Input Low (LVDS) I/O Input High (LVDS) I/O Output Low (LVDS) I/O Output High (LVDS) Input Leakage Current (no pull-up or pull-down) Input Leakage Current (with internal pull-down) Input Leakage Current (with internal pull-up) AVDD VIL VIH VOL VOH VIL VIH VOL VOH VIL VIH VOL VOH VICM VIL VIH VOL VOH IIL1 IIL2 IIL3 +1.1 0 +2.0 0 +2.4 0 +1.7 0 +2.0 − 0.3 SVREF + 0.18 (0.125) +1.2 +1.2 +0.8 +3.6 +0.4 +3.6 +0.7 +3.6 +0.4 +2.7 SVREF − 0.18 (0.125) SVDD + 0.3 V V V V V V V V V V V V V V V V V V +2.4 +2.5 +2.6 V Minimum +1.1 +3.15 +2.4 (+1.7) +2.4 Typical +1.2 +3.3 +2.5 (+1.8) +2.5 Maximum +1.3 +3.45 +2.6 (+1.9) +2.6 Unit V V V V Notes See JESD8-9 (JESD8-15A) standard. See JESD8-9 (JESD8-15A) standard. 0 − 0.3 VICM + 0.05 +0.832 +1.243 0 0 (LPDL) −150 (LPDL) +1.01 +1.377 VDD VICM − 0.05 +1.9 +1.197 +1.509 1 200 (MPUL) 0 (MPUL) μA μA μA 1 1 AMCC Proprietary 47 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 9. Recommended DC Operating Conditions (Sheet 2 of 2) Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter I/O Maximum Allowable Overshoot (3.3V LVTTL) I/O Maximum Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: 1. LPDL is least positive down level; MPUL is most positive up level. Symbol VMAO VMAU TC −0.6 −40 Minimum Typical Maximum +3.9 0 +85 Unit V V °C Notes Table 10. I/O Input Capacitance Parameter 3.3V LVTTL 2.5V CMOS 2.5/1.8V SSTL2 PCI Express differential data receiver PCI Express differential data transmitter PCI Express differential clock receiver Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 Maximum 2.3 2.1 3.2 1.59 1.16 0.188 Unit pF pF pF pF pF pF Notes 48 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM Frequency (MHz) 333 400 533 667 Notes: 1. 2. 3. 4. 5. Values are estimates and subject to change. DDR1 running at 333MHz., PLB running at 166MHz. DDR1 running at 400MHz., PLB running at 200MHz. DDR1 running at 355MHz., PLB running at 177MHz. DDR1 running at 333MHz., PLB running at 166MHz. +1.2V 1.15 1.25 1.25 1.27 +1.8V 0 0 0 0 +2.5V 0.54 0.60 0.58 0.54 +3.3V 0.10 0.14 0.12 0.10 Total 1.79 1.99 1.95 1.91 Unit W W W W Notes 1, 2 1, 3 1, 4 1, 5 Table 12. Typical DC Power Supply Requirements with DDR2 SDRAM Frequency (MHz) 333 400 533 667 Notes: 1. 2. 3. 4. 5. Values are estimates and subject to change. DDR2 running at 333MHz., PLB running at 166MHz. DDR2 running at 400MHz., PLB running at 200MHz. DDR2 running at 355MHz., PLB running at 177MHz. DDR2 running at 333MHz., PLB running at 166MHz. +1.2V 1.15 1.25 1.25 1.27 +1.8V 0.26 0.28 0.27 0.26 +2.5V 0.17 0.17 0.20 0.17 +3.3V 0.10 0.14 0.12 0.10 Total 1.689 1.84 1.84 1.80 Unit W W W W Notes 1, 2 1, 3 1, 4 1, 5 Table 13. DC Power Supply Loads with DDR1 SDRAM Parameter VDD (+1.2V) active operating current AVDD (+1.2V) active operating current AHVDD (+2.5V) active operating current OVDD (+3.3V) active operating current SVDD + EOVDD (+2.5V) active operating current SAVDD (+2.5V) active operating current EAVDD (+2.5V) active operating current Notes: 1. Typical and Maximum values are estimates and subject to change. Symbol IDD1.2 IADD IAHDD IODD IDD ISADD IEADD Typical 920 40 100 40 200 100 100 Maximum 1390 50 120 50 240 120 120 Unit mA mA mA mA mA mA mA Notes 1 1 1 1 1 1 1 AMCC Proprietary 49 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 14. DC Power Supply Loads with DDR2 SDRAM Parameter VDD (+1.2V) active operating current AVDD (+1.2V) active operating current AHVDD (+2.5V) active operating current OVDD (+3.3V) active operating current SVDD (+1.8V) active operating current EOVDD (+2.5V) active operating current SAVDD (+2.5V) active operating current EAVDD (+2.5V) active operating current Notes: 1. Typical and Maximum values are estimates and subject to change. Symbol IDD IADD IAHDD IODD ISDD IEODD ISADD IEADD Typical 920 40 100 40 180 20 100 100 Maximum 1390 50 120 50 210 30 120 120 Unit mA mA mA mA mA mA mA mA Notes 1 1 1 1 1 1 1 1 Test Conditions Clock timing and switching characteristics are specified in accordance with minimum operating conditions shown in the table “Recommended DC Operating Conditions” on page 47. For all signals, AC specifications are characterized at TC = 85°C with the test load shown in the figure to the right. Table 15. System Clocking Specifications Symbol CPU PFC SysClk Input SCFC SCTCS SCTCH SCTCL SCRT Other Clocks VCOFC PLBFC OPBFC VCO frequency PLB frequency OPB frequency 600 133 66 1800 200 100 MHz MHz MHz Frequency Edge stability (phase jitter, cycle-to-cycle) High time (% of nominal period) Low time (% of nominal period) Rise time 33.33 na 40 40 na 100 ± 0.1 60 60 0.4 MHz ns % % ns Processor clock frequency (must be ≥ SCFC) 333.33 666.66 MHz Parameter Min Max Units Output Pin 10pF 50 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Figure 3. Clocking Waveform Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant) signals. Rise time should be measured between 0.7V and 1.7V. 1.7 (2.0) V 1.25 (1.5) V 0.7 (0.8) V TCH TC TCL AMCC Proprietary 51 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Spread Spectrum Clocking Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EX. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EX the following conditions must be met: • The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405EX with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. • The maximum frequency deviation must not exceed −3%, and the modulation frequency must not exceed 40kHz. In some cases, on-board PPC405EX peripherals impose more stringent requirements (see Note 1). • Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Caution: The system designer must ensure that any SSCG used with the PPC405EX meets these requirements and does not adversely affect other aspects of the system. 52 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 16. Peripheral Interface I/O Clock Timings Clock GMCTxClk frequency GMCTxClk high time GMCTxClk low time GMCRxClk frequency GMCRxClk high time GMCRxClk low time GMCGTxClk GMCMDClk GMCRefClk GMCRefClk edge stability (phase jitter, cycle-to-cycle) GMCRefClk rise time GMCRefClk high time GMCRefClk low time GMCnRxClk GMCnTxClk UARTSerClk TmrClk PerClk TCK USB2Clk (60MHz ± 0.05%) PCIEnClkC, T (Differential clock input) Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The maximum OPB clock frequency is 100MHz. na 57.97 100 na Min 125 45% of nominal 55% of nominal 125 45% of nominal 55% of nominal 125 2.5 125 na na 40% of nominal 60% of nominal 125 125 Max 125 – – 125 – – 125 25 125 ± 0.1 0.4 – – 125 125 1000/(2TOPB1 + 2ns) 100 100 20 60.03 250 Units MHz ns ns MHz ns ns MHz MHz MHz ns ns ns ns MHz MHz MHz MHz MHz MHz MHz MHz AMCC Proprietary 53 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Figure 4. Input Setup and Hold Timing Waveform Clock 1.25 (1.5)V TIS MIN Inputs 1.25 (1.5)V Valid TIH MIN Figure 5. Output Delay and Float Timing Waveform Clock 1.25 (1.5)V TOV MAX TOH MIN Outputs 1.25 (1.5)V Valid MAX TOF MIN 1.25 (1.5)V Outputs 1.25 (1.5)V 54 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 17. I/O Specifications—All CPU Speeds (Sheet 1 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal PCI Express Interface PCIEnATB PCIEnRx PCIEnRx PCIEnTx PCIEnTx Ethernet GMII Interface GMCCD GMCCrS GMCMDIO GMCRxD0:7 GMCTxD0:7 GMCRxDV GMCRxEr GMCTxEr GMCTxEn GMCMDIO GMCnRxD0:3 GMCnRxCtl GMCnTxD0:3 GMCnTxCtl Internal Peripheral Interface IICnSData UARTnCTS UARTnRTS UARTnDSR UARTnDCD UARTnDTR UARTnRI UARTnRx UARTnTx SCPDI SCPDO USB2Data0:7 USB2Dir USB2Next USB2Stop DMA Interface DMAAck0:3 DMAReq0:3 DMAEOT0:3 Interrupts Interface IRQ0:9 AMCC Proprietary 15.75 10.46 55 2.8 2.8 2.8 1 1 1 5.3 5.3 5.3 1.0 1.0 1.0 15.75 15.75 15.75 10.46 10.46 10.46 4 4 4 4 0 0 0 0 5 5 5 5 2 2 2 2 15.75 15.75 15.75 15.75 15.75 15.75 15.75 na 15.75 na 15.75 15.75 15.75 15.75 15.75 10.46 10.46 10.46 10.46 10.46 10.46 10.46 na 10.46 na 10.46 10.46 10.46 10.46 10.46 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 1 1 1 1 1 00 00 00 00 00 00 00 00 00 1 1 1 1 1 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.8 2.8 2.8 2.8 2.8 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 1.2 1.2 1.2 1.2 1.2 na 5.51 5.51 na 5.51 na na 5.51 5.51 5.51 na na 5.51 5.51 na 7.23 7.23 na 7.23 na na 7.23 7.23 7.23 na na 7.23 7.23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 na na na na na na Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) IOH (min) IOL (min) Clock Notes Ethernet RGMII Interface (n = 0 or 1) PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 17. I/O Specifications—All CPU Speeds (Sheet 2 of 2) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal JTAG Interface TCK TDI TDO TMS TRST System Interface GPIO00:10 GPIO11:15 GPIO16:27 GPIO28 GPIO29:31 Halt SysErr SysReset TestEn 11.08 5.51 11.08 15.75 11.08 na 5.51 5.51 na 7.37 7.23 7.37 10.46 7.37 na 7.23 7.23 na na na 15.75 na na na na 10.46 na na Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) IOH (min) IOL (min) Clock Notes 56 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 18. I/O Specifications—333 MHz to 667 MHz CPU Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) IOH (minimum) 11.08 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11.08 11.08 11.08 11.08 11.08 na 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 IOL (minimum) 7.37 7.37 7.37 7.37 7.37 7.37 na 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 Clock Notes External Peripheral Interface PerClk PerAddr05:31 PerCS0:3 PerData00:31 PerDataPar0:3 PerOE PerReady PerRW PerWBE0:3 PerBLast PerErr ExtReset BusReq HoldReq HoldAck ExtAck ExtReq NFALE NFCE0:3 NFCLE NFData0:15 NFRdyBusy NFREn NFWEn PLB Clk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk 1 AMCC Proprietary 57 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet DDR 1/2 SDRAM I/O Specifications The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the same frequency as the PLB clock signal and is in phase with the PLB clock signal. Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual). The signals are terminated as indicated in Figure 6 for the DDR timing data in the following sections. Board Layout Restrictions TBP Clocking TBP Figure 6. DDR SDRAM Simulation Signal Termination Model MemClkOut 10pF 120 Ω 10pF MemClkOut VTT = SOVDD/2 50 Ω Addr/Ctrl (DDR2) Addr/Ctrl/Data/DQS/DM (DDR1) PPC405EX 30pF Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. It is not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout. DDR2 SDRAM On-Die Termination Impedance Setting For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations. 58 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 19. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:31 ECC0:7 DM0:4 MemClkOut MemAddr00:14 BA0:2 RAS CAS WE BankSel0:1 MemClkEn DQS0:4 MemODT0:1 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Output Current (mA) I/O H (maximum) I/O L (maximum) DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated over best case and worst case processes with speed, junction temperature, and voltage as follows: Table 20. DDR SDRAM Write Operation Conditions Case Best Worst Process Speed Fast Slow Junction Temperature (°C) −40 +125 Voltage (V) +1.3 +1.1 Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions. The timing numbers in the following sections are obtained using a simulation that assumes a model as shown in Figure 6. AMCC Proprietary 59 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 7. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut TSA Addr/Cmd TSK THA TDS TDS DQS TSD MemData THD TSD THD TSK = Delay from rising edge of MemClkOut to rising/falling edge of signal (skew) TSA = Setup time for address and command signals to MemClkOut THA = Hold time for address and command signals from MemClkOut TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ) THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ) TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS Note: The timing data in the following tables is based on simulation runs using Einstimer. Table 21. I/O Timing—DDR SDRAM TDS Notes: 1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle. 2. Clock speed is 200MHz. Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 TDS (ns) Minimum 4 4 4 4 4 Maximum 6 6 6 6 6 60 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 22. I/O Timing—DDR SDRAM TSK, TSA, and THA Signal Name MemAddr00:14 BA0:2 BankSel0:1 MemClkEn CAS RAS WE 0.20 0.20 +2.3 +2.3 TSK (ns) Minimum Maximum TSA (ns) Minimum THA (ns) Minimum Table 23. I/O Timing—DDR SDRAM Write TimingTSD and THD Notes: 1. TSD and THD are measured under worst case conditions. 2. Clock speed for the values in the table is 200MHz. 3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns). 4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (for example, TSD − 1.25 + 0.25TCYC). Signal Names MemData00:07, DM0 MemData08:15, DM1 MemData16:23, DM2 MemData24:31, DM3 ECC0:7, DM4 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 TSD (ns) 0.84 0.84 0.84 0.84 0.84 THD (ns) 1.15 1.15 1.15 1.15 1.15 DDR SDRAM Read Operation The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS signal. The Data must be centered to these edges for correct operation. The PPC405EX can delay with very fine granularity the DQS through register programming. DDR SDRAM MemClkOut0 and Read Clock Delay In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency. The data is stored in the eight Flip Flops of the Stage 1, such that it can be transferred later within a 8x period. AMCC Proprietary 61 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Figure 8. DDR SDRAM Read Data Path Ext FeedBack Signals DDR 1X Clock FF: Flip-Flop MemDCFdbkD Driver Coarse Delay FeedBack Signal Gen CAS Lat Delay Read Start Read Latency adjust circuit Rec Fine Delay DDR 1X Clock Stage 2 Store DQS aligned FBK signal Feedback Data Capture Window 0 Cycles Delay +1 Oversampling Fine Delay MemDCFdbkR T1 T2 T3 T4 adjust 1 7 Q2_Ovs 0 2 4 6 Oversampling Clock Package pins Mux FF D FF FF C Q2 Compare (x32) Mux Read FIFO Upper PLB bus [0:63] DQ Data (x32) DQS Rising Edge Sync Stage 1 FF 1 3 5 7 Stage 2 FF FF (x32) C Lower Stage 3 Q3 D FF PLB bus [64:127] DQS Programmed Read DQS Delay DQS Falling Edge Sync DDR 1X Clock PLB 1X Clock DDR SDRAM Read Cycle Timing The following diagram illustrates the relationship of the signals involved with a DDR read operation. Figure 9. DDR SDRAM Memory Data and DQS DQS TSD MemData THD 62 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Table 24. I/O Timing—DDR SDRAM Read Timing TSD and THD 1. TSD and THD are measured under worst case conditions. 2. Clock speed for the values in the table is 200MHz. 3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns). 4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.25 + 0.25TCYC). Signal Names MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 Read Data vs DQS Set up TSD (ns) 0.35 0.35 0.35 0.35 0.35 Read Data vs DQS Hold THD (ns) 0.45 0.45 0.45 0.45 0.45 In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal routing. It is recommended that the signal length for all of the DQS signals be matched. The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the data in Stage 1. AMCC Proprietary 63 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Figure 10. DDR SDRAM Read Cycle Timing—Example Oversampling Guard Band DDR 1X Clock DDR 2X Clock Memclk (Diff.) DQS at MemCntl Pin Data at Pin D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Feedback Output DDR 1X Clock cycle Delayed DQS T1 Store 1st Data in Stage 2 T2 T3 T4 Data Out Stage 1 (0) Data Out Stage 1 (1) Data out Stage 1 (2) Valid High Data Out Stage 2 Low D1 D0 D2 D3 PLB 1X Clock 64 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Initialization The following describes the method by which initial chip settings are established when a system reset occurs. Strapping When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default initial conditions before PPC405EX start-up. The actual instant of capture is the nearest system clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V, or 10kΩ to +5V. The recommended pull-down is 1KΩ to GND. These pins are only used for strap functions during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation appear below the pin number. Table 25. Strapping Pin Assignments Pin Strapping Initialization Source EBC 8-bit wide ROM EBC 16-bit wide ROM EBC 16-bit wide ROM EBC 8-bit wide NAND Flash EBC 8-bit wide NAND Flash IIC ROM at address 0xA8 EBC 8-bit wide ROM IIC ROM at address 0xA4 Option A B C D E G F H F04 (UART0DCD) 0 0 0 0 1 1 1 1 F02 (UART0DSR) 0 0 1 1 0 0 1 1 G02 (UART0CTS) 0 1 0 1 0 1 0 1 Note: See the PPC405EX Embedded Processor User’s Manual for option descriptions and other details regarding the boot process. AMCC Proprietary 65 PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Revision Log Date 02/27/2007 03/01/2007 Version 1.00 1.01 Initial creation of document. Updates following review of initial document. Change package drawing to eliminate confusion. Expand system memory map. Define FSource0 signal as Reserved. Add Recommended Operating Conditions data. Add thermal data. Misc. updates and additions. Misc. updates and additions including some limited timing data. Correct one of three ball numbers assigned to PerData28. Swap four balls between VDD and GND. 05/24/2007 1.04 Swap one ball between OVDD and SVDD. Correct typographical errors in Table 3. Add missing alphabetical entries for PerAddr05, NAND Flash, and IIC1. Add output current values to Tables 15 and 16. Input various review comments. Update Table 6 Notes column. Update Block Diagram. Swap SAVDD an EAVDD signal name assignments on package balls. 06/04/2007 1.05 Add two UART configurations. Add DDR SDRAM section extracted from 460EX with changes appropriate for 405EX. Update timing information for all interfaces. Add power values. Update I/O capacitance values. Remove Confidential status. Input various review comments. Input review comments and corrections. Change default signals for GPIO balls to GPIO00–GPIO27 signals. Eliminate confusing terminology in initialization section. Change voltage names so that SDRAM voltage is always SVDD for both DDR1 and DDR2 types. Six voltage pins originally labeled SVDD changed to EOVDD. Update GMCRefClk specifications (rise time, jitter, etc.) Contents of Modification 03/22/2007 1.02 04/24/2007 1.03 06/07/2007 1.06 06/28/2007 1.07 07/12/2007 08/21/2007 1.08 1.09 66 AMCC Proprietary PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 Preliminary Data Sheet Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation. AMCC Proprietary 67