440GX

Part Number 440GX Revision 1.15 – August 30, 2007 440GX Power PC 440GX Embedded Processor Features • PowerPC® 440 processor core operating up to 800MHz with 32KB I- and D-caches (with parity checking) • On-chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory • Selectable processor:bus clock ratios (Refer to the Clocking chapter in the PPC440GX Embedded Processor User’s Manual for details) • Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 166MHz (200MHz for 800MHz Rev F parts) • External Peripheral Bus (32 bits) for up to eight devices with external mastering • DMA support for external peripherals, internal UART and memory • PCI-X V1.0a interface (32 or 64 bits, up to 133MHz) with support for conventional PCI V2.3 • Two Ethernet 10/100/1000Mbps half- or fullduplex interfaces. Operational modes supported are SMII, GMII, RGMII, TBI and RTBI. Data Sheet • TCP/IP Acceleration Hardware (TAH) provided for 10/100/1000 Mbps ports that performs checksum processing, TCP segmentation, and includes support for jumbo frames • Programmable Interrupt Controller supports interrupts from a variety of sources. • I2O Messaging unit for message transfer between the CPU and PCI-X • Programmable General Purpose Timers (GPT) • Two serial ports (16750 compatible UART) • Two IIC interfaces • General Purpose I/O (GPIO) interface available • JTAG interface for board level testing • Processor can boot from PCI memory • Available in ceramic (RoHs and non-RoHS compliant versions) and plastic packages (RoHS and non-RoHS compliant versions). Description Designed specifically to address high-end embedded applications, the PowerPC 440GX (PPC440GX) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, DDR SDRAM controller, configurable 256KB SRAM to be used as L2 cache or softwarecontrolled on-chip memory, PCI-X bus interface, Gigabit Ethernet interfaces, TCP/IP acceleration hardware, I2O messaging unit, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: CMOS Cu-11, 0.13 μm Packages: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) or Plastic Ball Grid Array (PBGA) in standard or RoHS compliant versions Power (estimated): Less than: 4W typical @533MHz 5W typical @667MHz 6W typical @800MHz (estimated) Supply voltages required: 3.3V, 2.5V, 1.5V AMCC 1 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLB Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2O Messaging Unit (IMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Figures PPC440GX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 25mm, 552-Ball Ceramic (CBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Tables Order Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O Specifications—500MHz–800MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O Timing—DDR SDRAM TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I/O Timing—DDR SDRAM TSK, TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 I/O Timing—DDR SDRAM TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I/O Timing—DDR SDRAM TSIN and TDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 AMCC 3 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Ordering and PVR Information For information on the availability of the following parts, contact your local AMCC sales office. Order Part Numbers Product Name PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX PPC440GX Order Part Number (See Notes and Key drawing) PPC440GX-3CC533S PPC440GX-3CC667S PPC440GX-3CF400C PPC440GX-3CF533C PPC440GX-3CF533CZ PPC440GX-3CF533E PPC440GX-3CF667C PPC440GX-3CF667CZ PPC440GX-3CF800C PPC440GX-3CF800CZ PPC440GX-3FF533C PPC440GX-3FF533E PPC440GX-3FF667C PPC440GX-3FF667E PPC440GX-3RF400C PPC440GX-3RF533C PPC440GX-3RF533CZ PPC440GX-3RF533E PPC440GX-3RF667C PPC440GX-3RF667CZ PPC440GX-3RF800C PPC440GX-3RF800CZ Processor Frequency 533MHz 667MHz 400MHz 533MHz 533MHz 533MHz 667MHz 667MHz 800MHz 800MHz 533MHz 533MHz 667MHz 667MHz 400MHz 533MHz 533MHz 533MHz 667MHz 667MHz 800MHz 800MHz Package 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA 25mm, 552 CBGA Rev Level C C F F F F F F F F F F F F F F F F F F F F PVR Value 0x51B21892 0x51B21892 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 0x51B21894 JTAG ID 0x32054049 0x32054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 0x52054049 4 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Order Part Numbers (Continued) Product Name PPC440GX PPC440GX PPC440GX PPC440GX Notes: 1. Package code: C = leaded ceramic, F = plastic, R = reduced-lead ceramic (RoHS compliant), N = lead-free plastic (RoHS compliant). 2. Case Temperature Range code: C = -40 °C to +85 °C, E = -40 °C to +105 °C for C package and -40 °C to +100 °C for F package, S = 40 °C to +85 °C and no L2 cache support. 3. Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray. 4. Revision code: C = rev 2.1, F = rev 3.1. Order Part Number (See Notes and Key drawing) PPC440GX-3NF533C PPC440GX-3NF533E PPC440GX-3NF667C PPC440GX-3NF667E Processor Frequency 533MHz 533MHz 667MHz 667MHz Package 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 PBGA 25mm, 552 PBGA Rev Level F F F F PVR Value 0x51B21894 0x51B21894 0x51B21894 0x51B21894 JTAG ID 0x52054049 0x52054049 0x52054049 0x52054049 Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440GX User’s Manual for details on accessing these registers. Order Part Number Key PPC440GX-3CC800Ex Shipping Package Part Number Grade 3 Reliability Package Case Temperature Range Processor Speed Revision Level AMCC 5 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet PPC440GX Functional Block Diagram Universal Interrupt Controller Clock Control Reset Timers MMU 63 internal 18 external Power Mgmt DCRs PPC440 Processor Core JTAG 32KB D-Cache Trace 32KB I-Cache Arb DCR Bus GP Timers GPIO IIC x2 UART x2 On-chip Peripheral Bus (OPB) L2 Controller SRAM 256KB DMA Controller (4-Channel) OPB Bridge Processor Local Bus (PLB) TAH External External Bus Master Bus Controller Controller 83MHz max 32-bit addr 32-bit data MAL 10/100 10/100/ x2 1000 x2 Ethernet I2O Messaging PCI-X Bridge DDR SDRAM Controller RGMII Bridge 1 GMII or 2 RGMII or 1 TBI or 2 RTBI ZMII Bridge 1 MII or 2 RMII or 4 SMII 133MHz max 166MHz max 32/64-bit data 13-bit addr 32/64-bit data The PPC440GX is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional blocks are integrated together to create an application-specific product (ASIC). This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture. Note: IBM CoreConnect buses provide: • 128-bit PLB interfaces up to 200MHz • 32-bit OPB interfaces up to 83.33MHz, 333MB/s Address Maps The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GX processor through the use of mtdcr and mfdcr instructions. 6 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet System Memory Address Map Function DDR SDRAM SRAM Local Memory1 Reserve IMU EBC Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved OPB Arbiter Reserved Internal Peripherals (Sheet 1 of 2) Sub Function Start Address 0 0000 0000 0 8000 0000 0 8000 4000 0 FFFF 0000 1 0000 0000 1 4000 0000 1 4000 0200 1 4000 0208 1 4000 0300 1 4000 0308 1 4000 0400 1 4000 0420 1 4000 0500 1 4000 0520 1 4000 0600 1 4000 0640 1 4000 0700 1 4000 0780 1 4000 0790 1 4000 07A0 1 4000 0800 1 4000 0900 1 4000 0A00 1 4000 0B00 1 4000 0C00 1 4000 0D00 1 4000 0E00 1 4000 0F00 1 F000 0000 1 FFE0 0000 End Address 0 7FFF FFFF 0 8000 3FFF 0 FFFE FFFF 0 FFFF FFFF 1 3FFF FFFF 1 4000 01FF 1 4000 0207 1 4000 02FF 1 4000 0307 1 4000 03FF 1 4000 041F 1 4000 04FF 1 4000 051F 1 4000 05FF 1 4000 063F 1 4000 06FF 1 4000 077F 1 4000 078F 1 4000 079F 1 4000 07FF 1 4000 08FF 1 4000 09FF 1 4000 0AFF 1 4000 0BFF 1 4000 0CFF 1 4000 0DFF 1 4000 0EFF 1 EFFF FFFF 1 FFDF FFFF 1 FFFF FFFF 254MB 2MB 256B 256B 256B 256B 256B 256B 256B 128B 16B 16B 64B 32B 32B 8B 8B 64KB 1GB Size 2GB 256KB GPIO Controller Ethernet PHY ZMII Ethernet PHY GMII Reserved Ethernet 0 Controller Ethernet 1 Controller General Purpose Timer TCPIP Accelerator 0 Ethernet 2 Controller TCPIP Accelerator 1 Ethernet 3 Controller Reserved Expansion ROM2 Boot ROM2, 3 AMCC 7 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet System Memory Address Map Function Reserved PCI-X I/O Reserved PCI-X External Configuration Registers PCI-X Reserved PCI-X Bridge Core Configuration Registers Reserved PCI-X Special Cycle PCI-X Memory Notes: 1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map. 2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended. 3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB). (Sheet 2 of 2) Sub Function Start Address 2 0000 0000 2 0800 0000 2 0C00 0000 2 0EC0 0000 2 0EC0 0008 2 0EC8 0000 2 0EC8 0100 2 0ED0 0000 2 0EE0 0000 End Address 2 07FF FFFF 2 0BFF FFFF 2 0EBF FFFF 2 0EC0 0007 2 0EC7 FFFF 2 0EC8 00FF 2 0EC8 00FF 2 0EDF FFFF F FFFF FFFF 1MB 55.76 GB 256B 8B 64MB Size 8 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet DCR Address Map 4KB of Device Configuration Registers Function Total DCR Address Space1 By function: Reserved Clocking Power On Reset System DCRs Memory Controller External Bus Controller External Bus Master I/F PLB Performance Monitor SRAM L2 Controller Reserved PLB PLB to OPB Bridge Out Reserved OPB to PLB Bridge In Power Management Reserved Interrupt Controller 0 Interrupt Controller 1 Clock, Control, and Reset Reserved DMA Controller Reserved Ethernet MAL Base Interrupt Controller Interrupt Controller 2 Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 bytes). 000 00C 00E 010 012 014 016 020 030 040 080 090 0A0 0A8 0B0 0B8 0C0 0D0 0E0 0F0 100 140 180 200 210 220 00B 00D 00F 011 013 015 01F 02F 03F 07F 08F 09F 0A7 0AF 0B7 0BF 0CF 0DF 0EF 0FF 13F 17F 1FF 20F 21F 3FF 12W 2W 2W 2W 2W 2W 10W 16W 16W 64W 16W 16W 8W 8W 8W 8W 16W 16W 16W 16W 64W 64W 128W 16W 16W 480W Start Address 000 End Address 3FF Size 1KW (4KB)1 AMCC 9 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include: • Up to 800MHz operation • PowerPC Book E architecture • 32KB I-cache, 32KB D-cache - UTLB Word Wide parity on data and tag address parity with exception force • Three logical regions in D-cache: locked, transient, normal • D-cache full line flush capability • 41-bit virtual address, 36-bit (64GB) physical address • Superscalar, out-of-order execution • 7-stage pipeline • 3 execution pipelines • Dynamic branch prediction • Memory management unit - 64-entry, full associative, unified TLB with parity - Separate instruction and data micro-TLBs - Storage attributes for write-through, cache-inhibited, guarded, and big or little endian • Debug facilities - Multiple instruction and data range breakpoints - Data value compare - Single step, branch, and trap events - Non-invasive real-time trace interface • 24 DSP instructions - Single-cycle multiply and multiply-accumulate - 32 x 32 integer multiply - 16 x 16 -> 32-bit MAC Internal Buses The PowerPC 440GX features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. Features include: • PLB - 128-bit implementation of the PLB architecture - Separate and simultaneous read and write data paths - 64-bit address - Simultaneous control, address, and data phases - Four levels of pipelining - Byte enable capability supporting unaligned transfers - 32- and 64-byte burst transfers - 166MHz, maximum 5.2GB/s (simultaneous read and write)(200MHz for 800MHz Rev F parts) - Processor:bus clock ratios of N:1 and N:2 10 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet • OPB - Dynamic bus sizing 32-, 16-, and 8-bit data path - 36-bit address - 83.33MHz, maximum 333MB/s • DCR - 32-bit data path - 10 bit address On-Chip SRAM Features include: • Four banks of 64KB each for a total of 256KB • Configurable as either Code (L2) cache or software-controlled on-chip memory, or SRAM • Memory cycles supported: - Single beat read and write, 1 to 16 bytes - 32- and 64-byte burst transfers - Guarded memory accesses • Sustainable 2.6GB/s peak bandwidth at 166MHz • Use as an L2 cache improves processor performance and reduces the PLB load - Cache coherency maintained by a hardware snoop mechanism or software - Data Array and Tag Array parity - Unified data and instruction cache - 4-way set associative - 36-bit addressing - Full LRU replacement algorithm - Write through, look aside • Use as Ethernet packet store allows Ethernet packets to be held for processing by the TAH unit PCI-X Interface The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI 32/64-bit conventional mode, compatible with PCI Version 2.3, is also supported. Reference Specifications: • PowerPC CoreConnect Bus (PLB) Specification Version 3.1 • PCI Specification Version 2.3 • PCI Bus Power Management Interface Specification Version 1.1 Features include: • PCI-X 1.0a - Split transactions - Frequency to 133MHz - 32- and 64-bit bus • PCI 2.3 backward compatibility - Frequency to 66MHz - 32- and 64-bit bus • Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface • Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter • Support for Message Signaled Interrupts AMCC 11 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet • • • • • • • Simple message passing capability Asynchronous to the PLB PCI Power Management 1.1 PCI register set addressable both from on-chip processor and PCI device sides Ability to boot from PCI-X bus memory Error tracking/status Supports initiation of transfer to the following address spaces: - Single beat I/O reads and writes - Single beat and burst memory reads and writes - Single beat configuration reads and writes (type 0 and type 1) - Single beat special cycles DDR SDRAM Memory Controller The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: • Registered and non-registered industry standard DIMMs • 64-bit memory interface with optional 8-bit ECC (SEC/DED) • Sustainable 2.6GB/s peak bandwidth at 166MHz (200MHz for 800MHz Rev F parts) • SSTL_2 logic • 1 to 4 chip selects • CAS latencies of 2, 2.5 and 3 supported • DDR200/266/333 support • Page mode accesses (up to eight open pages) with configurable paging policy • Programmable address mapping and timing • Hardware and software initiated self-refresh • Power management (self-refresh, suspend, sleep) External Peripheral Bus Controller (EBC) Features include: • Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported • Up to 83.33MHz operation (333MB/s) • Burst and non-burst devices • 8-, 16-, 32-bit byte-addressable data bus • 32-bit address, 4GB address space • Peripheral Device pacing with external “Ready” • Latch data on Ready, synchronous or asynchronous • Programmable access timing per device - 256 Wait States for non-burst - 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS • Programmable address mapping • External DMA Slave Support 12 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet • External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440GX interfaces to the physical layer, but the PHY is not included on the chip. Features include: • One to four 10/100 interfaces running in full- and half-duplex modes - One full Media Independent Interface (MII) with 4-bit parallel data transfer - Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer - Four Serial Media Independent Interfaces (SMII) • One or two GMII interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s - One full Gigabit Media Independent Interface (GMII) with 8-bit parallel data transfer - Two Reduced Gigabit Media Independent Interfaces (RGMII) with 4-bit parallel data transfer • One or two TBI interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s - One full Ten Bit Interface (TBI) with 10-bit parallel data transfer - Two Reduced Ten Bit Interfaces (RTBI) with 4-bit parallel data transfer • Jumbo frame support (9016 byte) - Support for Ethernet II formatted frames (RFC894) - Support for IEEE formatted frames (RFC1042) - Handles VLAN-tagged frames TCP/IP Acceleration Hardware (TAH) Features include: • Offloads Gigabit Ethernet protocol processing from the CPU • Checksum verification for TCP/UDP/IP headers in the receive path • Checksum generation for TCP/UDP/IP headers in the transmit path • TCP segmentation support in the transmit path DMA Controller Features include: • Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers • Four channels • Scatter/Gather capability for programming multiple DMA operations • 8-, 16-, 32-bit peripheral support (OPB and external) • 64-bit addressing • 128 byte FIFO buffer • Address increment or decrement • Supports internal and external peripherals • Support for memory mapped peripherals AMCC 13 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet • Support for peripherals running on slower frequency buses Serial Port Features include: • One 8-pin UART and one 4-pin UART interface provided • Selectable internal or external serial clock to allow wide range of baud rates • Register compatibility with 16750 register set • Complete status reporting capability • Fully programmable serial-interface characteristics • Supports DMA using internal DMA engine IIC Bus Interface Features include: • Two IIC interfaces provided • • • • • • • • • • • • • Support for Philips® Semiconductors I2C Specification, dated 1995 Operation at 100kHz or 400kHz 8-bit data 10- or 7-bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed VDD IIC interface Two independent 4 x 1 byte data buffers Twelve memory-mapped, fully programmable configuration registers One programmable interrupt request signal Provides full management of all IIC bus protocols Programmable error recovery General Purpose Timers (GPT) Provides a separate time base counter and additional system timers in addition to those defined in the processor core. • 32-bit Time Base Counter driven by the OPB bus clock • Seven 32-bit compare timers General Purpose IO (GPIO) Controller • Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. • The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. • Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). 14 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Universal Interrupt Controller (UIC) Four Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. Features include: • 18 external interrupts • 63 internal interrupts • Edge triggered or level-sensitive • Positive or negative active • Non-critical or critical interrupt to the on-chip processor core • Programmable interrupt priority ordering • Programmable critical interrupt vector for faster vector processing PLB Performance Monitor The PLB Performance Monitor (PPM) provides hardware for counting certain events associated with PLB transactions. The contents of the counters can be read by software for analysis and enhancement of PLB performance, or software debug. The data includes identification and duration of the events. I2O Messaging Unit (IMU) The IMU interfaces to the PLB as a master or slave and allows messages to be transferred between two PLB masters (for example, the 440 CPU and PCI-X). Features include: • Three messaging methods - 4 Message registers—2 inbound, 2 outbound - 2 Doorbell registers—1 inbound, 1 outbound - 4 Circular queues—2 inbound, 2 outbound • Up to 7 different interrupt outputs generated • Support for interrupt masking JTAG Features include: • IEEE 1149.1 Test Access Port • IBM RISCWatch Debugger support • JTAG Boundary Scan Description Language (BSDL) AMCC 15 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet 25mm, 552-Ball Ceramic (CBGA) Package Top View Chip A1 Corner A PPC440GX–3xxfffx 1 24 Part Number Lot Number AD Capacitor Notes: 1. All dimensions are in mm. 2. RoHS compliant reduced-lead package available. 3. Reduced-lead package dimensions are in parentheses (dimension). Bottom View 25.0 ± 0.2 23.0 AD AC AB AA Y W V U T R 25.0 ± 0.2 P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 0.8 ± 0.04 Solderball x 552 (0.7 ± 0.1) 1.00 Typ 2.31 max (2.20 max) 1.89 min (2.00 min) AAAAAAAA 8.4 0.81 max (0.60 max) 0.71 min (0.40 max) 3.977 max (3.707 max) 3.379 min (3.179 min) 0.857 max (0.907 max) 0.779 min (0.779 min) 16 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet 25mm, 552-Ball Plastic (FC-PBGA) Package Top View A1 Corner A 1 24 ® PPC440GX 3xxfffx Lot Number AAAAAAAA Part Number AD Notes: 1. All dimensions are in mm. 2. Available in lead-free, RoHS compliant version. Bottom View 25.0 23.0 AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 0.66 ± 0.1 Solderball x 552 1.00 Typ 1 ± 0.3 1.214 Ref 25.0 7.5 23.0 0.5 ± 0.1 3.191 ± 0.17 0.508 Ref AMCC 17 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 50 where the signals in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary name appearing first. These signals are listed only once, and appear alphabetically by the primary name. Signals Listed Alphabetically Signal Name AGND AGND AGND AMVDD APVDD ASVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIXC0 [BE1]PCIXC1 [BE2]PCIXC2 [BE3]PCIXC3 [BE4]PCIXC4 [BE5]PCIXC5 [BE6]PCIXC6 [BE7]PCIXC7 BusReq[TrcTS1] CAS ClkEn0 ClkEn1 ClkEn2 ClkEn3 (Sheet 1 of 24) Ball J01 J24 AA11 AB11 G01 G24 AA16 DDR SDRAM AD09 AB15 W14 DDR SDRAM AD11 AD05 F14 E16 C19 F20 PCI-X C08 C03 G09 F09 AA24 AB05 AD17 AB10 DDR SDRAM Y09 W09 51 External Master Peripheral DDR SDRAM 54 51 50 51 51 Power—MemClkOut PLL analog voltage Power—PCI-X PLL analog voltage Power—SysClk PLL analog voltage 57 57 57 Power—Analog ground 57 Interface Group Page 18 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DMAAck0 DMAAck1 DMAAck2[GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0] DMAAck3[GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1] DMAReq0 DMAReq1 DMAReq2[GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4] DMAReq3[GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4] DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh2 (Sheet 2 of 24) Ball T16 AA18 AB14 P13 AA09 AA07 Y03 V03 AC05 N05 P07 P06 P11 R03 M11 N11 P01 AC20 AC16 AC14 AB13 AC11 AC09 Y04 T01 AA05 A05 System 56 DDR SDRAM 51 External Slave Peripheral 53 External Slave Peripheral 53 DDR SDRAM 51 Interface Group Page AMCC 19 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3 EMCMDClk EMCMDIO EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1 EMCRxD0, EMC0RxD0, EMC0RxD EMCRxD1, EMC0RxD1, EMC1RxD EMCRxD2, EMC1RxD0, EMC2RxD, GMCTxD0, GMC0TxD0, TBITxD0, RTBI0TxD0 EMCRxD3, EMC1RxD1, EMC3RxD GMCTxD1, GMC0TxD1, TBITxD1, RTBI0TxD1 EMCRxDV, EMC1CrSDV, GMCTxD4, GMC1TxD0, TBITxD4, RTBI1TxD0 EMCRxErr, EMC0RxErr, GMCTxD6, GMC1TxD2, TBITxD6, RTBI1TxD2 EMCTxClk, EMCRefClk EMCTxD0, EMC0TxD0, EMC0TxD EMCTxD1, EMC0TxD1, EMC1TxD EMCTxD2, EMC1TxD0, EMC2TxD, GMCTxD2, GMC0TxD2, TBITxD2, RTBI0TxD2 EMCTxD3, EMC1TxD1, EMC3TxD, GMCTxD3, GMC0TxD3, TBITxD3, RTBI0TxD3 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn, GMCRxClk, GMC0RxClk, TBIRxClk0, RTBI0RxClk (Sheet 3 of 24) Ball AB07 AB06 AD06 W07 DDR SDRAM U09 AC03 AB04 AD04 J07 K07 J08 L05 J02 G03 E01 A07 Ethernet 51 Ethernet Ethernet Ethernet Ethernet Ethernet 51 51 51 51 51 51 Interface Group Page H09 K01 K03 J06 L09 K05 J04 Ethernet Ethernet Ethernet 51 51 51 Ethernet 51 J03 L06 C05 Ethernet Ethernet 51 51 20 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name EOT0/TC0 EOT1/TC1 EOT2/TC2[GMCRxD2, GMC0RxD2, TBIRxD2, RTBI0RxD2] EOT3/TC3[GMCRxD3, GMC0RxD3, TBIRxD3, RTBI0RxD3] ExtAck[TrcTS2] ExtReq[TrcTS3] ExtReset [GMCCD, GMC1RxClk, RTBI1RxClk]TrcTS1[GPIO27] [GMCCrS, GMC1TxClk, RTBI1TxClk]TrcTS6 GMCRefClk [GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0]DMAAck2 [GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1]DMAAck3 [GMCRxD2, GMC0RxD2, TBIRxD2, RTBI0RxD2]EOT2/TC2 [GMCRxD3, GMC0RxD3, TBIRxD3, RTBI0RxD3]EOT3/TC3 [GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0][GPIO28]TrcTS2 [GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1][GPIO29]TrcTS3 [GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2][GPIO30]TrcTS4 [GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3][GPIO31]TrcTS5 [GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4]DMAReq2 GMCRxEr, GMC1RxCtl, TBIRxD9, RTBI1RxD4 GMCTxEr, GMC1TxCtl, TBITxD9, RTBI1TxD4 [GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4]DMAReq3 [GMCTxClk, TBIRxClk1]GPIO11 (Sheet 4 of 24) Ball R16 P15 P16 M16 AA22 AB23 T17 P03 R01 L01 P06 P11 P16 M16 Ethernet R07 P09 R09 T06 N11 P04 Ethernet Ethernet Ethernet Note: Used as initialization strapping input. Ethernet Ethernet 51 51 51 External Master Peripheral External Master Peripheral External Master Peripheral Ethernet Ethernet Ethernet 54 54 54 51 51 51 External Slave Peripheral 53 Interface Group Page L07 51 P01 P14 51 51 AMCC 21 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND (Sheet 5 of 24) Ball B06 B10 B13 B17 B21 D04 D08 D12 D15 D19 D23 F02 F06 F10 F13 Power F17 F21 H04 H08 H12 H15 H19 H23 K02 K06 K10 K13 K17 K21 M04 57 Interface Group Page 22 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND (Sheet 6 of 24) Ball M08 M12 M15 M19 M23 N02 N06 N10 N13 N17 N21 R04 R08 R12 R15 R19 R23 U02 U06 U10 U13 U17 U21 W04 W08 W12 W15 W19 W23 Power 57 Interface Group Page AMCC 23 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND (Sheet 7 of 24) Ball AA02 AA06 AA10 AA13 AA17 AA21 AC04 AC08 AC12 AC15 AC19 Power 57 Interface Group Page 24 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name [GPIO00]IRQ00 [GPIO01]IRQ01 [GPIO02]IRQ02 [GPIO03]IRQ03 [GPIO04]IRQ04 [GPIO05]IRQ05 [GPIO06]IRQ06 [GPIO07]IRQ07 [GPIO08]IRQ08 [GPIO09]IRQ09 [GPIO10]IRQ10 GPIO11[GMCTxClk, TBIRxClk1] [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0[IRQ13] [GPIO19]TrcBS1[IRQ14] [GPIO20]TrcBS2[IRQ15] [GPIO21]TrcES0[IRQ16] [GPIO22]TrcES1[IRQ17] [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 [GPIO26]TrcTS0 [GPIO27]TrcTS1[GMCCD, GMC1RxClk, RTBI1RxClk] [GPIO28]TrcTS2[GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0] [GPIO29]TrcTS3[GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1] [GPIO30]TrcTS4[GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2] [GPIO31]TrcTS5[GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3] AMCC (Sheet 8 of 24) Ball N18 L20 P20 L18 N14 M20 M14 P18 N20 P22 V18 P14 C18 J16 G06 E05 H11 H14 N16 P17 T20 T21 P23 N09 P08 T05 T04 P03 R07 P09 R09 T06 System 56 Interface Group Page 25 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name Halt HoldAck[TrcTS4] HoldReq[TrcTS5] IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] IRQ00[GPIO00] IRQ01[GPIO01] IRQ02[GPIO02] IRQ03[GPIO03] IRQ04[GPIO04] IRQ05[GPIO05] IRQ06[GPIO06] IRQ07[GPIO07] IRQ08[GPIO08] IRQ09[GPIO09] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 [IRQ13][GPIO18]TrcBS0 [IRQ14][GPIO19]TrcBS1 [IRQ15][GPIO20]TrcBS2 [IRQ16][GPIO21]TrcES0 [IRQ17][GPIO22]TrcES1 (Sheet 9 of 24) Ball V05 Y21 Y23 G11 G13 H11 H14 N18 L20 P20 L18 N14 M20 M14 P18 N20 Interrupts P22 V18 E21 C22 N16 P17 T20 T21 P23 55 System External Master Peripheral External Master Peripheral IIC Peripheral IIC Peripheral IIC Peripheral IIC Peripheral Interface Group Page 56 54 54 55 55 55 55 26 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 (Sheet 10 of 24) Ball Y19 AD20 Y20 AB20 AD18 AD16 AB18 Y14 V13 V11 W16 Y11 V10 V09 DDR SDRAM V08 51 DDR SDRAM 51 Interface Group Page AMCC 27 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 (Sheet 11 of 24) Ball AD21 AB21 AC22 AA20 U16 V17 AD19 AB19 W18 V16 Y17 AB16 AC18 Y18 R14 AB17 DDR SDRAM AA14 AD15 T15 V15 Y16 U14 T13 Y15 AD13 AD14 V14 Y13 P12 AB12 Y12 V12 51 Interface Group Page 28 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemVRef1 MemVRef2 (Sheet 12 of 24) Ball W11 AD12 Y10 T12 U11 T11 T10 AD10 AB08 AD08 R11 Y07 AC07 AB09 Y06 Y08 DDR SDRAM AA01 AA03 AB02 Y01 AB03 Y02 V07 V01 T08 U07 W01 W03 V06 T07 W05 U05 T14 DDR SDRAM T09 51 51 Interface Group Page AMCC 29 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball (Sheet 13 of 24) Ball A01 A02 A03 A22 A23 A24 B01 B02 B23 B24 C01 C24 A physical ball does not exist at these ball coordinates. AB01 AB24 AC01 AC02 AC23 AC24 AD01 AD02 AD03 AD22 AD23 AD24 NA Interface Group Page 30 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD PCIX133Cap PCIXAck64 (Sheet 14 of 24) Ball B04 B12 B19 D02 D10 D17 F08 F15 F23 H06 H10 H13 H21 K04 K08 K19 M02 M17 N08 N23 R06 R17 R21 U04 U19 W02 AA23 G08 D09 PCI-X PCI-X 50 50 Power 57 Interface Group Page AMCC 31 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name PCIXAD00 PCIXAD01 PCIXAD02 PCIXAD03 PCIXAD04 PCIXAD05 PCIXAD06 PCIXAD07 PCIXAD08 PCIXAD09 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 PCIXAD28 PCIXAD29 PCIXAD30 PCIXAD31 (Sheet 15 of 24) Ball C17 B09 G10 E10 C10 A10 F11 G12 G14 A15 C15 E15 G15 B16 C16 D16 PCI-X E18 E19 F18 G18 D20 A20 A21 C21 F22 B22 G21 E23 C23 F24 D22 D24 50 Interface Group Page 32 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 PCIXAD59 PCIXAD60 PCIXAD61 PCIXAD62 PCIXAD63 (Sheet 16 of 24) Ball H03 H01 L08 F01 D01 J05 H05 G02 E02 C02 A08 G05 F03 D03 B03 H07 PCI-X G04 E04 C04 A04 F05 D05 B05 C09 E06 C06 A06 F07 E07 D07 B07 E08 50 Interface Group Page AMCC 33 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXCap PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 PCIXReq3 PCIXReq4 PCIXReq5 PCIXReq64 PCIXReset PCIXSErr (Sheet 17 of 24) Ball F14 E16 C19 F20 PCI-X C08 C03 G09 F09 L23 E03 E13 A11 E22 C22 N22 PCI-X M18 R22 P19 G07 M07 E12 A14 L04 F16 A17 E24 E21 E20 PCI-X R20 G23 R18 E09 M24 A18 PCI-X PCI-X PCI-X 50 50 50 50 PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X 50 50 50 50 50 50 50 50 PCI-X PCI-X PCI-X PCI-X 50 50 50 50 50 Interface Group Page 34 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name PCIXStop PCIXTRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 (Sheet 18 of 24) Ball L12 C12 D11 C11 B11 A12 A19 D18 E11 M03 N01 E14 C20 A16 A13 B14 C14 D14 B20 L15 L21 L22 M22 M01 L24 P24 T19 R24 U22 U24 N03 V20 V23 V21 External Slave Peripheral Note: PerAddr00 is the most significant bit (msb) on this bus. 53 PCI-X PCI-X Interface Group Page 50 50 AMCC 35 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7 (Sheet 19 of 24) Ball C07 U18 E17 L10 V04 T24 External Slave Peripheral L03 T03 L13 U03 53 Interface Group External Slave Peripheral External Master Peripheral Page 53 54 36 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 [PerErr]TrcTS6 PerOE (Sheet 20 of 24) Ball H24 H22 H20 G20 G19 H18 J23 J22 J21 J20 J19 J18 J17 J15 J14 J13 J12 J11 J10 J09 L14 K24 K22 K20 K18 K16 K14 K11 K09 L19 L17 L16 P21 M09 External Master Peripheral External Slave Peripheral 54 53 External Slave Peripheral Note: PerData00 is the most significant bit (msb) on this bus. 53 Interface Group Page AMCC 37 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerReady[RcvrInh] PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE RAS [RcvrInh]PerReady RefVEn SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS (Sheet 21 of 24) Ball T23 T22 External Slave Peripheral W20 U20 N07 P05 T18 V19 External Slave Peripheral W22 W24 P02 AD07 N07 L02 U12 U15 W10 W17 AA08 AA15 AC06 AC13 AC21 G22 T02 P10 V22 Y24 Y22 M05 U01 AB22 System System System JTAG JTAG JTAG System System JTAG 56 56 56 55 55 55 56 56 55 Power 57 External Slave Peripheral DDR SDRAM System System 53 51 56 56 53 External Slave Peripheral External Slave Peripheral 53 53 53 Interface Group Page 38 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name TrcBS0[GPIO18][IRQ13] TrcBS1[GPIO19][IRQ14] TrcBS2[GPIO20][IRQ15] TrcClk TrcES0[GPIO21][IRQ16] TrcES1[GPIO22][IRQ17] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27][GMCCD, GMC1RxClk, RTBI1RxClk] [TrcTS1]BusReq TrcTS2[GPIO28][GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0] [TrcTS2]ExtAck TrcTS3[GPIO29][GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1] [TrcTS3]ExtReq TrcTS4[GPIO30][GMCRxD6, GMC1RxD2, TBIRxD6, RTBI1RxD2] [TrcTS4]HoldAck TrcTS5[GPIO31][GMCRxD7, GMC1RxD3, TBIRxD7, RTBI1RxD3] [TrcTS5]HoldReq TrcTS6[GMCCrS, GMC1TxClk, RTBI1TxClk] TrcTS6[PerErr] TRST UART0_CTS UART0_DCD (Sheet 22 of 24) Ball N16 P17 T20 R05 T21 P23 N09 P08 T05 T04 P03 AA24 R07 AA22 P09 AB23 R09 Y21 T06 Y23 R01 P21 N24 C13 V24 Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace Trace JTAG UART Peripheral UART Peripheral Note: Used as initialization strapping input. UART Peripheral Note: Used as initialization strapping input. UART Peripheral UART Peripheral UART Peripheral UART Peripheral 57 57 57 57 57 57 57 57 57 57 57 57 57 55 54 54 Trace 57 Trace 57 Trace 57 Interface Group Page UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx V02 B18 H16 G16 G17 54 54 54 54 54 AMCC 39 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed Alphabetically Signal Name UART0_Tx UART1_DSR/CTS[GPIO14] UART1_RTS/DTR[GPIO15] UART1_Rx[GPIO12] UART1_Tx[GPIO13] UARTSerClk VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD (Sheet 23 of 24) Ball L11 G06 E05 C18 J16 A09 B08 B15 D06 D13 D21 F04 F12 F19 H02 H17 Power K12 K15 K23 M06 M10 M13 M21 N04 N12 N15 57 UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral Interface Group Page 54 54 54 54 54 54 40 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed Alphabetically Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE (Sheet 24 of 24) Ball N19 R02 R10 R13 U08 U23 W06 Power W13 W21 AA04 AA12 AA19 AC10 AC17 Y05 DDR SDRAM 51 57 Interface Group Page AMCC 41 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look up the primary signal name in “Signals Listed Alphabetically” on page 18. Signals Listed by Ball Assignment Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 Signal Name No ball No ball No ball PCIXAD51 DrvrInh2 PCIXAD58 EMCRxD2 * PCIXAD42 UARTSerClk PCIXAD05 PCIXFrame PerAddr03 PerAddr12 PCIXM66En PCIXAD09 PerAddr11 PCIXPErr PCIXSErr PerAddr04 PCIXAD21 PCIXAD22 No ball No ball No ball Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 No ball No ball (Sheet 1 of 6) Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 Signal Name No ball PCIXAD41 PCIXC5 * PCIXAD50 EMCTxErr * PCIXAD57 PerBLast PCIXC4 * PCIXAD55 PCIXAD04 PerAddr01 PCIXTRDY UART0_CTS PerAddr14 PCIXAD10 PCIXAD14 PCIXAD00 UART1_Rx * PCIXC2 * PerAddr10 PCIXAD23 PCIXGnt1 * PCIXAD28 No ball Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Signal Name PCIXAD36 OVDD PCIXAD45 GND PCIXAD53 VDD PCIXAD61 GND PCIXAck64 OVDD PerAddr00 GND VDD PerAddr15 GND PCIXAD15 OVDD PerAddr05 GND PCIXAD20 VDD PCIXAD30 GND PCIXAD31 Signal Name PCIXAD46 OVDD PCIXAD54 GND PCIXAD62 VDD PCIXAD01 GND PerAddr02 OVDD GND PerAddr13 VDD PCIXAD13 GND UART0_DTR OVDD PerAddr16 GND PCIXAD25 No ball No ball 42 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed by Ball Assignment Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 Signal Name EMCRxD1 * PCIXAD40 PCIXClk PCIXAD49 UART1_RTS/DTR * PCIXAD56 PCIXAD60 PCIXAD63 PCIXReq64 PCIXAD03 PerAddr06 PCIXIRDY PCIXDevSel PerAdd09 PCIXAD11 PCIXC1 * PerCS0 PCIXAD16 PCIXAD17 PCIXReq2 PCIXReq1 * PCIXGnt0 PCIXAD27 PCIXReq0 Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 (Sheet 2 of 6) Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 Signal Name APVDD for PCI PLL PCIXAD39 EMCRxD0 * PCIXAD48 PCIXAD43 UART1_DSR/CTS * PCIXIDSel PCIX133Cap PCIXC6 * PCIXAD02 IIC0SClk PCIXAD07 IIC0SDA PCIXAD08 PCIXAD12 UART0_RTS UART0_Rx PCIXAD19 PerData04 PerData03 PCIXAD26 SysClk PCIXReq4 ASVDD for SysClk PLL Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 Signal Name PCIXAD33 VDD PCIXAD32 GND PCIXAD38 OVDD PCIXAD47 GND EMCRxD3 * OVDD IIC1SClk * GND OVDD IIC1SDA * GND UART0_RI VDD PerData05 GND PerData02 OVDD PerData01 GND PerData00 Signal Name PCIXAD35 GND PCIXAD44 VDD PCIXAD52 GND PCIXAD59 OVDD PCIXC7 * GND PCIXAD06 VDD GND PCIXC0 * OVDD PCIXParLow GND PCIXAD18 VDD PCIXC3 * GND PCIXAD24 OVDD PCIXAD29 AMCC 43 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed by Ball Assignment Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 Signal Name AGND EMCRxClk * EMCTxD3 * EMCTxD2 * PCIXAD37 EMCTxClk * EMCCD * EMCMDClk PerData19 PerData18 PerData17 PerData16 PerData15 PerData14 PerData13 UART1_Tx * PerData12 PerData11 PerData10 PerData9 PerData8 PerData7 PerData6 AGND Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 (Sheet 3 of 6) Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 Signal Name GMCRefClk RefVEn PerCS4 PCIXParHigh EMCMDIO EMCTxEn * GMCTxEr * PCIXAD34 EMCTxD0 * PerCS1 UART0_Tx PCIXStop PerCS6 PerData20 PerAddr17 PerData31 PerData30 IRQ03 * PerData29 IRQ01 * PerAddr18 PerAddr19 PCIXCap PerAddr22 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 Signal Name PerAddr21 OVDD PerAddr07 GND TestEn VDD PCIXINT GND PerOE VDD DMAReq1 GND VDD IRQ06 * GND EOT3/TC3 * OVDD PCIXGnt3 GND IRQ05 * VDD PerAddr20 GND PCIXReset Signal Name EMCRxDV * GND EMCRxErr * OVDD EMCTxD1 * GND EMCCrS * OVDD PerData28 GND PerData27 VDD GND PerData26 VDD PerData25 GND PerData24 OVDD PerData23 GND PerData22 VDD PerData21 44 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed by Ball Assignment Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 Signal Name PerAddr08 GND PerAddr28 VDD DMAAck0 GND PerReady * OVDD TrcES2 * GND DMAReq2 * VDD GND IRQ04 * VDD TrcBS0 * GND IRQ00 * VDD IRQ08 * GND PCIXGnt2 OVDD TRST Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 (Sheet 4 of 6) Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 Signal Name TrcTS6 * VDD DMAReq0 GND TrcClk OVDD TrcTS2 * GND TrcTS4 * VDD MemData42 GND VDD MemData14 GND EOT0/TC0 OVDD PCIXReq5 GND PCIXReq3 OVDD PCIXGnt4 GND PerAddr25 Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Signal Name DQS7 SysErr PerCS5 TrcTS0 * TrcES4 * TrcTS5 * MemData61 MemData56 MemVRef2 MemData38 MemData37 MemData35 MemData22 MemVRef1 MemData18 DM0 ExtReset PerWBE0 PerAddr24 TrcBS2 * TrcES0 * PerPar1 PerPar0 PerCS3 Signal Name DMAReq3 * PerWE TrcTS1 * GMCRxEr * PerR/W DMAAck2 * DMAAck1 TrcES3 * TrcTS3 * SysReset DMAAck3 * MemData28 DM3 GPIO11 * EOT1/TC1 EOT2/TC2 * TrcBS1 * IRQ07 * PCIXGnt5 IRQ02 * TrcTS6 * IRQ09 * TrcES1 * PerAddr23 AMCC 45 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signals Listed by Ball Assignment Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 Signal Name TmrClk GND PerCS7 OVDD MemData63 GND MemData57 VDD ECC4 GND MemData36 SVDD GND MemData21 SVDD MemData04 GND PerClk OVDD PerPar3 GND PerAddr26 VDD PerAddr27 Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 (Sheet 5 of 6) Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 Signal Name MemData58 OVDD MemData59 GND MemData62 VDD ECC3 GND ClkEn3 SVDD MemData32 GND VDD BankSel1 GND MemAddr10 SVDD MemData08 GND PerPar2 VDD PerWBE2 GND PerWBE3 Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Signal Name MemData51 MemData53 DM6 DQS6 WE MemData46 MemData43 MemData47 ClkEn2 MemData34 MemAddr11 MemData30 MemData27 MemAddr7 MemData23 MemData20 MemData10 MemData13 MemAddr00 MemAddr02 HoldAck * TDO HoldReq * TDI Signal Name MemData55 UART0_DSR DM7 PerCS2 Halt MemData60 MemData54 MemClkOut0 MemClkOut0 MemAddr12 MemAddr9 MemData31 MemAddr8 MemData26 MemData19 MemData09 MemData05 IRQ10 * PerWBE1 PerAddr29 PerAddr31 TCK PerAddr30 UART0_DCD 46 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signals Listed by Ball Assignment Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 Signal Name MemData48 GND MemData49 VDD DQS8 GND DM5 SVDD DM4 GND AGND VDD GND MemData16 SVDD BA0 GND DM1 VDD MemData03 GND ExtAck * OVDD BusReq * Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 No ball MemData50 MemData52 ECC6 CAS ECC1 ECC0 MemData40 MemData45 ClkEn1 AMVDD for MemClk PLL MemData29 DQS3 DM2 BankSel0 MemData11 MemData15 MemAddr6 MemData07 MemAddr3 MemData01 TMS ExtReq * No ball (Sheet 6 of 6) Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Signal Name No ball No ball ECC5 GND DM8 SVDD MemData44 GND DQS5 VDD DQS4 GND SVDD DQS2 GND DQS1 VDD MemData12 GND DQS0 SVDD MemData02 No ball No ball Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Signal Name No ball No ball No ball ECC7 BankSel3 ECC2 RAS MemData41 BA1 MemData39 BankSel2 MemData33 MemData24 MemData25 MemData17 MemAddr5 ClkEn0 MemAddr4 MemData06 MemAddr01 MemData00 No ball No ball No ball Signal Name AMCC 47 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Description The PPC440GX embedded controller is provided in a 552-ball, ball grid array package. The following tables describe the package level pinout. Pin Summary Group Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AxVDD AGnd OVDD SVDD VDD Gnd Total Power Pins Reserved Total Pins No. of Pins 343 63 406 3 3 27 9 34 70 146 0 552 In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed Alphabetically” on page 18 for the pin (ball) number to which each signal is assigned. Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals Listed Alphabetically” on page 18. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr00:31) are used as outputs by the PPC440GX to broadcast an address to external slave devices when the PPC440GX has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GX. In this example, the pins are also bidirectional, serving both as inputs and outputs. Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. 48 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Strapping” on page 89). Note that these are not multiplexed pins since the function of the pins is not programmable. AMCC 49 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Functional Description (Sheet 1 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name PCI-X Interface PCIXAD00:63 PCIXC0:7[BE0:7] PCIXCap PCIX133Cap PCIXClk Address/Data bus (bidirectional). PCI-X Command[Byte Enables]. Capable of PCI-X operation. PCI-X devices are 133 MHz capable. Provides timing to the PCI interface for PCI transactions. I/O I/O I O I 3.3V PCI 3.3V PCI 3.3V LVTTL 3.3V PCI 3.3V PCI 5 Description I/O Type Notes Note: If the PCI-X interface is not being used, drive this pin with a 3.3V clock signal at a frequency between 1 and 66MHz Indicates the driving device has decoded its address as the target of the current access. Driven by the current master to indicate beginning and duration of an access. Indicates that the specified agent is granted access to the bus. When using an external PCI/PCI-X arbiter, connect the external arbiter's Grant line to this signal. Indicates that the specified agent is granted access to the bus. Indicates that the specified agent is granted access to the bus. Used as a chip select during configuration read and write transactions. Level sensitive PCI interrupt. Indicates initiating agent’s ability to complete the current data phase of the transaction. Capable of 66MHz operation. Even parity across PCIAD32:63 and PCIXC0:3[BE4:7]. Even parity across PCIAD0:31 and PCIXC0:3[BE0:3]. Reports data parity errors during all PCI transactions except a Special Cycle. An indication to the PCI-X arbiter that the specified agent wishes to use the bus. When using an external PCI/PCI-X arbiter, connect the external arbiter's Request line to this signal. An indication to the PCI-X arbiter that the specified agent wishes to use the bus. Asserted by the current bus master, indicating a 64-bit transfer. Indicates the target can transfer data using 64 bits. Brings PCI device registers and logic to a consistent state. Reports address parity errors, data parity errors on the Special Cycle command, or other catastrophic system errors. Indicates the current target is requesting the master to stop the current transaction. PCIXDevSel PCIXFrame I/O I/O 3.3V PCI 3.3V PCI 4 4 PCIXGnt0 PCIXGnt1 PCIXGnt2:5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr I/O I/O O I O I/O I I/O I/O I/O 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V LVTTL w/pull-up 3.3V PCI 3.3V PCI 3.3V PCI 4 4 5 4 5 4 PCIXReq0 I/O 3.3V PCI 4 PCIXReq1:5 PCIXReq64 PCIXAck64 PCIXReset PCIXSErr PCIXStop I I/O I/O O I/O I/O 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 4 4 4 4 4 50 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signal Functional Description (Sheet 2 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name PCIXTRDY DDR SDRAM Interface BA0:1 BankSel0:3 CAS ClkEn0:3 DM0:8 DQS0:8 ECC0:7 MemAddr00:12 MemClkOut0 MemClkOut0 MemData00:63 MemVRef1:2 RAS WE Ethernet Interface EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3 EMCMDClk EMCMDIO MII: Collision detection RMII 1: Receive error GMII: 1000Mbps Transmit clock RGMII: Transmit clock TBI: Transmit clock RTBI: Transmit clock MII: Carrier sense RMII 0: Carrier sense data valid GMII: Transmit data RGMII 1: Transmit data TBI: Transmit data RTBI 1: Transmit data MII and RMII: Management data clock MII and RMII: Transfer command and status information between MII and PHY Bank Address supporting up to four internal banks. Selects up to four external DDR SDRAM banks. Column Address Strobe. Clock Enable. One for each bank. Memory write data byte lane masks. MEMDM8 is the byte lane mask for the ECC byte lane. Byte lane data strobe. DQS8 is the data strobe for the ECC byte lane. ECC check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Memory reference voltage (SVREF) input. Row Address Strobe. Write Enable. O O O O O I/O I/O O O I/O I O O 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Voltage Ref Receiver 2.5V SSTL_2 2.5V SSTL_2 Description I/O I/O Type 3.3V PCI Notes 4 Indicates the target agent’s ability to complete the current data phase of the transaction. I/O 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS O I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS AMCC 51 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Functional Description (Sheet 3 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name EMCRxD0:3, EMC0RxD0:1, EMC1RxD0:1, EMC0RxD, EMC1RxD, EMC2RxD, EMC3RxD, GMCTxD0:1, GMC0TxD0:1, TBITxD0:1, RTBI0TxD0:1 EMCRxDV, EMC1CrSDV, GMCTxD4, GMC1TxD0, TBITxD4, RTBI1TxD0 EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1 EMCRxErr, EMC0RxErr, GMCTxD6, GMC1TxD2, TBITxD6, RTBI1TxD2 EMCTxClk, EMCRefClk EMCTxD0:3, EMC0TxD0:1, EMC1TxD0:1, EMC0TxD, EMC1TxD, EMC2TxD, EMC3TxD, GMCTxD2:3, GMC0TxD2:3, TBITxD2:3, RTBI0TxD2:3 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn, GMCRxClk, GMC0RxClk, TBIRxClk0, RTBI0RxClk GMCCD, GMC1RxClk, RTBI1RxClk MII: Receive data RMII 0: Receive data RMII 1: Receive data SMII 0: Receive data SMII 1: Receive data SMII 2: Receive data SMII 3: Receive data GMII: Transmit data RGMII 0: Transmit data TBI: Transmit data RTBI 0: Transmit data MII: Receive data valid RMII 1: Carrier sense data valid GMII: Transmit data RGMII 1: Transmit data TBI: Transmit data RTBI 1: Transmit data MII: Receive clock GMII: Transmit data RGMII 1: Transmit data TBI: Transmit data RTBI 1: Transmit data MII: Receive error RMII 0: Receive error GMII: Transmit data RGMII 1: Transmit data TBI: Transmit data RTBI 1: Transmit data MII: Transmit clock RMII and SMII: Reference clock MII: Transmit data RMII 0: Transmit data RMII 1: Transmit data SMII 0: Transmit data SMII 1: Transmit data SMII 2: Transmit data SMII 3: Transmit data GMII: Transmit data RGMII 0: Transmit data TBI: Transmit data RTBI 0: Transmit data MII: Transmit data enabled RMII 0: Transmit data enabled SMII: Sync signal MII: Transmit error: RMII: Transmit data enabled GMII: Receive clock RGMII: Receive clock TBI: Receive clock 0 RTBI: Receive clock GMII: Collision detection RGMII: Receive clock RTBI: Receive clock Description I/O Type Notes I/O 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS I 3.3V tolerant 2.5V CMOS 5 O 3.3V tolerant 2.5V CMOS O 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS I 3.3V tolerant 2.5V CMOS 5 52 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signal Functional Description (Sheet 4 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name GMCCrS, GMC1TxClk, RTBI1TxClk GMCRefClk GMCRxD0:3, GMC0RxD0:3, TBIRxD0:3, RTBI0RxD0:3 GMCRxD4:7, GMC1RxD0:3, TBIRxD4:7, RTBI1RxD0:3 GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4 GMCRxEr, GMC1RxCtl, TBIRxD9, RTBI1RxD4 GMCTxEn, GMC0TxCtl, TBITxD8, RTBI0TxD4 GMCTxEr, GMC1TxCtl, TBITxD9, RTBI1TxD4 GMCTxClk TBIRxClk1 GMII: Carrier sense RGMII: Transmit clock RTBI: Transmit clock GMII, RGMII, TBI and RTBI: Gigabit reference clock GMII: Receive data RGMII: Receive data TBI: Receive data RTBI: Receive data GMII: Receive data RGMII: Receive data TBI: Receive data RTBI: Receive data GMII: Receive data valid RGMII: Receive control TBI: Receive data RTBI: Receive data GMII: Receive error RGMII: Receive control TBI: Receive data RTBI: Receive data GMII: Transmit data enable RGMII: Transmit control TBI: Transmit data RTBI: Transmit data GMII: Transmit error RGMII: Transmit control TBI: Transmit data RTBI: Transmit data GMII: 10/100Mbps Transmit clock TBI: Receive clock 1 Description I/O I/O Type 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 5 Notes I I I 3.3V tolerant 2.5V CMOS I 3.3V tolerant 2.5V CMOS I/O 3.3V tolerant 2.5V CMOS O 3.3V tolerant 2.5V CMOS O 3.3V tolerant 2.5V CMOS 6 I/O 3.3V LVTTL 5 External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 Used by the PPC440GX to indicate that data transfers have occurred. Used by slave peripherals to indicate they are prepared to transfer data. End Of Transfer/Terminal Count. Peripheral address bus used by PPC440GX when not in external master mode, otherwise used by external master. Note: PerAddr00 is the most significant bit (msb) on this bus. External peripheral data bus byte enables. Used by either the peripheral controller, DMA controller, or external master to indicates the last transfer of a memory access. External peripheral device select. Peripheral data bus used by PPC440GX when not in external master mode, otherwise used by external master. Note: PerData00 is the most significant bit (msb) on this bus. O I I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 5 1, 5 PerAddr00:31 PerWBE0:3 PerBLast PerCS0:7 PerData00:31 I/O I/O I/O O I/O 1 1, 2 1, 4 2 1 AMCC 53 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Functional Description (Sheet 5 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name PerOE PerPar0:3 PerReady Description Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC440GX is the bus master, it enables the selected device to drive the bus. External peripheral data bus byte parity. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC440GX when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise, it used by the external master as an input to indicate the direction of transfer. Write Enable. Low when any of the four PerWBE0:3 signals are low. I/O O I/O I Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Notes 2 1 PerR/W I/O 3.3V LVTTL 1, 2 PerWE O 3.3V LVTTL 2 External Master Peripheral Interface BusReq ExtAck ExtReq ExtReset HoldAck HoldReq PerClk PerErr UART Peripheral Interface Serial clock input that provides an alternative to the internally generated serial clock. Used in cases where the allowable internally generated clock rates are not satisfactory. This input can be individually connected to either or both UART0 and UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. Bus Request. Used when the PPC440GX needs to regain control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GX to indicate that a data transfer occurred. External Request. Used by an external master to indicate it is prepared to transfer data. Peripheral Reset. Used by an external master and by synchronous peripheral slaves. Hold Acknowledge. Used by the PPC440GX to transfer ownership of peripheral bus to an external master. Hold Request. Used by an external master to request ownership of the peripheral bus. Peripheral Clock. Used by an external master and by synchronous peripheral slaves. External Error. Used as an input to record external master errors and external slave peripheral errors. O O I O O I O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 5 1, 5 1, 4 UARTSerClk I 3.3V LVTTL 1, 4 UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI I O I I I O O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 4 4 6 6 1, 4 4 4 1, 4 54 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signal Functional Description (Sheet 6 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR IIC Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA Interrupts Interface IRQ00:10 IRQ11:12 IRQ13:17 JTAG Interface TCK TDI TDO TMS Test Clock. Test Data In. Test Data Out. Test Mode Select. Test Reset. During chip power-up, this signal must be low from the start of VDD ramp-up until at least 16 SysClk cycles after VDD is stable in order to initialize the JTAG controller. I I O I 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 1 1 4 External interrupt Requests 0 through 10. External interrupt Requests 11 through 12. External interrupt Requests 13 through 17. I I I 3.3V LVTTL 3.3V PCI 3.3V LVTTL 1, 5 IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V IIC 3.3V IIC 1, 2 1, 2 1, 2 1, 2 UART1 Receive data. UART1 Transmit data. UART1 Data Set Ready or Clear To Send. The choice is determined by a DCR register bit setting. UART1 Request To Send or Data Terminal Ready. The choice is determined by a DCR register bit setting. Description I/O I/O I/O I/O I/O Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Notes 1, 4 1, 4 1, 4 1, 4 TRST I 5 AMCC 55 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Signal Functional Description (Sheet 7 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name System Interface SysClk SysErr Main system clock input. Set to 1 when a machine check is generated. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. The signal is implemented as an open-drain output (two states; 0 or open circuit). During chip power-up, this signal must be low from the start of VDD ramp-up until at least 16 SysClk cycles after VDD is stable. Processor timer external input clock. Halt from external debugger. General purpose I/O 0 through 10. To access these functions, software must set DCR register bits. Test Enable. Receiver Inhibit. Active only when TestEn is active. Reference Voltage Enable. Do not connect for normal operation. Pull up for Boundary Scan Description Language (BSDL) testing. Driver Inhibit. Used for test purposes only. Tie up for normal operation Clock O 3.3V LVTTL 3.3V LVTTL Description I/O Type Notes SysReset I/O 3.3V LVTTL 1, 2 TmrClk Halt GPIO00:31 TestEn RcvrInh RefVEn DrvrInh2 I I I/O I I I I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V LVTTL w/pull-down 3.3V LVTTL w/pull-up 2 3 1, 4 56 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Signal Functional Description (Sheet 8 of 8) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ) 4. If not used, must pull up (recommended value is 3kΩ to 3.3V) 5. If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 Trace branch execution status. Trace data capture clock, runs at 1/4 the frequency of the processor. Trace Execution Status is presented every fourth processor clock cycle. Additional information on trace execution and branch status. I/O O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description I/O Type Notes Note: The trace signals, TrcTS0:6, are duplicated on two sets of TrcTS0:5 (multiplexed with GPIO signals) chip balls and are multiplexed with other signals in both cases. This allows users to choose which set of multiplexed signals they wish to use along with the TrcTS0:6 signals. The trace signals in this set are primary signals. Additional information on trace execution and branch status. I/O 3.3V tolerant 2.5V CMOS TrcTS1:5 (multiplexed with EBC signals) TrcTS6 (multiplexed with EBC and Ethernet signals) Power Pins AGND GND AxVDD OVDD SVDD VDD Note: The trace signals in this set are secondary signals. Additional information on trace execution and branch status. I/O 3.3V LVTTL Note: This trace signal is the primary signal. PLL (analog) voltage ground. Ground. 1.5V—Filtered voltages input for PLLs (analog circuits) Note: A separate filter for each of the three voltages is recommended. 3.3V supply—I/O (except DDR SDRAM, Ethernet) 2.5V supply—DDR SDRAM, Ethernet 1.5V supply—Logic voltage. I/O 3.3V LVTTL na na na na na na na na na na na na AMCC 57 440GX – Power PC 440GX Embedded Processor Revision 1.15 – August 30, 2007 Data Sheet Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings. Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface, except DDR SDRAM) PLL Supply Voltages Supply Voltage (DDR SDRAM Logic) Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case Temperature under bias Notes: 1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GX. A separate filter, as shown below, is recommended for each voltage: VDD L AxVDD L – SMT ferrite bead chip, Murata BLM31A700S or equivalent. C – 0.1 μF ceramic Symbol VDD OVDD AxVDD SVDD VIN TSTG TC Value 0 to +1.65 0 to +3.6 0 to +1.65 0 to +2.7 0 to +3.6 -55 to +150 -40 to +120 Unit V V V V V °C °C 2 1 Notes C 2. This value is not a specification of the operational temperature range; it is a stress rating only. 58 AMCC Revision 1.15 – August 30, 2007 440GX – Power PC 440GX Embedded Processor Data Sheet Package Thermal Specifications Thermal resistance values for the CBGA and PBGA packages in a convection environment are as follows: Airflow ft/min (m/sec) 0 (0) Junction-to-case thermal resistance 100 (0.51)