BD160GT54DE

Am29BDD160G Data Sheet For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifications and ordering information. The following document contains information on Spansion memory products. Although the doc-ument is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro-priate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 24960 Revision D Amendment 5 Issue Date June 7, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29BDD160G 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory NOTE: For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifications and ordering information. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. (–40°C to 85°C, 56 MHz and below only) — Zero latency between read and write operations — Two bank architecture: 75%/25% User-Defined x16 or x32 Data Bus Dual Boot Block — Top and bottom boot in the same device Flexible sector architecture — Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes sectors Manufactured on 0.17 µm process technology SecSi (Secured Silicon) Sector (256 Bytes) — Current version of device has 64 Kbytes; future versions will have 256 bytes — Factory locked and identifiable: 16 bytes for secure, random factory Electronic Serial Number; remainder may be customer data programmed by AMD — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed Programmable Burst interface — Interface to any high performance processor — Modes of Burst Read Operation: Linear Burst: 4 double words (x32), 8 words (x16) and double words (x32), and 32 words (x16) with wrap around Single power supply operation — Optimized for 2.5 to 2.75 volt read, erase, and program operations Compatible with JEDEC standards (JC42.4) — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance read access — Initial/random access time as fast as 54 ns — Burst access time as fast as 9 ns for ball grid array package Ultra low power consumption — Burst Mode Read: 90 mA @ 66 MHz max — Program/Erase: 50 mA max — Standby mode: CMOS: 60 µA max Minimum 1 million write cycles guaranteed per sector 20 year data retention at 125°C VersatileI/OTM control — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.65 V to 2.75 V compatible I/O signals SOFTWARE FEATURES Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector (requires only VCC levels) Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-definable 64-bit password Supports Common Flash Interface (CFI) Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion HARDWARE FEATURES Program Suspend/Resume & Erase Suspend/Resume — Suspends program or erase operations to allow reading, programming, or erasing in same bank Hardware Reset (RESET#), Ready/Busy# (RY/BY#), and Write Protect (WP#) inputs ACC input — Accelerates programming time for higher throughput during system production Package options — 80-pin PQFP — 80-ball Fortified BGA Publication# 24960 Rev: D Amendment: 5 Issue Date: June 7, 2006 Refer to AMD’s Website (www.amd.com) for the latest information. GENERAL DESCRIPTION The Am29BDD160 is a 16 Megabit, 2.5 Volt-only single power s u pply bu rs t mode fl as h memory dev i ce . The dev i ce c a n b e conf i g u red for e i ther 1,04 8 ,576 word s i n 16- bi t mode or 524,2 88 d o ub le word s i n 32-bit mode. The device can also be programmed in standard EPROM programmers. The device offers a configurable burst interface to 16/32-bit microprocessors and microcontrollers. To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst Address Valid (ADV#), and Clock (CLK). E a ch dev i ce re qui res o nly a s i n gle 2 . 5 or 2 . 6 Volt power supply (2.5 V to 2.75 V) for both read and write functions. A 12.0-volt VPP is not required for program or erase opera tions, altho ugh an acceleration pin is a v ai l ab le i f f as ter progr a mm i ng perform a nce i s r equired. The device is entirely command set compatible with the J EDEC s ingle-power-s upply Flas h standard. The s oftw a re comm a nd s et i s c omp a t ib le w i th the comm a nd s et s o f the 5 V Am2 9 F and 3 V A m2 9 LV Flash families. Commands are written to the command register using standard microprocessor write timing. Reg is ter content s s erve a s i np u t s t o a n i ntern a l sta te-m ach ine that controls the erase and programm i ng c i rc ui try. Wr i te cycle s a l s o i ntern a lly l a tch a ddre ss e s a nd d at a n eeded for the progra mmi ng a nd eras e operat ion s. Rea di ng data ou t of the device is si m i l a r to re a d i ng from other Fl as h or EPROM devices. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can begin programming or erasi ng i n one b ank, a nd then s i m u lta neous ly re a d from the other bank, with zero latency. This releases the system from waiting for the completion of program or eras e operat i on s. S ee S i mu lta neo us Re a d/Wri te Operations Overview and Restrictions on page 13. The dev i ce prov i de s a 2 56-byte S ecSi ™ ( S ecured Si l i con) S ector w i th a n one-t i me-progr a mm ab le (OTP) mechanism. In addition, the device features several levels of sector protection, whi ch can disab le b oth the program and erase operations in certain sectors or sector groups: Persistent Sector Protection is a command s ector protect i on method th a t repla ce s t he old 12 V controlled protection method; Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank. The device defaults to the Persistent Sector Protection mode. The customer must then choose if the Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always available, independent of the other protection method chosen. The VersatileI/O™ (VCCQ ) feature allows the output volt a ge gener a ted on the dev i ce to b e determ i ned based on the VIO level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. In addition, inputs and I/Os that are driven externally are capable of handling 3.6 V. The ho s t s y s tem c a n detect whether a p rogra m or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection m easu res i ncl ude a l ow V CC detector tha t a utomat ic ally inh ibits wri te operat i on s d u ri ng power tr a n si t i on s. The pa ss word and s oftware s ector protect i on f e a t u re d isab le s b oth program and erase operations in any combination of sectors of memory. This can be achieved in-system at VCC level. The Program/Era s e S uspend/Eras e Re sume fe ature enables the user to put erase on hold for any period of time to read data from, or program data to, any s ector th a t i s n ot s elected for er asu re . Tr u e b a ckground erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machi ne to reading array data. The dev ice offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The s y s tem c a n a l s o pl a ce the dev i ce i nto the s tandby mode . P ower con su mpt i on i s g re a tly reduced in both these modes. AMD’s F l as h technology com bi ne s y e a r s o f Fl as h memory m a n u f a ct u r i ng exper i ence to prod u ce the highest levels of quality, reliability and cost effectiveness. The devi ce electric ally erases all b its with in a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. 2 Am29BDD160G June 7, 2006 TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 x16 Mode .................................................................................. 9 x32 Mode .................................................................................. 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Table 1. Device Bus Operation .......................................................12 Dynamic Protection Bit (DYB) ............................................. 25 Table 11. Sector Protection Schemes ............................................ 26 VersatileI/O™ (VIO) Control .................................................... 13 Requirements for Reading Array Data ................................... 13 Simultaneous Read/Write Operations Overview and Restrictions ................................... 13 Overview ............................................................................. 13 Restrictions .......................................................................... 13 Table 2. Bank Assignment for Boot Bank Sector Devices ................................................................................13 Persistent Sector Protection Mode Locking Bit ....................... 26 Password Protection Mode ..................................................... 26 Password and Password Mode Locking Bit ............................ 26 64-bit Password ................................................................... 27 Write Protect (WP#) ................................................................ 27 SecSi™ (Secured Silicon) Sector Protection .......................... 27 SecSi Sector Protection Bit ..................................................... 28 Persistent Protection Bit Lock ................................................. 28 Hardware Data Protection ...................................................... 28 Low VCC Write Inhibit ........................................................... 28 Write Pulse “Glitch” Protection ............................................ 28 Logical Inhibit ....................................................................... 28 Power-Up Write Inhibit ......................................................... 28 VCC and VIO Power-up And Power-down Sequencing ......... 28 Table 12. Sector Addresses for Top Boot Sector Devices ............. 29 Table 13. Sector Addresses for Bottom Boot Sector Devices ........ 30 Table 14. CFI Query Identification String ....................................... 31 Table 15. CFI System Interface String ........................................... 31 Table 16. CFI Device Geometry Definition ..................................... 32 Table 17. CFI Primary Vendor-Specific Extended Query ............... 32 Simultaneous Read/Write Operations With Zero Latency ...... 13 Table 3. Top Boot Bank Select .......................................................14 Table 4. Bottom Boot Bank Select ..................................................14 Writing Commands/Command Sequences ............................ 14 Accelerated Program and Erase Operations ....................... 14 Autoselect Functions ........................................................... 14 Automatic Sleep Mode (ASM) ................................................ 14 RESET#: Hardware Reset Pin ............................................... 15 Output Disable Mode .............................................................. 15 Autoselect Mode ..................................................................... 15 Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) .16 Command Definitions . . . . . . . . . . . . . . . . . . . . . 34 Reading Array Data in Non-burst Mode .................................. 34 Reading Array Data in Burst Mode ......................................... 34 Read/Reset Command ........................................................... 34 Autoselect Command ............................................................. 35 Program Command Sequence ............................................... 35 Accelerated Program Command ............................................ 35 Unlock Bypass Command Sequence ..................................... 35 Figure 4. Program Operation ......................................................... 36 Asynchronous Read Operation (Non-Burst) ........................... 16 Figure 1. Asynchronous Read Operation........................................ 16 Synchronous (Burst) Read Operation .................................... 17 Linear Burst Read Operations ................................................ 17 Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .................17 CE# Control in Linear Mode ................................................ 18 ADV# Control In Linear Mode .............................................. 18 RESET# Control in Linear Mode ......................................... 18 OE# Control in Linear Mode ................................................ 18 IND/WAIT# Operation in Linear Mode ................................. 18 Table 7. Valid Configuration Register Bit Definition for IND/WAIT# 20 Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation............................................................................... 20 Unlock Bypass Entry Command .......................................... 36 Unlock Bypass Program Command .................................... 36 Unlock Bypass Chip Erase Command ................................ 36 Unlock Bypass CFI Command ............................................ 36 Unlock Bypass Reset Command ......................................... 37 Chip Erase Command ............................................................ 37 Sector Erase Command ......................................................... 37 Figure 5. Erase Operation.............................................................. 38 Sector Erase and Program Suspend Command .................... 38 Sector Erase and Program Suspend Operation Mechanics ... 38 Table 18. Allowed Operations During Erase/Program Suspend ... 38 Burst Access Timing Control ............................................... 21 Initial Burst Access Delay Control ....................................... 21 Table 8. Burst Initial Access Delay ..................................................21 Figure 3. Initial Burst Delay Control ................................................ 21 Configuration Register ............................................................ 22 Table 9. Configuration Register Definitions .....................................22 Table 10. Configuration Register After Device Reset .....................24 Initial Access Delay Configuration .......................................... 24 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . 24 Persistent Sector Protection ................................................... 24 Persistent Protection Bit (PPB) ............................................ 25 Persistent Protection Bit Lock (PPB Lock) .......................... 25 Sector Erase and Program Resume Command ..................... 39 Configuration Register Read Command ................................. 39 Configuration Register Write Command ................................. 39 Common Flash Interface (CFI) Command .............................. 39 SecSi Sector Entry Command ................................................ 41 Password Program Command ................................................ 41 Password Verify Command .................................................... 41 Password Protection Mode Locking Bit Program Command .. 42 Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 42 SecSi Sector Protection Bit Program Command .................... 42 PPB Lock Bit Set Command ................................................... 42 DYB Write Command ............................................................. 42 Password Unlock Command .................................................. 42 PPB Program Command ........................................................ 43 June 7, 2006 Am29BDD160G 3 All PPB Erase Command ....................................................... 43 DYB Write ............................................................................... 43 PPB Lock Bit Set .................................................................... 43 DYB Status ............................................................................. 43 PPB Status ............................................................................. 44 PPB Lock Bit Status ............................................................... 44 Non-volatile Protection Bit Program And Erase Flow ............. 44 Table 19. Memory Array Command Definitions (x32 Mode) ...........45 Table 20. Sector Protection Command Definitions (x32 Mode) ......46 Table 21. Memory Array Command Definitions (x16 Mode) ...........47 Table 22. Sector Protection Command Definitions (x16 Mode) ......48 Key to Switching Waveforms . . . . . . . . . . . . . . . 56 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 56 Figure 13. Input Waveforms and Measurement Levels ................. 56 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 14. VCC and VIO Power-up Diagram ................................. 57 Figure 15. Conventional Read Operations Timings ....................... 60 Figure 16. Burst Mode Read (x32 Mode)....................................... 60 Figure 17. Asynchronous Command Write Timing ........................ 61 Figure 18. Synchronous Command Write/Read Timing................. 61 Figure 19. RESET# Timings .......................................................... 63 Figure 20. WP# Timing .................................................................. 63 Figure 21. Program Operation Timings.......................................... 65 Figure 22. Chip/Sector Erase Operation Timings .......................... 66 Figure 23. Back-to-back Cycle Timings ......................................... 66 Figure 24. Data# Polling Timings (During Embedded Algorithms). 67 Figure 25. Toggle Bit Timings (During Embedded Algorithms)...... 67 Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations... 68 Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings .. 68 Figure 28. Sector Protect/Unprotect Timing Diagram .................... 69 Figure 29. Alternate CE# Controlled Write Operation Timings ...... 71 DQ7: Data# Polling ................................................................. 49 RY/BY#: Ready/Busy# ........................................................... 49 Figure 6. Data# Polling Algorithm ................................................... 50 DQ6: Toggle Bit I .................................................................... 50 DQ2: Toggle Bit II ................................................................... 50 Reading Toggle Bits DQ6/DQ2 .............................................. 51 DQ5: Exceeded Timing Limits ................................................ 51 Figure 7. Toggle Bit Algorithm......................................................... 51 DQ3: Sector Erase Timer ....................................................... 52 Table 23. Write Operation Status ....................................................52 Figure 8. Maximum Negative Overshoot Waveform ....................... 53 Figure 9. Maximum Positive Overshoot Waveform......................... 53 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ......................................................................................... 55 Figure 11. Typical ICC1 vs. Frequency............................................. 55 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 12. Test Setup...................................................................... 56 Table 24. Test Specifications ..........................................................56 Erase and Programming Performance . . . . . . . 72 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 72 PQFP and Fortified BGA Pin Capacitance . . . . . 72 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 73 PQR080–80-Lead Plastic Quad Flat Package ....................... 73 LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm) ......... 74 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 75 4 Am29BDD160G June 7, 2006 PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: VCC = 2.5 – 2.75 V Speed Option (Clock Rate) Max Initial/Asynchronous Access Time, ns (tACC) Max Burst Access Delay (ns) Max Clock Rate (MHz) Min Initial Clock Delay (clock cycles) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) Am29BDD160G Synchronous/Burst or Asynchronous 54D (66 MHz) 54 9 FBGA/9.5 PQFP 66 3 58 20 64C (56 MHz) 64 10 FBGA/10 PQFP 56 3 69 65A (40 MHz) 67 17 40 2 71 28 Note: The 54D, 64C, and 65A speed options are tested and guaranteed to operate only at the 66 MHz, 56MHz, and 40MHz frequencies respectively. Operation and other frequencies is not warranted. BLOCK DIAGRAM VCC VSS RDY Buffer DQ0–DQ15 A0–A18 RDY Erase Voltage Generator WE# RESET# ACC WP# WORD# State Control Command Register VIO Input/Output Buffers PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder Timer Address Latch VCC Detector Y-Gating X-Decoder Cell Matrix ADV# CLK Burst State Control IND/ WAIT# Burst Address Counter A0–A20 DQ0–DQ31 A0–A18 June 7, 2006 Am29BDD160G 5 BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT VCC VSS OE# Y-Decoder A0–A18 Upper Bank Address Upper Bank Latches and Control Logic 16/32# A0–A18 RESET# WE# CE# ADV# DQ0–DQ31 A0–A18 X-Decoder STATE CONTROL & COMMAND REGISTER Status DQ0–DQ31 Control DQ0–DQ31 X-Decoder Lower Bank A0–A18 Lower Bank Address 6 Am29BDD160G Latches and Control Logic Y-Decoder DQ0–DQ31 A0–A18 June 7, 2006 CONNECTION DIAGRAM IND/WAIT# RESET# WORD# RY/BY# ADV# WP# WE# OE# CE# DQ16 DQ17 DQ18 DQ19 VCCQ VSS DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VCCQ VSS DQ28 DQ29 DQ30 DQ31 A-1 A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 80-pin PQFP 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ACC VCC VSS A10 A11 A12 A13 A14 A15 A3 A4 A5 A6 A7 A8 A9 CLK VCC VSS NC NC NC VCCQ DQ15 DQ14 DQ13 DQ12 VSS VCCQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSS VCCQ DQ3 DQ2 DQ1 DQ0 NC A18 A17 A16 June 7, 2006 Am29BDD160G 7 CONNECTION DIAGRAMS 80-Ball Fortified BGA A8 A2 A7 A3 A6 A6 A5 VSS A4 ACC A3 VCC A2 A14 A1 A15 B8 A1 B7 A4 B6 A5 B5 A8 B4 A9 B3 A12 B2 A13 B1 A16 C8 A0 C7 A-1 C6 A7 C5 NC C4 A10 C3 A11 C2 A18 C1 A17 D8 DQ29 D7 DQ30 D6 DQ31 D5 NC D4 NC D3 NC D2 DQ0 D1 DQ3 E8 VCCQ E7 DQ26 E6 DQ28 E5 DQ27 E4 DQ1 E3 DQ2 E2 DQ4 E1 VCCQ F8 VSS F7 DQ24 F6 DQ25 F5 RY/BY# F4 DQ5 F3 DQ6 F2 DQ7 F1 VSS G8 VCCQ G7 DQ23 G6 DQ21 G5 DQ22 G4 DQ9 G3 DQ10 G2 DQ8 G1 VCCQ H8 DQ20 H7 J8 DQ16 J7 K8 WORD# K7 NC K6 WE# K5 VCC K4 VSS K3 CLK K2 RESET# K1 VCCQ DQ18 IND/WAIT# H6 DQ19 H5 DQ17 H4 WP# H3 DQ11 H2 DQ12 H1 DQ13 J6 OE# J5 CE# J4 NC J3 ADV# J2 DQ14 J1 DQ15 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or d a t a i ntegri ty m a y b e comprom is ed i f the p a ck a ge body is exposed to temperatures above 150°C for prolonged periods of time. 8 Am29BDD160G June 7, 2006 PIN CONFIGURATION A–1 = Least significant address bit for the 16-bit data bus, and selects between the high and low word. A –1 is not used for the 32-bit mode (WORD# = VIH). = 19-bit address bus for 16 Mb device. A9 supports 12 V autoselect inputs. = 32-bit data inputs/outputs/float = Selects 16-bit or 32-bit mode. When WORD# = VIH, data is output on DQ31–DQ0. When WORD# = VIL, data is output on DQ15–DQ0. = Chip Enable Input. This signal is asynchronous relative to CLK for the burst mode. = Output Enable Input. This signal is asynchronous relative to CLK for the burst mode. = Write enable. This signal is asynchronous relative to CLK for the burst mode. = Device ground = Pin not connected internally = Ready/Busy output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. VIO (VCCQ) VCC RESET# CLK = Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. = Load Burst Address input. Indicates that the valid address is present on the address inputs. = End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs. = Provides data valid feedback only when the burst length is set to continuous. = Write Protect input. When WP# = VOL, the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. = Acceleration input. When taken to 12 V, program and erase operations are accelerated. When not used for acceleration, ACC = VSS to VCC. = Output Buffer Power Supply (1.65 V to 2.75 V) = Chip Power Supply (2.5 V to 2.75 V) = Hardware reset input A0–A18 DQ0–DQ31 WORD# ADV# IND# WAIT# WP# CE# OE# ACC WE# VSS NC RY/BY# LOGIC SYMBOLS x16 Mode 20 A-1 to A18 CLK CE# OE# WE# RESET# ADV# ACC WP# VIO (VCCQ) WORD# RY/BY# IND/WAIT# DQ0–DQ15 16 x32 Mode 19 A0–A18 CLK CE# OE# WE# RESET# ADV# ACC WP# VIO (VCCQ) WORD# RY/BY# IND/WAIT# DQ0–DQ31 32 June 7, 2006 Am29BDD160G 9 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29BDD160 G T 54 D PB E TEMPERATURE RANGE I = Industrial (–40°C to +85°C) F = Industrial (–40°C to +85°C) with Pb-Free Package E = Extended (–40°C to +125°C) K = Extended (–40°C to +125°C) with Pb-Free Package PACKAGE TYPE K = 80-Pin Plastic Quad Flat Package (PQFP) PQR080 PB = 80-Ball Fortified Ball Grid Array (Fortified BGA) 1.0 mm pitch, 13 x 11 mm package (LAA080) CLOCK RATE A = 40 MHz C = 56 MhZ D = 66 MHz SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE T = Top sector B = Bottom sector PROCESS TECHNOLOGY G = 0.17 µm DEVICE NUMBER/DESCRIPTION Am29BDD160G 16 Megabit (1 M x 16-Bit/512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Valid Combinations for PFQP Packages AM29BDD160GT54D, AM29BDD160GB54D AM29BDD160GT64C, AM29BDD160GB64C AM29BDD160GT65A, AM29BDD160GB65A KI, KE, KF, KK Valid Combinations for Fortified BGA Packages Order Number Package Marking BD160GT54D, AM29BDD160GT54D, BD160GB54D AM29BDD160GB54D AM29BDD160GT64C, I, E, PBI, BD160GT64C, AM29BDD160GB64C F, K PBE BD160GB64C AM29BDD160GT65A, BD160GT65A, AM29BDD160GB65A BD160GB65A Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 10 Am29BDD160G June 7, 2006 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subs ection s d es crib e ea ch of these operations in further detail. June 7, 2006 Am29BDD160G 11 Table 1. Operation Autoselect Manufacturer Code Read Cycle 1 Read Cycle 2 CE# L L L OE# L L L Device Bus Operation RESET# H H H CLK X X X ADV# X X X Addresses (Note 1) A9 = VID, A6 = L, A1 = L, A0 = L A9 = VID, A6 = L, A1 = L, A0 = H A9 = VID, A7–A0 = 0Eh Data (DQ0–DQ31) 0000001h (Note 2) 000007Eh (Note 2) 0000008h Top Boot Block 0000000h WE# H H H Autoselect Device Code Read Cycle 3 L L H H X X A9 = VID, A7–A0 = 0Fh Bottom Boot Block 0000001h DOUT DIN HIGH Z HIGH Z HIGH Z 00000001h, (protected) A6 = H 00000000h (unprotect) A6 = L Read Write Standby (CE#) Output Disable Reset L L H L X L H X H X H L X H X H H H H L X X X X X X X X X X AIN AIN X HIGH Z X PPB Protection Status (Note 4) L L H H X X Sector Address, A9 = VID, A7 – A0 = 02h Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data bus Terminate Current Burst Read Cycle Terminate Current Burst Read Cycle with RESET# Terminate Current Burst Read Cycle; Start New Burst Read Cycle L L X L H H H H H AIN X X Burst Data Out H X X X H H H L X X X X X HIGH Z HIGH Z L H H H AIN X Legend: L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care. Notes: 1. DQ31–DQ16 are HIGH Z when WORD# = VIL 2. 3. 4. 5. When WORD# = VIL, DQ31-DQ16 are floating WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB Addresses are A0:A18 for the x32 mode and A–1:A18 for x16 mode. 12 Am29BDD160G June 7, 2006 VersatileI/O™ (VIO) Control The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The output voltage generated on the device is determined based on the VIO (VCCQ) level. A VIO of 1.65–1.95 volts is targeted to provide for I/O tolerance at the 1.8 volt level. A VCC and VIO of 2.5–2.75 volts makes the device appear as 2.5 volt-only. Address/Control signals are 3.6 V tolerant with the exception of CLK. tions and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Simultaneous Read/Write Operations Overview and Restrictions Overview Simultaneous Operation is an advances functionality providing enhanced speed and flexibility with minimum overhead. Simultaneous Operation does this by allowing an operation to be executed (embedded operation) in a b ank (bus y bank), then goi ng to the other bank (non-busy bank) and performing desired operations. The BDD160’s Simultaneous Operation has been optimized for applications that could most benefit from this c a p abi l i ty. T hes e a ppl i c a ti on s s tore code i n the b i g bank, while stori ng data in the small bank. The best example of this is when a Sector Erase Operation (as a n em b edded oper a t i on) i n the s m a ll (bus y) b a nk, while performing a Burst/synchronous Read Operation in the big (non-busy) bank. Restrictions The BDD160’s Simultaneous Operation is tested by executing an embedded operation in the small (busy) ba nk wh i le perform i ng other oper a t i on s i n the b i g (non-busy) bank. However, the opposite case is neither tested nor valid. That is, it is not tested by executi ng a n em b edded opera t i on i n the b i g ( bus y) b a nk wh i le perform i ng other oper a t i on s i n the s m a ll (non-busy) bank. See Table 2 Bank assi gnment for Boot Bank Sector Devices. Table 2. Bank Assignment for Boot Bank Sector Devices Bottom Boot Sector Devices Big Bank Small Bank Word/Double Word Configuration The WORD# pin controls whether the device data I/O pins operate in the word or double word configuration. If the WORD# pin is set at VIH, the device is in double word config urati on, DQ31–DQ0 are active and controlled by CE# and OE#. If the WORD# pin is set at VIL, the device is in word configuration, and only data I/O pins DQ15–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ31–DQ16 are tri-stated. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control a nd g a te s a rr a y d a t a t o the o u tp u t p i n s. W E# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This en su re s t h a t no s p u r i o us a lter a t i on of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for re ad access u ntil the command register contents are altered. Address access time (tACC) is the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE# to valid data at the output pins. The output enab le a cce ss t i me (t OE ) i s t he del a y from the f a ll i ng edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least t ACC–tOE time and CE# has been asserted for at least tCE–tOE time). See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica- Top Boot Sector Devices Bank 1 Bank 2 Small Bank Big Bank Al s o s ee Tab le 1 8 , “Allowed Oper a t i on s D u r i ng Er as e/Progr a m S us pend,” on p a ge 38. A l s o s ee Table 12, “Sector Addresses for Top Boot Sector Dev i ce s ,” on p a ge 2 9 a nd s ee Tab le 1 3 , “ S ector Addresses for Bottom Boot Sector Devices,” on page 30. Simultaneous Read/Write Operations With Zero Latency The device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to rea d from or program to another loc ation w i th i n the s a me b a nk (except the s ector b e i ng er as ed) . R efer to the DC Ch a r a cter is t i c s t ab le for June 7, 2006 Am29BDD160G 13 r e a d-wh i le-progr a m a nd re a d-wh i le-er as e c u rrent specifications. Simultaneous read/write operations are valid for both the main Flash memory array and the SecSi OTP sector. Simultaneous operation is disabled during the CFI and Password Program/Verify operati ons. PPB Program/Erase operations and the Password Unlock operation permit reading data from the large (75%) bank while reading the operation status of these commands from the small (25%) bank. Table 3. Top Boot Bank Select Bank Bank 1 Bank 2 A18:A17 00 01, 1X The AC Characteristics section contains timing specific a ti on tab le s a nd t i m ing d ia gra m s for eras e or program operations. Accelerated Program and Erase Operations The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH (12V) on the ACC pi n, the device autom atica lly enter s t he Unlock Byp ass m ode . T he s y s tem m a y then write the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses the higher voltage on the ACC pin to accelerate the operation. A sector that is being protected with the WP# pin will still be protect during accelerated program or Erase. Note that the ACC pin must not be a t V HH d u ri ng any opera ti on other th an a ccelerated programming, or device damage may result. Autoselect Functions I f the s y s tem wr i te s t he a u to s elect comm a nd s equence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0 . S tand ard rea d cycle tim ing s apply i n this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Table 4. Bank Bank 1 Bank 2 Bottom Boot Bank Select A18 0X, 10 11 Writing Commands/Command Sequences To write a command or command sequence (which incl udes progra mming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, in the x32-mode the device accepts program data in 32-bit words and in the x16 mode the dev i ce a ccept s p rogr a m d a t a i n 16- bi t words. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Byp ass m ode, only two wri te cycle s a re required to program a word or byte, instead of four. The Sector Erase and Program Suspend Command secti on h as d et ail s o n progra mm i ng d at a t o the dev i ce using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 12 and 13 indicate the address space that each sector occupies. A “sector address” consists of the address bi ts required to uniquely select a sector. The “Command Definitions” section h as details on erasi ng a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timing applies in this mode. Refer to the “Autoselect Mode” section for more information. ICC2 in the DC Characteristics table represents the active current specification for erase or program modes. Automatic Sleep Mode (ASM) The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the dev i ce a u tom a t i c a lly en ab le s t h is m ode when a ddresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the f irs t acti ve CLK level i s gre a ter tha n tACC o r the CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data. ICC8 in the “DC Characteristics” section of page 53 represents the automati c sleep mode current specification. Standby Mode When the system is not respondi ng or writing to the device, it can place the device in the standby mode. In th is m ode, c urrent con su mpt i on i s g re atly red uced, a nd the o u tp u t s a re pl a ced i n the h i gh i mped a nce state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at Vcc ± 0.2 V. The dev i ce re qui re s s t a nd a rd a cce ss t i me (t CE) for read access, before it is ready to read data. 14 Am29BDD160G June 7, 2006 If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 i n the “DC Cha racteris ti c s ” secti on on pa ge 5 3 represents the standby current specification. Caution: entering the standby mode via the RESET# pin also resets the device to the read mode and floats the data I/O pins. Furthermore, entering ICC7 during a program or erase operation will leave erroneous data in the address locations being operated on at the time of the RESET# pulse. These locations require updati ng a fter the dev i ce re su me s s t a nd a rd oper a t i on s. Refer to the “RESET#: Hardware Reset Pin” section for further discussion of the RESET# pin and its functions. operation when RESET# was asserted, the user must wait 11 µs before accessing that bank. Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locati ons be ing operated on at the ti me of dev ice res et. These locations need updating after the reset operation is complete. See Figure 19 for tim ing specifications. A s s er t i ng RE S E T # a c t i v e d u r i ng V C C a nd V I O power-up is required to guarantee proper device initialization until VCC and VIO have reached their steady state voltages. Output Disable Mode See Table 1 Device Bus Operation for OE# Operation in Output Disable Mode. RESET#: Hardware Reset Pin The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0” on this pin forces the device out of any mode that is currently executing back to the reset state. The RESET# pin may be tied to the system reset circuitry. A s y s tem re s et wo u ld th us a l s o re s et the dev i ce . To avoid a potential bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data output pins for the duration of the RESET pulse. All pins are “don’t care” during the reset operation. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset oper a t i on i s i ntern a lly complete . T h is a ct i on re qui re s between 1 µs and 7µs for either Chip Erase or Sector Er as e . T he RY/BY# p i n c a n b e u s ed to determ i ne when the re s et oper a t i on i s c omplete . O therw is e, allow for the maximum reset time of 11 µs. If RESET# is asserted when a program or erase operation is not executing (RY/BY# = “1”), the reset operation will complete within 500 ns. Since the Am29BDD160 is a Sim u lt a neo us O per a t i on dev i ce the u s er m a y re a d a bank after 500 ns i f the b a nk was i n the re a d/re s et mode at the time RESET# was asserted. If one of the banks was in the middle of either a program or erase Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verific ation, thro u gh i dent i f i er code s o u tp u t on DQ7–DQ0 . T h is mode i s p r i m a ri ly i ntended for progra mm i ng e qui pment to a u tom a t i c a lly m a tch a d ev i ce to b e progr a mmed w i th i t s c orre s pond i ng progr a mm i ng algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode re quires VID on address pi n A 9. Address pins A6, A1, a nd A0 m us t b e a s s hown i n Tab le 12 (top boot devices) or Table 13 (bottom boot devices). In addition, when verifying sector protection, the sector address mus t appear on the appropriate highes t order a ddre ss b i t s ( s ee Tab le s 11 a nd 12) . S ee Tab le 5 shows the remaining address bits that are don’t care. When all necessary bits ha ve been set a s required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To acce ss the a uto s elect codes in-sy s tem, the hos t s ys tem c a n i ssu e the a u to s elect comm a nd v ia t he comm a nd . T h is m ethod doe s n ot re qui re V ID . S ee “Command Definitions” for details on using the autoselect mode. June 7, 2006 Am29BDD160G 15 Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) A5 to A4 X X L DQ7 to DQ0 0001h 007Eh 0008h 0000h (top boot block) Description Manufacturer ID: AMD Autoselect Device Code A18 to CE# OE# WE# A11 A10 L L L L L L H H H X X X X X X A9 VID VID VID A8 X X X A7 X L L A6 L L L A3 X L H A2 X L H A1 L L H A0 L H L Read Cycle 1 Read Cycle 2 Read Cycle 3 L L H X X VID X L L L H H H H 0001h (bottom boot block) 0000h (unprotected) PPB Protection Status L L H SA X VID X L L L L L H L 0001h (protected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20. Asynchronous Read Operation (Non-Burst) The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection. OE# is the output control and should be used to gate data to the output pins if the device is selected. The dev i ce i s p ower- u p i n a n a s ynchrono us r e a d mode. In the asynchronous mode the device has two control functi ons whi ch must be satisfied in order to obtai n data at the outputs. CE# is the power control and should be used for device selection. OE# is the output control and should be used to gate data to the output pins if the device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable a cce ss t i me (t CE ) i s t he del a y from the s t ab le a ddre ss e s a nd s t ab le CE# to v a l i d d a t a a t the o u tp u t pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least tACC–tOE time). CE# CLK ADV# A0-A18 DQ0-DQ31 OE# WE# IND/WAIT# VIH Float Float VOH Address 0 Address 1 Address 2 Address 3 D0 D1 D2 D3 D3 Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required. Figure 1. Asynchronous Read Operation 16 Am29BDD160G June 7, 2006 Synchronous (Burst) Read Operation The Am29BDD160 is capable of performing burst read operation s to improve total system data throughput. The device is available in three burst modes of operation : li nea r and burst mode . 2, 4 and 8 doub le word (x3 2) a nd 4 a nd 8 word (x16) a cce sse s a re conf i gurable as either sequential burst accesses. 16 and 32 word (x16) access es are only confi gurable as linear burst accesses. Additional options for all burst modes i ncl u de i n i t ia l a cce ss d el a y conf i g u r a t i on s ( 2–16 CLKs) Device configuration for burst mode operation is accomplished by writing the Configuration Register with the desired burst configuration information. Once the Configuration Register i s wri tten to enab le burs t mode operation, all subsequent reads from the array are returned using the burst mode protocols. Like the main memory access, the SecSi Sector memory is accessed with the same burst or asynchronous timing as defined i n the Conf ig urati on Regis ter. H owever, the user must recognize that continuous burst operations past the 256 byte SecSi boundary returns invalid data. B u rs t re a d opera t i on s o cc u r only to the m ai n fl as h memory arrays. The Configuration Register and protecti on b i t s a re tre a ted a s s i ngle cycle re a ds , even when b u r s t mode i s e n ab led . R e a d oper a t i on s t o Table 6. Data Transfer Sequence (Independent of the WORD# pin) Two Linear Data Transfers, (x32 only) the s e loc a t i on s r e su lt s i n the d a t a r em ai n i ng v a l i d while OE# is at VIL, regardless of the number of CLK cycles applied to the device. Linear Burst Read Operations Li nea r bu rs t re ad mode rea ds e ither 4, 8, 16, or 3 2 words (1 word = 16 bits), depending upon the Configuration Register option. If the device is configured with a 32 bit interface (WORD# = VIH), the burst access is compr is ed of 4 clocked re a d s f or 8 w ord s a nd 16 clocked reads for 32 words (See Table 6 for all valid bu r s t o u tp u t s e qu ence s ) . T he n u m b er of clocked reads is doubled when the device is configured in the 16-bit data bus mode (WORD# = VIL). The IND/WAIT# pin transitions acti ve (VIL ) during the las t trans fer of data during a linear burst read before a wrap around, i nd i c a t i ng th a t the s y s tem s ho u ld i n i t ia te a nother ADV# to start the next burst access. If the system cont i n u e s t o clock the dev i ce, the next a cce ss w r a p s around to the sta rti ng a ddre ss of the prev ious bu rs t access. The IND/WAIT# signal remains inactive (floating) when not active. See Table 6 for a complete 32 and 16 bit data bus i nterface order. 16 and 3 2 word opti on s are re stricted to se quent ia l bu rst a ccesses, only. 16-Bit and 32-Bit Linear and Burst Data Order Output Data Sequence (Initial Access Address) (x16) 0-1 (A0 = 0) 1-0 (A0 = 1) 0-1-2-3 (A0:A-1/A1-A0 = 00) Four Linear Data Transfers 1-2-3-0 (A0:A-1/A1-A0 = 01) 2-3-0-1 (A:A-1/A1-A0 = 10) 3-0-1-2 (A0:A-1/A1-A0 = 11) 0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000) 1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001) 2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010) 3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011) 4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100) 5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101) 6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110) 7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111) Eight Linear Data Transfers June 7, 2006 Am29BDD160G 17 Table 6. Data Transfer Sequence (Independent of the WORD# pin) 16-Bit and 32-Bit Linear and Burst Data Order (Continued) Output Data Sequence (Initial Access Address) (x16) 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000) 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 (A2:A-1/ A3-A0 = 0001) 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 (A2:A-1/ A3-A0 = 0010) 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 (A2:A-1/ A3-A0 = 0011) 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 (A:A-1/ A3-A0 = 0100) 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 (A2:A-1/ A3-A0 = 0101) 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 (A2:A-1/ A3-A0 = 0110) Sixteen Linear Data Transfers (X16 Only) 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 (A2:A-1/ A3-A0 = 0111) 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 (A2:A-1/ A3-A0 = 1000) 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 (A2:A-1/ A3-A0 = 1001) A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 (A2:A-1/ A3-A0 = 1010) B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A (A2:A-1/ A3-A0 = 1011) C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B (A2:A-1/ A3-A0 = 1100) D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C (A2:A-1/ A3-A0 = 1101) E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D (A2:A-1/ A3-A0 = 1110) F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E (A2:A-1/ A3-A0 = 1111) 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000) 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-0 (A3:A-1 = 00001) Thirty-Two Linear Data Transfers : U-V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T (A3:A-1 = 11110) V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U (A3:A-1 = 11111) CE# Control in Linear Mode The CE# (Chip Enable) pin enables the Am29BDD160 during read mode operations. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during the burst linea r or bu rst cycle, the devi ce i mmed iately exi ts the burst sequence and floats the DQ bus and IND/WAIT# si gn a l . R e s ta rt i ng a bu r s t cycle i s a ccompl is hed b y taking CE# and ADV# to VIL. ADV# Control In Linear Mode The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE# and ADV# are at VIL and the device is configured for either linear burst mode operation. A burst access is initiated and the a ddre ss i s l a tched on the f i rst risi ng CLK edge when ADV# i s a ct i ve or u pon a r isi ng ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the prev i o us a ddre ss i s d is c a rded a nd s ubs e qu ent b u r s t transfers are invalid until ADV# transitions to VIH before a c lock edge, wh i ch i n i t ia te s a n ew b u r s t s equence. RESET# Control in Linear Mode The RESET# pin immediately halts the linear burst acce ss w hen t a ken to V I L . T he DQ d a t a b us a nd IND/WAIT# signal float. Additionally, the Configuration Register contents are reset back to the default condition where the device is placed in as ynchronous access mode. OE# Control in Linear Mode The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus and the IND/WAIT# pin. De-asserting the OE# pin to VIH during a burst opera ti on flo a t s the d at a b us a nd the IND/WAIT# p i n . However, the device will continue to operate internally as if the burst sequence continues until the linear burst is complete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse. The DQ bus and IND/WAIT# signal remain in the float state until OE# is taken to VIL. IND/WAIT# Operation in Linear Mode The IND/WAIT#, or End of B u r s t Ind i c a tor s i gn a l (when in linear modes ), i nforms the s ystem that the last address o f a bu rst sequ ence is on the DQ dat a bus. For example, i f a 4-word li nea r burst access is 18 Am29BDD160G June 7, 2006 en ab led u si ng a 16-bi t DQ bus (WORD# = V IL ), the IND/WAIT# signal transitions active on the fourth acce ss. I f the s a me s cen a ri o i s u s ed, b u t i n s te a d the 32-bit DQ bus is enabled, the IND/WAIT# signal transiti on s acti ve on the s econd a cce ss. T he IND/WAIT# signal has the same delay and setup timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# s i gn a l . I f OE# i s a t V IH, the IND/WAIT# s i gn a l floats and is not driven. If OE# is at VIL, the IND/WAIT# signal is driven at VIH until it transitions to VIL indicating the end of burst sequence. The IND/WAIT# signal timing and duration is (See “Configuration Register” for more i nformation). The following table lis ts the vali d combin ations of the Config urat ion Register bi ts th at impact the IND/WAIT# timing. June 7, 2006 Am29BDD160G 19 Table 7. DOC 0 0 WC 0 1 CC 1 1 Definition Valid Configuration Register Bit Definition for IND/WAIT# IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge CE# CLK 3 Clock Delay ADV# A0-A18 Address 1 Address 1 Latched Address 2 Invalid D1 D2 D3 D0 OE# IND/WAIT# Note: Operation is shown for the 32-bit data bus. For a 16-bit data bus, A-1 is required. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around. Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation 20 Am29BDD160G June 7, 2006 Burst Access Timing Control In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial access delay, delivery of data on the CLK edge, and the length of time data is held. Initial Burst Access Delay Control The Am29BDD160 contains options for initial access delay of a burst access. The initial access delay has no effect on asynchronous read operations. Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first valid clock edge a fter ADV# a ss ert i on (or the r isi ng edge of ADV#) until the first valid CLK edge when the data is valid. The b u r s t a cce ss i s i n i t ia ted a nd the a ddre ss i s latched on the first rising CLK edge when ADV# is acti ve or upon a risi ng ADV# edge, wh ichever come s first. (See Table 8 describes the initial access delay confi gu rati ons.) If the Clock Conf ig u ra ti on bi t i n the Control Register is set to falling edge (CR6 = 0), the definition remains the same for the initial delay setting wi th the excepti on tha t da ta i s v al i d after the f all ing edge. Table 8. Burst Initial Access Delay Initial Burst Access (CLK cycles) CR13 0 0 0 0 0 0 0 0 CR12 0 0 0 0 1 1 1 1 CR11 0 0 1 1 0 0 1 1 CR10 0 1 0 1 0 1 0 1 54D, 64C, 65A 2 3 4 5 6 7 8 9 1st CLK 2nd CLK 3rd CLK 4th CLK 5th CLK CLK ADV# A18-A0 DQ31-DQ03 DQ31-DQ04 DQ31-DQ05 Valid Address Address 1 Latched Three CLK Delay D0 D1 D0 D2 D1 D0 D3 D2 D1 D4 D3 D2 Four CLK Delay Five CLK Delay Figure 3. Initial Burst Delay Control Notes: 1. Burst access starts with a rising CLK edge and when ADV# is active. 2. 3. 4. 5. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge. CR [13-10] = 1 or three clock cycles CR [13-10] = 2 or four clock cycles CR [13-10] = 3 or Five clock cycles June 7, 2006 Am29BDD160G 21 Burst CLK Edge Data Delivery The Am29BDD160 is capable of delivering data on either the rising or falling edge of CLK. To deliver data on the rising edge of CLK, bit 6 in the Control Register (CR6) is set to 1. To deliver data on the falling edge of CLK, bit 6 in the Control Register is cleared to 0. The default configuration is set to the rising edge. Burst Data Hold Control The device is capable of holding data for one CLKs. The default configuration is to hold data for one CLK and is the only valid state. Asserting RESET# During A Burst Access If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults b ack to asynchronous read mode. Refer to RESET#: Hardware Reset Pin for more information on the RESET# function. Configuration Register does not occupy any addressable memory location, but rather, is accessed by the Configuration Register commands. The Configuration Reg is ter i s re a dab le a ny ti me, however, wr it i ng the Configuration Register is restricted to times when the Em b edded Algori thm™ i s n ot a ct i ve . I f the u s er a ttempts to wri te the Configu rat ion Register while the Embedded Algorithm™ is active, the write operation is ignored and the contents of the Configuration Register remain unchanged. The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. Data on DQ31–DQ16 is ignored during a write operation when WORD# = VIL. During a read operation, DQ31–DQ16 returns all zeroes. Table 9 shows the Configuration Register. Also, Configuration Register reads operate the same as Autoselect comm and read s. When the comma nd is i ssu ed, the b a nk a ddre ss i s l a tched a long w i th the comm a nd . R e a d s o per a t i on s t o the b a nk th a t w as specified during the Configuration Register read comma nd return Conf ig ura tion Register contents. R ea d operations to the other bank return flash memory data. E i ther b a nk a ddre ss i s p erm i tted when wr i t i ng the Configuration Register read command. Configuration Register The Am29BDD160 contains a Configuration Register for configuring read accesses. The Configuration Register is accessed by the Configuration Register Read and the Configuration Register Write commands. The Table 9. CR15 RM CR14 Reserved CR13 IAD3 Configuration Register Definitions CR12 IAD2 CR11 IAD1 CR10 IAD0 CR9 DOC CR8 WC CR7 BS CR6 CC CR5 Reserved CR4 Reserved CR3 Reserved CR2 BL2 CR1 BL1 CR0 BL0 Configuration Register CR15 = Read Mode (RM) 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) CR14 = Reserved for Future Enhancements These bits are reserved for future use. Set these bits to “0”. 22 Am29BDD160G June 7, 2006 Table 9. Configuration Register Definitions (Continued) CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0) Speed Options 54D, 64C, 65A: 0000 = 2 CLK cycle initial burst access delay 0001 = 3 CLK cycle initial burst access delay 0010 = 4 CLK cycle initial burst access delay 0011 = 5 CLK cycle initial burst access delay 0100 = 6 CLK cycle initial burst access delay 0101 = 7 CLK cycle initial burst access delay 0110 = 8 CLK cycle initial burst access delay 0111 = 9 CLK cycle initial burst access delay—Default CR9 = Data Output Configuration (DOC) 0 = Hold Data for 1-CLK cycle—Default 1 = Reserved CR8 = IND/WAIT# Configuration (WC) 0 = IND/WAIT# Asserted During Delay—Default 1 = IND/WAIT# Asserted One Data Cycle Before Delay CR7 = Burst Sequence (BS) 0 = Reserved 1 = Linear Burst Order—Default CR6 = Clock Configuration (CC) 0 = Reserved 1 = Burst Starts and Data Output on Rising Clock Edge—Default CR5–CR3 = Reserved For Future Enhancements (R) These bits are reserved for future use. Set these bits to “0.” CR2–CR0 = Burst Length (BL2–BL0) 000 = Reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (8-byte) Burst Data Transfer - x16 and x32 Linear 010 = 128 bit (16-byte) Burst Data Transfer - x16 and x32 Linear 011 = 256 bit (32-byte) Burst Data Transfer - x16 Linear Only and x32 Linear 100 = 512 bit (64-byte) Burst Data Transfer - x16 Linear Only - Default 101 = Reserved, burst accesses disabled (asynchronous reads only) 110 = Reserved, burst accesses disabled (asynchronous reads only) 111 = Reserved June 7, 2006 Am29BDD160G 23 Table 10. CR15 RM 1 CR14 Reserve 0 CR13 IAD3 0 Configuration Register After Device Reset CR12 IAD2 1 CR11 IAD1 1 CR10 IAD0 1 CR9 DOC 0 CR8 WC 0 CR7 BS 1 CR6 CC 1 CR5 Reserve 0 CR4 Reserve 0 CR3 Reserve 0 CR2 BL2 1 CR1 BL1 0 CR0 BL0 0 Initial Access Delay Configuration The frequency configuration informs the device of the n u m b er of clock s t h a t m us t el a p s e a fter ADV# i s driven active before data will be available. This value is determined by the input clock frequency. SECTOR PROTECTION The Am2 9BDD160 features s everal level s of s ector protection, whi ch can disab le b oth the program and erase operations in certain sectors or sector groups Sector and Sector Groups The distinction between sectors and sector groups is fundamental to sector protection. Sector are individual sectors that can be indivi dually s ector protected/unprotected. These are the outermost 4 kword boot sector s , th a t i s , S A0 to S A7 a nd S A 38 t o S A45 . S ee tables 11 and 12. Sector groups are a collection of three or four adjacent 32 kword sectors. For example, sector group SG8 is comprised of sector SA8 to SA10. When any sector in a sector group is protected/unprotected, every sector in that group is protection/unprotected. See Tables 11 and 12. Persistent Sector Protection A comma nd s ector protecti on method th at repl aces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase to the two outermost 8 Kbytes sectors in the 75% bank All p a rts d ef ault to operate i n the Persis tent S ector Protection mode. The customer must then choose if the Persistent or Password Protection method is most de si r ab le . T here a re two one-t i me progr a mm ab le non-vol at i le bi t s t ha t def ine whi ch s ector protecti on method will be used. If the customer decides to continue using the Persistent Sector Protection method, they m us t s et the P er sis tent S ector Protect i on Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the c ustomer dec ides to u se the pass word method, they must set the Password Mode Locking Bit. This w i ll perm a nently s et the p a rt to opera te only u si ng password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Pa ss word Mode Lock i ng Bi t p erm a nently s elects the protection mode. I t i s n ot po ssible to s wi tch b etween the two methods once a locki ng bi t has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protect i on method wh i le a t the same time enhancing flexibility by providing three different sector protection states: ■ Persistently Locked—A sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command ■ Unlocked—The sector is unprotected and can be changed by a simple command 24 Am29BDD160G June 7, 2006 In order to achieve these states, three types of “bits” are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four sectors (see the sector addre ss t able s for s pec i f i c s ector protect ion gro u pings). All 8 Kbyte boot-block sectors have indivi dual s ector Per sistent Protecti on Bi ts (PPB s) for gre ater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibili ty of the u s er to perform the preprogr a mm i ng operation. Otherwise, an already erased sector PPBs has t he potentia l of be i ng over-er as ed . There i s n o h a r dw a r e m ech a n is m t o pr ev ent s ec tor PP B s over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot b e ch a nged . W hen cle a red (“0”), the PPB s a re changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A vol ati le protecti on bi t is a ssi gned for each sector. After power-up or hardware reset, the contents of all DYB s i s “ 0” . E a ch DYB i s i nd i v i d ua lly mod i f iab le through the DYB Write Command. When the p a rt s a re f i r s t s h i pped, the PPB s a re cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power u p cle a red ( s ectors n ot protected) . T he Protect i on State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By i ssuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. Thes e are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very eas y to switch back and forth between the protected and unprotected condi t ions. Th is a llows s oftwa re to easi ly protect sectors against inadvertent changes yet does not prevent the e as y remov a l of protect i on when changes are needed. The DYBs maybe set or cleared as often as needed. The PPB s a llow for a m ore s t a t i c, a nd d i ff i c u lt to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desi red settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clea r the PPB Lock i s t o go thro u gh a p ower cycle . System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code c a n s et the PPB Lock to d isab le a ny f u rther changes to the PPBs during system operation. The WP# write protect pin adds a final level of hardware protection to the two outermost 8 Kbytes sectors in the 75% bank. When this pin is low it is not possible to change the contents of these two sectors. It i s possible to have s ectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a si mple DYB Wri te comma nd s e qu ence i s a ll th at i s necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respecti vely. If there i s a need to change the s t a t us o f the per sis tently locked s ector s , a f ew more steps are required. First, the PPB Lock bit must b e d isab led b y e i ther p u tt i ng the dev i ce thro u gh a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs , and the device operates normally again. Note: to achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. June 7, 2006 Am29BDD160G 25 Table 11. Sector Protection Schemes PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable co u ld not pl a ce the dev i ce i n p ass word protect i on mode. DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable Password Protection Mode The Password Sector Protection Mode method allows an even hi gher level of s ecu ri ty th an the Persis tent S ector Protect i on Mode . There a re two m ai n di fferences between the Persistent Sector Protection and the Password Sector Protection Mode: ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command mus t be written to the fl as h, a long w i th a p ass word . T he fl as h dev i ce i ntern a lly comp a re s t he g i ven p ass word w i th the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not m a tch, the fl as h dev i ce doe s n oth i ng . T here i s a bui lt- i n 2 µs d el a y for e a ch “pass word check . ” Th is delay is intended to thwart any efforts to run a program that tries all possible combi nations i n order to crack the password. Tab le 11 cont ai n s a ll po ssib le com bi n a t i on s o f the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed u nti l the next power cycle cle a rs the PPB lock. If the PPB is cleared, the sector can be dynamic a lly locked or u nlocked . T he DYB then control s whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modif i ed the content s o f the protected s ector. A n er as e command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. Password and Password Mode Locking Bit In order to s elect the P ass word s ector protect i on s cheme, the cus tomer m us t fi rs t progra m the password. One method of choosing a password would be to correlate it to the unique Electronic Serial Number (ESN) of the particular flash device. Another method could generate a database where all the passwords are stored, each of which correlates to a serial number on the device. Each ES N i s different for every fl as h device; therefore each password should be different for every flash device. While programming in the password reg i on, the c us tomer m a y perform P ass word Verify operations. Once the de si red p ass word i s p rogr a mmed i n, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protecti on locking bit prevents programming of the password protection mode locking bit. This guarantees that an unauthorized user 26 Am29BDD160G June 7, 2006 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefu lly consi dered, m a y le ad to u nrecoverable errors. The user must be sure that the Password Protection method is desired when setting the P assword Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations a re d isab led, there i s n o me a n s t o ver i fy wh a t the password i s afterwards. If the password is l ost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bi t i s disabled from programmi ng, g uarantee ing that no changes to the protection scheme are allowed. 64-bit Password The 64- bi t P ass word i s l oc a ted i n i t s o wn memory space and is accessible through the use of the Password Program and Verify commands (see Password Veri fy Comm a nd). T he p ass word f u nct i on work s i n con ju nct i on w i th the P ass word Mode Lock i ng B i t, which when set, prevents the P assword Verify command from reading the contents of the pass word on the pins of the device. during the entire program or erase operation of the two outermost sectors in the 75% bank. SecSi™ (Secured Silicon) Sector Protection The S ec Si S ector i s a 2 56- b yte fl as h memory a re a th a t i s e i ther progr a mm ab le a t the c us tomer or b y AMD at the request of the customer. The SecSi Sector Entry command enables the host system to address the S ec Si S ector for progr a mm i ng or re a d i ng . T he SecSi sector address range is 00000h–0003Fh for the top bootblock configuration and 7FFC0h–7FFFFh for the bottom b ootb lock conf i g u ra t i on . A ddre ss ra nge 00040h–007FFh for the top bootblock and 7F800h–7FFBFh return invalid data when addressed with the SecSi sector enabled. Unlike previous flash memory devices, the Am2 9 BDD160 a llow s s i m u lt a neous o perat i on wh i le the S ec Si s ector i s e n ab led . H owever, there a re a number of restrictions associated with simultaneous operation and device operation when the SecSi sector is enabled: 1. The SecSi sector is not available for reading while the Password Unlock, any PPB program/erase operation, or Password programming are in progress. Reading to any location in the small (25%) sector will return the status of these operations until these operations have completed execution. 2. Writing the corresponding DYB associated with the overlaid bootblock sector results in the DYB NOT being updated. This is only accomplished when the SecSi sector is not enabled. 3. Reading the corresponding DYB associated with the overlaid bootblock sector results in reading inv al i d d at a w hen the PPB Lock/DYB Ver i fy command is issued. This function is only accomplished when the SecSi sector is not enabled. 4. All commands are available for execution when the SecSi sector is enabled except the following list. Issuing the following commands while the SecSi sector i s e n ab led re su lt s i n the comm a nd b e i ng ignored. ■ All Unlock Bypass commands ■ CFI ■ Accelerated Program ■ Program and Sector Erase Suspend ■ Program and Sector Erase Resume 5. Executing the Sector Erase command is permitted when the SecSi sector is enabled, however, there is no provision for erasing the SecSi sector with the Sector Erase command, regardless of the protection status. The Sector Erase command will erase all other sectors when the SecSi sector is enabled. Write Protect (WP#) The dev i ce fe a t u re s a h a rdw a re protect i on opt i on using a write protect pin that prevents programming or erasing, regardless of the state of the sector’s Persistent or Dynamic Protection Bits. The WP# pin is associated with the two outermost 8Kbytes sectors in the 75% bank. The WP# p in has n o effect on any other sector. When WP# is taken to VIL, programming and erase operations of the two outermost 8 Kbytes sectors i n the 75 % b a nk a re d isab led . B y t a k i ng WP# back to VIH, the two outermost 8 Kbytes sectors are enabled for program and erase operations, depending upon the status of the individual sector Persistent or Dynamic Protection Bits. If either of the two outermost sectors Persistent or Dynamic Protection Bits are programmed, program or erase operations are inhibited. If the sector Persistent or Dynamic Protection Bits are b oth erased, the two s ectors a re a v ai l ab le for programming or erasing as long as WP# remains at VIH. The user must hold the WP# pi n at ei ther V IH o r VIL June 7, 2006 Am29BDD160G 27 6. Executing the Chip Erase command is permitted when the SecSi sector is enabled. The Chip Erase command erases all sectors in the memory array except for sector 0 in top-bootblock configuration and sector 45 in bottom-bootblock configuration. The S ec Si S ector i s a o ne-t i me progr a mm ab le memory area that cannot be erased. 7. Executing the SecSi Sector Entry command during program or erase suspend mode is allowed. The Sector Erase/Program Resume command is dis abled while the SecSi sector is enabled, and the user cannot resume programming of the memory array until the Exit SecSi Sector command is written. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection agai ns t in advertent writes. In addi tion, the following hardware data protection measures prevent accidental er asu re or progra mm i ng, whi ch mi ght otherw is e b e caus ed by s purious sys tem level signal s during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power- u p a nd power-down . T he comm a nd reg is ter and all internal erase/program circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection SecSi Sector Protection Bit The S ec Si S ector Protect i on B i t prevents p rogra mming of the SecSi sector memory area. Once set, the SecSi sector memory area contents are non-modi fiable. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locki ng B i t a fter power-u p re s et . I f the P ass word Mode Lock i ng B i t i s s et, wh i ch i nd i c a te s t he dev i ce i s i n Password Protection Mode, the PPB Lock Bit is also s et a fter a h ardw a re re s et (RE S ET# a ss erted) or a power- u p re s et . T he ONLY me a n s f or cle a ri ng the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the P ass word Unlock comma nd cle a r s t he PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit back to a “1”. If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection Mode. Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH). Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power-up, the device does not accept commands on the risi ng edge of WE#. The internal state machine is automatically reset to reading array data on power-up. VCC and VIO Power-up And Power-down Sequencing The dev i ce i mpo s e s no re s tri cti on s on V CC a nd V IO power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC and VIO power se quence unt il the respective s uppli es reach their operating voltages. Once, VCC and VIO attain their re s pect i ve oper a t i ng volt a ge s , de- ass ert i on of RESET# to VIH is permitted. 28 Am29BDD160G June 7, 2006 Table 12. Sector Addresses for Top Boot Sector Devices x16 Address Range (A18:A-1) 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-F8FFFh F9000h-F9FFFh FA000h-FAFFFh FB000h-FBFFFh FC000h-FCFFFh FD000h-FDFFFh FE000h-FEFFFh FF000h-FFFFFh x32 Address Range (A18:A0) 00000h-007FFh 00800h-00FFFh 01000h-017FFh 01800h-01FFFh 02000h-027FFh 02800h-02FFFh 03000h-037FFh 03800h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1FFFFh 20000h-23FFFh 24000h-27FFFh 28000h-2BFFFh 2C000h-2FFFFh 30000h-33FFFh 34000h-37FFFh 38000h-3BFFFh 3C000h-3FFFFh 40000h-43FFFh 44000h-47FFFh 48000h-4BFFFh 4C000h-4FFFFh 50000h-53FFFh 54000h-57FFFh 58000h-5BFFFh 5C000h-5FFFFh 60000h-63FFFh 64000h-67FFFh 68000h-6BFFFh 6C000h-6FFFFh 70000h-73FFFh 74000h-77FFFh 78000h-7BFFFh 7C000h-7C7FFh 7C800h-7CFFFh 7D000h-7D7FFh 7D800h-7DFFFh 7E000h-7E7FFh 7E800h-7EFFFh 7F000h-7F7FFh 7F800h-7FFFFh Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Bank 1 (Note 2) Bank 2 (Note 2) Sector SA0 (Note 1) SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 (Note 3) SA45 (Note 3) Sector Group SG0 SG1 SG2 SG 3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 Notes: 1. SecSi Sector overlays this sector when enabled. 2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2. 3. This sector has the additional WP# pin sector protection feature. June 7, 2006 Am29BDD160G 29 Table 13. Sector Addresses for Bottom Boot Sector Devices x16 Address Range (A18:A-1) 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-F8FFFh F9000h-F9FFFh FA000h-FAFFFh FB000h-FBFFFh FC000h-FCFFFh FD000h-FDFFFh FE000h-FEFFFh FF000h-FFFFFh x32 Address Range (A18:A0) 00000h-007FFh 00800h-00FFFh 01000h-017FFh 01800h-01FFFh 02000h-027FFh 02800h-02FFFh 03000h-037FFh 03800h-03FFFh 04000h-07FFFh 08000h-0BFFFh 0C000h-0FFFFh 10000h-13FFFh 14000h-17FFFh 18000h-1BFFFh 1C000h-1FFFFh 20000h-23FFFh 24000h-27FFFh 28000h-2BFFFh 2C000h-2FFFFh 30000h-33FFFh 34000h-37FFFh 38000h-3BFFFh 3C000h-3FFFFh 40000h-43FFFh 44000h-47FFFh 48000h-4BFFFh 4C000h-4FFFFh 50000h-53FFFh 54000h-57FFFh 58000h-5BFFFh 5C000h-5FFFFh 60000h-63FFFh 64000h-67FFFh 68000h-6BFFFh 6C000h-6FFFFh 70000h-73FFFh 74000h-77FFFh 78000h-7BFFFh 7C000h-7C7FFh 7C800h-7CFFFh 7D000h-7D7FFh 7D800h-7DFFFh 7E000h-7E7FFh 7E800h-7EFFFh 7F000h-7F7FFh 7F800h-7FFFFh Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Bank 1 (Note 2) Bank 2 (Note 2) Sector SA0 (Note 1) SA1 (Note 1) SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 (Note 3) Sector Group SG0 SG1 SG2 SG 3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 Notes: 1. This sector has the additional WP# pin sector protection feature. 2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 1 and BA = 11 for Bank 2. 3. SecSi Sector overlays this sector when enabled. 30 Am29BDD160G June 7, 2006 COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outli nes device a nd host system softw are interrog ation h a nd s h a ke, wh i ch a llow s s pec i fi c vendor-s pec i f i ed softwa re algorithm s to be u sed for entire fam ili es of devices. Softw are su pport can then be devi ce-independent, JEDEC ID-i ndependent, and forwa rd- and ba ckw a rd-comp a tible for the s pec i f i ed fl as h dev i ce families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any t i me the dev i ce i s r e a dy to re a d a rr a y d a t a. T he s y s tem c a n re a d CFI i nform a t i on a t the a ddre ss e s given in Tables 13–16. To terminate reading CFI data, the system must write the reset command. T he sy s tem c an al s o wri te the CFI q uery comm and when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 13–16. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specific a t i on a nd CFI P ub l i c a t i on 100, a v ai l ab le v ia t he World W i de We b a t http : //www .a md . com/product s /nvd/overview/cfi.html . A ltern a ti vely, conta ct a n AMD representative for copies of these documents. Table 14. CFI Query Identification String Addresses (x32 Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (x16 Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 15. Addresses (x32 Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (x16 Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0023h 0027h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0007h 0000h CFI System Interface String Description VCC Min. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt VCC Max. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single word/doubleword program 2N µs Typical timeout for Min. size buffer program 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for word/doubleword program 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) June 7, 2006 Am29BDD160G 31 Table 16. CFI Device Geometry Definition Addresses (x32 Mode) 27h Addresses (x16 Mode) 4Eh Data 0015h Device Size = 2 byte Flash Device Interface description (for complete description, please refer to CFI publication 100) 0000 = x8-only asynchronous interface 28h 29h 50h 52h 0005h 0000h 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via BYTE# with asynchronous interface 0003 = x 32-only asynchronous interface 0005 = supports x16 and x32 via WORD# with asynchronous interface 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0000h 0000h 0003h 0004h 0007h 0000h 0020h 0000h 001Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Max. number of byte in multi-byte program = 2N (00h = not supported) Number of Erase Block Regions within device 0003 = Speed options 54D, 65D, 65A Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) N Description Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Table 17. Addresses (x32 Mode) 40h 41h 42h 43h 44h Addresses (x16 Mode) 80h 82h 84h 86h 88h CFI Primary Vendor-Specific Extended Query Data 0050h 0052h 0049h 0031h 0033h Description Query-unique ASCII string “PRI” Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (DQ1, DQ0) 00 = Required, 01 = Not Required 45h 8Ah 0004h Silicon Revision Number (DQ5–DQ2 0000 = CS49 0001 = CS59 0010 = CS99 0011 = CS69 0100 = CS119 32 Am29BDD160G June 7, 2006 Table 17. CFI Primary Vendor-Specific Extended Query (Continued) Addresses (x32 Mode) Addresses (x16 Mode) Data Erase Suspend (1 byte) 00 = Not Supported 01 = To Read Only 02 = To Read and Write Sector Protect (1 byte) 00 = Not Supported, X = Number of sectors in per group Temporary Sector Unprotect 00h = Not Supported, 01h = Supported Sector Protect/Unprotect scheme (1 byte) 01 =29F040 mode, 02 = 29F016 mode 03 = 29F400 mode, 04 = 29LV800 mode 05 = 29BDS640 mode (Software Command Locking) 06 = BDD160 mode (New Sector Protect) 07 = 29LV800 + PDL128 (New Sector Protect) mode Simultaneous Operation (1 byte) 00h = Not Supported, X = Number of sectors in all banks except Bank 1 Burst Mode Type 00h = Not Supported, 01h = Supported Page Mode Type 00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) ACC (Acceleration) Supply Maximum 00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) Top/Bottom Boot Sector Flag (1 byte) 00h = Uniform device, no WP# control, 01h = 8 x 8 Kb sectors at top and bottom with WP# control 02h = Bottom boot device 03h = Top boot device 04h = Uniform, Bottom WP# Protect 05h = Uniform, Top WP# Protect If the number of erase block regions = 1, then ignore this field Program Suspend 00 = Not Supported 01 = Supported Write Buffer Size 2(N+1) word(s) Bank Organization (1 byte) 00 = If data at 4Ah is zero XX = Number of banks Bank 1 Region Information (1 byte) XX = Number of Sectors in Bank 1 Bank 2 Region Information (1 byte) XX = Number of Sectors in Bank 2 Bank 3 Region Information (1 byte) XX = Number of Sectors in Bank 3 Bank 4 Region Information (1 byte) XX = Number of Sectors in Bank 4 Description 46h 8Ch 0002h 47h 48h 8Eh 90h 0001h 0000h 49h 92h 0006h 4Ah 4Bh 4Ch 4Dh 4Eh 94h 96h 98h 9Ah 9Ch 001Fh 0001h 0000h 00B5h 00C5h 4Fh 9Eh 0001h 50h A0h 0001h 51h A2h 0000h 57h AEh 0002h 58h 59h B0h B2h 000Fh 001Fh 5Ah 5Bh B4h B6h 0000h 0000h June 7, 2006 Am29BDD160G 33 COMMAND DEFINITIONS Wri ting speci fic address and data commands or s equences into the command register initiates device oper a t i on s. Tab le s 1 8 -21 def i ne the v a l i d reg is ter command sequences. Writing incorrect address and data value s o r wr i t i ng them i n the i mproper s equence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the risi ng edge of WE# or CE#, whi chever happens first. Refer to the AC Characteristics section for timing diagrams. The RES ET# comm and wi ll not termi n ate the B urst mode . S ystem reset (power on re set) w ill termi nate the Burst mode. The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output Enable (OE#) to control norm a l re a d a nd wri te oper a ti ons. Moreover, three a dd i t i on a l control p i n s h a ve b een added to allow easy interface with minimal glue logic to a wide range of microprocessors / microcontrollers for high performance Burst read capability. These add i t i on a l p i n s a re Addre ss Va l i d (ADV#) a nd Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst mode read operation is a synchronous operation tied to the edge of the clock. The microprocessor / microcontroller supplies only the initial address, all subsequent addresses are automatically generated by the device with a timing defined by the Configuration Register definition. The Burst read cycle consists of an address phase and a corresponding data phase. During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock period. Together with the edge of the CLK, the starting burst addre ss i s l o a ded i nto the i ntern a l B u r s t Addre ss Counter. The internal Burst Address Counter can be configured to either the Linear modes (See “Initial Access Delay Configuration”). During the data phase, the first burst data is available after the initial access time delay defined in the Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK will trigger the output data with the burst output delay and sequence defined in the Configuration Register. Tables 17–20 show all the commands executed by the dev i ce . T he dev i ce a u tom a t i c a lly powers u p i n the read/reset state. It is not necessary to issue a read/reset command after power-up or hardware reset. Reading Array Data in Non-burst Mode The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the dev i ce a ccept s a n Er as e S us pend command, the device enters the Erase Suspend mode. The system can read array data using the standard re a d t i m i ng s , except th a t i f i t re a d s a t a n a ddre ss within erase-suspended sectors, the device outputs status data. After completing a programming operat i on i n the Er ase S us pend mode, the s y s tem m a y once again read array data with the same exception. See Sector Erase and Program Suspend Command for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. section. See also Asynchronous Read Operation (Non-Burst) in the Key to S w i tch i ng Wa veform s s ect i on for more information. See the Sector Erase and Program Resume Command sections for more information on this mode. Read/Reset Command After power-up or hardware reset, the Am29BDD160 automatically enter the read state. It is not necessary to issue the res et command after power-up or hardware reset. Standard microprocessor cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted since the Configuration Register is at its reset state with burst accesses disabled. The Reset command is executed when the user needs to ex i t a ny of the other u s er comm a nd s e qu ence s (such as autoselect, program, chip erase, etc.) to ret u rn to re a d i ng a rra y d a t a. T here i s n o l a tency b etween exec u t i ng the Re s et comm a nd a nd re a d i ng array data. Reading Array Data in Burst Mode The device is capable of very fast Burst mode read operations. The configuration register sets the read config uration, burst order, frequency confi gurati on, and burst length. Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are ignored. The device operates like a conventional Flash device. Data is available tACC/tCE nanoseconds after address becomes stable, CE# become asserted. The device enters the burst mode by enabling synchronous burst re ads i n the config urati on reg ister. The device exits burst mode by disabl ing synchronous burst reads i n the configuration register. (See Command Definitions). 34 Am29BDD160G June 7, 2006 The Reset command does not disable the SecSi sector if it is enabled. This function is only accomplished by issuing the SecSi Sector Exit command. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, man ufacturer and devi ce codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to VID. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The Am29BDD160 contains an Autoselect Command operati on to supplement tradi tional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The bank address (BA) is latched during the autoselect command sequence write operation to distinguis h whi ch ba nk the Au tos elect comma nd references. Re ad ing the other b ank a fter the A u tos elect command is written results in reading array data from the other bank and the specified address. Following the comm a nd wr i te, a r e a d cycle from a ddre ss (BA)XX00h retr i eve s t he m a n u f a ct u rer code of (BA)XX01h . T hree s e qu ent ia l re a d cycle s a t a ddresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID (see Tables 19 and 20). All manufacturer and device codes exhibit odd parity with the MSB of the lower byte (DQ7) defined as the parity bit. (The Autoselect Command requires the user to execu te the Rea d/Re set comm and to return the devi ce back to reading the array contents.) Except for Program Suspend, any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across s ector b o u nd a r i e s. A b i t cannot be pro g rammed from a “0” back to a “1”. Attempti ng to do s o may h alt the opera ti on and s et DQ5 to “1,” or c aus e the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Accelerated Program Command The Accelerated Chip Program mode is designed to i mprove the Word or Do ub le Word progr a mm i ng speed. Improving the programming speed is accomplished by using the ACC pin to supply both the wordline voltage and the bitline current instead of using the VPP pump and drain pump, which is limited to 2.5 mA. Because the external ACC pin is capable of supplying significantly large amounts of current compared to the drain pump, all 32 bits are available for programming with a single programming pulse. This is an enormous improvement over the standard 5-bit programming. If the us er is ab le to s upply an extern al power su pply and connect it to the ACC pin, significant time savings are realized. In order to enter the Accelerated Program mode, the ACC pin must first be taken to VHH (12 V ± 0.5 V) and followed by the one-cycle command with the program address and data to follow. The Accelerated Chip Program command is only executed when the device is in Unlock Byp ass mode a nd d u ri ng norm a l rea d/re s et operating mode. In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1. The Accelerated Program command is not permitted if the SecSi sector is enabled. Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further control s or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Tables 18 and 20 shows the address and d a t a r e qui rement s f or the progr a m comm a nd s equence. During the Embedded Program algorithm, the system can determine the status of the program operation by usi ng DQ7, DQ6, or RY/BY#. (S ee Write Operation Status for information on these status bits.) When the Embedded Program algorithm is complete, the device returns to reading array data and addresses are no longer l a tched. Note tha t a n a ddress c ha nge i s required to begin read valid array data. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the progra m address and data. Additional data is programmed in June 7, 2006 Am29BDD160G 35 the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 18 and 20 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass res et command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Address es are don’t care for both cycles. The device then returns to reading array data. Figure 5 illustrates the algorithm for the program operation. See the Erase/Program Operations table in AC Characteristics for parameters, and to Figure 22 for timing diagrams. and CFI commands. This feature permits slow PROM progr a mmer s t o s i gn i f i c a ntly i mprove progr a mming/erase throughput since the command sequence often requires microseconds to execute a single write opera ti on. Therefore, once the Unlock Bypass c ommand is issued, only the two-cycle program and erase bypass commands are required. The Unlock Bypass Command is ignored if the SecSi sector is enabled. To retu rn back to normal operation, the Unlock Bypass Reset Command must be issued. The following four sections de scribe the comm ands that may be executed within the unlock bypass mode. Unlock Bypass Program Command The Unlock Bypass Program command is a two-cycle comm a nd th at con sis ts o f the a ct ua l progr am command (A0h) and the program address/data combinat i on . Th is c omm a nd doe s n ot re qui re the two-cycle “unlock” sequence since the Unlock Bypass command was previously issued. As with the standard program comm a nd, m u lt i ple Unlock Byp ass P rogr a m commands can be issued once the Unlock Bypass command is issued. To return back to standard read operations, the Unlock Bypass Reset command must be issued. The Unlock Bypass Program Command is ignored if the SecSi sector is enabled. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Unlock Bypass Chip Erase Command The Unlock Bypass Chip Erase command is a 2-cycle command that consists of the erase setup command (80h) and the actual chip erase command (10h). This command does not require the two-cycle “unlock” sequence since the Unlock Bypass command was previo us ly i ssu ed . U nl i ke the s t a nd ard er as e comm a nd, there is no Unlock Bypass Eras e S uspend or Eras e Resume commands. To return back to standard read operations, the Unlock Bypass Reset command must be issued. The Unlock Bypass Program Command is ignored if the SecSi sector is enabled. Unlock Bypass CFI Command The Unlock Byp ass C FI comm a nd i s a v ai l ab le for PROM programmers and target systems to read the CFI codes while in Unlock Bypass mode. See Common Flas h Memory Interf a ce (CFI) for s pec i f i c CFI codes. To return back to standard read operations, the Unlock Bypass Reset command must be issued. Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Tables 18 and 20 for program command sequence. Figure 4. Program Operation Unlock Bypass Entry Command The Unlock Bypass command, once issued, is used to bypass the “unlock” sequence for program, chip erase, The Unlock Bypass Program Command is ignored if the SecSi sector is enabled. 36 Am29BDD160G June 7, 2006 Unlock Bypass Reset Command The Unlock Bypass Reset command places the device i n s t a nd a rd re a d/re s et oper a t i ng mode . O nce executed, normal read operations and user command sequences are available for execution. The Unlock Bypass Program Command is ignored if the SecSi sector is enabled. tor address (any address location wi thin the desired sector) is latched on the falling edge of WE# or CE# (whi chever occurs l ast) while the comm and (30h) is latched on the rising edge of WE# or CE# (whichever occurs first). Specifying multiple sectors for erase is accomplished by wri ti ng the si x bus cycle opera tion, as d es cribed above, and then following it by additional writes of only the l as t cycle of the S ector Er as e comm a nd to a ddresses or other sectors to be erased. The ti me between S ector Er as e comm a nd wr i te s m us t b e le ss than 80 µs, otherwise the command is rejected. It is recommended that processor i nterrupts be disabled during this time to guarantee this critical timing conditi on . The interrupts c a n be re-en ab led after the l as t Sector Erase command is written. A time-out of 80 µs from the rising edge of the last WE# (or CE#) will initiate the execution of the Sector Erase command(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset. Once the 80 µs window has timed out and erasure has begun, only the Erase Suspend command is recognized (see Sector Erase and Progra m Suspend Command a nd Sector Erase and Program Resume Command sections). If that occurs, the sector erase command sequ ence s ho u ld b e re i n i t ia ted once th a t b a nk h as returned to reading array data, to ensure data integrity. Loading the sector erase registers may be done in any sequence and with any number of sectors. Sector erase does not require the user to program the device prior to erase. The device automatically preprogr a m s a ll memory loc a t i on s , w i th i n s ector s t o b e erased, prior to electrical erase. When erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. The system is not required to provide any controls or timings during s ector er as e oper a t i on s. T he Er as e S us pend a nd Erase Resume commands may be written as often as required during a sector erase operation. Automatic sector erase operations begin on the rising edge of the WE# or CE# pulse of the last sector erase command issued, and once the 80 µs time-out window has expired. The status of the sector erase operation is determined three ways: ■ Data# polling of the DQ7 pin ■ Checking the status of the toggle bit DQ6 ■ Checking the status of the RY/BY# pin F u rther s t a t us o f dev i ce a ct i v i ty d u r i ng the s ector erase opera tion is determi ned using toggle bi t DQ2 (refer to DQ2: Toggle Bit II). When the Embedded Erase algorithm is complete, the dev ice returns to reading array data, and addresses are no longer latched. Note that an address change is required to begin read valid array data. Chip Erase Command The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single comma nd . C h i p er as e i s a s i x- bus c ycle oper a t i on . There are two “unlock” write cycles, followed by writing the erase “set up” command. Two more “unlock” write cycles are followed by the chip erase command. Chip erase does not erase protected sectors. The ch i p er as e oper a t i on i n i t ia te s t he Em b edded Erase algorithm, which automatically preprograms and verifies the entire memory to an all zero pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Note that a hardware reset immediately terminates the programming operation. The command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse (whichever occurs first) in the command sequence. The status of the erase operation is determined three ways: ■ Data# polling of the DQ7 pin (see DQ7: Data# Polling) ■ Checking the status of the toggle bit DQ6 (see DQ6: Toggle Bit I) ■ Checking the status of the RY/BY# pin (see RY/BY#: Ready/Busy#) Once erasu re h as b eg u n, only the Eras e S us pend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the dev ice returns to reading array data, and addresses are no longer latched. Note that an address change is required to begin read valid array data. Figu re 5 illustrates the Emb edded Erase Algorithm . See the Erase/Program Operations tables in AC Characteristics for parameters, and to Figure 22 for timing diagrams. Sector Erase Command The Sector Erase command is used to erase individual sectors or the entire flash memory contents. Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the erase “set u p” comm a nd . Two more “ u nlock” wri te cycle s a re then followed by the erase command (30h). The sec- June 7, 2006 Am29BDD160G 37 Figure 5 illustrates the Embedded™ Erase Algorithm, using a typical command sequence and bus operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and to Figure 22 for timing diagrams. The counter is incremented by one every time an erase pulse is initiated, regardless of whether or not that erase pulse is successful. An erase pulse is terminated immediately when the suspend command is executed. A new erase pulse is initiated when the resume command is executed (and the counter is incremented). ■ Given that 300 successful erase pulses are required, a successful sector erase operation shall have a maximum of 5680 erase suspends. The Sector Erase and Program Suspend command is i gnored i f wr i tten d u r i ng the exec u t i on of the Ch i p Erase operation or Embedded Program Algorithm (but will reset the chip if written improperly during the command sequences). Writing the Sector Erase and Progr a m comm a nd d u r i ng the S ector Er as e t i me-o u t results in immediate termination of the time-out period and suspension of the erase operation. Once in Erase Suspend, the device is available for reading (note that in the Erase Suspend mode, the Reset command is not required for read operations and is ignored) or progr a m oper a t i on s i n s ector s n ot b e i ng er as ed . A ny other comm a nd wr i tten d u r i ng the Er as e S us pend mode is ignored, except for the Sector Erase and Program Resume command. Writing the Erase and Progra m Re sume comm a nd re su me s t he s ector er as e operation. The bank address of the erase suspended bank is required when writing this command If the Sector Erase and Program Suspend command is written during a programming operation, the device sus pend s progra mm ing opera t ion s a nd a llow s o nly read operations in sectors not selected for programming. Further nesting of either erase or programming operations is not permitted. Table 18 summarizes permissible operations during Erase and Program S uspend . ( A b us y s ector i s o ne th a t i s s elected for programming or erasure.): Table 18. Allowed Operations During Erase/Program Suspend Sector Busy Sector Non-busy sectors Program Suspend Program Resume Read Only Erase Suspend Erase Resume Read or Program START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Tables 18 and 20 for erase command sequence. 2. See DQ3: Sector Erase Timer for more information. Figure 5. Erase Operation Sector Erase and Program Suspend Command The Sector Erase and Program Suspend command allows the user to interrupt a Sector Erase or Program operation and perform data read or programs in a sector that is not being erased or to the sector where a programming operation was initiated. This command is appl ic able only du ri ng the S ector Eras e a nd Programming operation, which includes the time-out period for Sector Erase. Sector Erase and Program Suspend Operation Mechanics ■ A successful erase pulse has a duration or 1.2 ms ± 20%, depending on the number of previous erase cycles (among other factors). ■ A successful sector erase operation requires 300 successful erase pulses. ■ An internal counter monitors the number of erase pulses initiated and has a maximum value of 5980. When the Sector Erase and Program Suspend command is written during a Sector Erase operation, the ch i p w i ll ta ke b etween 0 . 1 µs a nd 20 µ s t o a ctua lly sus pend the oper a t i on a nd go i nto the er as e s us pended read mode (pseudo-read mode), at which time the user can read or program from a sector that is not eras e s us pended . Re ad ing da ta i n th is m ode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. Poll i ng DQ6 on two i mmed iately consec u ti ve re a ds from a g i ven a ddre ss p rov i de s t he s y s tem w i th the 38 Am29BDD160G June 7, 2006 ability to determine if the device is in Erase or Program Suspend. Before the device enters Erase or Program Suspend, the DQ6 pin toggles between two immediately consecutive reads from the same address. After the dev i ce h as e ntered Er as e s us pend, DQ6 s top s toggling between two immediately consecutive reads to the same address. During the Sector Erase operation and also in Erase suspend mode, two immediately consecutive readings from the erase-suspended sector causes DQ2 to toggle. DQ2 does not toggle if reading from a non-busy (non-erasing) sector (stored data is read). No bits are toggled during program suspend mode . Softwa re mus t keep track of the fact that the device is in a suspended mode. After entering the erase-suspend-read mode, the system may read or program within any non-suspended sector: ■ A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase suspend command is issued; read operations thereafter return array data. Read operations from the other bank return array data with no latency. ■ A program operation while in the erase suspend mode is the same as programming in the regular program mode, except that the data must be programmed to a sector that is not erase suspended. Write operation status is obtained in the same manner as a normal program operation. tents. The contents of the Configuration Register are place on DQ15–DQ0. If WORD# is at VIH (32-bit DQ B us ), the content s o f DQ 3 1–DQ16 are XXXXh a nd s ho u ld b e i gnored . T he u s er s ho u ld exec u te the Re a d/Re s et comm a nd to pl a ce the dev i ce b a ck i n standard user operation after executing the Configuration Register Read command. The Conf ig ura ti on Regis ter Rea d Comma nd is fu lly operational if the SecSi sector is enabled. Configuration Register Write Command The Configuration Register Write command is used to modify the contents of the Configuration Register. Execution of this command is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration Register Write command is preceded by the standard two-cycle “unlock” sequence, followed by the Configuration Regis ter Wri te comm a nd (D0h), a nd f i n a lly followed b y writing the contents of the Configuration Register to any address. The contents of the Configuration Register a re pl a ce on DQ15–DQ0 . I f WORD# i s a t V IH ( 3 2- bi t DQ B us ), the content s o f DQ 3 1–DQ16 a re XXXXh a nd a re i gnored . Wr i t i ng the Conf i g u r a t i on Reg is ter wh i le a n Em b edded Algori thm™ or Eras e Suspend modes are executing results in the contents of the Configuration Register not being updated. The Conf ig ura ti on Regis ter Rea d Comma nd is fu lly operational if the SecSi sector is enabled. Sector Erase and Program Resume Command The S ector Eras e a nd Progr a m Re su me comm a nd (30h) resumes a Sector Erase or Program operation th a t h as been s us pended . A ny fu rther wri te s o f the S ector Er as e a nd Progr a m Re su me comm a nd i gnored. However, another Sector Erase and Program Suspend command can be written after the device has re su med s ector eras e oper a t i on s. Note th a t u nt i l a suspended program or erase operation has resumed, the contents of that sector are unknown. The Sector Erase and Program Resume Command is ignored if the SecSi sector is enabled. Common Flash Interface (CFI) Command The Common Fl as h Interf a ce (CFI) comm a nd provides device size, geometry, and capability information directly to the users system. Flash devices that support CFI, have a “Query Command” that returns inform a t i on a b o u t the dev i ce to the s y s tem . T he Q u ery structure contents are read at the specific address locations following a single system write cycle where: ■ A 98h query command code is written to 55h address location within the device’s address space ■ The device is initially in any valid read state, such as “Read Array” or “Read ID Data” Other dev i ce s t a t is t i c s m a y ex is t w i th i n a l ong s equence of commands or data input; such sequences must first be completed or terminated before writing of the 9 8 H Q u ery comm a nd, otherw is e i nv a l i d Qu ery data structure output may result. No t e t h a t f or d a t a b u s b i t s g r e a te r th a n DQ 7 (DQ31–DQ8), the valid Query access code has all zeroes (“0”s) in the upper DQ bus loc ations. Thus, the 16-bit Query command code is 0098h and the 32-bit Query command code is 00000098h. To terminate the CFI operation, it is necessary to execute the Read/Reset command. Configuration Register Read Command The Configuration Register Read command is used to verify the contents of the Configuration Register. Execution of this command is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration Register Read command is preceded by the standard two-cycle “unlock” sequence, followed by the Configuration Regis ter Re a d comm and (C6h), and f i n a lly followed b y performing a read operation to the bank address specified when the C6h command was written. Reading the other bank results in reading the flas h memory con- June 7, 2006 Am29BDD160G 39 The CFI command is not permitted if the SecSi sector is e nab led a nd S im u lt aneous O perat ion i s disabled once the command is entered. S ee Common Fl as h Memory Interface (CFI) for the specific CFI command codes. 40 Am29BDD160G June 7, 2006 SecSi Sector Entry Command The SecSi Sector Entry command enables the SecSi (OTP) sector to overlay the 8 KB outermost sector in the s m a ll (25 % ) b a nk . T he S ec Si s ector overl a y s 00000h–0003 Fh for the top b ootblock confi gu rati on and 7FFC0h–7FFFFh for the bottom bootblock confiur a t i on . A ddre ss r a nge 00040h–007FFh for the top b oot b lock a nd 7F 8 00h–7FFBFh ret u rn i nv a l i d d a t a when addressed with the SecSi sector enabled. The followi ng comm ands are permi tted after i ssuing the SecSi Sector Entry command: 1. Autoselect 2. Password Program (x16 and x32) 3. Password Verify 4. Password Unlock (x16 and x32) 5. Read/Reset 6. Program 7. Chip and Sector Erase 8. SecSi Sector Protection Bit Program 9. PPB Program 10. All PPB Erase 11. PPB Lock Bit Set 12. DYB Write 13. DYB/PPB/PPB Lock Bit Verify 14.Security Reset 15. Configuration Register Write 16. Configuration Register Read The followi ng comm and s a re un a v ai l able when the S ecSi sector i s en ab led. I ssuing the followi ng commands while the SecSi sector is enabled results in the command being ignored. 1. Unlock Bypass 2. CFI 3. Accelerated Program 4. Program and Sector Erase Suspend 5. Program and Sector Erase Resume The SecSi Sector Entry command is allowed when the device is in either program or erase suspend modes. If the SecSi sector is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erasure on the SecSi sector if the overlayed sector was undergoing programming or erasure. The host system must ensure that the device resume any s uspended program or erase operation after exiting the SecSi sector. Executing any of the PPB program/erase commands, or P ass word Unlock comm a nd re su lt s i n the s m a ll bank (25% bank) returning the status of these opera- t i on s w h i le they a re i n progre ss , th us m a k i ng the SecSi sector unavailable for reading. If the SecSi sector is enabled while the DYB command is issued, the DYB for the overlayed sector is NOT updated. Reading the DYB status using the PPB Lock Bit/DYBDYB verify command when the SecSi sector is enabled returns invalid data. Password Program Command The Password Program Command permits programmi ng the p assword tha t i s used a s part of the h ardw a re protect i on s cheme . T he a ct ua l p ass word i s 64-bits long. Depending upon the state of the WORD# pi n, multi ple P ass word Progra m Commands a re required. For a x16 bit data bus, 4 Password Program commands are required to program the password. For a x32 bit data bus, 2 Password Program commands are re qui red. The us er m us t enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle u nlock cycle, the p ass word progr a m command, and all the password data. There is no special addressing order required for programming the password . A l s o, when the p ass word i s u ndergo i ng programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the dev i ce to norm a l oper a t i on . O nce the P ass word i s written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the SecSi sector is enabled. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F’s onto the DQ data bus. The P ass word Ver i fy comm a nd i s p erm i tted i f the SecSi sector is enabled. Also, the device will not opera te i n S i m ult a neo us O pera ti on when the P ass word Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are v al id during the Pass word June 7, 2006 Am29BDD160G 41 Verify. Writing the Read/Reset command returns the device back to normal operation. The SecSi Sector Protection Bit Program command is permitted if the SecSi sector is enabled. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. O nce progra mmed, the P ass word Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as progr a m w i tho u t m a rg i n, the P ass word Protect i on Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Password Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled. PPB Lock Bit Set Command The PPB Lock B i t S et comm a nd i s u s ed to s et the PPB Lock b i t i f i t i s c le a red e i ther a t re s et or i f the P ass word Unlock comm a nd w as s u cce ss f u lly exec u ted . T here i s n o PPB Lock B i t Cle a r comm a nd . Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the P ass word Unlock comm a nd i s e xec u ted . U pon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locki ng B it i s set, the PPB Lock Bi t status is reflected as s et, even after a power-on re s et cycle. E x i ti ng the PPB Lock B i t S et command is accomplished by writing the Read/Reset command. The PPB Lock B i t S et comm a nd i s p erm i tted i f the SecSi sector is enabled. DYB Write Command The DYB Write command is used to set or clear a DYB for a g i ven s ector. T he h i gh order a ddre ss b i t s (A18–A11) are i ssu ed at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock B i t . T he DYB s a re cle a red a t power- u p or h a rdw a re re s et . Ex i t i ng the DYB Wr i te command is accomplished by writing the Read/Reset command. The DYB Wr i te comm a nd i s p erm i tted i f the S ec Si sector is enabled. Persistent Sector Protection Mode Locking Bit Program Command The Persis tent S ector Protect i on Mode Lock i ng B i t Progra m Comma nd program s the Persistent S ector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent S ector Protecti on Mode Lock i ng B i t Progra m Command should be reissued to improve program margin. By d isab l i ng the progr a m c i rcui try of the P ass word Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Lock i ng B i t Progra m comm a nd i s a ccompl is hed b y writing the Read/Reset command. The Persis tent S ector Protect i on Mode Lock i ng B i t Program command is permitted if the SecSi sector is enabled. Password Unlock Command The Password Unlock command is used to clear the PPB Lock B it so th at the PPBs c an be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlock ing f uncti on to occu r. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. The P assword Unlock f u nct i on i s a ccompl is hed b y wri t i ng Pass word Unlock comm a nd and d a ta to the dev i ce to perform the clea r i ng of the PPB Lock Bi t . The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data bus and 4 times for a x16 data bus. A0 is used to determine whether the 32 bit data quantity is used to match the upper 32 bits or lower 32 bits. A0 and A-1 is us ed for m atch i ng when the x16 b i t d a ta b us i s s e- SecSi Sector Protection Bit Program Command The Sec Si Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the S ec Si S ector Protect i on B i t i s v er i f i ed a s p rogrammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margi n. E x iting the V CC-level SecSi S ector Protection Bit Program Command is accomplished by writing the Read/Reset command. 42 Am29BDD160G June 7, 2006 l ected (WORD# = 0). Wri t i ng the P ass word Unlock command is address order specific. In other words, for the x32 data bus configuration, the lower 32 bits of the password are written first and then the upper 32 bits of the password are written. For the x16 data bus configuration, the lower address A0:A-1= 00, the next Password Unlock comm a nd i s t o A0 : A -1 = 01, then to A0:A-1= 10, and finally to A0:A-1= 11. Writing out of sequence results in the Password Unlock not returning a m a tch w i th the p ass word a nd the PPB Lock B i t remains set. Once the Password Unlock command is entered, the RDY/BSY# pin goes LOW indicating that the device is busy. Also, reading the small bank (25% bank) results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the large bank (75% bank) returns actual array data. Approximately 1uSec is required for each portion of the unlock. Once the f i r s t port i on of the p ass word u nlock complete s (RDY/B S Y# i s n ot dr i ven a nd DQ6 doe s not toggle when read), the Password Unlock command is issued ag ai n, only th is t i me w i th the next p art of the p ass word . If WORD# = 1, the s econd P ass word Unlock command is the final command before the PPB Lock Bit is cleared (assuming a valid password). If WORD# = 0, this is the fourth Password Unlock command. In x16 mode, four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY# signal goes LOW and read ing the devi ce results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands (2 for x3 2 b us and 4 for x16 bus), the order, a nd when to re a d the PPB Lock b i t to conf i rm s uccessful password unlock The P ass word Unlock comm a nd i s p erm i tted i f the SecSi sector is enabled. All PPB Erase Command The All PPB Er as e comm a nd i s u s ed to er as e a ll PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specifi c sector address is re qui red. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute a nd the comm a nd w i ll t i me-o u t w i tho u t er asi ng the PPBs. The hos t s y stem mus t determ ine whether all PPB has been fully erased by noting the status of DQ0 in the s ixth cycle of the All PPB Erase comm and . If DQ0 = 1, the entire six-cycle All PPB Erase command sequence must be reissued until DQ0 = 1. I t i s the re s pon sibi l i ty of the u s er to preprogr a m all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the SecSi sector is enabled. DYB Write The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per s ector. I f the PPB i s s et, the s ector is protected rega rdle ss of the va lu e of the DYB . If the PPB i s cle ared, s etti ng the DYB to a 1 p rotects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. The DYB Wr i te comm a nd i s p erm i tted i f the S ec Si sector is enabled. PPB Program Command The PPB Program command i s u sed to progra m, or s et, a g i ven PPB . E a ch PPB i s i nd i v i d ua lly progr a mmed ( bu t i s b u lk er as ed w i th the other PPB s ) . The specific sector address (A18–A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. The host system must determine whether a PPB has been fully programmed by noting the status of DQ0 in the sixth cycle of the PPB Program command. If DQ0 = 0, the entire six-cycle PPB Program command sequence must be reissued until DQ0 = 1. PPB Lock Bit Set The PPB Lock Bit set command is used for setting the DYB, wh i ch i s a v ol a t i le bi t th at i s c le a red at re s et . There i s o ne DYB per s ector. I f the PPB i s s et, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. The PPB Lock command is permitted if the SecSi sector is enabled. DYB Status The programming of the DYB for a given sector can be verified by writing a DYB status verify command to the device. June 7, 2006 Am29BDD160G 43 PPB Status The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector c a n b e ver i fi ed by wri ti ng a P PB Lock B it s t at us verify command to the device. status is read on DQ0. Figure 4 shows a typical flow for progr a mm i ng the non-vol a t i le b i t a nd F i g u re 5 shows a typical flow for erasing the non-volatile bits. The SecSi Sector Protection, Password Locking, Persistent S ector Protection Mode Locki ng bits are not era sable a fter they are progra mmed . However, the PPBs are both erasable and programmable (depending upon device security). Unlike Single High Voltage Sector Protect/Unprotect, the A6 pin no longer functions as the program/erase s elector nor the progr a m/er as e m a rg i n en ab le . I ns te a d, th is f u nct i on i s a ccompl is hed b y i ssui ng the specific command for either program (68h) or erase (60h). In asynchronous mode, the DQ6 toggle bit indicates whether the program or erase sequence is active. (In synchronous mode, ADV# indicates the status.) If the DQ6 toggle b i t toggle s wi th e i ther OE# or CE#, the non-vol a t i le b i t progr a m or er as e oper a t i on i s i n progress. When DQ6 stops toggling, the value of the non-volatile bit is available on DQ0. Non-volatile Protection Bit Program And Erase Flow The device uses a standard command sequence for programming or erasing the SecSi Sector Protection, Password Locking, Persistent Sector Protection Mode Locking, or Persistent Protection Bits. Unlike devices th a t h a ve the S i ngle H i gh Volt a ge S ector Unprotect/Protect feature, the Am29BDD160 has the standard two-cycle unlock followed by 60h, which places the device into non-volatile bit program or erase mode. Once the mode is entered, the specific non-volatile bit 44 Am29BDD160G June 7, 2006 Table 19. Cycles Command (Notes) Read (5) Reset (6) Autoselect (7) Program Chip Erase Sector Erase Program/Erase Suspend (12) Program/Erase Resume (13) CFI Query (14, 15) Accelerated Program (16) Configuration Register Verify (15) Configuration Register Write (17) Unlock Bypass Entry (18) Unlock Bypass Program (18) Unlock Bypass Erase (18) Unlock Bypass CFI (14, 18) Unlock Bypass Reset (18) Manufacturer ID Device ID (11) Memory Array Command Definitions (x32 Mode) Bus Cycles (Notes 1–4) First RA XXX 555 555 555 555 555 BA BA 55 XX 555 555 555 XX XX XX XX RD F0 AA AA AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 XX 00 PA 2AA 2AA 2AA PA XX PD 55 55 55 PD 10 (BA)555 555 555 C6 D0 20 (BA)XX XX RD WD 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 555 555 555 555 555 90 90 A0 80 80 (BA)X00 (BA)X01 PA 555 555 01 7E PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X0E 08 (BA)X0F 00/01 Second Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr Data Addr Data 1 1 4 6 4 6 6 1 1 1 2 3 4 3 2 2 1 2 Legend: BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Determined by A18 and A17, see Tables 11 and 12 for more detail. PA = Program Address (A18:A0). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data (DQ31:DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. 4. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or device ID information. See the Autoselect Command section for more information. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock Bypass Reset command must be executed to return to normal operation. RA = Read Address (A18:A0). RD = Read Data (DQ31:DQ0) from location RA. SA = Sector Address (A18:A11) for verifying (in autoselect mode), erasing, or applying security commands. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care 9. This command is ignored during any embedded program, erase or suspended operation. 10. Valid read operations include asynchronous and burst read mode operations. 11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates top boot block, 01h indicates bottom boot block. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Program/Erase Suspend mode. The Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. Asynchronous read operations. 16. ACC must be at VID during the entire operation of this command. 17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. 5. 6. 7. 8. June 7, 2006 Am29BDD160G 45 Table 20. Cycles Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (5, 6) SecSi Protection Bit Status Password Program (5, 7, 8) Password Verify Password Unlock (7, 8) PPB Program (5, 6) All PPB Erase (5, 9, 10) PPB Status (11, 12) PPB Lock Bit Set PPB Lock Bit Status DYB Write (7) DYB Erase (7) DYB Status (12) PPMLB Program (5,6) PPMLB Status (5) SPMLB Program (5, 6) SPMLB Status (5) Sector Protection Command Definitions (x32 Mode) Bus Cycles (Notes 1-4) First XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 555 555 555 (BA) 555 555 555 (BA) 555 555 555 555 555 88 90 60 60 38 C8 28 60 60 90 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 SL RD(0) PL 48 PL RD(0) XX OW OW 00 68 RD(0) OW 48 OW RD(0) Second Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr Data Addr Data 1 3 4 6 6 4 4 5 6 6 4 3 4 4 4 4 6 6 6 6 PWA[0-1] PWD[0-1] PWA[0-1] PWD[0-1] PWA[0-1] PWD[0-1] (SA)WP WP (SA)X02 68 60 00/01 (SA)WP (SA)WP 48 40 (SA)WP RD(0) (SA)WP RD(0) DYB = Dynamic Protection Bit OW = Address (A5–A0) is (011X10). PPB = Persistent Protection Bit PWA = Password Address. A0 selects between the low and high 32-bit portions of the 64-bit Password PWD = Password Data. Must be written over two cycles. PL = Password Protection Mode Lock Address (A5–A0) is (001X10) RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if unprotected, DQ0 = 0. 1. See Table 1 for description of bus operations. All values are in hexadecimal. RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SA = Sector Address where security command applies. Address bits A18:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10) WP = PPB Address (A5–A0) is (111X10) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 7. 8. 9. Data is latched on the rising edge of WE#. The entire four bus-cycle sequence must be entered for each portion of the password. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 2. 3. 4. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. The reset command returns the device to reading the array. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 5. 6. 10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. 46 Am29BDD160G June 7, 2006 Table 21. Cycles Command (Notes) Read (5) Reset (6) Autoselect (7) Program Chip Erase Sector Erase Program/Erase Suspend (12) Program/Erase Resume (13) CFI Query (14, 15) Accelerated Program (16) Configuration Register Verify (15) Configuration Register Write (17) Unlock Bypass Entry (18) Unlock Bypass Program (18) Unlock Bypass Erase (18) Unlock Bypass CFI (14, 18) Unlock Bypass Reset (18) Manufacturer ID Device ID (11) Memory Array Command Definitions (x16 Mode) Bus Cycles (Notes 1–4) First RA XXX AAA AAA AAA AAA AAA BA BA AA XX AAA AAA AAA XX XX XX XX RD F0 AA AA AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 XX 00 PA 555 555 555 PA XX PD 55 55 55 PD 10 (BA)555 AAA AAA C6 D0 20 (BA)XX XX RD WD 555 555 555 555 555 55 55 55 55 55 AAA AAA AAA AAA AAA 90 90 A0 80 80 (BA)X00 (BA)X02 PA AAA AAA 01 7E PD AA AA 555 555 55 55 555 SA 10 30 (BA)X1C 08 (BA)X1E 00/01 Second Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr Data Addr Data 1 1 4 6 4 6 6 1 1 1 2 3 4 3 2 2 1 2 Legend: BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Determined by A18 and A17, see Tables 11 and 12 for more detail. PA = Program Address (A18:A-1). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. 3. 4. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are AAA or 555h as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or device ID information. See the Autoselect Command section for more information. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock Bypass Reset command must be executed to return to normal operation. RA = Read Address (A18:A-1). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A18:A11) for verifying (in autoselect mode), erasing, or applying security commands. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care 9. This command is ignored during any embedded program, erase or suspended operation. 10. Valid read operations include asynchronous and burst read mode operations. 11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates top boot block, 01h indicates bottom boot block. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Program/Erase Suspend mode. The Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. Asynchronous read operations. 16. ACC must be at VID during the entire operation of this command. 17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. 5. 6. 7. 8. June 7, 2006 Am29BDD160G 47 Table 22. Cycles Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (5, 6) SecSi Protection Bit Status Password Program (5, 7, 8) Password Verify Password Unlock (7, 8) PPB Program (5, 6) All PPB Erase (5, 9, 10) PPB Status (11, 12) PPB Lock Bit Set PPB Lock Bit Status DYB Write (7) DYB Erase (7) DYB Status (12) PPMLB Program (5, 6) PPMLB Status (5) SPMLB Program (5, 6) SPMLB Status (5) Sector Protection Command Definitions (x16 Mode) Bus Cycles (Notes 1-4) First Second Third Addr AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA (BA) AAA AAA AAA (BA) AAA AAA AAA AAA AAA Data 88 90 60 60 38 C8 28 60 60 90 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 SL RD(0) PL 48 PL RD(0) XX OW OW 00 68 RD(0) OW 48 OW RD(0) Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr Data Addr Data XXX AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 1 3 4 6 6 5 4 5 6 6 4 3 4 4 4 4 6 6 6 6 PWA[0–3] PWD[0–3] PWA[0–3] PWD[0–3] PWA[0–3] PWD[0–3] (SA)WP WP (SA)X04 68 60 00/01 (SA)WP (SA)WP 48 40 (SA)WP RD(0) (SA)WP RD(0) Legend: DYB = Dynamic Protection Bit OW = Address (A5–A0) is (011X10). PD3:0 = Four 32-bit quantities representing the password. PPB = Persistent Protection Bit PWA = Password Address. A0:A-1 selects between the low and high 16-bit portions of the 64-bit Password PWD = Password Data.Must be written over four cycles. PL = Password Protection Mode Lock Address (A5-A0) is (001X10) RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0. 1. See Table 1 for description of bus operations. RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SA = Sector Address where security command applies. Address bits A18:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10) WP = PPB Address (A5–A0) is (111X10) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 8. 2. 3. 4. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are AAA or 555h as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. The reset command returns the device to reading the array. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. Data is latched on the rising edge of WE#. 9. The entire four bus-cycle sequence must be entered for each portion of the password. PWA[0–3] represent the four addresses over which the password is stored. PWD[0–3] represent the four word data that comprise the password. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 5. 6. 10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. 7. 48 Am29BDD160G June 7, 2006 WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 23 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. gori thm, Er as e S us pend, Er as e S us pend-Progr a m mode, or sector erase time-out. If the u s er a ttempt s t o wr i te to a p rotected s ector, Data# polling will be activated for about 1 µs: the device will then return to read mode, with the data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit (DQ6) will be activated for about 150 µs; the device will then return to re a d mode, w i tho u t h av i ng eras ed the protected sector. Table 23 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. Figure 27 shows the timing diagram for synchronous status DQ7 data polling. DQ7: Data# Polling The Am29BDD160 features a Data# polling flag as a method to indicate to the host system whether the embedded a lgorithms are i n progress or are complete . During the Embedded Program Algorithm an attempt to read the bank in which programming was initiated will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true last data written to DQ7. Note that DATA# polling returns invalid data for the address being programmed or erased. For ex a mple, the d a t a r e a d for a n a ddre ss p rogrammed as 0000 0000 1000 0000b will return XXXX XXXX 0XXX XXXX b d ur i ng a n Em b edded Progr am operation. Once the Embedded Program Algorithm is complete, the true data is read back on DQ7. Note that a t the i n s t a nt when DQ7 s w i tche s t o tru e d a ta , the other bits may not yet be true. However, they will all be tru e d a t a o n the next re a d from the dev i ce . P le as e note th a t D a t a# poll i ng m a y g i ve m is le a d i ng s t a tus when an attempt is made to write to a protected sector. For chip erase, the Data# polling flag is valid after the r isi ng edge of the s i xth WE# p u l s e i n the s i x wr i te pulse sequence. For sector erase, the Data# polling is valid after the last rising edge of the sector erase WE# pulse. Data# polling must be performed at sector addresses within any of the sectors being erased and not a sector that is a protected sector. Otherwise, the status may not be valid. DQ7 = 0 during an Embedded Erase Algorithm (chip erase or sector erase operation) but will return a “1” after the operation completes because it will have dropped back into read mode. In asynchronous mode, just prior to the completion of the Em b edded Algor i thm oper a t i on s , DQ7 m a y change asynchronously while OE# is asserted low. (In synchronous mode, ADV# exhibits this behavior.) The status information may be invalid during the instance of transition from status information to array (memory) data. An extra validity check is therefore specified in the d a t a p oll i ng a lgori thm . T he v a l i d a rr a y d a t a o n DQ31–DQ0 (DQ15–DQ0 when WORD# = 0) is available for reading on the next successive read attempt. The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Al- RY/BY#: Ready/Busy# The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output is low, the device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any additional program or erase commands with the exception of the Erase suspend command. If the device has entered Erase Suspend mode, the RY/BY# output will be floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE# pulse. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the re set opera tion i s complete. If RESET# is a sserted when a program or erase operation is not executing (RY/BY# pin is “floating”), the reset operation is completed in a time of tREADY (not during Embedded Algor i thm s ) . T he s y s tem c a n re a d d a t a t RH a fter the RESET# pin returns to VIH. Since the RY/BY# pin is an open-drain output, several RY/BY# pi ns can be ti ed together in p arallel with a pull-up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is an open drain. Table 23 shows the outputs for RY/BY#. Figures 15, 19, 21 and 22 shows RY/BY# for read, reset, program, and erase operations, respectively. June 7, 2006 Am29BDD160G 49 START Read DQ7–DQ0 Addr = VA During an Embedded Program or Erase algorithm operation, two immediately consecutive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determ i ne whether a s ector i s a ct i vely er asi ng or i s erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must a lso u se DQ2 to determ ine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. PASS DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Table 23 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 explains the algorithm. Figure 25 in the AC Characteristics section shows the toggle bit timing diagrams. Figure 25 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Figure 27 shows the timing diagram for synchronous toggle bit status. DQ2: Toggle Bit II Figure 6. Data# Polling Algorithm The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system performs two immediately consecutive reads at addresses within those sector s t h a t h a ve b een s elected for er asu re . ( For asynchronous mode, either OE# or CE# can be used to control the re a d cycle s. F or synchronous m ode, ADV# is used.) But DQ2 cannot distinguish whether DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. 50 Am29BDD160G June 7, 2006 the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot dis t ing uis h whi ch s ectors a re selected for erasu re . Thus, both status bits are required for sector and mode information. Refer to Table 23 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 25 shows the toggle bit timing diagram. Figure 25 shows the differences between DQ2 and DQ6 in graphical form. Figure 27 shows the timing diagram for synchronous DQ2 toggle bit status. START Read Byte (DQ0-DQ7) Address = VA Read Byte (DQ0-DQ7) Address = VA (Note 1) DQ6 = Toggle? No Reading Toggle Bits DQ6/DQ2 Refer to Figure 25 for the following discussion. Whenever the system initially begins reading toggle bit stat us , i t m us t perform two i mmed ia tely con s ec u t i ve reads of DQ7–DQ0 to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the s econd re a d, the s y s tem wo u ld comp a re the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two immediately consecutive read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit i s toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggl i ng, the dev i ce d i d not complete the oper a t i on successfully, and the system must write the reset command to return to reading array data. T he rem ai n i ng s cen a r i o i s t h a t the s y s tem i n i t ia lly determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous p a ra gra ph . A ltern a t i vely, i t m a y choos e to perform other system tasks. In this case, the system must start at the begi nning of the a lgorithm when it retu rns to determine the status of the operation (top of Figure 7). Yes No DQ5 = 1? Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA (Notes 1, 2) DQ6 = Toggle? No Yes FAIL PASS Notes: 1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 7. Toggle Bit Algorithm The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously progra mmed to “0 . ” Only an era s e operati on can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset comma nd to retu rn the devi ce to rea di ng array data. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. June 7, 2006 Am29BDD160G 51 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can g ua r a ntee th a t the t i me b etween a dd i t i on a l s ector erase commands will always be less than 50 µs. See also the Sector Erase Command section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the dev ice wi ll accept a dd it iona l s ector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the l as t comm a nd m i ght not h ave b een a ccepted. Table 23 shows the outputs for DQ3. Table 23. Write Operation Status Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 52 Am29BDD160G June 7, 2006 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C VCC , VIO (Note 1) . . . . . . . . . . . . . . . . –0.5 V to +3.0 V ACC, A9, OE#, and RESET# (Note 2) . . . . . . . . . . . –0.5 V to +13.0 V Address, Data, Control Signals (with the exception of CLK (Note 1) . . –0.5 V to +3.6 V All other pins (Note 1) . . . . . . . . . . . . –0.5 V to +5.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –0.7 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +0.7 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A 9 , OE#, and RESET# may overshoot VSS to –0.7 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9 is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. See Figure 9. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. VCC+0.7 V VCC+0.5 V –0.7 V 20 ns 20 ns 20 ns +0.8 V –0.5 V –0.7 V 20 ns 20 ns Figure 8. Maximum Negative Overshoot Waveform 20 ns Figure 9. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . –40°C to +125°C VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . 2.5 V to 2.75 V VIO Supply Voltages VIO for all devices . . . . . . . . . . . . . . . . 1.65 V to 2.75 V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. June 7, 2006 Am29BDD160G 53 DC CHARACTERISTICS CMOS Compatible Parameter ILI ILIWP ILO ICCB Description Input Load Current Input Load Current, WP# Output Leakage Current VCC Active Burst Read Current (Note 1) VCC Active Asynchronous Read Current (Note 1) Test Conditions VIN = VSS to VIO, VIO = VIO max VIN = VSS to VIO, VIO = VIO max VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIL 56 MHz 8 Double-Word 66 MHz 1 MHz 40 20 4 50 50 60 30 90 60 60 20 –0.5 0.7 x VIO –0.2 0.7 x VCC VCC = 2.5 V IOL = 4.0 mA, VCC = VCC min VOL = 0.4 V IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min 8 0.85 x VCC VIO –0.1 1.6 2.0 11.5 0.3 x VIO 3.6 0.3 x VIO 2.75 12.5 0.45 mA mA mA µA mA µA µA mA V V V V V V mA V V V 70 90 mA Min Typ Max ±1.0 –25 ±1.0 Unit µA µA µA ICC1 ICC3 ICC4 ICC5 (Note 5) ICC6 ICC7 (Note 5) ICC8 (Note 5) IACC VIL VIH VILCLK VIHCLK VID VOL IOLRB VHH VOH VLKO CE# = VIL, OE# = VIL VCC Active Program Current (Notes 2, 4) CE# = VIL, OE# = VIH, ACC = VIH VCC Active Erase Current (Notes 2, 4) VCC Standby Current (CMOS) VCC Active Current (Read While Write) VCC Reset Current Automatic Sleep Mode Current VACC Acceleration Current Input Low Voltage Input High Voltage CLK Input Low Voltage CLK Input High Voltage Voltage for Autoselect Output Low Voltage RY/BY#, Output Low Current Accelerated (ACC pin) High Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 3) CE# = VIL, OE# = VIH, ACC = VIH VCC= VCC max, CE# = VCC ± 0.3 V CE# = VIL, OE# = VIL RESET# = VIL VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V ACC = VHH Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. 3. 4. 5. ICC active while Embedded Erase or Embedded Program is in progress. Not 100% tested. Maximum ICC specifications are tested with VCC = VCCmax. Current maximum has been increased significantly from datasheet Revision B+4, Dated April 8, 2003. 54 Am29BDD160G June 7, 2006 DC CHARACTERISTICS (Continued) Zero Power Flash 5 Supply Current in mA 4 3 2 1 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 20 2.7 V 16 Supply Current in mA 12 8 4 0 1 2 3 Frequency in MHz Note: T = -40 °C 4 5 Figure 11. Typical ICC1 vs. Frequency June 7, 2006 Am29BDD160G 55 TEST CONDITIONS Table 24. Test Specifications Test Condition Output Load CL Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes are IN3064 or equivalent 30 5 0.0 V – VIO VIO/2 VIO/2 54D, 64C 65A Unit Device Under Test 1 TTL gate 100 pF ns V V V Figure 12. Test Setup Output timing measurement reference levels KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS KS000010-PAL SWITCHING WAVEFORMS VIO VSS Input VIO/2 V Measurement Level VIO/2 V Output Figure 13. Input Waveforms and Measurement Levels 56 Am29BDD160G June 7, 2006 AC CHARACTERISTICS VCC and VIO Power-up Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Test Setup Min Min Min Speed 50 50 50 Unit µs µs µs Figure 14. VCC and VIO Power-up Diagram tVCS VCC tVIOS VIOP tRSTH RESET# June 7, 2006 Am29BDD160G 57 AC CHARACTERISTICS Asynchronous Read Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std. tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Max Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min Min Min 10 0 10 2 ns ns ns ns CE# = VIL OE# = VIL OE# = VIL Test Setup Max Max Max Max Max Min Speed Options 54D 54 54 58 20 10 2 64C 64 64 69 65A 67 67 71 28 Unit ns ns ns ns ns ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 12 and Table 24 for test specifications 58 Am29BDD160G June 7, 2006 AC CHARACTERISTICS Burst Mode Read Parameter JEDEC Std. tIACC tBACC tADVCS tADVCH tADVP tBDH tDVCH tDIND tINDH tIACC tCLK tCR tCF tCH tCL tCH tACS tACH tOE tDF tEHQZ tOEZ tCEZ tCES Description Asynchronous Access Time ADV# Valid Clock to Output Delay (See Note) Burst Access Time Valid Clock to Output Delay ADV# Setup Time to Rising (Falling) Edge of CLK ADV# Hold Time ADV# Pulse Width Data Hold Time from Next Clock Cycle Valid Data Hold from CLK CLK to Valid IND/WAIT# IND/WAIT# Hold from CLK CLK to Valid Data Out, Initial Burst Access CLK Period Max CLK Rise Time CLK Fall Time CLK High Time CLK Low Time CE# Hold Time Address Setup Time to CLK (See Note) Address Hold Time from ADV# Rising Edge (See Note) Output Enable to Output Valid Output Enable to Output High Z Max Chip Enable to Output High Z CE# Setup Time to Clock Max Min 10 10 4 15 15 5 17 17 6 ns ns Max Max Min Min Min Min Min Max Min 2 2.5 2.5 3 5 1 20 3 3 ns 6 2 7 2 60 3 3 2.5 2.5 3 3 ns ns ns ns ns ns ns ns Max Max Min Min Min Max Min Max Min Max Min 2 9 FBGA 9.5 PQFP 2 54 15 15 4 3 10 FBGA 10 PQFP 3 60 18 3 17 3 68 25 ns 54D 54 9 FBGA 9.5 PQFP 4 2 15 18 Speed Options 64C 64 10 FBGA 10 PQFP 5 65A 67 17 7 Unit ns ns ns ns ns ns ns ns ns ns Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. tIACC may also be calculated using the following formula: tIACC = (clock delays) x (clock period) + tBACC. June 7, 2006 Am29BDD160G 59 AC CHARACTERISTICS tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC OE# 0V Figure 15. Conventional Read Operations Timings tCES CE# CLK tADVCS ADV# tADVCH tACS A0: A18 Aa tCEZ tACH DQ0: DQ31 tIACC OE#* tBDH tBACC Da Da + 1 Da + 2 Da + 3 Da + 31 tOE tOEZ IND# Figure 16. Burst Mode Read (x32 Mode) 60 Am29BDD160G June 7, 2006 AC CHARACTERISTICS CLK ADV# CE# tCS tCH A18-A0 DQ31-DQ0 Stable Address tWC Valid Data tAS tAH tDS tDH WE# OE# tOEH tWPH IND/WAIT# Figure 17. Asynchronous Command Write Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. CE# tCES CLK tADVCS tADVP ADV# ttACS AS tACH tACS tWC tACH Valid Address tADVCH tEHQZ Data Out tWCKS tDH tDF tOE A18-A0, WORD# Valid Address DQ31-DQ0 Data In tWADVH OE# WE# IND/WAIT# tDS tWP 10 ns Figure 18. Synchronous Command Write/Read Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. June 7, 2006 Am29BDD160G 61 AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. tREADY tREADY tRP tRH tRPD tRB tREADY tRH tREADY tDRNE Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time RESET# Active for Bank NOT Executing Embedded Algorithm RESET# High Time before Read RESET# Active for Bank Executing Embedded Algorithm RESET# Delay to Read Mode During Normal Erase RESET# Delay to Read Mode if RESET# is held active for maximum delay (see previous two parameters) Test Setup Max Max Min Min Min Min Max Max Max Max All Speed Options 11 500 500 50 20 0 500 50 11 7 Unit µs ns ns ns µs ns ns ns µs µs tRMX Max 50 ns Note: Not 100% tested. 62 Am29BDD160G June 7, 2006 AC CHARACTERISTICS RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timing to Bank NOT Executing Embedded Algorithm Reset Timing to Bank Executing Embedded Algorithm tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 19. RESET# Timings DQ31-DQ0 Program/Erase Command tDS tDH WE# tWPWS tWP WP# RY/BY# Valid WP# tCH tWPRH Figure 20. WP# Timing June 7, 2006 Am29BDD160G 63 AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std. tWC tA S tAH tD S tDH tOES tGHWL tELWL tWHEH tGHWL tC S tCH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup to WE# Rising Edge Data Hold from WE# Rising Edge Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time CE# Setup to CLK tWLWH tWHWL tWHWH1 tWHWH2 tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY tWPWS tWPRH Notes: 1. Not 100% tested. 2. See the section for more information. WE# Width Write Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# RY/BY# Delay After WE# Rising Edge WP# Setup to WE# Rising Edge with Command WP# Hold after RY/BY# Rising Edge Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Max Min Max All Speed Options 60 0 25 15 2 0 0 0 0 7 25 30 9 0.5 50 0 90 20 2 ns ns µs sec. µs ns ns ns ns Unit ns ns ns ns ns ns ns ns ns 64 Am29BDD160G June 7, 2006 AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC tAS PA Read Status Data (last two cycles) Addresses 555h PA tAH PA CE# OE# tWP tCH tWHWH1 WE# tCS tWPH tDS tDH PD Data A0h Status DOUT tBUSY RY/BY# tRB VCC tVCS Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 21. Program Operation Timings June 7, 2006 Am29BDD160G 65 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh Read Status Data tAS SA 555h for chip erase VA tAH VA CE# OE# tWP WE# tCH tCS tDS tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC tRB Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status). Figure 22. Chip/Sector Erase Operation Timings tWC Addresses Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE# tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tCPH tCP tGHWL tWPH tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Figure 23. Back-to-back Cycle Timings 66 Am29BDD160G June 7, 2006 AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z tWC VA VA tOE tDF Complement Complement True Valid Data High Z DQ0–DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 24. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 25. Toggle Bit Timings (During Embedded Algorithms) June 7, 2006 Am29BDD160G 67 AC CHARACTERISTICS Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations CE# CLK AVD# Addresses VA VA OE# tOE tOE Status Data Status Data Data RDY 1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data. 4. Data polling requires burst access time delay. Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings 68 Am29BDD160G June 7, 2006 VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h/48h*** Sector Protect: 150 μs Sector Unprotect: 15 ms Valid* Data 1 μs CE# 60h 60h/68h** Status WE# OE# * Valid address for sector protect: A6 = 0, A1 = 1, A0 = 0. Valid address for sector unprotect:A6 = 1, A1 = 1, A0 = 0. ** Command for sector protect is 68h. Command for sector unprotect is 60h. *** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h. Figure 28. Sector Protect/Unprotect Timing Diagram June 7, 2006 Am29BDD160G 69 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std. tWC tA S tAH tDS tDH tOES tGHEL tWLEL tEHWH tGHEL tW S tWH tWADVS tWP tWADVH tWCKS tELEH tEHEL tWHWsH1 tWHWH2 tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time WE# Rising Edge Setup to ADV# Falling Edge WE# Width WE# Falling Edge After ADV# Falling Edge WE# Rising Edge Setup to CLK Rising Edge CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ All Speed Options 65 0 45 35 2 0 0 0 0 5 15 0 5 35 30 9 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs sec. Notes: 1. Not 100% tested. 2. See the section for more information. 70 Am29BDD160G June 7, 2006 AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWPH tWP tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. Figure 29. Alternate CE# Controlled Write Operation Timings June 7, 2006 Am29BDD160G 71 ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Double Word Program Time Word (x16) Program Time Accelerated Double Word Program Time Accelerated Chip Program Time Chip Program Time (Note 3) x16 x32 Typ (Note 1) 1.0 23 18 15 8 5 10 12 Max (Note 2) 5 230 250 210 130 50 100 s 120 Unit s s µs µs µs s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2.5 V VCC, 1M cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 145°C, VCC = 2.5 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 19 and 20 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1M cycles. 7. PPBs have a minimum program/erase cycle endurance of 100 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, ACC, and WP#) Input voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. M in –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA PQFP AND FORTIFIED BGA PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years 72 Am29BDD160G June 7, 2006 PHYSICAL DIMENSIONS PQR080–80-Lead Plastic Quad Flat Package June 7, 2006 Am29BDD160G 73 PHYSICAL DIMENSIONS LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm) 74 Am29BDD160G June 7, 2006 REVISION SUMMARY Revision B (September 30, 2002) Initial public release. number of delay cycles callouts. Moved start of Valid Address cycle. Falling CLK Edge Output and Two-CLK Data Hold Deleted figure. Distinctive Characteristics Ch a nged m a x i m u m power con su mpt i on on b u r s t mode read, progra m/erase operati ons , and sta ndby mode. Burst Mode Read table Changed tCES specification from 7, 8, and 9 ns to 4, 5, and 6 ns, respectively. DC Characteristics table Deleted I CC2 s pec i f i c a t i on . C h a nged I CCB O E# te s t condition from VIH to VIL. Added 1 MHz test condition to ICC1 ; ch anged OE# test cond iti on from VIH to V IL . Cha nged ICC3 and I CC4 max i mum v al ues and a dded typ i c a l v a l u e s. C h a nged m a x i m u m v a l u e s f or I CC5 , ICC7, and ICC8. Added Note 4 to table. AC Characteristics Erase and Program Operations table: Replaced TBDs for tAH and tWP with values. Erase and Programming Performance table Replaced TBDs and existing typical and maximum values with new values. See Table 9 , Configuration Register Definitions Modified descriptions for CR3–CR10. See Table 16 , CFI Device Geometry Definition Mod i f i ed de s cr i pt i on of d a t a a t a ddre ss 2 Ch (x 3 2 mode); added data 0003h. DC Characteristics Added maximum ICC6 specification. AC Characteristics Asynchronous Read Operations: Changed tCE specific ati on s for 54D, 65D, 64C, a nd 65A s peed opt ions. Changed tDF specifications for 65A and 90A speed options. Revision B+1 (October 7, 2002) Revision B+4 (April 8, 2003) Distinctive Characteristics Corrected typo in Single power supply operation. Corrected typo in Performance characteristics. Product Selector Guide Updated Max Burst Access Delay for the 54D, 65D, 64C, and 80C speed options. Global Removed reference s t o i nterle a v i ng oper a t i on s throughout datasheet. Table 6. 16-Bit and 32-Bit Linear and Interleaved Burst Data Order Removed 2nd row for “Four Interleaved Data Transfers” and “Eight Interleaved Data Transfers”. Continuous Burst Read Operations, Figure 3. and Figure 4. Wait Function During Continuous Burst Reads at Wordline Boundary, Figure 5. and Figure 6. Odd/Even Starting address Continuous Burst Mode Alignment Removed from datasheet. Table 9. Configuration Register Definitions Added “Reserved” references to table. Sector Protection Added Sector and Sector Group section. Revision B+2 (October 14, 2002) Distinctive Characteristics, DC Characteristics Changed VCC CMOS standby current to 30 mA max. Absolute Maximum Ratings Changed maximum rating for VCC to 3.0 V. Revision B+3 (November 22, 2002) Product Selector Guide Added availability note. Changed minimum initial clock delay and maximum CE# access time on 54D, 65D, 64C, and 65A speeds. Ch anged maxi mum OE# access time on 65A and 90A speeds. Ordering Information Added availability note. See Table 8 , Burst Initial Access Delay Deleted definitions and settings columns and added initial burst access columns. Figure 3, Initial Burst Delay Control Mod i f i ed dr a w i ng : D eleted a rrow s c onnect i ng a ddress/data cycles. Deleted setting callouts. Changed June 7, 2006 Am29BDD160G 75 Sector Erase and Program Suspend Operation Mechanics Added bulleted section. Absolute Maximum Ratings and Operating Ranges Added VIO Changed 1.65 V to –0.5 V Changed 2.3 V to 2.5 V CMOS Compatible Removed “VIO” from Max column of output high voltage row. Figure 16. Burst Mode Read (x32 mode) Corrected typos to subscripts. Corrected values for the tBACC and tDIND for the 54D, 65D, 64C, and 80C speed options. Figure 17. Asynchronous Command Write Timing Added tWC and tWPH. Figure 18. Synchronous Command Write/ Read Timing Added tWC and tWPH. Hardware Reset (RESET#) Corrected tREADY max. Figure 20. WP# Write Timing Added tWP. Figure 23. Back-to-back Cycle Timings Added tWPH. Figure 24. Data# Polling Timings (During Embedded Algorithms) Added tWC. Figure 29. Alternate CE# Controlled Write Operation Timings Added tWP and tWPH Erase and Programming Performance Changed the sector erase time typical to 1.0. DQ7: Data# Polling, DQ6: Toggle Bit I and DQ2: Toggle Bit II Added reference to Figure 27. Absolute Maximum Ratings Added ACC reference. CMOS Compatible Corrected Max values for the ICC5, 7, and 8 Added Note #5. Figure 27. Synchronous Data Polling Timings/Toggle Bit Timing Added Figure. Simultaneous Read/Write Operations Overview and Restrictions Added Sections and table. Table 7. Burst Initial Access Delay, Table 8. Configuration Register Definitions, Table 23. Test Specifications, Asynchronous Read Operations, and Burst Mode Read Removed the 65D, 80C, and 90A speed options from tables. Revision C (May 19, 2003) No revisions made, repost on web. Revision C+1 (May 29, 2003) Distinctive Characteristics Changed the standby mode to 60 μA. Product Selector Guide Changed the standard voltage range to 2.5-2.75 V Output Disable Mode Replace paragraph. Synchronous (Burst) Read Operation Removed reference to “contin uous sequentia l” from section. Figure 3. Initial Burst Delay Control Renumbered waveform to read two, three, four. Toggle Bit I Added sentence to second paragraph of section. CMOS Compatible Removed reference to continuous burst from table. Burst Mode Read Changed the tIACC Max for the 65A speed option to 67 ns. Revision B+5 (May 6, 2003) Global Converted data sheet from Advanced Information to Preliminary. Ordering Information Removed some OPNs and markings. Automatic Sleep Mode (ASM) and Standby Mode Reworded first paragraph. 76 Am29BDD160G June 7, 2006 Figure 15. Typical ICC1 vs. Frequency Renumbered Supply Current axis, removed 2.3 V graph, and changed other graph to 2.5 V. Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings Deleted line under the pulse in OE#. Revision D (June 30, 2003) Global Converted to a Preliminary Datasheet. Revision D+1 (June 30, 2003) Global Removed “Preliminary” status from data sheet. Distinctive Characteristics Added temperature range to simultaneous read/write operations section. DC Characteristics Inserted IACC field to table. Revision C+2 (June 26, 2003) Product Selector Guide Added Note. Synchronous (Burst) Read Operation, ADV#Control In Linear Mode, and IND/WAIT# Operation in Linear Mode Removed feature. Revision D2 (January 7, 2005) Table. 7 Valid Configuration Register Bit Definition for IND/WAIT# Removed features. Table 20. Sector Protection Command Definitions (x32 mode) Changed the address for OW A5-A0 to 011X10. Table 22. Sector Protection Command Definitions (x16 mode) Changed the PWA sector to A0:A-1 Figure 11. Typical ICC1 vs. Frequency Changed 2.5 to 2.7 and made T= 40°C Burst Mode Read Changed tBACC for 54D to 9 FBGA and 9.5 PQFP. Changed tDIND for 54D to 9 FBGA and 9.5 PQFP and for the 64C to 10 FBGA and 10 PQFP. Figure 27. Synchronous Data Polling Timing/Toggle Bit Timing Added note 4. Added note on cover page and first page of data sheet that the Am29BDD160G has been superceded by the Spansion S29CD016G. Revision D3 (February 2, 2005) Ordering Information Added lead free to package. Added new package types to valid combinations. Revision D4 (November 4, 2005) Block Diagram: Changed “DQ0-DQ15 to DQ0-DQ31” in the block diagram. Connection Diagram: Restored labels to figure. Absolute Maximum Ratings: C hanged voltages in vvershoot diagrams. AC Characteristics, Burst Mode Read table: Deleted parameters tDS, tDH, tAS, tAH, tCS Revision D5 (June 7, 2006) Global: Restored previous formatting to document. Trademarks Copyright © 2003–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. June 7, 2006 Am29BDD160G 77