NG80386SX-40

FINAL Am386®SX/SXL/SXLV High-Performance, Low-Power, Embedded Microprocessors DISTINCTIVE CHARACTERISTICS s Member of the E86™ CPU series – 16-bit data bus – 24-bit address bus – 16-Mbyte address range – Long-term stable supply from AMD s 40-, 33- and 25-MHz operating speeds s Ideal for embedded applications – True Static design for low-power applications – 3–5 V operation (at 25 MHz) – Ideal for cost-sensitive designs – True DC (0 MHz) operation s Industry Standard Architecture – Supports world’s largest software base for x86 architectures – Wide range of chipsets and BIOS available – Fully compatible with all 386SX systems and software s System Management Mode (SMM) for system and power management (Am386SXLV only) – System Management Interrupt (SMI) for power management independent of processor operating mode and operating system – SMI coupled with I/O instruction break feature provides transparent power off and auto resume of peripherals which may not be “power aware” – SMI is non-maskable and has higher priority than Non-Maskable Interrupt (NMI) – Automatic save and restore of the microprocessor state s 100-lead Plastic Quad Flat Pack (PQFP) package s Extended temperature version available GENERAL DESCRIPTION The Am386®SX/SXL/SXLV microprocessors are lowcost, high-performance CPUs for embedded applications. Embedded customers benefit from using the Am386 microprocessor in a number of ways. The Am386SX/SXL/SXLV microprocessors provide embedded customers access to very inexpensive processors and the highest performance of any 386SX available anywhere. The 16-bit data path allows for inexpensive memory design. Full static operation, coupled with 3-V supplies, benefit customers who desire low-power designs. Standby Mode allows the Am386SXL/SXLV microprocessors to be clocked down to 0 MHz (DC) and retain full register contents. A float pin places all outputs in a three-state mode to facilitate board test and debug. Additionally, the Am386SXLV microprocessor comes with System Management Mode (SMM) for system and power management. SMI (System Management Interrupt) is a non-maskable, higher priority interrupt than NMI and has its own code space (1 Mbyte in Real Mode and 16 Mbyte in Protected Mode). SMI can be coupled with the I/O instruction break feature to implement transparent power management of peripherals. SMM can be used by system designers to implement system and power management code independent of the operating system or the processor mode. Since the Am386SX/SXL/SXLV microprocessors are supported as an embedded product in the E86 family, customers can rely on long-term supply of product, and extended temperature products. In addition, customers have access to the largest selection of inexpensive development tools, compilers, and chipsets. A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to market. The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package. Publication# 21020 Rev: A Amendment/0 Issue Date: April 1997 FINAL ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. I NG 80386 SX –40 SPEED OPTION –40 = 40 MHz –33 = 33 MHz –25 = 25 MHz PROCESSOR TYPE SX = SX Processor SXL = SX Processor with Static Clock Implementation SXLV = SXL Processor with Low-Voltage and SMI PROCESSOR FAMILY Am386 Family PACKAGE TYPE NG=100-Lead Plastic Quad Flat Pack (PQB-100) TEMPERATURE RANGE Blank = Commercial (TCASE = 0°C to +100°C) I = Industrial (TCASE = –40°C to +100°C) Valid Combinations –25 NG80386 SX –33 –40 SXL SXLV ING80386 SX –25 –33 –25 –25 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL BLOCK DIAGRAM Segmentation Unit Effective Address Bus Paging Unit Adder 25 Page Cache Control and Attribute PLA Code Fetch/Page Table Fetch Linear Address Bus Physical Address Bus Bus Control Request Prioritizer Control 3-Input Adder 32 Descriptor Registers Limit and Attribute PLA 32 Effective Address Bus HOLD, INTR, NMI, ERROR, BUSY, RESET, HLDA, FLT, SMI*, IIBEN* 32 Protection Test Unit Displacement Bus Address Driver Pipeline/ Bus Size Control MUX/ Transceivers BHE, BLE, A23-A1 M/IO, D/C, W/R, LOCK, ADS, NA, READY, SMIADS*, SMIRDY* D15-D0 Internal Control Bus Barrel Shifter, Adder Multiply/ Divide Register File Status Flags Decode and Sequencing Instruction Decoder Code Stream Prefetcher/ Limit Checker 16-Byte Code Queue Instruction Prefetch 32 ALU Control Control ROM Control 3-Decoded Instruction Queue Instruction Predecode Dedicated ALU Bus 32 Bit ALU * – On Am386SXLV only 32 FUNCTIONAL DESCRIPTION True Static Operation (Am386SXL/SXLV Only) The Am386SXL/SXLV microprocessor incorporates a true static design. Unlike dynamic circuit design, the Am386SXL/SXLV device eliminates the minimum operating frequency restriction. It may be clocked from its maximum speed all the way down to 0 MHz (DC). System designers can use this feature to design portable applications with long battery life. plifies the design of power-conscious portable applications in the following ways. s Eliminates the need for software in BIOS to save and restore the contents of registers. s Allows simpler circuitry to control stopping of the clock since the system does not need to know the state of the processor. Standby Mode (Am386SXL/SXLV Only) The true static design of the Am386SXL/SXLV microprocessor allows for a Standby Mode. At any operating speed, the microprocessor will retain its state (i.e., the contents of all its registers). By shutting off the clock completely, the device enters Standby Mode. Since power consumption is proportional to clock frequency, operating power consumption is reduced as the frequency is lowered. In Standby Mode, typical current draw is reduced to less than 20 microamps at DC. Not only does this feature save battery life, but it also sim- Lower Operating Icc (Am386SXL/SXLV Only) True static design also allows lower operating Icc when operating at any speed. Performance on Demand (Am386SXL/SXLV Only) The Am386SXL/SXLV microprocessor retains its state at any speed from 0 MHz (DC) to its maximum operating speed. With this feature, system designers may vary the operating speed of the system to extend the battery life in portable systems. Am386SX/SXL/SXLV Microprocessors Data Sheet 3 FINAL For example, the system could operate at low speeds during inactivity or polling operations. However, upon interrupt, the system clock can be increased up to its maximum speed. After a user-defined time-out period, the system can be returned to a low (or 0 MHz) operating speed without losing its state. This design maximizes battery life while achieving optimal performance. to the SMM code is executed. This Real mode code can perform its system management function and then resume execution of the normal system software by executing an RES3 instruction which will reload the saved processor state and continue execution in the main system memory space. See Figure 1 for a general flowchart of an SMM operation. CPU Interface—Pin Functions The CPU interface for SMM consists of three pins dedicated to the SMI function. One pin, SMI, is the interrupt input. The other two pins, SMIADS and SMIRDY, provide the control signals necessary for the separate SMM mode memory space. Benefits of Lower Operating Voltage (Am386SXLV Only) The Am386SXLV microprocessor has an operating voltage range of 3.0 V to 5.5 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for portable applications. Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V reduces power consumption by 56%. This directly translates to a doubling of battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor. A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise generation and provides a less hostile environment for board design. Lower operating voltage also reduces electromagnetic radiation noise and makes FCC approval easier to obtain. SMI sampled active (Low) Current instruction finishes execution, normal ADS goes inactive CPU saves state to separate SMM memory space, starting at address 60000h SMM—System Management Mode (Am386SXLV Only) The Am386SXLV microprocessor has a System Management Mode (SMM) for system and power management. This mode consists of two features: System Management Interrupt (SMI) and I/O instruction break. SMI—System Management Interrupt SMI is implemented by using special bus interface pins. This interrupt method can be used to perform system management functions such as power management independent of processor operating mode (Real, Protected, or Virtual 8086 modes). SMI can also be invoked in software. This allows system software to communicate with SMI power management code. In addition, the UMOV instruction allows data transfers between SMI and normal system memory spaces. Activating the SMI pin invokes a sequence that saves the operating state of the processor into a separate SMM memory space, independent of the main system memory. After the state is saved, the processor is forced into Real mode and begins execution at address FFFFF0h in the SMM memory space where a far jump CPU enters Real Mode, starts code fetches at location FFFFF0h in SMM memory space Real Mode SMM interrupt handler code execution (after FAR JUMP) Restore saved state from 60000h with RES3 (0F 07) opcode sequence Normal code execution resumes 16305C–002 Figure 1. SMM Flow 4 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL Description of SMM Operation (Am386SXLV Only) The execution of a System Management Interrupt has four distinct phases: the initiation of the interrupt via SMI, a processor state save, execution of the SMM interrupt code, and a processor state restore (to resume normal operation). Interrupt Initiation A System Management Interrupt is initiated by the driving of a synchronous, active Low pulse on the SMI pin until the first SMIADS is asserted. This pulse period will ensure recognition of the interrupt. The CPU drives the SMI pin active after the completion of the current operation (active bus cycle, instruction execution, or both). The active drive of the pin by the CPU is released at the end of the interrupt routine following the last register read of the saved state. The CPU drives SMI High for two CLK2 cycles prior to releasing the drive of SMI. An SMI cannot be masked off by the CPU, and it will always be recognized by the CPU, regardless of operating modes. This includes the Real, Protected, and Virtual-8086 modes of the processor. While the CPU is in SMM, a bus hold request via the HOLD pin is granted. The HLDA pin goes active after bus release and the SMIADS pin floats along with the other pins that normally float during a bus hold cycle. SMI does not float during a Bus Hold cycle. Processor State Save The first set of SMM bus transfer cycles after the CPU’s recognition of an active SMI is the processor saving its state to an external RAM array in a separate address space from main system memory. This is accomplished by using the SMIADS and SMIRDY pins for initiation and termination of bus cycles, instead of the ADS and READY pins. The 24-bit addresses to which the CPU saves its state are 60000h–600CBh and 60100h–60127h. These are fixed address locations for each register saved. To ensure valid operation, pipelining must be disabled while the processor is in SMM. There are 114 data transfer cycles. SMI Code Execution After the processor state is saved to the separate SMM memory space, the execution of the SMM interrupt routine code begins. The processor enters Real mode, sets most of the register values to “reset” values (those values normally seen after a CPU reset), and begins fetching code from address FFFFF0h in the separate SMM memory space. Normally, the first thing the interrupt routine code does is a FAR JUMP to the Real mode entry point for the SMM interrupt routine, which is also in SMM memory space. Both INTR and NMI are disabled upon entry into SMM. The SMM code can be located anywhere within the 1-Mbyte Real mode address space, except for where the processor state is saved. I/O cycles, as a result of the IN, OUT, INS, and OUTS instructions, will go to the normal address space, utilizing the normal ADS and READY bus interface signals. This facilitates power management code manipulating system hardware registers as needed through the standard I/O subsystem; a separate I/O space is not implemented. Processor State Restore (Resuming Normal Execution) Returning to normal code execution in the main system memory, including restoring the processor operating mode, is accomplished by executing a special code sequence. This code invokes a restore CPU state operation that reloads the CPU registers from the saved data in the RAM controlled by SMIADS and SMIRDY. The ES:EDI register pair must point to the physical address of the processor save state (6000h). In Real mode the address is calculated as ES•16 + EDI offset. The saved state should not cross a 64K boundary. The RES3 instruction (0F 07) should be executed to start the restore state operation. After completion of the restore state operation, the SMI pin will be deactivated by the CPU and normal code execution will continue at the point where it left off before the SMI occurred. There are 114 data transfer cycles in the restore operation. Software Features (Am386SXLV Only) Several features of the SMI function provide support for special operations during the execution of the system’s software. These features involve the execution of reserved opcodes to induce specific SMI-related operations. Software SMI Generation Besides hardware initiation of the SMI via the SMI pin, there is also a software-induced SMI mechanism. Generating a soft SMI involves setting a control bit (Bit 12) in the Debug Control Register (DR7) and executing an SMI instruction (opcode F1h). The functional sequence of the software-based SMI is identical to the hardware-based SMI with the exception that the SMI pin is not initially driven active by an external source. Upon execution of a soft SMI opcode, the SMI pin is driven active (Low) by the processor before the save state operation begins. Memory Transfers to Main System Memory While executing an SMI routine, the interrupt code can initiate memory data reads and writes to the main system memory using the normal ADS and READY pins. This initiation is accomplished by using reserved opcodes that are special forms of the MOV instruction (called UMOV). The UMOV opcodes can move byte, Am386SX/SXL/SXLV Microprocessors Data Sheet 5 FINAL word, or double word register operands to or from main system memory. Multiple data transfers using the normal ADS and READY pins will occur if the operands are misaligned relative to the effective address used. The UMOV opcodes are 0F 10h, 0F 11h, 0F 12h, and 0F 13h. The UMOV instruction can use any of the 386 addressing modes, as specified in the ModR/M byte of the opcode. Note that the 16- and 32-bit versions are the same opcodes with the exception of the 66h operand size prefix. service routine normally returns to the instruction following the I/O instruction that caused the break. By modifying the saved state instruction pointer, the routine can choose to return to the I/O instruction that caused the break and re-execute that instruction. The default is to return to the following instruction (except for REP I/O string instruction). To re-execute the I/O instruction that caused the break, the SMI service routine must copy the I/O instruction pointer over the default pointer. This feature is particularly useful when an application program requests an access to a peripheral that has been powered down. The SMI service routine can restore power to the peripheral and initiate a re-execution sequence transparent to the application program. This re-execution feature should only be used if the SMI is in response to an I/O trap with IIBEN active. Note that the I/O instruction break feature is not enabled for memory mapped I/O devices or for coprocessor bus cycles even if IIBEN is active. I/O Instruction Break Timing The I/O Instruction Break feature requires that SMI be sampled active (Low) by the processor at least three CLK2 edges before the CLK2 edge that ends the I/O cycle with an active READY signal. This timing applies for both pipelined and non-pipelined cycles. If this timing constraint is not met, additional instructions may be executed by the internal execution unit prior to entering SMM. Depending on the state of the prefetch queue at the time the SMI is asserted, instruction fetch cycles may occur on the normal ADS interface before the SMM save state process begins with the assertion of SMIADS. However, this fetched code will not be executed. I/O Instruction Break (Am386SXLV Only) The Am386SXLV microprocessor has an I/O instruction break feature that allows the system logic to implement I/O trapping for peripheral devices. To enable the I/O Instruction break feature, IIBEN must first be asserted active Low. On detecting an I/O instruction, the processor prevents the execution unit from executing further instructions until READY is driven active Low by the system. Once READY is driven active, the execution unit either immediately responds to any active interrupt request or continues executing instructions following the I/O instruction that caused the break. The I/O instruction break feature can be used to allow system logic to implement I/O trapping for peripheral devices. On sensing an I/O instruction, the system drives the SMI pin active before driving READY active. This ensures that the interrupt service routine is executed immediately following the I/O instruction that caused the break. (If the I/O instruction break feature is not enabled via IIBEN, several instructions could execute before the SMI service routine is executed.) The SMI service routine can access the peripheral for which SMI was asserted and modify its state.The SMI 6 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL CONNECTION DIAGRAM 100-Lead Plastic Quad Flat Pack (PQFP) Package—Top Side View VCC D7 VCC D10 D11 D12 VSS VCC D13 D14 D15 A23 D2 VSS A22 VSS VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 D0 VSS HLDA HOLD VSS NA READY VCC VCC VCC VSS VSS VSS VSS CLK2 ADS BLE A1 BHE NC VCC VSS M/IO D/C W/R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 37 38 39 40 41 42 43 44 26 34 35 36 45 46 47 48 49 50 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A21 D1 D3 D4 D5 D6 D8 D9 A20 A19 A18 A17 VCC A16 VCC VSS VSS A15 A14 A13 VSS A12 A11 A10 A9 A8 VCC A7 A6 A5 A4 A3 A2 Top Side View LOCK NC FLT *IIBEN *SMIRDY *SMIADS VCC INTR VSS VCC Notes: Pin 1 is marked for orientation NC = Not connected; connection of an NC pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only; NC on Am386SX/SXL Am386SX/SXL/SXLV Microprocessors Data Sheet ERROR PEREQ NMI VCC RESET BUSY VSS *SMI NC NC NC NC VCC VSS VSS 7 FINAL CONNECTION DIAGRAM 100-Lead Plastic Quad Flat Pack (PQFP) Package—Pin Side View LOCK NC FLT IIBEN* SMIRDY* SMIADS* VCC RESET BUSY VSS ERROR PEREQ NMI VCC INTR VSS VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 W/R D/C M/IO VSS VCC NC BHE A1 BLE ADS CLK2 VSS VSS VSS VSS VCC VCC VCC READY NA VSS HOLD HLDA VSS D0 44 45 46 47 48 49 50 SMI* NC NC NC NC VCC VSS VSS 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 A11 A12 VSS A13 A14 A15 VSS VSS VCC A16 VCC A17 A18 A19 A20 Pin Side View D1 D2 VSS VCC D12 VSS VCC D10 D11 D13 D14 D15 A22 VSS VSS D6 D7 VCC D3 D4 D5 D8 D9 A23 Notes: Pin 1 is marked for orientation NC = Not connected; connection of an NC pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only; NC on Am386SX/SXL 8 Am386SX/SXL/SXLV Microprocessors Data Sheet A21 FINAL PIN DESIGNATION TABLE (Sorted by Functional Grouping) Address Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Pin No. 18 51 52 53 54 55 56 58 59 60 61 62 64 65 66 70 72 73 74 75 76 79 80 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Data Pin Name Pin No. 1 100 99 96 95 94 93 92 90 89 88 87 86 83 82 81 Control Pin Name ADS BHE BLE BUSY CLK2 D/C ERROR FLT HLDA HOLD IIBEN* INTR LOCK M/IO NA NMI PEREQ READY RESET SMI* SMIADS* SMIRDY* W/R Pin No. 16 19 17 34 15 24 36 28 3 4 29 40 26 23 6 38 37 7 33 43 31 30 25 NC Pin No. 20 27 44 45 46 47 VCC VSS Pin No. Pin No. 8 9 10 21 32 39 42 48 57 69 71 84 91 97 2 5 11 12 13 14 22 35 41 49 50 63 67 68 77 78 85 98 * On Am386SXLV only; NC on Am386SX/SXL PIN DESIGNATION TABLE (Sorted by Pin Number) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name D0 VSS HLDA HOLD VSS NA READY VCC VCC VCC VSS VSS VSS VSS CLK2 ADS BLE A1 BHE NC Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name VCC VSS M/IO D/C W/R LOCK NC FLT IIBEN* SMIRDY* SMIADS* VCC RESET BUSY VSS ERROR PEREQ NMI VCC INTR Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name VSS VCC SMI* NC NC NC NC VCC VSS VSS A2 A3 A4 A5 A6 A7 VCC A8 A9 A10 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name A11 A12 VSS A13 A14 A15 VSS VSS VCC A16 VCC A17 A18 A19 A20 A21 VSS VSS A22 A23 Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name D15 D14 D13 VCC VSS D12 D11 D10 D9 D8 VCC D7 D6 D5 D4 D3 VCC VSS D2 D1 * On Am386SXLV only; NC on Am386SX/SXL Am386SX/SXL/SXLV Microprocessors Data Sheet 9 FINAL PIN DESCRIPTIONS A23–A1 Address Bus (Outputs) Outputs physical memory or port I/O addresses. ADS Address Status (Active Low; Output) Indicates that a valid bus cycle definition and address (W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being driven at the Am386SX/SXL/SXLV microprocessor pins. Bus cycles initiated by ADS must be terminated by READY. BHE, BLE Byte Enables (Active Low; Outputs) Indicate which data bytes of the data bus take part in a bus cycle. BUSY Busy (Active Low; Input) Signals a busy condition from a processor extension. BUSY has an internal pull-up resistor. CLK2 CLK2 (Input) Provides the fundamental timing for the Am386SX/ SXL/SXLV microprocessor. D15–D0 Data Bus (Inputs/Outputs) Inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data during memory and I/O write cycles. D/C Data/Control (Output) A bus cycle definition pin that distinguishes data cycles, either memory or I/O, from control cycles which are interrupt acknowledge, halt, and code fetch. ERROR Error (Active Low; Input) Signals an error condition from a processor extension. ERROR has an internal pull-up resistor. FLT Float (Active Low; Input) An input which forces all bidirectional and output signals, including HLDA, to the three-state condition. FLT has an internal pull-up resistor. The pin, if not used, should be disconnected. HLDA Bus Hold Acknowledge (Active High; Output) Output indicates that the Am386SX/SXL/SXLV microprocessor has surrendered control of its logical bus to another bus master. HOLD Bus Hold Request (Active High; Input) Input allows another bus master to request control of the local bus. IIBEN (Am386SXLV Only) I/O Instruction Break Enable (Active Low; Input) Enables the I/O instruction break feature. IIBEN has a dynamic internal pull-up resistor. The IIBEN pull-up is active during RESET and whenever the signal is not driven active Low by the system. INTR Interrupt Request (Active High; Input) A maskable input that signals the Am386SX/SXL/ SXLV microprocessor to suspend execution of the current program and execute an interrupt acknowledge function. LOCK Bus Lock (Active Low; Output) A bus cycle definition pin that indicates that other system bus masters are not to gain control of the system bus while it is active. M/IO Memory/IO (Output) A bus cycle definition pin that distinguishes memory cycles from input/output cycles. NA Next Address (Active Low; Input) Used to request address pipelining. NC No Connect Should always be left unconnected. Connection of an NC pin may cause the processor to malfunction or be incompatible with future steppings of the Am386SX/ SXL/SXLV microprocessor. NMI Non-Maskable Interrupt Request (Active High; Input) A non-maskable input that signals to the Am386SX/ SXL/SXLV microprocessor to suspend execution of the current program and execute an interrupt acknowledge function. PEREQ Processor Extension Request (Active High; Input) Indicates that the processor has data to be transferred by the Am386SX/SXL/SXLV microprocessor. PEREQ has an internal pull-down resistor. 10 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL READY Bus Ready (Active Low; Input) Terminates the bus cycle initiated by ADS. RESET Reset (Active High; Input) Suspends any operation in progress and places the Am386SX/SXL/SXLV microprocessor in a known reset state. SMI (Am386SXLV Only) System Management Interrupt (Active Low; I/O) A non-maskable interrupt pin that signals to the Am386SXLV microprocessor to suspend execution and enter System Management Mode. SMI has an internal pull-up resistor. SMI has a dynamic internal pull-up resistor that is disabled when the processor is in SMM. SMI is not three-stated during Hold Acknowledge bus cycles. SMIADS (Am386SXLV Only) SMI Address Status (Active Low; Output) When active, this pin indicates that a valid bus cycle definition and address (W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being driven at the Am386SXLV microprocessor pins while in the System Management mode. Bus cycles initiated by SMIADS must be terminated by SMIRDY. SMIRDY (Am386SXLV Only) SMI Ready (Active Low; Input) This input terminates the current bus cycle to the SMM mode address space in the same manner the READY pin does for the normal mode address space. SMIRDY has an internal pull-up resistor. READY and SMIRDY must not be tied together. VCC System Power (Input) Provides the 5 V nominal DC supply input. VSS System Ground (Input) Provides the 0-V connection from which all inputs and outputs are measured. W/R Write/Read (Output) A bus cycle definition pin that distinguishes write cycles from read cycles. LOGIC SYMBOL 2X Clock CLK2 A23–A1 FLT 2 BLE, BHE RESET NMI INTR Bus Cycle Control ADS NA READY PEREQ W/R Bus Cycle Definition D/C M/IO LOCK SMI SMIADS SMIRDY IIBEN HOLD *On Am386SXLV only D15–D0 16 Data Bus 23 Address Bus Float Interrupt Control Am386SXLV Microprocessor BUSY ERROR Math Coprocessor Control System Management Mode Control* HLDA Bus Arbitration Control 16305C–003 Am386SX/SXL/SXLV Microprocessors Data Sheet 11 FINAL ABSOLUTE MAXIMUM RATINGS Storage Temperature ....................... –65°C to +150°C Ambient Temperature Under Bias .... –65°C to +125°C OPERATING RANGES Supply Voltage with respect to Vss..... –0.5 V to +7.0 V Voltage on Other Pins................ –0.5 V to (Vcc +0.5) V Stresses above those listed may cause permanent damage to the device. Functionality at or above these limits is not implied. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. Vcc =3.0 V to 3.6 V; TCASE =0°C to +100°C Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges for 25 MHz Am386SXLV Final Symbol VIL VIH VILC VIHC VOL Parameter Description Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage IOL = 0.5 mA: A23–A1, D15–D0 IOL = 0.5 mA: BHE, BLE, W/R, D/C, SMIADS, M/IO, LOCK, ADS, HLDA, SMI IOL = 2 mA: A23–A1, D15–D0 IOL = 2.5 mA: BHE, BLE, W/R, D/C, SMIADS, LOCK, ADS, M/IO, HLDA, SMI Output High Voltage IOH = 0.1 mA: A23–A1, D15–D0 IOH = 0.1 mA: BHE, BLE, W/R, D/C, SMIADS, LOCK, ADS, M/IO, HLDA, SMI IOH = 0.5 mA: A23–A1, D15–D0 IOH = 0.5 mA: BHE, BLE, W/R, D/C, SMIADS, LOCK, ADS, M/IO, HLDA, SMI Input Leakage Current (All pins except PEREQ, BUSY, ERROR , SMI, SMIRDY, FLT, IIBEN) Input Leakage Current (PEREQ pin) Input Leakage Current (BUSY, ERROR , SMI, SMIRDY, FLT, IIBEN) Output Leakage Current Supply Current (Note 8) CLK2 = 50 MHz: Oper. Freq. 25 MHz Standby Current (Note 8) Input or I/O Capacitance Output Capacitance CLK2 Capacitance (Note 5) (Note 1) Notes (Note 1) Min –0.3 2.0 Max +0.8 VCC +0.3 +0.8 VCC +0.3 0.2 0.2 0.45 0.45 Unit V V V V V V V V –0.3 2.4 VOH (Note 5) (Note 6) VCC –0.2 VCC–0.2 VCC–0.45 VCC –0.45 V V V V ILI 0 V ≤ VIN ≤ VCC (Note 7) VIH = VCC –0.1 V VIH = 2.4 V (Note 2) VIL = 0.1 V VIL = 0.45 V (Note 3) 0.1 V ≤ VOUT ≤ VCC VCC = 3.3 V ICC Typ = 95 ICCSB Typ = 10µA FC = 1 MHz (Note 4) FC = 1 MHz (Note 4) FC = 1 MHz (Note 4) ±10 300 200 –300 –200 +15 VCC = 3.6 V 115 150 10 12 20 µA µA µA µA µA µA mA µA pF pF pF IIH IIL ILO ICC ICCSB CIN COUT CCLK Notes: 1. 2. 3. 4. 5. 6. 7. 8. The Min value, –0.3, is not 100% tested. PEREQ input has an internal pull-down resistor. BUSY, ERROR , FLT, SMI, IIBEN, and SMIRDY inputs each have an internal pull-up resistor. Not 100% tested. Outputs are CMOS and will pull rail-to-rail if the load is not resistive. VOH SMI only valid on SMI output when exiting SMM for two CLK2 periods. SMI and IIBEN leakage Low will be ILI when pull-up is inactive and IIL when pull-up is active. Inputs at rails (VCC or VSS). 12 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL ABSOLUTE MAXIMUM RATINGS Storage Temperature ....................... –65°C to +150°C Ambient Temperature under Bias .... –65°C to +125°C OPERATING RANGES Supply Voltage with respect to VSS .... –0.5 V to +7.0 V Voltage on Other Pins................–0.5 V to (Vcc +0.5) V Stresses above those listed may cause permanent damage to the device. Functionality at or above these limits is not implied. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges 25 and 33 MHz: Vcc = 5 V ± 10%; TCASE = 0°C to +100°C (commercial); TCASE = –40°C to +100°C (industrial) 40 MHz: Vcc = 5 V ± 5%; TCASE = 0°C to +100°C Final Symbol VIL VIH VILC VIHC VOL Parameter Description Input Low Voltage Input High Voltage CLK2 Input Low Voltage CLK2 Input High Voltage Output Low Voltage IOL = 4 mA: A23–A1, D15–D0 IOL = 5 mA: BHE, BLE,W/R, D/C, SMIADS*, M/IO, LOCK, ADS, HLDA, SMI* Output High Voltage IOH = 1.0 mA: A23–A1, D15–D0 IOH = 0.2 mA: A23–A1, D15–D0 IOH = 0.9 mA: BHE, BLE, W/R, D/C, SMIADS*, LOCK, ADS, M/IO, HLDA, SMI* IOH = 0.18 mA: BHE, BLE, W/R, D/C, SMIADS*, LOCK, ADS, M/IO, HLDA, SMI* Input Leakage Current (All pins except PEREQ, BUSY, ERROR , SMI*, SMIRDY*, FLT, and IIBEN*) Input Leakage Current (PEREQ pin) Input Leakage Current (BUSY, ERROR , SMI*, SMIRDY*, FLT, IIBEN*) Output Leakage Current: Am386SX/SXL Am386SXLV Supply Current (Note 8) CLK2 = 50 MHz: Oper. Freq. 25 MHz CLK2 = 66 MHz: Oper. Freq. 33 MHz CLK2 = 80 MHz: Oper. Freq. 40 MHz Standby Current (Note 8) Input or I/O Capacitance Output or I/O Capacitance CLK2 Capacitance (Note 5) (Note 1) Notes (Note 1) Min –0.3 2.0 Max +0.8 VCC +0.3 +0.8 VCC +0.3 0.45 0.45 Unit V V V V V V –0.3 2.7 VOH (Note 5) (Note 6*) 2.4 VCC –0.5 2.4 VCC –0.5 V V V V ILI 0 V ≤ VIN ≤ VCC (Note 7) VIH = 2.4 V (Note 2) VIL = 0.45 V (Note 3) 0.1 V ≤ VOUT ≤ VCC 0.45 V ≤ VOUT ≤ VCC VCC Typ = 5.0 V ICC Typ = 160 ICC Typ = 210 ICC Typ = 255 ICCSB Typ = 20 µA FC = 1 MHz (Note 4) FC = 1 MHz (Note 4) FC = 1 MHz (Note 4) ±15 200 µA µA µA µA µA V mA mA mA µA pF pF pF IIH IIL ILO ICC –400 ±15 ±15 VCC = 5.5 190 245 295 150 10 12 20 ICCSB CIN COUT CCLK Notes: * On Am386SXLV only 1. The Min value, –0.3, is not 100% tested. 2. PEREQ input has an internal pull-down resistor. 3. BUSY, ERROR, FLT, SMI*, IIBEN*, and SMIRDY* inputs each have an internal pull-up resistor. 4. Not 100% tested. 5. Outputs are CMOS and will pull rail-to-rail if the load is not resistive. 6. VOH SMI only valid on SMI output when exiting SMM for two CLK2 periods (on Am386SXLV only). 7. SMI and IIBEN leakage Low will be ILI when pull-up is inactive and IIL when pull-up is active (on Am386SXLV only). 8. Inputs at rails (VCC or VSS), outputs unloaded, PEREQ Low, ERROR High, BUSY High, and FLT High. Am386SX/SXL/SXLV Microprocessors Data Sheet 13 FINAL SWITCHING CHARACTERISTICS The switching characteristics given consist of output delays, input setup requirements, and input hold requirements. All switching characteristics are relative to the CLK2 rising edge crossing the 2.0-V level. Switching characteristic measurement is defined in Figure 2. Inputs must be driven to the voltage levels indicated by Figure 2 when switching characteristics are measured. Output delays are specified with minimum and maximum limits measured, as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct operation. Outputs ADS, W/R, D/C, M/IO, LOCK, BHE, BLE, A23–A1, HLDA, and SMIADS* only change at the beginning of phase one. D15–D0 and SMI* write cycles only change at the beginning of phase two. The READY, HOLD, BUSY, ERROR , PEREQ, FLT, D15– D0, IIBEN*, and SMIRDY* read cycles inputs are sampled at the beginning of phase one. The NA, INTR, NMI, and SMI* inputs are sampled at the beginning of phase two. * – On Am386SXLV only; NC on Am386SX/SXL Tx φ1 CLK2 2V φ2 A (A23–A1, BHE, BLE, ADS, M/IO, D/C, W/R, LOCK, HLDA, SMIADS*) B Min Max VT Valid Output n+1 Valid VT Output n A B Min Max VT Valid Output n+1 (D15–D0, SMI*) Valid VT Output n C D (NA, INTR, NMI, SMI*) VT Valid Input VT C D (READY, HOLD, FLT, ERROR , BUSY, PEREQ, D15–D0, IIBEN*, SMIRDY*) Legend: A–Maximum Output Delay Characteristic B–Minimum Output Delay Characteristic C–Minimum Input Setup Characteristic D–Minimum Input Hold Characteristic VT Valid Input VT Notes: 1. Input waveforms have tr ≤ 2.0 ns from 0.8 V–2.0 V (on Am386SXLV only). 2. On Am386SX/SXL, VT = 1.5; on Am386SXLV, VT = 1.0 V for VCC ≤ 3.6 V and 1.5 V for VCC > 3.6 V. 3. * = On Am386SXLV only. 16305C–003 Figure 2. Drive Levels and Measurement Points for Switching Characteristics 14 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges at 25 MHz VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C (Commercial); TCASE = –40°C to +100°C (Industrial) VCC = 3.0 V–5.5 V; TCASE = 0°C to +100°C (Am386SXLV only) Symbol Parameter Description Operating Frequency: Am386SX CPU Am386SXL/SXLV CPU CLK2 Period CLK2 High Time: Am386SXLV CPU CLK2 High Time: Am386SX/SXL CPU CLK2 High Time: Am386SX/SXL CPU CLK2 Low Time: Am386SXLV CPU CLK2 Low Time: Am386SX/SXL CPU CLK2 Low Time: Am386SX/SXL CPU CLK2 Fall Time: Am386SX/SXL CPU Am386SXLV CPU CLK2 Rise Time: Am386SX/SXL CPU Am386SXLV CPU A23–A1 Valid Delay A23–A1 Float Delay BHE, BLE, LOCK Valid Delay BHE, BLE, LOCK Float Delay M/IO, D/C, W/R, ADS Valid Delay SMIADS Valid Delay W/R, M/IO, D/C, ADS Float Delay SMIADS Float Delay D15–D0 Write Data Valid Delay D15–D0 Write Data Hold Time D15–D0 Write Data Float Delay HLDA Valid Delay HLDA Float Delay: Am386SX/SXL Am386SXLV NA Setup Time NA Hold Time READY Setup Time SMIRDY Setup Time READY Hold Time SMIRDY Hold Time D15–D0 Read Data Setup Time D15–D0 Read Data Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI, INTR Setup Time SMI Setup Time NMI, INTR Hold Time SMI Hold Time PEREQ, ERROR , BUSY, FLT, IIBEN5 Setup Time PEREQ, ERROR , BUSY, FLT, IIBEN5 Hold Time SMI Valid Delay SMI Float Delay Notes Half CLK2 freq. Half CLK2 freq. at VIHC at 2 V at (VCC–0.8 V) at 0.8 V at 2 V at 0.8 V (VCC–0.8 V) to 0.8 V 2.4 V to 0.8 V 0.8 V to 2.4 V 0.8 V to (VCC–0.8 V) CL = 50 pF CL = 50 pF (Note 1) CL = 50 pF CL = 50 pF (Note 5) (Note 1) (Notes 1, 5) Ref. Figures Final Min Max 2 25 0 25 20 4 7 4 5 7 5 7 7 4 4 4 4 4 4 4 4 7 2 4 4 4 4 5 3 9 9 4 4 7 5 9 3 8 3 6 6 6 4 6 5 4 4 17 30 17 30 17 25 30 30 23 22 22 22 30 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 2 2a 2b 3 3a 3b 4 5 6 7 8 9 10 10s 11 11s 12 12a 13 14 14f (Note 3) (Note 3) (Note 3) (Note 3) (Note 1) CL = 50 pF CL = 50 pF (Note 1) CL = 50 pF (Notes 1, 4) 3, 4 3 4 4 3 4 4 4 3 4 3 8 15 8 15 8 8 15, 18 15 8, 9 10 15 8 15, 16 15 7 ns 7 ns 16 19 7 ns 19s (Note 5) 7 ns 7 ns 20 20s (Note 5) 7 ns 21 7 ns 22 7 ns 23 7 ns 24 7 ns 25 17 ns 26 17 ns 27 (Note 2) 7 ns (Note 5) 7 ns 27s 28 (Note 2) 7 ns (Note 5) 7 ns 28s 29 (Note 2) 7 ns 30 (Note 2) 7 ns (Note 5) 8, 15 22 ns 31 32 (Notes 1, 4, 5) 16 30 ns Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Only during FLT assertion. 5. On Am386SXLV only. Am386SX/SXL/SXLV Microprocessors Data Sheet 15 FINAL SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 33 MHz VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C Symbol Parameter Description Operating Frequency: Am386SX CPU Am386SXL CPU CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A23–A1 Valid Delay A23–A1 Float Delay BHE, BLE, LOCK Valid Delay BHE, BLE, LOCK Float Delay M/IO, D/C, W/R, ADS Valid Delay W/R, M/IO, D/C, ADS Float Delay D15–D0 Write Data Valid Delay D15–D0 Write Data Hold Time D15–D0 Write Data Float Delay HLDA Valid Delay HLDA Float Delay NA Setup Time NA Hold Time READY Setup Time READY Hold Time D15–D0 Read Data Setup Time D15–D0 Read Data Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI, INTR Setup Time NMI, INTR Hold Time PEREQ, ERROR , BUSY Setup Time PEREQ, ERROR , BUSY Hold Time Notes Half CLK2 freq. Half CLK2 freq. Ref. Figures Final Min Max 2 33 0 33 15 6.25 4 6.25 4.5 4 4 4 15 4 20 4 15 4 20 4 15 4 20 7 23 2 4 17 4 20 4 20 5 2 7 4 5 3 9 2 5 2 5 5 5 4 Unit MHz 1 4 ns 2a at 2 V 4 ns 2b at 3.7 V 4 ns 3a at 2 V 4 ns 3b at 0.8 V 4 ns 4 3.7 V to 0.8 V (Note 3) 4 ns 5 0.8 V to 3.7 V (Note 3) 4 ns 8 ns 6 CL = 50 pF 7 (Note 1) 15 ns CL = 50 pF 8 ns 8 (Note 1) 15 ns 9 10 CL = 50 pF 8 ns (Note 1) 15 ns 11 8 ns 12 CL = 50 pF 12a CL = 50 pF 10 ns 13 (Note 1) 15 ns 8 ns 14 CL = 50 pF 14f 15 ns 15 7 ns 7 ns 16 19 7 ns 7 ns 20 21 7 ns 22 7 ns 23 7 ns 24 7 ns 25 17 ns 26 17 ns 27 (Note 2) 7 ns 28 (Note 2) 7 ns (Note 2) 7 ns 29 30 (Note 2) 7 ns Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Min time is not 100% tested. 16 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 40 MHz VCC = 5.0 V ± 5%; TCASE = 0°C to +100°C (Am386SX only) Symbol Parameter Description Operating Frequency CLK2 Period CLK2 High Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A23–A1 Valid Delay A23–A1 Float Delay BHE, BLE, LOCK Valid Delay BHE, BLE, LOCK Float Delay M/IO, D/C, W/R, ADS Valid Delay W/R, M/IO, D/C, ADS Float Delay D15–D0 Write Data Valid Delay D15–D0 Write Data Hold Time D15–D0 Write Data Float Delay HLDA Valid Delay HLDA Float Delay NA Setup Time NA Hold Time READY Setup Time READY Hold Time D15–D0 Read Data Setup Time D15–D0 Read Data Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI, INTR Setup Time NMI, INTR Hold Time PEREQ, ERROR , BUSY, FLT Setup Time PEREQ, ERROR , BUSY, FLT Hold Time Notes Half CLK2 frequency Ref. Figures Final Min Max Unit 2 40 MHz 12.5 250 ns 4.5 ns 4.5 ns 4 ns 4 ns 4 13 ns 4 20 ns 4 13 ns 4 20 ns 4 13 ns 4 20 ns 7 18 ns 2 ns 4 17 ns 4 17 ns 4 17 ns 5 ns 2 ns 7 ns 4 ns 4 ns 3 ns 4 ns 2 ns 4 ns 2 ns 5 ns 5 ns 5 ns 4 ns 1 5 2 at 2.7 V 5 3 at 0.8 V 5 4 2.7 V to 0.8 V (Note 3) 5 5 0.8 V to 2.7 V (Note 3) 5 6 CL = 50 pF 8 7 (Note 1) 15 8 CL = 50 pF 8 9 (Note 1) 15 10 CL = 50 pF 8 11 (Note 1) 15 12 CL = 50 pF (Note 4) 8 12a CL = 50 pF 10 13 (Note 1) 15 14 CL = 50 pF 15 14f 15 15 7 16 7 19 7 20 7 21 7 22 7 23 7 24 7 25 17 26 17 27 (Note 2) 7 28 (Note 2) 7 29 (Note 2) 7 30 (Note 2) 7 Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Min time is not 100% tested. Am386SX/SXL/SXLV Microprocessors Data Sheet 17 FINAL t1 t2 VIHC CLK2 2.0 V 0.8 V t5 t3 t4 Figure 3. CLK2 Timing (Am386SXLV 25 MHz) t1 t2a t2b VCC – 0.8 V CLK2 2.0 V 0.8 V t5 t3a t3b t4 16305C–004 15022B-031 Figure 4. CLK2 Timing (Am386SX/SXL 25 and 33 MHz) t1 t2 VCC – 0.8 V CLK2 2.0 V 0.8 V t5 t3 t4 Figure 5. CLK2 Timing (Am386SX 40 MHz) Am386SX/SXL/SXLV CPU Output 15022B-031a CL 15022B–032 Figure 6. AC Test Circuit 18 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL SWITCHING WAVEFORMS Tx φ2 φ1 Tx φ2 φ1 Tx CLK2 t19, t19s* READY, SMIRDY* t23 HOLD t21 D15–D0 (Inputs) t29 BUSY, ERROR , IIBEN*, PEREQ, FLT t15 NA t27, t27s* SMI*, INTR, NMI t28, t28s* t16 t30 t22 t24 t20, t20s* * – On Am386SXLV only Figure 7. Input Setup and Hold Timing Am386SX/SXL/SXLV Microprocessors Data Sheet 19 FINAL φ2 CLK2 t8 BHE+, BLE+ BE3–BE0*, LOCK W/R, M/IO, D/C, ADS, SMIADS* Valid n t10, t10s* φ1 Tx φ2 φ1 Min Max Valid n+1 Min Valid n t6 Min A23–A1 Valid n t12 D15–D0 (Outputs) Valid n t31 SMI* Valid n Max Valid n+1 Max Valid n+1 Min Max Valid n+1 Min Max Valid n+1 HLDA+ + – On Am386SX/SXL only * – On Am386SXLV only Figure 8. Output Valid Delay Timing 20 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL T1 φ1 φ2 CLK2 W/R t12 Min Max D15–D0 Valid n 13605C–007 Figure 9. Write Data Valid Delay Timing T1 φ1 CLK2 φ2 W/R Min t12a D15–D0 Valid n 16305C–008 Figure 10. Write Data Hold Timing Am386SX/SXL/SXLV Microprocessors Data Sheet 21 FINAL Reset ≥ 15 CLK2 duration if not going to request self-test. ≥ 80 CLK2 duration before requesting self-test. Internal Initialization Cycle 1 Non-Pipelined (Read) T1 T2 * * * If self-test is performed, add (220) + 60* to these numbers. 1 2 3 17 18 19 395 396 397 398 * CLK2 * Approximately Reset φ2 φ1 φ2 CLK (Internal) No self-test BUSY (Note 1) Low to begin self-test (Note 2) ERROR BHE, BLE, W/R, M/IO, HLDA A23–A1, D/C, LOCK Up to 30 CLK2 ADS High During Reset Up to 30 CLK2 Low Up to 30 CLK2 High During Reset Valid 1 During Reset Valid 1 Asserted to indicate 387DX math coprocessor protocol Negated to allow sensing of a 387DX math coprocessor φ1 φ 2 φ1 φ 2 φ1 φ 2 NA READY D15–D0 SMI (Floating) Notes: 1. BUSY should be held stable for eight CLK2 periods before and after the CLK2 period in which the RESET falling edge occurs. 2. If self-test is requested, the Am386SXLV microprocessor outputs remain in their reset state as shown here. 16305C–009 Figure 11. Bus Activity from Reset Until First Code Fetch (Am386SXLV Only) 22 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL φ1 CLK2 FLT Control Data Address Reset SMI Valid Valid Valid Valid φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 φ1 Figure 12. Entering and Exiting FLT (Am386SXLV Only) 16306B–008 φ1 CLK2 φ1 φ1 φ1 φ1 φ1 φ1 SMM in progress SMI Drive released by CPU SMIADS System may initiate another SMI when necessary* CPU driving SMI System control of SMI *Once initiated, the system must hold SMI Low until the first SMIADS. At this time, the system cannot drive SMI until three CLK2 cycles after the CPU drives SMI High. (The CPU will drive SMI High for two CLK2 cycles. The additional clock allows the CPU to completely release SMI and prevents any driver overlap.) Figure 13. Initiating and Exiting SMM (Am386SXLV Only) 16306B–011 φ2 CLK2 SMM in progress φ2 SMI RESET CPU drives SMI High for two CLK2 cycles 6–8 clocks after RESET is asserted. Figure 14. RESET and SMI (Am386SXLV Only) 16306B–010 Am386SX/SXL/SXLV Microprocessors Data Sheet 23 FINAL Cycle 0 φ2 CLK2 t9 BHE, BLE, LOCK t11, t11s* W/R, M/IO, D/C, ADS, SMIADS* Min Min φ1 Cycle 1 Th φ2 φ1 Cycle 2 Ti or T1 φ 2 Max t8 Min Max (High Z) t10, t10s* Max (High Z) t7 t6 Min Max Min Max Min Max A23–A1 (High Z) t13 t12 Min Max Min Max D15–D0 (High Z) t13—Also applies to data float when write cycle is followed by read or idle t14f Min Max t14 Min Max HLDA SMI* Valid 0 Min Valid 1 Max Valid 2 t31 * – On Am386SXLV only Figure 15. Output Float Delay and HLDA and SMI* Valid Delay Timing 24 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL φ2 CLK2 t9 BHE, BLE, LOCK t11, t11s W/R, M/IO, D/C, ADS, SMIADS φ1 Th φ2 φ1 Ti or T1 φ 2 Min Max t8 Min Max (High Z) t10, t10s Min Max (High Z) t7 t6 Min Max Min Max Min Max A23–A1 (High Z) t13 t12 Min Max Min Max D15–D0 (High Z) t14f HLDA Min Max t14 Min Max (High Z) t32 SMI Min Max (High Z) t31 Min Max 16305C–012 Figure 16. Output Float Delay Entering and Exiting FLT (Am386SXLV Only) RESET φ 2 or φ 1 CLK2 t26 Initialization Sequence φ 2 or φ 1 φ2 φ1 RESET t25 The second internal processor phase following RESET High-to-Low transition (provided t25 and t26 are met) is φ2. 15021B–084 Figure 17. RESET Setup and Hold Timing and Internal Phase Am386SX/SXL/SXLV Microprocessors Data Sheet 25 FINAL nom + 6 nom + 3 nom Output Valid Delay (ns) nom –3 nom –6 nom –9 50 75 100 125 CL (picofarads) 150 Note: This graph will not be linear outside the CL range shown. 15021B–079 Figure 18. Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (CL =120 pF) nom + 9 nom + 6 nom + 3 Output Valid Delay (ns) nom nom –3 nom –6 75 100 125 CL (picofarads) 150 Note: This graph will not be linear outside the CL range shown. 15021B–080 Figure 19. Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (CL =75 pF) 26 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL nom + 9 nom + 6 Output Valid Delay (ns) nom + 3 nom nom –3 50 75 100 125 CL (picofarads) 150 Note: This graph will not be linear outside the CL range shown. 15021B–081 Figure 20. Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (CL =50 pF) 8 6 Rise Time (ns) 0.8 V – 2.0 V 4 2 8 50 75 100 125 CL (picofarads) 150 Note: This graph will not be linear outside the CL range shown. 15021B–082 Figure 21. Typical Output Rise Time Versus Load Capacitance at Maximum Operating Temperature Am386SX/SXL/SXLV Microprocessors Data Sheet 27 FINAL DIFFERENCES BETWEEN THE Am386SX/SXL/SXLV AND Am386DX/DXL CPU The following are the major differences between the Am386SX/SXL/SXLV and the Am386DX/DXL CPU. For brevity, throughout this section the Am386SX/SXL/ SXLV CPU is referred to as the SX CPU, and the Am386DX/DXL CPU is referred to as the DX CPU. s The SX CPU generates byte selects on BHE and BLE (like the 8086 and 80286) to distinguish the upper and lower bytes on its 16-bit data bus. The DX CPU uses four byte selects, BE3–BE0, to distinguish between the different bytes on its 32-bit bus. s The SX CPU has no bus sizing option. The DX CPU can select between either a 32-bit bus or a 16-bit bus by use of the BS16 input. The SX CPU has a 16-bit bus size. s The NA pin operation in the SX CPU is identical to that of the NA pin on the DX CPU with one exception: the DX CPU NA pin cannot be activated on 16bit bus cycles (where BS16 is Low in the DX CPU case), whereas NA can be activated on any SX CPU bus cycle. s The contents of all SX CPU registers at reset are identical to the contents of the DX CPU registers at reset, except for the DX register. The DX register contains a component-stepping identifier at reset, that is: – In the DX CPU, after reset: DH = 3 indicates DX CPU DI = revision number – In the SX CPU, after reset: DH = 23H indicates SX CPU DL = revision number s The DX CPU uses A31 and M/IO as selects for the math coprocessor. The SX CPU uses A23 and M/IO as selects. s The DX CPU prefetch unit fetches code in four-byte units. The SX CPU prefetch unit reads two bytes as one unit (like the 80286). In BS16 mode, the DX CPU takes two consecutive bus cycles to complete a prefetch request. If there is a data read or write request after the prefetch starts, the DX CPU will fetch all four bytes before addressing the new request. s Both the DX CPU and SX CPU have the same logical address space. The only difference is that the DX CPU has a 32-bit physical address space and the SX CPU has a 24-bit physical address space. The SX CPU has a physical memory address space of up to 16 Mbyte instead of the 4 Gbyte available to the DX CPU. Therefore, in SX CPU systems, the operating system must be aware of this physical memory limit and should allocate memory for applications programs within this limit. If a DX CPU system uses only the lower 16 Mbyte of physical address, then there will be no extra effort required to migrate DX CPU software to the SX CPU. Any application which uses more than 16 Mbyte of memory can run on the SX CPU, if the operating system utilizes the SX CPU’s paging mechanism. In spite of this difference in physical address space, the SX CPU and the DX CPU can run the same operating systems and applications within their respective physical memory constraints. s The SX CPU has an input called FLT, which threestates all bi-directional and output pins, including HLDA, when asserted. It is used with ON-Circuit Emulation (ONCE). 28 Am386SX/SXL/SXLV Microprocessors Data Sheet FINAL PACKAGE THERMAL SPECIFICATIONS The Am386SX/SXL/SXLV processors are specified for operation when TCASE (the case temperature) is within the range of 0°C to +100°C for commercial parts, and –40°C to +100°C for industrial parts. TCASE can be measured in any environment to determine whether the Am386SX/SXL/SXLV processors are within the specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. The ambient temperature (TA) is guaranteed as long as TCASE is not violated. The ambient temperature can be calculated from θJC and θJA and from these equations: TJ = TCASE + P • θJC TA = TJ – P • θJA TCASE = TA + P • [θJA – θJC] where: TJ, TA, TCASE = Junction, Ambient, and Case Temperature = Junction-to-Case and Junction-to-Ambient θJC, θJA Thermal Resistance, respectively P = Maximum Power Consumption In the 100-lead PQFP package, θJA=45.0 and θJC=11.0. ELECTRICAL SPECIFICATIONS The Am386SX/SXL/SXLV CPU has modest power requirements. However, its high clock frequency and 47 output buffers (address, data, control, and HLDA) can cause power surges as multiple output buffers drive new signal levels simultaneously. For clean on-chip power distribution at high frequency, 14 V CC a nd 18 V SS pins separately feed functional units of the Am386SX/SXL/SXLV CPU. Power and ground connections must be made to all external VCC and VSS pins of the Am386SX/SXL/SXLV CPU. On the circuit board, all VCC pins should be connected on a VCC plane, and VSS pins should be connected on a GND plane. PEREQ input has an internal pull-down resistor of approximately 20 Kohms, built into the Am386SX/SXL/ SXLV CPU to keep these signals inactive when a 387SX-compatible math coprocessor is not present in the system (or temporarily removed from its socket). In typical designs, the external pull-up resistors shown in Table 1 are recommended. However, a particular design may have reason to adjust the resistor values recommended here, or alter the use of pull-up resistors in other ways. Other Connection Recommendations For reliable operation, always connect unused inputs to an appropriate signal level. NC pins should always remain unconnected. Connection of NC pins to VCC or VSS will result in component malfunction or incompatibility with future steppings of the Am386SX/SXL/SXLV CPU. Particularly when not using the interrupts or bus hold (as when first prototyping), prevent any chance of spurious activity by connecting these associated inputs to GND: Pin 40 38 4 Signal INTR NMI HOLD Power Decoupling Recommendations Liberal decoupling capacitors should be placed near the Am386SX/SXL/SXLV CPU. The Am386SX/SXL/ SXLV CPU driving its 24-bit address bus and 16-bit data bus at high frequencies can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the Am386SX/SXL/ SXLV CPU and decoupling capacitors as much as possible. Resistor Recommendations The ERROR, FLT, and BUSY inputs have internal pullup resistors of approximately 20 Kohms, and the Table 1. Pin 16 26 Signal ADS LOCK If not using address pipelining, connect pin 6 (NA ) through a pull-up in the range of 20 Kohms to VCC. Recommended Resistor Pull-Ups to VCC Pull-Up Value 20 Kohms ± 10% 20 Kohms ± 10% Purpose Lightly pull ADS inactive during Am386SX/SXL/SXLV CPU Hold Acknowledge states. Lightly pull LOCK inactive during Am386SX/SXL/ SXLV CPU Hold Acknowledge states. Am386SX/SXL/SXLV Microprocessors Data Sheet 29 FINAL PHYSICAL DIMENSIONS PQB 100 (Plastic Quad Flat Pack, Trimmed and Formed) 0.875 0.885 Pin 100 0.897 0.903 0.747 0.753 Pin 75 Pin 1 I.D. 0.747 0.753 0.875 0.885 0.897 0.903 Pin 25 Pin 50 0.008 0.012 TOP VIEW 0.010 MIN FLAT SHOULDER 0.045 X45° CHAMFER 0° MIN 7° TYP. 0.025 BASIC 0.130 0.150 0.160 0.180 SEATING PLANE 0.015 R 0.008 GAGE PLANE 0.036 0.046 0.010 7° TYP. 0.065 REF 0.60 REF BOTTOM VIEW 0.020 0.040 0°≤0≤8° END VIEW 16-038-PQB PQB100 DB90 3-6-97 lv Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 is a registered trademark; and E86 is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 30 Am386SX/SXL/SXLV Microprocessors Data Sheet