A43E06161V-75F

A43E06161 Preliminary Document Title 512K X 16 Bit X 2 Banks Synchronous DRAM Revision History Rev. No. 0.0 0.1 512K X 16 Bit X 2 Banks Synchronous DRAM History Initial issue Modify tSS from 3ns to 2ns Modify tSH from 1.5ns to 1ns Modify ICC6 from 0.5mA to 200μA Issue Date May 3, 2005 July 31, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.1) AMIC Technology, Corp. A43E06161 Preliminary Features Low power supply - VDD: 1.8V - VDDQ: 1.8V LVCMOS compatible with multiplexed address Dual banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Deep Power Down Mode Clock Frequency: 105MHz @ CL=3 (-95) 133MHz @ CL=3 (-75) 512K X 16 Bit X 2 Banks Synchronous DRAM Industrial operating temperature range: -40ºC to +85ºC for –U Pb-Free type for -F Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) Available in 50-pin TSOP(II) package General Description The A43E06161 is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 X 524,288 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Configuration TSOP (II) NC/RFU VDDQ VDDQ UDQM VSSQ DQ13 DQ12 DQ11 DQ10 VSSQ DQ15 DQ14 CKE VSS DQ9 DQ8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 A43E06161V 1 VDD 2 DQ0 3 DQ1 4 VSSQ 5 DQ2 6 DQ3 7 VDDQ 8 DQ4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DQ7 CS BA A10/AP CAS RAS LDQM VSSQ VDDQ VDD A0 A1 A2 DQ5 DQ6 WE A3 PRELIMINARY (July, 2005, Version 0.1) 1 AMIC Technology, Corp. VSS CLK NC A9 A8 A7 A6 A5 A4 A43E06161 Block Diagram LWE I/O Control Data Input Register Bank Select LDQM Row Buffer Refresh Counter Row Decoder Output Buffer Sense AMP 512K X 16 CLK Address Register 512K X 16 DQi LCBR LRAS Column Buffer ADD Column Decoder Latency & Burst Length LRAS LCAS LRAS LCBR LWE LWCBR Timing Register Programming Register LDQM CLK CKE CS RAS CAS WE L(U)DQM PRELIMINARY (July, 2005, Version 0.1) 2 AMIC Technology, Corp. A43E06161 Pin Descriptions Symbol Name Description CLK CS System Clock Chip Select Active on the positive going edge to sample all inputs. Disables or Enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE Clock Enable CKE should be enabled at least one clock + tss prior to new command. Disable input buffers for power down in standby. Row / Column addresses are multiplexed on the same pins. A0~A10/AP Address Row address : RA0~RA10, Column address: CA0~CA7 Selects bank to be activated during row address latch time. BA Bank Select Address Selects band for read/write during column address latch time. Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection RAS Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +1.7V~1.95V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. CAS WE L(U)DQM DQ0-15 VDD/VSS VDDQ/VSSQ NC/RFU PRELIMINARY (July, 2005, Version 0.1) 3 AMIC Technology, Corp. A43E06161 Absolute Maximum Ratings* Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +2.6V Storage Temperature (TSTG) . . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . 0.8W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA *Comments Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Capacitance (TA=25°C, f=1MHz) Parameter Symbol Condition Min Typ Max Unit Input Capacitance CI1 CI2 A0 to A10, BA CLK, CKE, CS , RAS , CAS , WE , UDQM, LDQM DQ0 to DQ15 2.0 2.0 4.0 4.0 pF pF Data Input/Output Capacitance CI/O 3.5 6.0 pF DC Electrical Characteristics Recommend operating conditions (Voltage referenced to VSS = 0V, TA = -25ºC to +70ºC or -40ºC to +85ºC) Parameter Symbol Min Typ Max Unit Note Supply Voltage DQ Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Output Loading Condition VDD VDDQ VIH VIL VOH VOL IIL IOL 1.7 1.7 0.8 x VDDQ -0.3 VDDQ-0.2 -1 -1.5 1.8 1.8 0 - 1.95 1.95 VDD+0.3 0.3 0.2 1 1.5 See Figure 1 V V V V V V µA µA Note 1 IOH = -0.1mA IOL = 0.1mA Note 2 Note 3 Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns). 2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V 3. Dout is disabled, 0V ≤ Vout ≤ VDD PRELIMINARY (July, 2005, Version 0.1) 4 AMIC Technology, Corp. A43E06161 Decoupling Capacitance Guide Line Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit µF µF Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ CDC1 CDC2 0.1 + 0.01 0.1 + 0.01 Note: 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. DC Electrical Characteristics (Recommended operating condition unless otherwise noted, TA = 0 to 70°C or -40ºC to +85ºC) Symbol Parameter Test Conditions CAS Latency Speed Unit Notes -75 20 0.3 0.1 5 -95 mA 1 Icc1 Icc2 P Icc2 PS ICC2N Operating Current (One Bank Active) Precharge Standby Current in powerdown mode Precharge Standby Current in non power-down mode Active Standby Current in powerdown mode Active Standby current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Self Refresh Current Deep Power Down Current Burst Length = 1 tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA CKE ≤ VIL(max), tCC = 15ns CKL ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable. CKE ≤ VIL(max), tCC = 15ns mA mA 2 ICC2NS ICC3 P 2 mA ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 10 mA ICC4 IOL = 0mA, Page Burst All bank Activated, tCCD = tCCD (min) tRC ≥ tRC (min) CKE ≤ 0.2V CKE ≤ 0.2V 20 mA 1 ICC5 ICC6 ICC7 20 200 10 mA µA µA 2 Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min). 2. Refresh period is 32ms. Addresses are changed only one time during tCC(min). PRELIMINARY (July, 2005, Version 0.1) 5 AMIC Technology, Corp. A43E06161 AC Operating Test Conditions (VDD = 1.8V ±0.3V, TA = 0°C to +70°C or -40ºC to +85ºC) Parameter Value Unit AC input levels Input timing measurement reference level Input rise and all time (See note3) Output timing measurement reference level Output load condition 1.8V 13.9Ω Output 0.9 x VDDQ / 0.2 0.5 x VDDQ tr / tf = 1 / 1 0.5 x VDDQ See Fig.2 V V ns V VOH(DC) = VDDQ-0.2V, IOH = -0.1mA VOL(DC) = 0.2V, IOL = 0.1mA ZO=50Ω VTT = 0.5V x VDDQ 50Ω OUTPUT 10.6Ω 30pF 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit AC Characteristics (AC operating conditions unless otherwise noted) Symbol Parameter Min -75 Max Min -95 Max Unit Note tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ CLK cycle time CLK to valid Output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 7.5 12 2.5 3 3 3 3 2 2 1 1 1000 6 9 6 8 9.5 15 2.5 3.5 3.5 3.5 3.5 2 2 1 1 - 1000 7 8 7 8 ns ns ns ns ns ns ns ns ns 1 1,2 2 3 3 3 3 2 CL=3 CL=2 - CL=CAS Latency. *All AC parameters are measured from half to half. Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. PRELIMINARY (July, 2005, Version 0.1) 6 AMIC Technology, Corp. A43E06161 Operating AC Parameter (AC operating conditions unless otherwise noted) Version Symbol Parameter -75 -95 Unit Note tRRD(min) tRCD(min) tRP(min) tRAS(min) Row active to row active delay RAS to CAS delay Row precharge time 2 27 27 57 2 28.5 28.5 57 100 CLK ns ns ns µs 1 1 1 1 Row active time tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) Row cycle time Last data in new col. Address delay Last data in row precharge Last data in to burst stop Col. Address to col. Address delay 84 7.5 2 7.5 7.5 85.5 8.5 2 9.5 9.5 ns ns CLK ns ns 1 2 1, 2 2 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. PRELIMINARY (July, 2005, Version 0.1) 7 AMIC Technology, Corp. A43E06161 Simplified Truth Table Command CKEn-1 CKEn CS RAS CAS WE L H H X H H L L L H X X H X V X H X L X DQM BA A10/ AP A9~A0 Notes Register Refresh Mode Register Set Auto Refresh Self Refresh Entry Exit H H L H H H H X H L H X X X X X L H L H L L L H L L L L L L H X L H L H L H L X L L H X L H H H L H X X H X V X X H X H X L L H X H L L H H H X X H X V X H X H X X X X X X X X V V V V OP CODE X X Row Addr. L H L H X L H X X Column Addr. Column Addr. 1,2 3 3 3 3 4 4 4,5 4 4,5 Bank Active & Row Addr. Read & Auto Precharge Disable Column Addr. Auto Precharge Enable Write & Auto Precharge Disable Column Addr. Auto Precharge Enable Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Deep Power Down Entry Deep Power Down Exit H H L H L H H H L X X X X X X X V X X X X X X X 7 6 7 X L H (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note : 1. OP Code : Operand Code A0~A10/AP,BA : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without Row precharge command is meant by “Auto”. Auto/Self refresh can be issued only at both precharge state. 4. BA : Bank select address. If “Low” at read, write, Row active and precharge, bank A is selected. If “High” at read, write, Row active and precharge, bank B is selected. If A10/AP is “High” at Row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read write command cannot be issued. Another bank read write command can be issued at every burst length. 6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2) 7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory. PRELIMINARY (July, 2005, Version 0.1) 8 AMIC Technology, Corp. A43E06161 Mode Register Filed Table to Program Modes Register Programmed with MRS Address BA A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function RFU RFU (Note 2) W.B.L TM CAS Latency BT Burst Length (Note 1) Test Mode A8 A7 Type A6 CAS Latency A5 A4 Latency Burst Type A3 Type A2 A1 Burst Length A0 BT=0 BT=1 0 0 1 1 0 1 0 1 Mode Register Set Vendor Use Only 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 3 Reserved Reserved Reserved Reserved 0 1 Sequential Interleave 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved 256(Full) Reserved Reserved 4 8 Reserved Reserved Reserved Reserved (Note 3) Write Burst Length A9 Length 0 1 Burst Single Bit Power Up Sequence 1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed. The device is now ready for normal operation. Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle. 2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled. 3. The full column burst (256bit) is available only at Sequential mode of burst type. PRELIMINARY (July, 2005, Version 0.1) 9 AMIC Technology, Corp. A43E06161 Burst Sequence (Burst Length = 4) Initial address Sequential A1 A0 Interleave 0 0 1 1 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 Burst Sequence (Burst Length = 8) Initial address Sequential A2 A1 A0 Interleave 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 PRELIMINARY (July, 2005, Version 0.1) 10 AMIC Technology, Corp. A43E06161 Device Operations Clock (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications. Clock Enable (CLK) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least “tSS + 1 CLOCK” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. Bank Select (BA) 1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply. The clock signal must also be asserted at the same time. 2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition. 3. Both banks must be precharged now. 4. Perform a minimum of 2 Auto refresh cycles to stabilize the internal circuitry. 5. Perform a MODE REGISTER SET cycle to program the CAS latency, burst length and burst type as the default value of mode register is undefined. At the end of one clock cycle from the mode register set cycle, the device is ready for operation. When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. cf.) Sequence of 4 & 5 may be changed. Mode Register Set (MRS) This SDRAM is organized as two independent banks of 524,288 words X 16 bits memory arrays. The BA inputs is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. When BA is asserted low, bank A is selected. When BA is asserted high, bank B is selected. The bank select BA is latched at bank activate, read, write mode register set and precharge operations. Address Input (A0 ~ A10/AP) The 19 address bits required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0~A10/AP). The 11 bit row address is latched along with RAS and BA during bank activate command. The 8 bit column address is latched along with CAS , WE and BA during read or write command. NOP and Device Deselect The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A10/AP and BA in the same cycle as CS , RAS , CAS , WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A10/AP and BA are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A10/AP and BA must be set to low for normal SDRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies. Bank Activate When RAS , CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS and WE , and all the address inputs are ignored. Power-Up The following sequence is recommended for POWER UP The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the PRELIMINARY (July, 2005, Version 0.1) 11 AMIC Technology, Corp. A43E06161 activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification. Burst Read DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Precharge The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. Burst Write The precharge operation is performed on an active bank by asserting low on CS , RAS , WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank activate command in the desired bank. “tRP” is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing “tRP” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank has to be precharged within tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state. Auto Precharge The burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank “tRDL” after the last data input to be written into the active row. See DQM OPERATION also. DQM Operation The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and “tRP” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write command is issued with low on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. Both Banks Precharge Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS and WE with high on A10/AP after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, both banks are in idle state. Auto Refresh The storage cells of SDRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and The DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from WE . The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified 12 PRELIMINARY (July, 2005, Version 0.1) AMIC Technology, Corp. A43E06161 by “tRC(min)”. The minimum number of clock cycles required can be calculated by driving “tRC” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms. Self Refresh WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of “tRC” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 2048 auto refresh cycles immediately after exiting self refresh. Deep Power Down Mode The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on The Deep Power Down Mode is an unique function on Low Power SDRAMs with very low standby currents. All internal voltage generators inside the Low Power SDRAMs are stopped and all memory data will be lost in this mode. To enter the Deep Power Down Mode all banks must be precharged and the necessary Precharged Delay tRP must occur. PRELIMINARY (July, 2005, Version 0.1) 13 AMIC Technology, Corp. A43E06161 Basic feature And Function Descriptions 1. CLOCK Suspend 1) Click Suspended During Write (BL=4) 2) Clock Suspended During Read (BL=4) CLK CMD CKE Masked by CKE Internal CLK Masked by CKE WR RD DQ(CL2) DQ(CL3) D0 D0 D1 D1 D2 D2 Not Written D3 D3 Q0 Q1 Q0 Q2 Q1 Q3 Q2 Suspended Dout Q3 Note: CLK to CLK disable/enable=1 clock 2. DQM Operation 1) Write Mask (BL=4) CLK CMD WR RD 2) Read Mask (BL=4) DQM Masked by CKE DQ(CL2) DQ(CL3) D0 D0 D1 D1 D3 D3 Q0 Hi-Z Hi-Z Masked by CKE Q1 Q1 Q3 Q2 Q3 DQM to Data-in Mask = 0CLK DQM to Data-out Mask = 2 2) Read Mask (BL=4) CLK CMD CKE RD DQM DQ(CL2) DQ(CL3) Q0 Hi-Z Hi-Z Q2 Q1 Hi-Z Hi-Z Q4 Q3 Hi-Z Hi-Z Q6 Q5 Q7 Q6 Q8 Q7 * Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. 2. DQM masks both data-in and data-out. PRELIMINARY (July, 2005, Version 0.1) 14 AMIC Technology, Corp. A43E06161 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4)Note 1 CLK CMD ADD DQ(CL2) DQ(CL3) tCCD Note2 RD A RD B QA0 QB0 QA0 QB1 QB2 QB0 QB1 QB3 QB2 QB3 2) Write interrupted by Write (BL =2) CLK CMD WR WR Note2 3) Write interrupted by Read (BL =2) WR tCCD A DB1 DQ(CL2) DQ(CL3) DA0 DA0 tCDL Note3 RD Note2 tCCD ADD DQ A DA0 B B QB0 QB1 QB0 QB1 DB0 tCDL Note3 Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst. By “ CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (= 1CLK). PRELIMINARY (July, 2005, Version 0.1) 15 AMIC Technology, Corp. A43E06161 4. CAS Interrupt (II) : Read Interrupted Write & DQM (1) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD RD D0 D1 WR D2 D3 RD WR DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (2) CL=3, BL=4 CLK RD RD Hi-Z D0 D1 WR D2 D3 Hi-Z D0 D1 WR D2 D3 Q0 Hi-Z Note 1 D0 D1 D2 D3 i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM RD WR D0 RD D1 WR D2 D3 D0 RD D1 WR D2 D3 D0 WR RD D1 WR D2 D3 Hi-Z DQ v) CMD DQM DQ Q0 RD D0 D1 WR D2 D3 Hi-Z Note 2 D0 D1 D2 D3 * Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. 2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. PRELIMINARY (July, 2005, Version 0.1) 16 AMIC Technology, Corp. A43E06161 5. Write Interrupted by Precharge & DQM CLK CMD DQM DQ D0 D1 D2 D3 Masked by DQM Note 2 WR PRE Note 1 Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. 6. Precharge 1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3 tRDL 2) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 PRE Q2 Q1 Q3 Q2 Q3 PRE 7. Auto Precharge 1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3 Note 1 Auto Precharge Starts 2) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 Q2 Q1 Q3 Q2 Note 1 Auto Precharge Starts Q3 * Note : 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other active bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. PRELIMINARY (July, 2005, Version 0.1) 17 AMIC Technology, Corp. A43E06161 8. Burst Stop & Precharge Interrupt 1) Write Interrupted by Precharge (BL=4) CLK CMD DQM DQ D0 D1 D2 tRDL D3 Note 1 2) Write Burst Stop (BL=8) CLK WR PRE CMD WR STOP DQ D0 D1 D2 tBDL (note 2) 3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0 Note 3 1 4) Read Burst Stop (BL=4) CLK CMD DQ(CL2) Q1 2 RD STOP Q0 Q1 Q0 Note 3 1 DQ(CL3) Q1 2 9. MRS Mode Register Set CLK Note 4 CMD PRE tRP MRS ACT 1CLK Note : 1. tRDL : 2CLK, Last Data in to Row Precharge. 2. tBDL : 1CLK, Last Data in to Burst Stop Delay. 3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively. 4. PRE : Both banks precharge if necessary. MRS can be issued only at all bank precharge state. PRELIMINARY (July, 2005, Version 0.1) 18 AMIC Technology, Corp. A43E06161 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal CLK CMD Note 1 2) Power Down (=Precharge Power Down) Exit CLK tSS CKE Internal CLK RD CMD Note 2 tSS NOP ACT 11. Auto Refresh & Self Refresh Note 3 1) Auto Refresh CKE Internal CLK CMD Note 4 ~ CLK PRE AR Note 5 CMD tRP tRC Note 6 2) Self Refresh CLK Note 4 ~ ~~ CMD CKE PRE SR ~ ~ tRP tRC * Note : 1. Active power down : one or more bank active state. 2. Precharge power down : both bank precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command. During tRC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, both banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is LOW. During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state. During tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended. ~ ~ ~ ~ CMD PRELIMINARY (July, 2005, Version 0.1) 19 AMIC Technology, Corp. A43E06161 12. About Burst Type Control Basic MODE Random MODE Sequential counting Interleave counting Random column Access tCCD = 1 CLK At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around. At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of convention DRAM. 13. About Burst Length Control 1 Basic MODE 2 4 8 Special MODE BRSW At MRS A2,1,0 = “000”. At auto precharge, tRAS should not be violated. At MRS A2,1,0 = “001”. At auto precharge, tRAS should not be violated. At MRS A2,1,0 = “010” At MRS A2,1,0 = “011”. Interrupt MODE At MRS A9=”1”. Read burst = 1,2,4,8, full page/write Burst =1 At auto precharge of write, tRAS should not be violated. Before the end of burst, Row precharge command of the same bank RAS Interrupt Stops read/write burst with Row precharge. (Interrupted by Precharge) tRDL= 2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. CAS Interrupt During read/write burst with auto precharge, CAS interrupt can not be issued. PRELIMINARY (July, 2005, Version 0.1) 20 AMIC Technology, Corp. A43E06161 Power On Sequence & Auto Refresh 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High level is necessary ~ CS tRP RAS tRC ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ DQM High level is necessary ~ ~ DQ Precharge (All Banks) Auto Refresh Auto Refresh ~ ~ High-Z ~ ~ ~ ~ WE ~ ~ A10/AP ~ ~ BA ~ ~ ADDR ~ ~ ~ ~ CAS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ KEY Ra ~ ~ ~ ~ ~ ~ KEY BS KEY Ra Mode Regiser Set Row Active (A-Bank) : Don't care PRELIMINARY (July, 2005, Version 0.1) 21 AMIC Technology, Corp. A43E06161 Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1 tCH 0 CLOCK tCC CKE tRAS tRC *Note 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tCL High tSH tSS CS tRCD tSH RAS tSS tSH CAS tSS tSH ADDR tSS *Note 2 *Note 2,3 tRP tCCD tSS Ca Cb tSH *Note 2,3 *Note 2,3 *Note 4 *Note 2 Ra Cc Rb BA BS BS BS BS BS BS *Note 3 *Note 3 *Note 3 *Note 4 A10/AP Ra Rb tSH WE tSS tSS DQM tRAC tSAC DQ tSLZ tOH Qa tSS tSHZ Db tSH Qc tSH Row Active Read Write Read Precharge Row Active : Don't care PRELIMINARY (July, 2005, Version 0.1) 22 AMIC Technology, Corp. A43E06161 * Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA Active & Read/Write 0 1 Bank A Bank B 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA Operation 0 0 1 0 1 1 Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. 4. A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA Precharge 0 0 1 0 1 X Bank A Bank B Both Bank PRELIMINARY (July, 2005, Version 0.1) 23 AMIC Technology, Corp. A43E06161 Read & Write Cycle at Same Bank @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE tRC CS tRCD *Note 1 High RAS *Note 2 CAS ADDR Ra Ca0 Rb Cb0 BA A10/AP Ra Rb WE DQM tOH DQ (CL = 2) Qa0 tRAC *Note 3 tSAC tOH DQ (CL = 3) Qa0 tRAC *Note 3 tSAC Qa1 Qa2 Qa3 *Note 4 Db0 Db1 Db2 tRDL Db3 Qa1 Qa2 Qa3 *Note 4 Db0 Db1 Db2 Db3 tSHZ tRDL tSHZ Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row enters precharge. Last valid output will be Hi-Z after tSHZ from the clock. 3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC 4. Output will be Hi-Z after the end of burst. (1,2,4 & 8) At Full page bit burst, burst is wrap-around. PRELIMINARY (July, 2005, Version 0.1) 24 AMIC Technology, Corp. A43E06161 Page Read & Write Cycle at Same Bank @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS tRCD RAS *Note 2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra tCDL tRDL WE *Note 2 *Note1 DQM *Note3 DQ (CL=2) Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 DQ (CL=3) Qa0 Qa1 Qb0 Dc0 Dc1 Dd0 Dd1 Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. PRELIMINARY (July, 2005, Version 0.1) 25 AMIC Technology, Corp. A43E06161 Page Read Cycle at Different Bank @Burst Length = 4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE *Note 1 High CS RAS *Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe BA A10/AP RAa RBb WE DQM DQ (CL=2) QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 DQ (CL=3) QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Row Active (A-Bank) Row Active (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) : Don't care * Note : 1. CS can be don’t care when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same. PRELIMINARY (July, 2005, Version 0.1) 26 AMIC Technology, Corp. A43E06161 Page Write Cycle at Different Bank @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS *Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tRDL tCDL WE *Note 1 DQM Row Active (B-Bank) Row Active with (A-Bank) Write (A-Bank) Write (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) : Don't care * Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same. PRELIMINARY (July, 2005, Version 0.1) 27 AMIC Technology, Corp. A43E06161 Read & Write Cycle at Different Bank @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA A10/AP RAa RBb RAc tCDL *Note 1 WE DQM DQ (CL=2) QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 DQ (CL=3) QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (B-Bank) Read (A-Bank) Row Active (B-Bank) Row Active (A-Bank) : Don't care * Note : tCDL should be met to complete write. PRELIMINARY (July, 2005, Version 0.1) 28 AMIC Technology, Corp. A43E06161 Read & Write Cycle with Auto Precharge I @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa RBb CAa CBb BA A10/AP RAa RBb WE DQM DQ (CL=2) QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 DQ (CL=3) QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care *Note : tRCD should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2, BRSW mode) PRELIMINARY (July, 2005, Version 0.1) 29 AMIC Technology, Corp. A43E06161 Read & Write Cycle with Auto Precharge II @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR Ra Rb Ca Cb Ra Ca BA A10/AP Ra Rb Ra WE DQM DQ (CL=2) Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Da0 Da1 DQ (CL=3) Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Row Active (A-Bank) Read with Auto Pre Charge (A-Bank) Read without Auto Precharge (B-Bank) Auto Precharge Strart Point (A-Bank) *Note 1 Precharge (B-Bank) Row Active (A-Bank) Write with Auto Precharge (A-Bank) Row Active (B-Bank) : Don't care * Note : When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point. - Any command can not be issued at A Bank during tRP after A Bank auto precharge starts. PRELIMINARY (July, 2005, Version 0.1) 30 AMIC Technology, Corp. A43E06161 Read & Write Cycle with Auto Precharge III @Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR Ra Ca Rb Cb BA A10/AP Ra Rb WE DQM DQ (CL=2) Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 DQ (CL=3) Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Db2 Db3 * Note 1 Row Active (A-Bank) Read with Auto Preharge (A-Bank) Auto Precharge Read with Start Point Auto Precharge (B-Bank) (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care * Note : Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point PRELIMINARY (July, 2005, Version 0.1) 31 AMIC Technology, Corp. A43E06161 Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Burst Length = Full Page) 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa CAa CAb BA * Note 1 * Note 1 A10/AP RAa WE DQM * Note 2 1 1 DQ (CL=2) QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 2 2 DQ (CL=3) QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) : Don't care * Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3. Burst stop is valid at every burst length. PRELIMINARY (July, 2005, Version 0.1) 32 AMIC Technology, Corp. A43E06161 Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Burst Length = Full Page) 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS CAS ADDR RAa CAa CAb BA * Note 1 * Note 1 A10/AP RAa tBDL tRDL WE * Note 3 DQM * Note 2 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care * Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell. It is defined by AC parameter of tBDL(=1CLK). 3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL(=2CLK). DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. Burst stop is valid only at every burst length. PRELIMINARY (July, 2005, Version 0.1) 33 AMIC Technology, Corp. A43E06161 Burst Read Single Bit Write Cycle @Burst Length=2, BRSW 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE High CS RAS * Note 2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10/AP RAa RBb RAc WE DQM DQ (CL=2) DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 DQ (CL=3) DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 Row Active (A-Bank) Row Active (B-Bank) Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank) Write with Auto Precharge (B-Bank) : Don't care * Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, The next cycle starts the precharge. PRELIMINARY (July, 2005, Version 0.1) 34 AMIC Technology, Corp. A43E06161 Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS RAS CAS ADDR Ra Ca Cb Cc BA A10/AP Ra WE * Note 1 DQM DQ Qa0 Qa1 Qa2 Qa3 tSHZ Qb0 Qb1 tSHZ Dc0 Dc2 Row Active Read Clock Suspension Read Read DQM Write Write DQM Clock Suspension : Don't care * Note : DQM needed to prevent bus contention. PRELIMINARY (July, 2005, Version 0.1) 35 AMIC Technology, Corp. A43E06161 Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ ~ * Note 2 tSS CKE * Note 1 tSS tSS ~ ~ tSS Ra *Note 3 ~ ~ CS ~ ~ CAS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RAS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Ca ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ DQM ~ ~ ~ ~ WE ~ ~ ~ ~ A10/AP Ra ~ ~ ~ ~ BA ~ ~ ~ ~ ADDR ~ ~ ~ ~ ~ ~ ~ ~ DQ Qa0 Qa1 Qa2 Precharge Power-down Entry Precharge Power-down Exit Row Active Active Power-down Entry Read Precharge Active Power-down Exit : Don't care * Note : 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least “1CLK + tSS” prior to Row active command. 3. Cannot violate minimum refresh specification. (32ms) PRELIMINARY (July, 2005, Version 0.1) 36 AMIC Technology, Corp. A43E06161 Self Refresh Entry & Exit Cycle 0 CLOCK * Note 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ ~ * Note 4 * Note 1 * Note 3 tSS CS * Note 5 ~ ~ ~ ~ ~ ~ * Note 7 ~ ~ RAS ~ ~ ~ ~ ~ ~ CKE tSS tRC min. * Note 6 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ * Note 7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ DQ Hi-Z Hi-Z Self Refresh Entry Self Refresh Exit ~ ~ ~ ~ DQM ~ ~ ~ ~ WE ~ ~ ~ ~ A10/AP ~ ~ ~ ~ BA ~ ~ ~ ~ ADDR ~ ~ ~ ~ CAS * Note : TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low”. (cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit. If the system uses burst refresh. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Auto Refresh : Don't care PRELIMINARY (July, 2005, Version 0.1) 37 AMIC Technology, Corp. A43E06161 Mode Register Set Cycle Auto Refresh Cycle 0 CLOCK 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 CKE *Note 2 CS High High tRC RAS * Note 1 * Note 3 Hi-Z Hi-Z MRS New Command Auto Refresh ~ ~ DQ ~ ~ DQM ~ ~ ~ ~ WE ~ ~ ~ ~ ADDR Key Ra ~ ~ ~ ~ CAS ~ ~ ~ ~ New Command : Don't care * Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE * Note : 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. PRELIMINARY (July, 2005, Version 0.1) 38 AMIC Technology, Corp. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ A43E06161 Deep Power Down Mode Entry CLK CKE CS WE CAS RAS ADDR DQM DQ input DQ output tRP High-Z Precharge Command Normal Mode Deep Power Down Entry Deep Power Down Mode PRELIMINARY (July, 2005, Version 0.1) 39 AMIC Technology, Corp. A43E06161 Deep Power Down Mode Exit ~ ~~ ~ ~~ CLK CKE CS ~~ ~~ ~~ ~~ ~~ ~~ RAS CAS WE 200 us tRP ~~ ~~ ~~ ~~ ~~ ~~ ~ ~~ ~ ~~ tRC Deep Power Down Exit All Banks Precharge Auto Refresh Auto Refresh Mode Register Set Extended Mode Register Set New Command Accepted Here The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command: 1. Maintain NOP input conditions for a minimum of 200µs 2. Issue precharge commands for all banks of the device 3. Issue eight or more auto-refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register PRELIMINARY (July, 2005, Version 0.1) 40 AMIC Technology, Corp. A43E06161 Function Truth Table (Table 1) Current State CS H L L L RAS CAS X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L L H L WE X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L H L X X BA Address Action Note X X X BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA X X X X RA PA X OP Code X X X NOP NOP ILLEGAL Row Active; Latch Row Address NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL 2 4 5 5 2 2 CA, A10/AP ILLEGAL IDLE L L L L H L Row Active L L L L L L H L L L L L L L H L L L L L L L H L L L L L L CA,A10/AP Begin Read; Latch CA; Determine AP CA,A10/AP Begin Write; Latch CA; Determine AP RA PA X X X X CA,AP RA PA X X X X ILLEGAL Precharge ILLEGAL NOP(Continue Burst to End →Row Active) NOP(Continue Burst to End →Row Active) Term burst →Row Active 3 3 2 3 Term burst; Begin Write; Latch CA; Determine AP ILLEGAL Term Burst; Precharge timing for Reads ILLEGAL NOP(Continue Burst to End→Row Active) NOP(Continue Burst to End→Row Active) ILLEGAL 3 3 2 3 2 Read CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP Write CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP RA A10/AP X X X X ILLEGAL Term Burst; Precharge timing for Writes ILLEGAL NOP(Continue Burst to End→Precharge) NOP(Continue Burst to End→Precharge) ILLEGAL Read with Auto Precharge CA,A10/AP ILLEGAL CA,A10/AP ILLEGAL RA, PA X ILLEGAL ILLEGAL 2 2 2 PRELIMINARY (July, 2005, Version 0.1) 41 AMIC Technology, Corp. A43E06161 Function Truth Table (Table 1, Continued) Current State CS H L RAS CAS X H H H H L L X H H H L L L X H H H L L L X H H L L X H H L L H L X H H L H H L X H H L H H L X H L H L WE X H L H L X X X H L X H L X X H L X H L X X X X X X BA Address Action Note X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X X X X X X NOP(Continue Burst to End→Precharge) NOP(Continue Burst to End→Precharge) ILLEGAL 2 2 2 Write with Auto Precharge L L L L L H L L CA,A10/AP ILLEGAL CA,A10/AP ILLEGAL RA, PA X X X X RA PA X X X X RA PA X X X X X X ILLEGAL ILLEGAL NOP→Idle after tRP NOP→Idle after tRP ILLEGAL Precharge L L L L H L L L L L L H L CA,A10/AP ILLEGAL ILLEGAL NOP→Idle after tRP ILLEGAL NOP→Row Active after tRCD NOP→Row Active after tRCD ILLEGAL 2 2 2 4 Row Activating CA,A10/AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP→Idle after tRC NOP→Idle after tRC ILLEGAL ILLEGAL ILLEGAL 2 2 2 2 Refreshing L L L Abbreviations RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address AP = Auto Precharge PA = Precharge All Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA). 5. Illegal if any banks is not idle. PRELIMINARY (July, 2005, Version 0.1) 42 AMIC Technology, Corp. A43E06161 Function Truth Table for CKE (Table 2) Current State CKE n-1 H CKE n X CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS CAS X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X X H L X X X X X Address Action Note X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh→ABI after tRC Exit Self Refresh→ABI after tRC ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down→ABI Exit Power Down→ABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 9 9 8 8 8 7 7 6 6 L L Self Refresh L L L L H Both Bank Precharge Power Down L L L L L L H H H All Banks Idle H H H H H L Any State Other than Listed Above H H L L H H H H H L X H H H H H L H L L L L L L L L H L H L Abbreviations : ABI = All Banks Idle Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to high transition to issue a new command. 7. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time “tSS + one clock” must be satisfied before any command other than exit. 8. Power-down and self refresh can be entered only from the all banks idle state. 9. Must be a legal command. PRELIMINARY (July, 2005, Version 0.1) 43 AMIC Technology, Corp. A43E06161 Ordering Information Part No. Min. Cycle Time (ns) Max. Clock Frequency (MHz) Access Time Package A43E06161V-75 A43E06161V-75F A43E06161V-75U A43E06161V-75UF A43E06161V-95 A43E06161V-95F A43E06161V-95U A43E06161V-95UF 7.5 7.5 7.5 7.5 9.5 9.5 9.5 9.5 133 133 133 133 105 105 105 105 6 ns 6 ns 6 ns 6 ns 7 ns 7 ns 7 ns 7 ns 50 TSOP (II) 50 Pb-Free TSOP (II) 50 TSOP (II) 50 Pb-Free TSOP (II) 50 TSOP (II) 50 Pb-Free TSOP (II) 50 TSOP (II) 50 Pb-Free TSOP (II) Note: -U is for industrial operating temperature range -40ºC to +85ºC. PRELIMINARY (July, 2005, Version 0.1) 44 AMIC Technology, Corp. A43E06161 Package Information TSOP 50L (Type II) Outline Dimensions unit: inches/mm Detail "A" 50 26 R0.15 REF. R0.15 REF. 0.25 E1 E θ L L1 1 D 25 Detail "A" A2 Seating Plane D b 0.1 Dimensions in inches A1 e A Dimensions in mm Min 0.05 0.95 0.30 0.12 20.855 11.56 10.06 0.40 0° Nom 1.016 20.955 11.76 10.16 0.800 0.50 Max 1.20 1.05 0.45 0.21 21.055 11.96 10.26 0.60 5° Symbol A A1 A2 b c D E E1 e L θ Min 0.002 0.037 0.012 0.005 0.821 0.455 0.396 0.016 0° Nom 0.040 0.825 0.463 0.400 0.031 0.020 - Max 0.047 0.041 0.018 0.008 0.829 0.471 0.404 0.024 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (July, 2005, Version 0.1) 45 AMIC Technology, Corp. c