AS1153-T

A S 11 5 3 / 5 5 / 5 7 / 5 8 S i n g l e / D u a l LV D S R e c e i v e r s D a ta S he e t 1 General Description The AS1153/55/57/58 are Single/Dual flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert them to LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling rates and reduced EMI emissions. The devices are guaranteed to receive data at speeds up to 260Mbps (130MHz) over controlled impedance media of approximately 100Ω. Supported transmission media are PCB traces, backplanes, and cables. The AS1155/58 are single LVDS receivers, and the AS1153/57 are dual LVDS receivers. The AS1157/58 features integrated parallel termination resistors (nominally 107Ω), which eliminate the requirement for discrete termination resistors, and reduce stub lengths. The AS1153/55 uses high impedance inputs and requires an external termination resistor when used in a point-to-point connection. The integrated Failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted. All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The devices are available in a 8-pin SOIC package. 2 Key Features ! ! ! ! ! ! ! ! ! Flow-Through Pinout Guaranteed 260Mbps Data Rate 300ps Pulse Skew (Max) Conform to ANSI TIA/EIA-644 LVDS Standards Single +3.3V Supply Operating Temperature Range: -40 to +85ºC Failsafe Circuit Integrated Termination (AS1157/58) 8-pin SOIC Package 3 Applications Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment. Figure 1. Block Diagrams AS1155/58 AS1153/57 IN1- VCC IN1- VCC IN1+ OUT1 IN1+ OUT1 N/C N/C IN2+ OUT2 N/C GND IN2- GND www.austriamicrosystems.com Revision 1.01 1 - 15 AS1153/55 Data Sheet - P i n o u t a n d P a c k a g i n g 4 Pinout and Packaging Pin Assignments Figure 2. AS1153/55 and AS1157/58 Pin Assignments (Top View) IN1IN1+ N/C N/C 1 2 8 7 VCC OUT1 N/C GND IN1IN1+ 1 2 8 7 VCC OUT1 OUT2 GND AS1155/58 3 4 6 5 IN2+ 3 IN24 AS1153/57 6 5 Pin Descriptions Table 1. AS1153/55 and AS1157/58 Pin Descriptions Pin Number AS1155/58 1 2 AS1153/57 1 2 3 4 5 7 8 3, 4, 6 5 6 7 8 Pin Name IN1IN1+ IN2+ IN2GND OUT2 OUT1 VCC N/C Description Inverting Differential Receiver Input Noninverting Differential Receiver Input Noninverting Differential Receiver Input Inverting Differential Receiver Input Ground LVCMOS/LVTTL Receiver Output LVCMOS/LVTTL Receiver Output Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. Not connected www.austriamicrosystems.com Revision 1.01 2 - 15 AS1153/55 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VCC to GND INx+, INx- to GND OUTx to GND Thermal Resistance ΘJA Storage Temperature Range Maximum Junction Temperature Operating Temperature Range -40 -65 Min -0.3 -0.3 -0.3 Max +5.0 +5.0 VCC + 0.3 128 +150 +150 +85 Units V V V ºC/W ºC ºC ºC The reflow peak soldering temperature (body temperature) specified is in compliance with IPC/JEDEC J-STD-020C “Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. Human Body Model, INx+, INxTypical 4-layer application Notes Package Body Temperature +260 ºC ESD Protection -4 +4 kV www.austriamicrosystems.com Revision 1.01 3 - 15 AS1153/55 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics DC Electrical Characteristics VCC = +3.0 to +3.6V, Differential Input Voltage |VID| = +0.1 to +1.0V, Common-Mode Voltage VCM = |VID/2| to 2.4V - |VID/2|,TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified). Table 3. DC Electrical Characteristics Parameter LVDS Inputs (INx+, INx-) Differential Input High Threshold Differential Input Low Threshold Input Current (AS1153/55) 1 Symbol Conditions Min Typ Max Unit VTH VTL IINx+, IINx- 100 -100 0.1V ≤ |VID| ≤ 0.6V 0.6V ≤ |VID| ≤ 1.0V VCC = 3.6V or 0, Figure 18 on page 9 VCC = 3.6V or 0, Figure 18 on page 9 -20 -25 90 40 107 100 20 25 132 mV mV µA µA Ω kΩ Differential Input Resistance (AS1157/58) Differential Input Resistance (AS1153/55) RDIFF RDIFF 2 LVCMOS/LVTTL Outputs (OUTx) IOH = 4.0mA (AS1153/ 55) IOH = 4.0mA (AS1157/ 58) VOL IOS Open, undriven short, or undriven 100Ω parallel termination VID = +100mV Open or undriven short VID = +100mV 2.7 2.7 2.7 2.7 3.2 3.2 3.2 3.2 0.1 0.25 V mA V Output High Voltage (Table 5) VOH Output Low Voltage Output Short-Circuit 3 Current Supply IOL = +4.0mA, VID = -100mV VID = 100mV, VOUTx = 0 15 AS1153/55/57/58, Inputs open Supply Current ICC 0.6 2.5 4.5 2 4.5 8 mA mA mA AS1155/58, |VID| = 200mV AS1153/57, |VID| = 200mV 1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. 2. 2xRIN = RDIFF 3. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. www.austriamicrosystems.com Revision 1.01 4 - 15 AS1153/55 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s AC Electrical Characteristics VCC = +3.0 to +3.6V, CLOAD = 10pF, Differential Input Voltage |VID| = 0.2 to 1.0V, Common-Mode Voltage VCM = |VID/2| to 2.4V -|VID/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TAMB = +25ºC (unless otherwise specified). Table 4. AC Electrical Characteristics Parameter Differential Propagation Delay Highto-Low Differential Propagation Delay Lowto-High Differential Pulse Skew (tPHLD - tPLHD) 3 1, 2 Symbol tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL 7, 8 Conditions Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 Figure 20 on page 11 and Figure 21 on page 12 All Channels Switching Min 1 1 Typ 1.8 1.8 250 Max 3.1 3.1 600 600 0.8 1.5 Unit ns ns ps ps ns ns ns ns MHz Differential Channel-to-Channel 4 Skew Differential Part-to-Part Skew Differential Part-to-Part Skew Rise Time Fall Time Maximum Operating Frequency Notes: 1. 2. 3. 4. 5. 6. 7. 5 6 0.4 0.4 130 160 1.0 1.0 fMAX 8. AC parameters are guaranteed by design and characterization. CL includes scope probe and test jig capacitance. tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device. tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same VCC and within 5ºC of each other. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated conditions. fMAX generator output conditions: a. Rise time = fall time = 1ns (0 to 100%) b. 50% duty cycle c. VOH = +1.3V d. VOL = +1.1V Output criteria: a. Duty cycle = 60% to 40% b. VOL = 0.4V (max) c. VOH = 2.7V (min) d. Load = 10pF www.austriamicrosystems.com Revision 1.01 5 - 15 AS1153/55 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 10pF, TAMB = +25ºC, unless otherwise noted. Figure 3. Supply Current vs. Frequency 50 Figure 4. Supply Current vs. Temperature 20 . 40 All Channels Switching . Supply Current (mA) 30 Supply Current (mA) 15 f = 100MHz 10 f = 1MHz 20 One Channel Switching 5 10 0 0 50 100 150 200 250 300 0 -45 -30 -15 0 15 30 45 60 75 90 Frequency (MHz) Temperature(°C) Figure 5. Diff. Threshold Voltage vs. VCC 30 High to Low VTH Figure 6. Output Short-Circuit Current vs. VCC 120 . Differential Output Voltage (mV) 25 20 15 Low to High VTL 10 5 0 3 3.1 3.2 3.3 3.4 3.5 3.6 Output Short Circuit Current (mA) . 100 80 60 40 20 0 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Supply Voltage(V) Figure 7. Output Low Voltage vs. VCC 75 74,5 74 73,5 73 72,5 72 3 3,1 3,2 3,3 3,4 3,5 3,6 Figure 8. Output High Voltage vs. VCC 3.2 . Output Voltage (mV) Output Voltage (V) . 3.1 3 2.9 2.8 2.7 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Supply Voltage (V) www.austriamicrosystems.com Revision 1.01 6 - 15 AS1153/55 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. Differential Propagation Delay vs. VCC 1.94 Figure 10. Differential Propagation Delay vs. Temp. 2.05 . Diff. Propagation Delay (ns) tPHLD 1.86 1.82 1.78 1.74 1.7 3 3.1 3.2 3.3 3.4 3.5 3.6 tPLHD Diff. Propagation Delay (ns) 1.9 . 2 1.95 1.9 tPLHD 1.85 tPHLD 1.8 1.75 -45 -30 -15 0 15 30 45 60 75 90 Supply Voltage(V) Temperature(°C) Figure 11. Differential Propagation Delay vs. VCM 2 Figure 12. Differential Propagation Delay vs. VID 2.25 . Diff. Propagation Delay (ns) Diff. Propagation Delay (ns) 1.95 1.9 tPHLD . 2 tPHLD 1.75 tPLHD 1.85 1.8 1.75 1.7 1.65 0 0.5 1 1.5 2 2.5 1.5 1.25 1 0.75 0.1 0.5 0.9 1.3 1.7 2.1 2.5 tPLHD Common-Mode Voltage(V) Differential-Input Voltage(V) Figure 13. Differential Propagation Delay vs. Load 3 . Diff. Propagation Delay (ns) 2.5 tPHLD 2 1.5 1 0.5 0 10 15 20 tPLHD 25 30 35 40 45 50 Capacitive Load (pF) www.austriamicrosystems.com Revision 1.01 7 - 15 AS1153/55 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 14. Differential Pulse Skew vs. VCC 300 Figure 15. Transition Time vs. Capacitive Load 1600 1400 tTHL . Differential Pulse Skew (ps) 250 200 150 100 50 0 3 3.1 3.2 3.3 3.4 3.5 3.6 Transition Time (ps) . 1200 1000 800 600 400 10 15 20 25 30 35 40 45 50 tTLH Supply Voltage(V) Capacitive Load (pF) Figure 16. Transition Time vs. VCC 400 390 380 tTHL Figure 17. Transition Time vs. Temperature 475 . . 450 425 400 375 350 325 300 -45 -30 -15 0 tTHL tTLH Transition Time (ps) 370 360 350 340 3 3.1 tTLH Transition Time (ps) 3.2 3.3 3.4 3.5 3.6 15 30 45 60 75 90 Supply Voltage(V) Temperature(°C) www.austriamicrosystems.com Revision 1.01 8 - 15 AS1153/55 Data Sheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1155/58 and AS1153/57 are 260Mbps, single/dual-channel LVDS receivers intended for high-speed, point-topoint, low-power applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output. The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to 2.4V. The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input voltage range, a ±1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground references of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated. LVDS Interface The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, resulting in higher data rates, reduced power consumption and EMI emissions, and less susceptibility to noise. The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground. The AS1157/58 has an integrated termination resistors connected internally across each receiver input. This internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC. Failsafe Circuit The devices contain an integrated Failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriven and shorted. Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are high impedance. A short condition also can occur because of a cable failure. The Failsafe circuit of the AS1153/55 and AS1157/58 automatically sets the output high if any of these conditions are true. The Failsafe input circuit (see Figure 18) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the Failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the Failsafe circuit pulls both inputs above VCC - 0.3V, activating the Failsafe circuit and thus forcing the device output high. Figure 18. Failsafe Input Circuit VCC VCC RIN2 RIN2 VCC - 0.3V INx+ RIN1 OUTx RIN1 INx+ RIN1 RDIFF RIN1 VCC - 0.3V OUTx INx- INx- AS1153/55 AS1157/58 www.austriamicrosystems.com Revision 1.01 9 - 15 AS1153/55 Data Sheet - A p p l i c a t i o n s 9 Applications Table 5. Function Table Input INx+ VID ≥ +100mV VID ≤ +100mV AS1153/55 – Open, undriven short, or undriven 100Ω parallel termination AS1157/58 – Open or undriven short Figure 19. Typical Application Circuit INxOutput OUTx H L H +3.3V +3.3V 0.001µF 0.1µF 0.001µF 0.1µF LVDS Signals LVTTL/LVCMOS Data Inputs LVTTL/LVCMOS Data Outputs Tx 107Ω Rx AS1152 AS1158 Single LVDS Receiver 100Ω Shielded Twisted Cable or Microstrip PC Board Traces Power-Supply Bypassing To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to pin VCC. Differential Traces Input trace characteristics can adversely affect the performance of the AS1155/58 and AS1153/57. ! ! ! ! Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor must also be matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices. Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential impedance. Avoid 90° turns (use two 45° turns). Minimize the number of vias to further prevent impedance irregularities. ! ! Cables and Connectors Supported transmission media include printed circuit board traces, backplanes, and cables. www.austriamicrosystems.com Revision 1.01 10 - 15 AS1153/55 Data Sheet - A p p l i c a t i o n s ! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. ! ! Termination Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections, and reduce EMI. ! The AS1157/58 has integrated termination resistors connected across the inputs of each receiver. The value of the integrated resistor is specified in Table 3. The AS1153/55 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance values may range between 90 to 132Ω depending on the characteristic impedance of the transmission medium. Use 1% surface-mount resistors. ! Board Layout The device should be placed as close to the interface connector as possible to minimize LVDS trace length. ! ! ! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals. Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. ! Figure 20. Propagation Delay and Transition Time Test Circuit INx+ Pulse Generator** INx50Ω 50Ω CL OUT Receiver AS1153/55, AS1157/58 * 50Ω required for pulse generator. ** When testing the AS1157/58, adjust the pulse generator output to account for internal termination resistor. www.austriamicrosystems.com Revision 1.01 11 - 15 AS1153/55 Data Sheet - A p p l i c a t i o n s Figure 21. Propagation Delay and Transition Time Waveforms INxVID = 0 INx+ tPLHD tPHLD VOH VID = (VINx+) - (VINx-) Note: VCM = (VIN- + VIN+) 2 80 80 VID VID = 0 50% 20 OUTx tTLH 50% 20 tTHL VOL www.austriamicrosystems.com Revision 1.01 12 - 15 AS1153/55 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package. Figure 22. 8-pin SOIC Package Diagram Table 6. 8-pin SOIC Package Dimensions SOIC - 8LD Symbol A1 B D E e H Note: 1. Lead coplanarity should be 0 to 0.10MM max. 2. Package surface finishing: Top: Matte (Charmilles #18~30) All Sides: Matte (Charmilles #18~30) Bottom: Smooth or Matte (Charmilles #18~30) 3. All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D) 4. Details of PIN #1 identifier are optional, but must be located within the zone indicated. 5.80 MILLIMETERS MIN 0.10 0.36 4.80 3.81 1.27 BSC 6.20 MAX 0.25 0.48 4.98 3.99 ZD A2 1.37 Symbol h L A MILLIMETERS MIN 0.25 0.41 1.52 0º 0.53 REF 1.57 MAX 0.50 1.27 1.72 8º www.austriamicrosystems.com Revision 1.01 13 - 15 AS1153/55 Data Sheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information Part Number AS1155 AS1155-T AS1158 AS1158-T AS1153 AS1153-T AS1157 AS1157-T Marking AS1155 AS1155 AS1158 AS1158 AS1153 AS1153 AS1157 AS1157 Description Single LVDS Receiver Single LVDS Receiver Single LVDS Receiver, with termination Single LVDS Receiver, with termination Dual LVDS Receiver Dual LVDS Receiver Dual LVDS Receiver, with termination Dual LVDS Receiver, with termination Delivery Form Package Type Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC www.austriamicrosystems.com Revision 1.01 14 - 15 AS1153/55 Data Sheet Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.01 15 - 15