AS8221_1

Data Sheet AS8221 F l e x R a y S t a n d a r d Tr a n s c e i v e r 1 General Description This document is subjected to change without notice. The AS8221 is a high speed automotive bus driver fully conforming to the FlexRay Electrical Physical Layer Specification V2.1 Rev B. The AS8221 operates as a bi-directional interface between the FlexRay Communication Controller and the twisted-pair copper wiring. The AS8221 provides an optimized host controller interface consisting of three low-active pins. The Enable (EN) and Standby (STBN) input pins for mode handling by the microcontroller and the Error (ERRN) out pin where system, chip failures or status information are signalled to the microcontroller. Signalling logic high on the Enable and Standby pin the device will enter NORMAL mode in case no fault condition is given and in this mode the device is fully operational meaning FlexRay communication is possible. Additionally a RECEIVE-0NLY mode is implemented, which can be accessed by the microcontroller where only FlexRay streams can be received in order to avoid unwanted disturbances on the FlexRay bus while listening to the bus traffic. In the low-power modes (STANDBY and SLEEP mode) very low power consumption is achieved. In case of undervoltage at one of the supply voltages (VBAT, VCC, and VIO) the device will change its mode to a low-power mode (either STANDBY or SLEEP mode) and the device will signal an error accordingly. In case of low voltage is detected on both VBAT and VCC the device will enter the POWER-OFF mode, where no operation is possible. A safe mechanism from the low-power modes to POWER-OFF mode and vice versa is implemented ensuring that no deadlock can happen during the startup phase. Ensuring application in safety critical environments a two wire busguardian interface is implemented where additional monitoring circuitries on the electronic-control-unit can activate and deactivate the transmitter and additionally on the receive enable output (RxEN) in low-power modes the wake conditions and in normal power modes the received FlexRay streams can be monitored. A thermal sensor circuit with an integral shutdown mechanism prevents damage to the device in extreme temperature conditions. The symmetrical transient control for the high- and low-side driver for both the bus-minus (BM) and bus-plus (BP) line allows an ideal balance of communications over different network topologies, with excellent EMC performance. 2 Key Features Compliant with FlexRay Electrical Physical Layer Specification V2.1 Rev. B Data transfer up to 10 Mbps Excellent EMC performance. High common mode range ensure excellent EMI Interface for Bus Guardian or supervision circuits Automatic thermal shutdown protection Supports 12V and 24V systems with very low sleep current Integrated power management system - Two inhibit pins for external voltage supply control - Local wake-up input - Remote wake-up capability via FlexRay bus in low-power modes Supports 2.5, 3, 3.3, 5 V microcontrollers, automatic adaptation to digital interface levels Protection against damage due to short circuit conditions on the bus (positive and negative battery voltage) Operating temperature range -40ºC to +125ºC Lead-free SSOP20 package 3 Applications The AS8221 FlexRay Standard Transceiver is best fitting for automotive FlexRay nodes where bus wake-up and voltage regulator control for voltage supplies is needed. The device addresses all ECUs connected to the permanent battery supply (clamp 30). The AS8221 can be used as only ECU wake-up component with very low power consumption in SLEEP mode. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 1 - 43 AS8221 Data Sheet - A p p l i c a t i o n s Figure 1. AS8221 FlexRay Standard Transceiver Block Diagram VIO AS8221 Bus Failure Detector STBN EN ERRN VIO Host Controller Interface RxD TxD TxEN Communication Controller Interface BP Internal Logic (IL) Transmitter BM BGE RxEN VBAT VBAT Bus Guardian Interface Receiver INH1 INH2 Power Supply Interface Wake-Up Detector VBAT VIO VCC GND WAKE www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 2 - 43 AS8221 Data Sheet - C o n t e n t s Contents 1 General Description.................................................................................................................................................................... 1 2 Key Features ............................................................................................................................................................................... 1 3 Applications ................................................................................................................................................................................ 1 4 Pin Assignments......................................................................................................................................................................... 5 4.1 Pin Descriptions........................................................................................................................................................................................ 5 5 Absolute Maximum Ratings....................................................................................................................................................... 7 6 Electrical Characteristics........................................................................................................................................................... 8 7 Typical Operating Characteristics........................................................................................................................................... 14 8 Detailed Description ................................................................................................................................................................. 15 8.1 Block Description.................................................................................................................................................................................... 15 8.2 Events..................................................................................................................................................................................................... 15 8.3 Operating Modes .................................................................................................................................................................................... 15 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 NORMAL Mode .......................................................................................................................................................................... 16 RECEIVE-ONLY Mode ............................................................................................................................................................... 16 STANDBY Mode......................................................................................................................................................................... 16 GO-TO-SLEEP Mode ................................................................................................................................................................. 16 SLEEP Mode .............................................................................................................................................................................. 16 8.4 Non Operating Mode .............................................................................................................................................................................. 16 8.4.1 POWER-OFF.............................................................................................................................................................................. 16 8.5 Undervoltage Events .............................................................................................................................................................................. 17 8.5.1 Undervoltage/Voltage Recovery VBAT ........................................................................................................................................ 17 8.5.2 Undervoltage/Voltage Recovery VIO ........................................................................................................................................... 17 8.5.3 Undervoltage/Voltage Recovery VCC.......................................................................................................................................... 17 8.6 Power On/Off Events.............................................................................................................................................................................. 17 8.7 Wake-Up Events..................................................................................................................................................................................... 17 8.7.1 Remote Wake-Up Event ............................................................................................................................................................. 17 8.7.2 Local Wake-Up Event ................................................................................................................................................................. 18 8.8 System Description................................................................................................................................................................................. 19 8.9 Fail Silent Behavior................................................................................................................................................................................. 20 8.9.1 RxEN / BGE timeout ................................................................................................................................................................... 20 8.9.2 State Transitions due to Under Voltage Detection...................................................................................................................... 20 8.9.3 State Transitions due to Voltage Recovery Detection ................................................................................................................ 20 8.10 Mode Transitions .................................................................................................................................................................................. 20 8.10.1 Operating Mode Transitions ..................................................................................................................................................... 21 8.10.2 ERRN Signalling ....................................................................................................................................................................... 23 8.11 Loss of ground ...................................................................................................................................................................................... 23 8.12 Error Flags Description......................................................................................................................................................................... 23 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 8.12.8 Undervoltage ............................................................................................................................................................................ 23 Bus Error (BUSERR) ................................................................................................................................................................ 23 BP Open Line (BP_OL) ............................................................................................................................................................ 23 BM Open Line (BM_OL) ........................................................................................................................................................... 23 BP Short Circuit to VCC (BP_VCC) ............................................................................................................................................ 24 BP Short Circuit to GND (BP_GND) ......................................................................................................................................... 24 BM Short Circuit to VCC (BM_VCC) ........................................................................................................................................... 24 BM Short Circuit to GND (BM_GND)........................................................................................................................................ 24 www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 3 - 43 AS8221 Data Sheet - C o n t e n t s 8.12.9 Short Circuit between BP and BM (BP_BM)............................................................................................................................. 24 8.12.10 Over Temperature (OT) .......................................................................................................................................................... 24 8.12.11 TxEN_BGE Timeout (TxEN_TO)............................................................................................................................................ 24 8.12.12 Error Flag (ERROR) ............................................................................................................................................................... 24 8.13 Status Flags Description....................................................................................................................................................................... 24 8.13.1 Local Wake Flag (LWAKE) ....................................................................................................................................................... 24 8.13.2 Remote Wake Flag (RWAKE) .................................................................................................................................................. 24 8.13.3 Power on Flag (PWON) ............................................................................................................................................................ 25 8.14 Error Flags and Status Flags Read-Out ............................................................................................................................................... 25 8.14.1 Error and Status Flag Bit Order ................................................................................................................................................ 25 8.15 Bus Driver............................................................................................................................................................................................. 26 8.15.1 Bus States ................................................................................................................................................................................ 26 8.16 Transceiver Timing ............................................................................................................................................................................... 27 8.17 Transmitter............................................................................................................................................................................................ 28 8.18 Receiver ............................................................................................................................................................................................... 30 8.18.1 Bus Activity and Idle Detection (only in NORMAL and RECEIVE-ONLY mode) ...................................................................... 30 8.18.2 Bus Data Detection (only in NORMAL and RECEIVE-ONLY mode)........................................................................................ 30 8.18.3 Receiver Test Signal................................................................................................................................................................. 32 8.19 Test Circuits .......................................................................................................................................................................................... 33 9 Appendix.................................................................................................................................................................................... 34 9.1 FlexRay Functional Classes ................................................................................................................................................................... 34 9.2 FlexRay Parameter Comparison ............................................................................................................................................................ 34 10 Package Drawings and Markings.......................................................................................................................................... 41 10.1 Revision History.................................................................................................................................................................................... 42 11 Ordering Information .............................................................................................................................................................. 43 www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 4 - 43 AS8221 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments SSOP20 Package INH2 INH1 EN VIO TxD TxEN RxD BGE STBN Reserved 1 2 3 4 5 6 7 8 9 10 20 19 18 17 n.u VCC BP BM GND WAKE VBAT ERRN RxEN n.u AS8221 16 15 14 13 12 11 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Name INH2 INH1 EN VIO TxD TxEN RxD BGE STBN Reserved Not used RxEN ERRN VBAT WAKE GND BM BP VCC Not used Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DO DO S AIO S AIO AIO S Digital Output. Receive data enable output Digital Output. Error diagnosis output and wake status output Supply Voltage. Battery supply voltage Analog Input. Local wake-up input Ground Analog Input/Output. Bus line Minus Analog Input/Output. Bus line Plus Supply voltage. Pin Type AIO AIO DI_PD S DI_PD DI_PU DO DI_PD DI_PD A/DIO_PD Description Analog Output. Inhibit 2 output for switching external voltage regulator Analog Output. Inhibit 1 output for switching external voltage regulator Digital Input. Enable input Supply Voltage. I/O supply voltage Digital Input. Transmit data input Digital Input. Transmitter enable input Digital Output. Receive data output Digital Input. Bus guardian enable input Digital Input. Standby input 1 1. To be connected to GND or to be unconnected www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 5 - 43 AS8221 Data Sheet - P i n A s s i g n m e n t s Where: S: supply pad AIO: Analog I/O DI: Digital output DI_PU: Digital input with pull-up DI_PD: Digital input with pull-down DO: Digital output A/DIO_PD: Analog/digital input/output with pull-down www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 6 - 43 AS8221 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 8 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Battery Supply Voltage (VBAT) Supply Voltage (VCC) Supply Voltage (VIO) DC Voltage at EN, STBN, ERRN, TxD, RxD, TxEN, BGE, RxEN DC Voltage on pin WAKE, INH1, INH2 DC Voltage at BP and BM Input current (latchup immunity) Electrostatic discharge at bus lines BP, BM, VBAT, WAKE Electrostatic discharge Transient voltage on BP, BM Min -0.3 -0.3 -0.3 -0.3 -0.3 -40 -100 -4 -2 -200 Max +50 +7.0 +7.0 VIO + 0.3 VBAT + 0.3 +50 100 +4 +2 +200 V mA kV kV V According to JEDEC 78 According to AEC-Q100-002 According to AEC-Q100-002 According to ISO7637 part3 test pulses a and b; class C; RL=45 Ω, CL= 100 pF; (see Figure 18 on page 33). According to ISO7637 part2 test pulses 1, 2, 3a and 3b; class C; RL=45 Ω, CL= 100 pF; (see Figure 18 on page 33). According to ISO7637 part2 test pulse 4; class C; RL=45 Ω, CL= 100 pF; (see Figure 18 on page 33). According to ISO7637 part2 test pulse 5b; class C; RL=45 Ω, CL= 100 pF; (see Figure 18 on page 33). mW ºC ºC ºC % Units V V V V VIO < VCC Notes -200 +200 V Transient voltage on VBAT +6.5 +50 V +50 Total power dissipation (all supplies and outputs) Storage temperature Junction temperature Package body temperature Humidity non-condensing 1 150 -55 -40 +150 +150 250 5 85 1. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 7 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Tvj = -40 to +150 ºC, VCC= +4.75V to +5.25V, VBAT= 6.5 to +50 V, VIO = +2.2 to VCC, RL= 45Ω, CL= 100 pF unless otherwise specified. Table 3. Electrical Characteristics Symbol Supply Voltage TAMB VCC-VIO Ambient temperature Difference of supplies VBAT=12V; low-power modes Tvj < 125ºC (see footnote 1) IBAT VBAT current consumption VBAT=12V; low-power modes Tvj < 150ºC Non-low-power modes Low-power Modes VCC = 0V to +5.25V (see footnote 1) ICC VCC current consumption Non-low-power modes: NORMAL, driver enabled; Non-low-power modes: NORMAL, driver enabled; RBUS = ∞Ω Non-low-power modes: RECEIVE-ONLY IIO State Transitions tSTBN_RxD tSTBN_RxEN tSLEEP_INH1 tSTANDBY_INH2 tSLEEP Transmitter VBUS_DIFF_D0 VBUS_DIFF_D1 ΔVBUS_DIFF Differential bus voltage low in NORMAL mode (Data0) Differential bus voltage high in NORMAL mode (Data1) Matching between Data0 and Data1 differential bus voltage in NORMAL mode Common mode bus voltage in case of Data0 in non-low-power modes Common mode bus voltage in case of Data1 in non-low-power modes VBPdata0 - VBMdata0; 40 ≤ RL ≤ 55Ω VBPdata1 - VBMdata1; 40 ≤ RL ≤ 55Ω VBUS_DIFF_D0 - VBUS_DIFF_D1 40 ≤ RL ≤ 55Ω VBPdata0/2 + VBMdata0/2 40 ≤ RL ≤ 55Ω VBPdata1/2 + VBMdata1/2 40 ≤ RL ≤ 55Ω -2 0.6 -200 0.4 * VCC 0.4 * VCC -1 1 0 0.5 * VCC 0.5 * VCC -0.6 2 200 0.6 * VCC 0.6 * VCC V V mV Delay STBN high to RxD high with wake flag set Delay STBN high to RxEN high with wake flag set Delay STBN high to INH1 high Delay STBN high to INH2 high GO-TO-SLEEP hold time INH1 high = 80% VBAT INH2 high = 80% VBAT INH1 low = 20% VBAT 1 1 1 1 10 9 9 11 11 26 50 50 50 50 70 µs µs µs µs µs VIO current consumption Low-power modes VIO = 0V to +5.25V Non-low power modes -40 -0.1 0 0 0 -5 0 0 0 -5 0 0.15 8 29 7 2.0 1 15 26 +25 +125 3.05 50 100 1 20 45 15 10 5 1000 ºC V µA µA mA µA mA mA mA µA µA Parameter Conditions Min Typ Max Units VBUS_COM_D0 V VBUS_COM_D1 V www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 8 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol ΔVBUS_COM VBUS_DIFF_Idle IBPBMShortMax IBMBPShortMax IBPGNDShortMax IBMGNDShortMax IBP-5VShortMax IBM-5VShortMax IBP27VShortMax IBM27VShortMax IBP48VShortMax IBM48VShortMax tTxD_BUS01 tTxD_BUS10 tTxD_MISMATCH tBUS10 tBUS01 tTxEN_BUS_Idle_Active tTxEN_BUS_Active_Idle tTxEN_MISMATCH tBGE_BUS_Idle_Active tBGE_BUS_Active_Idle tBUS_Idle_Active tBUS_Active_Idle tTxEN_timeout Parameter Matching between Data0 and Data1 common mode voltage Absolute differential bus voltage in bus idle mode Absolute max current when BP is shorted to BM Absolute max current when BP is shorted to GND Absolute max current when BM is shorted to GND Absolute max current when BP is shorted to -5 V Absolute max current when BM is shorted to -5 V Absolute max current when BP is shorted to 27 V Absolute max current when BM is shorted to 27 V Absolute max current when BP is shorted to 48 V Absolute max current when BM is shorted to 48 V Delay time from TxD to BUS positive edge Delay time from TxD to BUS negative edge Delay time from TxD to BUS mismatch Fall time differential bus voltage Rise time differential bus voltage Delay time from TxEN to bus active Delay time from TxEN to bus idle Delay time from TxEN to bus mismatch Delay time from BGE to bus active Delay time from BGE to bus idle Differential bus voltage transition time: idle to active Differential bus voltage transition time: active to idle TxEN timeout 1.5 |tTxEN_BUS_Idle_Active tTxEN_BUS_Active_Idle| Conditions VBUS_COM_D0 - VBUS_COM_D1 40 ≤ RL ≤ 55Ω Load on BM/BM: 40Ω || 100pF VBP=VBM VBP= 0V VBM= 0V VBP= -5V VBM= -5V VBP= 27V VBM= 27V VBP= 48V VBM= 48V tTxD_RISE = 5ns tTxD_FALL = 5ns tTxD_BUS10 - tTxD_BUS01 80% - 20% of VBUS 20% - 80% of VBUS -4 3.75 3.75 Min -200 Typ 0 0 35 48 48 48 48 71 71 72 72 22 22 0 12 12 14 10 4 15 11 5 2 4.9 Max 200 30 +100 +100 +100 +100 +100 +100 +100 +100 +100 50 50 4 18.75 18.75 50 50 50 50 50 30 30 15 Units mV mV mA mA mA mA mA mA mA mA mA ns ns ns ns ns ns ns ns ns ns ns ns ms www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 9 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol Receiver RBP, RBM RDIFF VBPidle, VBMidle VBPidle_low, VBMidle_low IBPidle IBMidle IBPleak, IBMleak VBUSActiveHigh BP, BM input resistance BP, BM differential input resistance Idle voltage in non-low-power modes on pin BP, BM Idle voltage in low-power modes on pin BP, BM Absolute idle output current on pin BP Absolute idle output current on pin BM Absolute leakage current, when not powered Activity detection differential input voltage high Activity detection differential input voltage low Idle mode; RBUS=∞ Idle mode; RBUS=∞ Non-low-power modes; VTxEN = VIO Load on BM/BM: 40Ω || 100pF Low-power modes Load on BM/BM: 40Ω || 100pF -40V < VBP < 50V -40V < VBM < 50V VBP = VBM = 5V, VCC = 0V, VBAT = 0V; VIO = 0V Non-low-power modes; VRECEIVE_COM: -10V < (VBP, VBM) < 15V Non-low-power modes; VRECEIVE_COM: -10V < (VBP, VBM)< 15V Pre-condition: activity already detected. Non-low-power modes; VRECEIVE_COM: -10V < (VBP, VBM)< 15V Pre-condition: activity already detected. Non-low-power modes; VRECEIVE_COM: -10V < (VBP, VBM)< 15V 2 x (⎜⎜VData0⎜- ⎜VData1⎜⎜) / (⎜VData0⎜+⎜VData1⎜) (see footnote 2) Non-low-power modes CRxD = 15 pF (see footnote 3) CRxD = 15 pF (see footnote 3) CRxD = 15 pF (see footnote 3) CRXD=15 pF; |tBUS_RxD10- tBUS_RxD01| (see footnote 3) (see footnote 4) 80% - 20% of VRxD; CRxD=15 pF (see footnote 3) 54 -10 36 36 10 20 0.4 * VCC -0.2 0 0 0 150 25 50 0.5 * VCC 0 2 2 7 225 40 80 0.6 * VCC +0.2 7.5 7.5 +25 400 KΩ KΩ V V mA mA µA mV Parameter Conditions Min Typ Max Units VBUSActiveLow -400 -225 -150 mV VData1 Data1 detection differential input voltage 150 225 300 mV VData0 Data0 detection differential input voltage -300 -225 -150 mV VDataErr VRECEIVE_COM tBUS_RxD10 tBUS_RxD01 tBIT Mismatch between Data0 and Data1 differential input voltage Max. common mode voltage range when receiving Delay from BUS to RxD negative edge Delay from BUS to RxD positive edge Bit time Delay time from BUS to RxD mismatch 10 +15 80 80 % V ns ns ns tRxD_ASYM 0 5 ns tRxD_FALL Fall time RxD voltage 2 5 ns www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 10 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol tRxD_RISE tBUSIdleDetection tBUSActivityDetection tBUSIdleReaction tBUSActivityReaction Wake-Up Detector tBWU_D0 tBWU_Idle tBWU_Detect VBWUTH VLWUTH ILWUL ILWUH tLWUFilter Supply Voltage Monitor VBATTHH VBATTHL VCCTHH VCCTHL VIOTHH VIOTHL tUV_DETECT tUV_REC Bus Error Detection ITHL ITHH Absolute bus current for low current detection Absolute bus current for high current detection NORMAL mode, Transmitter enabled NORMAL mode, Transmitter enabled 5 40 mA mA VBAT undervoltage recovery threshold VBAT undervoltage detection threshold VCC under-voltage recovery threshold VCC undervoltage detection threshold VIO undervoltage recovery threshold VIO undervoltage detection threshold Detection time for undervoltage at VBAT, VCC, VIO Detection time for undervoltage recovery at VBAT, VCC, VIO 3.5 2.5 3.5 2.5 1.25 0.75 100 0.7 4 3 4 3 1.6 1.1 300 2 4.5 3.5 4.5 3.5 2.0 1.5 700 5 V V V V V V ms ms Data0 detection time in remote wake-up pattern Idle or Data1 detection time in remote wake-up pattern Total remote wake-up detection time Bus wake-up detection threshold Local wake-up detection threshold Low level input current on local WAKE pin High level input current on local WAKE pin Local wake filter time VBAT = 12V; VLWAKE = 2V for t < tLWUFilter VBAT = 12V; VLWAKE = 4V for t < tLWUFilter -10V < (VBP, VBM) < 15V -10V < (VBP, VBM) < 15V -10V < (VBP, VBM) < 15V -10V < (VBP, VBM) < 15V 1 1 48 -300 2 -20 5 1 2 2 73 -250 2.8 -10 11 20 4 4 140 -150 4 -5 20 40 µs µs µs mV V µA µA µs Parameter Rise time RxD voltage Idle detection time Activity detection time Idle reaction time Activity reaction time Conditions 20% - 80% of VRxD; CRxD=15 pF (see footnote 3) VBUS: 400mV → 0V VBUS: 0V → 400mV VBUS: 400mV → 0V VBUS: 0V → 400mV 50 100 50 100 173 173 192 200 200 250 300 350 ns ns ns ns Min Typ 2 Max 5 Units ns www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 11 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol VSHORT tBUS_ERROR Over Temperature OTTH OTTL Power Supply Interface ΔVOINH ⏐IIL⏐ High level voltage drop on INH1, INH2 Leakage current Threshold for detecting TxD as on logical high Threshold for detecting TxD as on logical low TxD high level input current TxD low level input current Threshold for detecting TxEN as on logical high Threshold for detecting TxEN as on logical low TxEN high level input current TxEN low level input current RxD high level output voltage RxD low level output voltage Threshold for detecting STBN as on logical high Threshold for detecting STBN as on logical low STBN high level input current STBN low level input current STBN de-bouncing time lowpower modes STBN de-bouncing time non-lowpower modes Threshold for detecting EN as on logical high Threshold for detecting EN as on logical low EN high level input current EN low level input current 0.3 * VIO 30 -5 0.3 * VIO 30 -5 0.1 0.1 IRxD = -4mA, VIO = 5V IRxD = 4mA, VIO = 5V 0.3 * VIO -5 -100 0.3 * VIO 30 -5 IINH = 0.2mA, VBAT = 5.5V SLEEP mode, VINH = 0V 0 0.15 0 0.48 * VIO 0.48 * VIO 52 0 0.48 * VIO 0.48 * VIO 0 -50 5 -30 100 5 0.7 * VIO 0.8 5 V µA Over temperature threshold Over temperature hysteresis 150 10 171 13 180 20 ºC ºC Parameter Differential voltage on BP and BM for detecting short circuit between bus lines Bus error detection time Conditions NORMAL mode, Transmitter enabled NORMAL mode, Transmitter enabled Min Typ 225 20 Max Units mV µs Communication Controller Interface VTxDIH VTxDIL ITxDIH ITxDIL VTxENIH VTXENIL ITxENIH ITxENIL VRxDOH VRxDOL Host Interface VSTBNIH VSTBNIL ISTBNIH ISTBNIL tSTBN_DEB_LP tSTBN_DEB_NLP VENIH VENIL IENIH IENIL 0.48 * VIO 0.48 * VIO 52 0 1 1 0.48 * VIO 0.48 * VIO 50 0 100 5 100 5 40 2 0.7 * VIO 0.7 * VIO V V µA µA µs µs V V µA µA 0.7 * VIO V V µA µA V V µA µA V V 0.8 * VIO 0.9 * VIO 1.0 * VIO 0 0.1 * VIO 0.2 * VIO www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 12 - 43 AS8221 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics Symbol tEN_DEB_LP tEN_DEB_NLP VERRNOH VERRNOL Bus Guardian Interface VBGEIH VBGEIL IBGEIH IBGEIL VRxENOH VRxENOL Read Out Interface tRO_EN_ERRN tRO_EN_TIMEOUT 1. 2. 3. 4. Propagation delay falling edge EN to ERRN error-read-out timeout 25 2 50 4.5 100 µs µs Threshold for detecting BGE as on logical high Threshold for detecting BGE as on logical low BGE high level input current BGE low level input current RxEN high level output voltage RxEN low level output voltage IRxEN = -4mA, VIO = 5V IRxEN = 4mA, VIO = 5V 0.3 * VIO 30 -5 0.48 * VIO 0.48 * VIO 51 0 100 5 0.7 * VIO V V µA µA V V Parameter EN de-bouncing time low-power modes EN de-bouncing time non-lowpower modes ERRN high level output voltage ERRN low level output voltage IERRN = -4mA, VIO = 5V IERRN = 4mA, VIO = 5V Conditions Min 0.1 0.1 Typ 1 1 Max 40 2 Units µs µs V V 0.8 * VIO 0.9 * VIO 1.0 * VIO 0 0.1 * VIO 0.2 * VIO 0.8 * VIO 0.9 * VIO 1.0 * VIO 0 0.1 * VIO 0.2 * VIO EN, STBN, ERRN, TxD, RxD, TxEN, BGE, RxEN, LWAKE, INH1, INH2: open Test condition: (VBP + VBM) / 2 = 2,5V ) ± 5% For test signal (see Figure 17) Guaranteed at specified bit time tBIT www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 13 - 43 AS8221 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics Figure 3. Bus Differential Voltage Figure 4. Bus Absolute Voltage Figure 5. Bus Differential Voltage Figure 6. Bus Differential Input Resistance www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 14 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS8221 is a FlexRay Transceiver operating as an interface between the Communication Controller and the wired bus lines. The AS8221 is designed to extend the application range for high speed and safety critical time triggered bus systems in an automotive environment. The drivers are short circuit protected against the positive and negative supply voltage to increase the robustness and reliability of automotive systems. The AS8221 operates at baudrates up to 10 Mbps. 8.1 Block Description The AS8221 consists of 9 functional blocks (see Figure 1): Table 4. Functional Blocks Functional Block Host Controller Interface (HCI) Communication Controller Interface (CCI) Bus Guarding Interface (BGI) Power Supply Interface (PSI) Internal Logic (IL) Short Description Digital interface between the Transceiver and the host controller (HC) The host interface comprises the read-out handler, which delivers failure and status information via the ERRN pin to the host controller. Digital interface between the Transceiver and the FlexRay communication controller (CC) Digital interface between the Transceiver and the FlexRay bus guardian (BG) or monitoring circuitry. The power supply interface consists of the voltage monitor (VM) with two analog inhibit outputs switching external voltage supplies. The digital signals from the functional blocks of the device are fed into the internal logic where the forwarding of FlexRay messages from analog side to digital interfaces and vice versa is done. The state machine is embedded in the Internal Logic and the handling of error, wake, and power-on flags is executed herein. The bus failure detector is directly connected to the bus pins, in order to detect several external failure conditions which may occur on the bus. The temperature protection turns off the output driver when reaching the specified internal temperature in order to protect the device. The transmitter provides the differential signalling according the FlexRay standard on the bus pins. The Receiver captures FlexRay valid signals at the bus pins and provides the received data streams to the Internal Logic. The wake-up detector recognizes valid wake-up frames on the bus, recognizes a wake signal on the local WAKE pin and signals valid wake-up events to the Internal Logic. Bus Failure Detector (BFD) Temperature Protection (TP) Transmitter Receiver Wake-Up Detector (WUD) 8.2 Events Transitions in order to change between the operation modes are possible only if events are detected. The device supports three type of events, events on the host controller interface (STBN, EN), detection of undervoltage or supply voltage recovery and wake events. Mode changes are only performed upon detected events. 8.3 Operating Modes The AS8221 provides the following operating modes: NORMAL: non-low-power mode RECEIVE-ONLY: non-low-power mode STANDBY: low-power mode GO-TO-SLEEP: low-power mode SLEEP: low-power mode www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 15 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.3.1 NORMAL Mode In this mode the Transceiver is able to send and receive data signals on the bus. TxEN and BGE enables and disables the transmission of data streams. INH1 and INH2 outputs are set high. RxD reflects bus data and bus state. The error-read-out-mechanism is enabled. In NORMAL mode, the transmitter state can be selected as shown in the Table 5. In case the over-temperature flag is set the Transmitter will be disabled. The bus wires are terminated to VCC/2 via Receiver input resistances. Table 5. Transmitter State BGE H H X L TxEN L L H X TxD H L X X Transmitter state Enabled Enabled Disabled Disabled Bus State Data1 (BP is driven high, BM is driven low) Data0 (BP is driven low, BM is driven High) Idle (BP and BM are not driven) Idle (BP and BM are not driven) If the differential bus voltage is higher than VBUSActiveHigh or lower than VBUSActiveLow for a time longer than tBUSActivityDetection, then activity is detected on the bus (Bus = active), RxEN is switched to logical “low” and RxD is released. If, after the activity detection, the differential bus voltage is higher than VData1, RxD is high. If, after the activity detection, the differential bus voltage is lover than VData0, RxD is low. If the absolute differential bus voltage is lower than VBUSActiveHigh and higher than VBUSActiveLow for a time longer than tBUSIdleDetection, then idle is detected on the bus (Bus = idle), RxEN and RxD are switched to logical “high” 8.3.2 8.3.3 RECEIVE-ONLY Mode STANDBY Mode In RECEIVE-ONLY mode the Transmitter is disabled but the Receiver is active. In this mode the Transceiver is not able to send and receive data signals from the bus, but the wake-up detector is active. The power consumption is significantly reduced with respect to the non-low-power operation modes. RxD and RxEN, reflects the negation of the wake-up flag. INH1 is set to high. If wake-up flag is set then INH2 is high, otherwise it is floating. The error-read-out-mechanism is not enabled. The bus wires are terminated to GND (bus state: Idle_LP). 8.3.4 GO-TO-SLEEP Mode In this mode the Transceiver has the same behavior as in STANDBY mode but if this mode is selected for a time longer than tSLEEP and the wake flag is cleared the device enters into the SLEEP mode. 8.3.5 SLEEP Mode In SLEEP mode only the bus wake and local wake detection is enabled. IN1 and INH2 are floating. 8.4 Non Operating Mode The AS8221 provides the following non operating mode: 8.4.1 POWER-OFF In this mode the Transceiver is not able to operate. RxD, RxEN are set to high and ERRN is set to low. INH1 and INH2 are floating. The bus wires are not connected to GND (bus state: Idle_HZ). www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 16 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.5 Undervoltage Events The device monitors the following three voltage supplies: VBAT: Battery supply voltage VIO: Supply voltage for I/O digital level adaptation VCC: Supply voltage (+5V) 8.5.1 Undervoltage/Voltage Recovery VBAT If VBAT voltage falls below VBATTHL for a time longer than tUV_DETECT then the undervoltage VBAT flag is set and it is reset if VBAT exceeds the voltage threshold VBATTHH for a time longer than tUV_REC or in case a wake-up event has been detected. The flag can be set or reset in all the modes. 8.5.2 Undervoltage/Voltage Recovery VIO If VIO voltage falls below VIOTHL for a time longer than tUV_DETECT then the undervoltage VIO flag is set and it is reset if VIO exceeds the voltage threshold VIOTHH for a time longer than tUV_REC or in case a wake-up event has been detected. The flag can be set or reset in all the operation modes. The flag is automatically reset at POWER-OFF. 8.5.3 Undervoltage/Voltage Recovery VCC If VCC voltage falls below VCCTHL for a time longer than tUV_DETECT then the undervoltage VCC flag is set and it is reset if VCC exceeds the voltage threshold VCCTHH for a time longer than tUV_REC or in case a wake-up event has been detected. The flag can be set or reset in all operation modes. The flag is automatically reset at POWER-OFF. 8.6 Power On/Off Events Starting from POWER-OFF mode a power on event occurs in case VBAT undervoltage flag is reset. Starting from every operation mode a POWER-OFF event occurs in case VBAT and VCC undervoltage flags are set. 8.7 Wake-Up Events A wake-up event can be detected only in low-power modes. The wake-up flag is set if the remote or local wake flag is set. The wake-up flag is reset if both the remote and local wake-up flags are reset. The remote wake-up flag is set if a remote wake-up event occurs. The local wake-up flag is set if a local wake-up event occurs. The remote and local wake-up flags are reset entering a low-power mode from a non-low-power mode, entering NORMAL mode, whenever an undervoltage event occurs and at POWER-OFF. 8.7.1 Remote Wake-Up Event A remote wake-up event, only possible in low-power mode, consists in the reception of at least two consecutive wake-up symbols via the bus within tBWU_Detect. The wake-up symbol is defined as Data0 longer than tBWU_D0 followed by idle or Data1 longer than tBWU_Idle as in Figure 7 unless an undervoltage or wake-up event is present. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 17 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 7. Signal for wake-up pattern recognition VBUS Wake-up Symbol Wake-up Symbol tBWU_D0 tBWU_Idle tBWU_D0 tBWU_Detect tBWU_Idle 8.7.2 Local Wake-Up Event In all low-power modes, if the voltage on the WAKE pin falls below VLWUTH for longer than tLWFilter, a local wake-up event is detected. At the same time the biasing of the pin is switched to pull-down. If the voltage on the WAKE pin rises above VLWUTH for longer than tLWFilter, a local wake-up event is detected. At the same time the biasing of the pin is switched to pull-up. The pull up and down mechanism is active in low-power and non-low-power modes. Figure 8. WAKE input pin behavior PULL-UP W AKE tLW UFilter V BAT t LW UFilter PULL-DOW N PULL-UP RxD / RxEN V IO INH V BAT www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 18 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.8 System Description Figure 9. State Diagram NORMAL Output: Input: EN = 1 INH1 = 1 STBN = 1 INH2 = 1 EN=1 WHILE (STBN=1) EN=0 WHILE (STBN=1) RECEIVE ONLY Output: Input: EN = 0 INH1 = 1 STBN = 1 INH2 = 1 STBN=1 WHILE (EN=1) WH _V VR ILE EC CC STBN = 1 WHILE (EN=1) OR WAKE WHILE (EN=1 AND STBN=1) OR VREC_VBAT WHILE (EN=1 AND STBN=1) OR VREC_VIO WHILE (EN=1 AND STBN=1) WAKE WHILE (EN=1 AND STBN=0) AN DS WH ILE OR TBN =1 (EN )T =1 HE AN N( VR DS EC TB _V N= CC ) 1) (EN UV_VCC =1 GO-TO-SLEEP Output: Input: EN = 1 INH1 = 1 STBN = 0 INH2 = float EN=0 WHILE (STBN=0) OR UV_VCC STANDBY Output: Input: EN = 0 INH1 = 1 STBN = 0 INH2 = float WAKE WHILE (EN=0 AND STBN=0) OR UV_VCC WHILE (EN=0 AND STBN=0) OR VREC_VCC WHILE (EN=0 AND STBN=0) OR WHILE (UV_VCC) EN=1 WHILE (STBN=0) OR WAKE WHILE (EN=1 AND STBN=0) OR VREC_VCC WHILE (EN=1 AND STBN=0) WAKE WHILE (EN=1 AND STBN=0) OR VREC_VBAT WHILE (EN=1 AND STBN=0) OR VREC_VIO WHILE (EN=1 AND STBN=0) UV _ VI Timer = tSLEEP ) =0 BN ) ST =0 D = N BN N (E R 0 A ST D LE O (EN= AN HI C) W VC LE OR N=0 E HI V_ (E R W (U AK T W ILE O ILE BA H H _V W W EC IO VR IO _V _V EC EC VR VR ND 0A B ST O W HI LE 0) N= POWER OFF STBN=1 WHILE (EN=0) OR WAKE WHILE (EN=0 AND STBN=1) OR VREC_VBAT WHILE (EN=0 AND STBN=1) OR VREC_VIO WHILE (EN=0 AND STBN=1) SLEEP Output: Input: EN = x INH1 = float STBN = 0 INH2 = float UV_VBAT THEN (RESET_WAKE) OR UV_VIO THEN (RESET_WAKE) UV_VBAT WHILE (UV_VCC) OR UV_Vcc WHILE (UV_VBAT) From any State (except Power Off) (EN=0 OR EN=1) OR (STBN=1 OR STBN=0) WHILE (UV_VBAT OR UV_VIO) OR UV_VBAT OR UV_VIO OR UV_VCC OR VREC_VCC Note: This state diagram does not include all transitions, which are shown in Table 7 Prefix of “WHILE” is an event and suffix in brackets checks the flags or in case of EN and STBN the input condition. For example: VREC_VBAT WHILE (EN=0 AND STBN=0) After the event VBAT supply voltage recovery is detected, the transition is performed if EN and STBN are “low”. Legend: UV_VBAT: Undervoltage event and/or flag for VBAT supply voltage UV_VIO: Undervoltage event and/or flag for VIO supply voltage UV_VCC: Undervoltage event and/or flag for VCC supply voltage VREC_VBAT: Voltage recovery event and/or flag for VBAT supply voltage VREC_VIO: Voltage recovery event and/or flag for VIO supply voltage VREC_VCC: Voltage recovery event and/or flag for VCC supply voltage Wake: Wake event and/or flag www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 UV_VBAT WHILE (UV_VCC) VREC_VBAT (U V _V CC ) STBN=0 WHILE (EN=0) OR UV_VCC WHILE WA KE STBN=1 WHILE (EN=0) OR WAKE WHILE (EN=0 AND STBN=1) OR VREC_VCC WHILE (EN=0 AND STBN=1) STBN=0 WHILE (EN=1) 19 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.9 Fail Silent Behavior 8.9.1 8.9.2 RxEN / BGE timeout State Transitions due to Under Voltage Detection In case no edges on RxEN and BGE within tTxEN_timeout are detected, the transmitter will stop transmitting the signals on RxD to the bus pins. In case of VBAT or VIO undervoltage is detected, SLEEP mode will be entered regardless the status of EN and STBN. In case VCC undervoltage is detected, STANDBY mode will be entered regardless the status of EN and STBN. VBAT and VIO undervoltage detection have higher priority than VCC undervoltage detection. In case undervoltage at VBAT and VCC is detected, POWER-OFF mode is entered (bus state: Idle_HZ). 8.9.3 State Transitions due to Voltage Recovery Detection If the voltage recovers the device will enter the mode selected by the EN and STBN pins, in case no undervoltage is present at the other supply pins. Starting from the POWER-OFF, the device enters the state selected by the host input pins (EN, STBN) only if VBAT or VCC recovers (VBAT ≥ VBATTHH or VCC ≥ VCCTHH) while VIO is available (undervoltage flag of VIO flag not set). If the VIO undervoltage flag is set, the STANDBY mode will be entered. In both cases the Power-On flag is set. If VBAT ≤ VBATTHL and VCC ≤ VCCTHL the device will be in POWER-OFF state, thus the bus wires are not terminated (bus state: Idle_HZ). 8.10 Mode Transitions In case of power-off event, the device enters POWER-OFF regardless VIO undervoltage flag, wake-up flags and regardless the selection at the host input pins. Starting from the POWER-OFF the device enters STANDBY only in case a power on event occurs. Starting from every operating mode the device enters SLEEP in case VBAT or VIO undervoltage flag is set regardless the VCC undervoltage flag, the wake-up flag and the state of the host input pins. Starting from every operating mode except SLEEP the device enters STANDBY in case VCC undervoltage flag is set and VBAT and VIO undervoltage flags are not set, regardless the wake-up flag indication and the host input pins state. Starting from a low-power mode the device enters the operation mode indicated by the host input pins if a wake-up event occurs. In case all the undervoltage flags are reset the operation mode is selected by the wake-up flag and the host pins according to Table 6. Table 6. Pin Signalling and Operating modes Inputs STBN EN Operation Mode OutPut RxD L Bus = Data_0 H Bus = Idle or Data_1 L Bus = Data_0 H Bus = Idle or Data_1 NOT [Wake-up flag] NOT [Wake-up flag] NOT [Wake-up flag] H ERRN RxEN L Bus = Active H Bus = Idle L Bus = Active H Bus = Idle NOT [Wake-up flag] NOT [Wake-up flag] NOT [Wake-up flag] H INH1 INH2 H H NORMAL NOT [Error flag] H H H L RECEIVE-ONLY NOT [Error flag] H H L L L X H L X X GO-TO-SLEEP STANDBY SLEEP POWER-OFF NOT [Wake-up flag] NOT [Wake-up flag] NOT [Wake-up flag] L H H Floating Floating Floating Floating Floating Floating Where: H = Digital level high L = Digital level low x = Do not care www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 20 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Floating = The Analog output is not driven Note: If GO-TO-SLEEP is selected for more than tSLEEP then the device will enter SLEEP only if the wake-up flag is not set otherwise it will remain in GO-TO-SLEEP. If wake-up flag is set INH2=H otherwise INH2=floating. Starting from SLEEP, if the wake-up flag is set, the device enters STANDBY regardless the host pins state and UV flags. Starting from SLEEP, if the wake-up flag is not set, the only operating mode that can be entered through host pins are the non-low-power modes. 8.10.1 Operating Mode Transitions Table 7. Transition Table Transition Start Point Destination RECEIVE-ONLY STANDBY NORMAL GO-TO-SLEEP SLEEP NORMAL RECEIVEONLY STANDBY SLEEP NORMAL Event S U S U U S S U U U U W S RECEIVE-ONLY U W S S GO-TO-SLEEP U STANDBY W U SLEEP U U W U STANDBY U S S L (1) L→H (1) L→H L L L L L L L L L (1) L→H L L L L L (2) H→L L H L (2) X→L (1) L→H (1) H→L H H (1) L→H (2) X→L L (2) X→L (1) L→H (2) X→L L L L L L X L L L L (1) L↔H X H L X L L L L X (1) L↔H L L (1) H→L L L H Under Voltage Flag VIO L L L (1) L→H L L L L (1) L→H L L L L L L L L VBAT L L L L (1) L→H L L L L (1) L→H L L L L L L L L L (1) L→H L L (1) H→L (2) H→L L (1) H→L (2) H→L L L VCC L (1) L→H L L Wake Flag X (2) X→L (2) X→L (2) X→L (2) X→L X (2) X→L (2) X→L (2) X→L (2) X→L L (1) L→H X L (1) L→H L H Host Input STBN H H (1) H→L H H H (1) H→L H H H H H (1) L→H H H L L EN (1) H→L H H H H (1) L→H L L L L H H L L L (1) L→H (1) L→H sleep timer enabled sleep timer disabled sleep timer enabled sleep timer disabled sleep timer enabled Remarks www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 21 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 7. Transition Table Transition Start Point Destination NORMAL STANDBY GO-TO-SLEEP SLEEP Event S S U S U U GO-TO-SLEEP W S NORMAL W U U S RECEIVE-ONLY W U U W STANDBY SLEEP U U U W GO-TO-SLEEP U U S S S SLEEP S U U U Under Voltage Flag VIO L L L L (1) L→H L L L (2) X→L L (1) H→L L (2) X→L L (1) H→L (2) X→L L (1) H→L (1) H→L (2) X→L L (1) H→L X H L H X (1) L→H L VBAT L L L L L (1) L→H L L (2) X→L (1) H→L L L (2) X→L (1) H→L L (2) X→L (1) H→L L L (2) X→L (1) H→L L X L H H (1) L→H X L VCC L L (1) L→H L L L L L (2) X→L L L L (2) X→L L L (2) X→L L L H (2) X→L L L X X L L L X (1) L↔H Wake Flag X X (2) X→L L (2) X→L (2) X→L (1) L→H L (1) L→H L L L (1) L→H L L (1) L→H L L L (1) L→H L L L L L L L L L Host Input STBN (1) L→H L L L L L L (1) L→H H H H (1) L→H H H H L L L X L L L X (1) L↔H (1) L↔H (1) L↔H X X X EN H (1) H→L H H H H H H H H H L H L L L L L X H H H (1) L↔H X X X X X X sleep timer disabled sleep timer disabled sleep timer disabled sleep timer disabled t≥tSLEEP Remarks Note: S = transition forced via EN, STBN; U = transition forced via undervoltage or voltage recovery; W = transition forced via WAKE (1) Indicates the action, that initiates the transition (2) Indicates the consequence after performed transition (3) In case the wake flag is set, it is not possible to enter SLEEP mode through a Sleep command, requested by the host. (4) In case an undervoltage on VBAT and VCC is detected, the device enters the POWER-OFF state. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 22 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.10.2 ERRN Signalling The ERRN signalling is shown in Table 8. Table 8. ERRN signalling SUPPLY VOLTAGE FLAG EVENT VIO L L L L L L L L H RWAKE FLAG X H L L L L→H H L→H X LWAKE FLAG X X X L L→H L L→H H X HOST COMMAND STBN H H H L L L L L X EN H L L X X X X X X ERRN Not failure If rising edge at EN, then NOT [error flag] else L If rising edge at EN, then NOT [error flag] else H H H→L H→L L L L 8.11 Loss of ground Whenever a loss of ground is detected, the bus lines are switched Idle_HZ with the precondition that the host pins are open. Either error or no error can be indicated on the ERRN pin. 8.12 Error Flags Description 8.12.1 Undervoltage UVVBAT_DET: The VBAT undervoltage flag is set if the VBAT voltage falls below VBATTHL for longer than tUV_DETECT and is reset if the VBAT voltage reaches a voltage level higher than VBATTHH for longer than tUV_DETECT. UVVIO_DET: The VIO undervoltage flag is set if the VCC voltage falls below VCCTHL for longer than tUV_DETECT and is reset if the VCC voltage reaches a voltage level for longer than VCCTHH after tUV_DETECT. UVVCC_DET: The VCC undervoltage flag is set if the VIO voltage falls below VIOTHL for longer than tUV_DETECT and is reset if the VIO voltage reaches a voltage level higher than VIOTHH for longer than tUV_DETECT. 8.12.2 Bus Error (BUSERR) The bus error flag is set if 2 consecutive rising edges on the TxD pin without any rising edge on the RxD pin are detected or if 2 consecutive falling edges on the TxD pin without any falling edge on the RxD pin are detected. This flag is reset if a rising edge on the TxD pin is followed by a rising edge on RxD pin before the next TxD rising edge or if a falling edge on the TxD pin is followed by a falling edge on RxD pin before the next TxD falling edge. This flag can be set or reset only in NORMAL mode when the transmitter is enabled. The flag is reset at POWER-OFF. 8.12.3 BP Open Line (BP_OL) The BP_OL can only be set/reset in NORMAL mode if the driver is enabled. The flag is set if the absolute current at BP is lower than ITHL during transmission of Data0 and Data1 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and if the absolute current at BP is higher than ITHL during transmission of Data0 and Data1 for a time longer than tBUS_ERROR. 8.12.4 BM Open Line (BM_OL) The BM_OL can only be set/reset in NORMAL mode if the driver is enabled. The flag is set if the absolute current at BM is lower than ITHL during transmission of Data0 and Data1 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and if the absolute current at BM is higher than ITHL during transmission of Data0 and Data1 for a time longer than tBUS_ERROR. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 23 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.12.5 BP Short Circuit to VCC (BP_VCC) The BP_VCC can only be set/reset in NORMAL mode if the driver is enabled while Data0 and Data1 are transmitted for longer than tBUS_ERROR. The flag is set if the absolute current at BP is lower than ITHL during transmission of Data1 longer than tBUS_ERROR and if the absolute current at BP is higher than ITHH during transmission of Data0 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and in case the setting conditions are not fulfilled. 8.12.6 BP Short Circuit to GND (BP_GND) The BP_GND can only be set/reset in NORMAL mode if the driver is enabled while Data0 and Data1 are transmitted for longer than tBUS_ERROR. The flag is set if the absolute current at BP is higher than ITHH during transmission of Data1 longer than tBUS_ERROR and if the absolute current at BP is lower than ITHL during transmission of Data0 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and in case the setting conditions are not fulfilled. 8.12.7 BM Short Circuit to VCC (BM_VCC) The BM_VCC can only be set/reset in NORMAL mode if the driver is enabled while Data0 and Data1 are transmitted for longer than tBUS_ERROR. The flag is set if the absolute current at BM is lower than ITHL during transmission of Data0 longer than tBUS_ERROR and if the absolute current at BM is higher than ITHH during transmission of Data1 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and in case the setting conditions are not fulfilled. 8.12.8 BM Short Circuit to GND (BM_GND) The BM_GND can only be set/reset in NORMAL mode if the driver is enabled while Data0 and Data1 are transmitted for longer than tBUS_ERROR. The flag is set if the absolute current at BM is higher than ITHH during transmission of Data0 longer than tBUS_ERROR and if the absolute current at BM is lower than ITHL during transmission of Data1 for a time longer than tBUS_ERROR. The flag is reset in POWER-OFF mode and in case the setting conditions are not fulfilled. 8.12.9 Short Circuit between BP and BM (BP_BM) The BP_BM can only be set or reset in NORMAL mode while the driver is active (edge at TxEN) for a time longer than tBUS_ERROR. The flag is set if the absolute value of the differential voltage is lower than VSHORT for a time tBUS_ERROR. The flag is reset in POWER-OFF mode and if the set condition is not fulfilled. 8.12.10 Over Temperature (OT) This flag can only be set or reset in the non-low-power modes. The flag is set if the junction temperature exceeds OTTH and it is reset if the junction temperature falls below OTTL. 8.12.11 TxEN_BGE Timeout (TxEN_TO) This flag can only be set in NORMAL mode if the driver is enabled (TxEN is low and BGE is high) for a time longer than tTxEN_max. It is reset during transition on TxEN or BGE or if the device exits NORMAL mode. If the flag is set the driver is disabled. 8.12.12 Error Flag (ERROR) The ERROR is signalled on the ERRN pin according to Table 6 and Table 8. The flag is set if at least one of the error flags in chapters 8.12.2 to 8.12.11 is set. The flag will be reset if none of the flags in chapters 8.12.2 to 8.12.11 is set. 8.13 Status Flags Description 8.13.1 Local Wake Flag (LWAKE) See chapter 8.7 Wake-Up Events on page 17 8.13.2 Remote Wake Flag (RWAKE) see chapter 8.7 Wake-Up Events on page 17 www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 24 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.13.3 Power on Flag (PWON) The PWON is set leaving the POWER-OFF state and it is reset entering a low-power mode after a non-low-power mode. 8.14 Error Flags and Status Flags Read-Out The readout mechanism consists of two information groups: 5. Error read-out 6. Status information read-out The read-out mechanism as serial transmission on Pin EN and ERRN: Table 9. Read-out Mechanism and Transceiver States State NORMAL mode RECEIVE-ONLY mode STANDBY mode GO-TO-SLEEP mode SLEEP mode Enabled/Disabled Enabled Enabled Disabled Disabled Disabled The error flags and the status flags can be read-out by applying a clock signal to pin EN in a non-low-power mode. A falling edge on pin EN starts the read-out loading the content of the error/status flag into the shift register and signaling the error flag on the ERRN pin. On the second falling edge the first flag (Bit 0) will be shifted out. The ERRN data is valid after tRO_EN_ERRN. If EN pin keeps on toggling after the last flag (Bit 15) the next flag again is Bit 0. The complete list of bits is shown in Table 10. If no transition is detected on pin EN for longer than tRO_EN_TIMEOUT the device enters the operation mode selected by the host pins. Figure 10. Timing of the read-out mechanism EN 50% V IO ERRN 50% V IO ERRN ERROR FLAG tRO_EN_ERRN Bit 0 Bit 1 Bit 2 ERRN t < tRO_EN_TIMEOUT t > tRO_EN__TIMEOUT 8.14.1 Error and Status Flag Bit Order Table 10. Bit order for the read-out sequence Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Description Undervoltage VBAT detected Undervoltage VIO detected Undervoltage VCC detected Bus error BP open line BP short circuit to VCC BP short circuit to GND Symbol UVVBAT_DET UVVIO_DET UVVCC_DET BUSERR BP_OL BP_VCC BP_GND www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 25 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 10. Bit order for the read-out sequence Bit Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Description BM open line BM short sourced to VCC BM short sourced to GND Short circuit between BP and BM Over temperature TxEN_BGE timeout Local wake flag Remote wake flag Power on flag Symbol BM_OL BM_VCC BM_GND BP_BM OT TxEN_TO LWAKE RWAKE PWON When the read-out mechanism is started, the first data information is the Bit 0 until Bit 15 is transmitted. Any re-initiation or repetitions is started with the first data Bit 0. 8.15 Bus Driver 8.15.1 Bus States Activity: The bus wires reflects the differential signal specified in chapter 8.17 Transmitter on page 28. Idle: The bus wires are terminated to VCC/2 via. receiver input resistances. Idle_LP: The bus wires are terminated to GND via receiver input resistances. Idle_HZ: The bus wires are not terminated to VCC/2 via. 1MΩ www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 26 - 43 AS8221 tTxD_BUS01 tTxD_BUS10 tBGE_BUS_Idle_Active tTxEN_BUS_Idle_Active Figure 11. Timing Diagram 8.16 Transceiver Timing Data Sheet - D e t a i l e d D e s c r i p t i o n TxD tBGE_BUS_Active_Idle tTxEN_BUS_Active_Idle 0.5 * VIO www.austriamicrosystems.com/flexray/AS8221 80 % tBUS_Idle_Active 30 mV -300 mV -300 mV 30 mV -300 mV 20 % tBUS_Active_Idle tBUS_RxD10 tBUSIdleReaction tBUSActivityReaction tBUS01 tBUS10 BGE 0.5 * VIO TxEN 0.5 * VIO Revision 1.1 300 mV VBUS RxD 0.5 * VIO RxEN 0.5 * VIO 27 - 43 tBUS_RxD01 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.17 Transmitter The transmitter generates out of a digital input signal on TxD the FlexRay differential bus voltage. The transmitter is only active in NORMAL mode if BGE is on logical high and TxEN is on logical low. Figure 12. Transmitter characteristics (TxD → BUS) V TxD 50% * VIO Data1: x * tBIT Data0: x * tBIT V BUS tTxD_BUS01 V BUS_DIFF_D1 80% * V BUS_DIFF_D1 300 mV + V BUS_DIFF_Idle - V BUS_DIFF_Idle tTxD_BUS10 tBUS01 tBUS10 - 300 mV 20% * V BUS_DIFF_D1 V BUS_DIFF_D0 Data1: x * tBIT Data0: x * t BIT Figure 13. Transmitter characteristics (TxEN → BUS) VTxEN 50% * VIO < tTxEN_timeout < tTxEN_timeout VBUS tTxEN_BUS_Active_Idle VBUS_DIFF_D1 300 mV + VBUS_DIFF_Idle - VBUS_DIFF_Idle tTxEN_BUS_Idle_Active tBUS_Active_Idle tBUS_Idle_Active - 300 mV VBUS_DIFF_D0 www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 28 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 14. Timing characteristics (BGE → BUS) VBGE 50% * VIO VBUS tBGE_BUS_Active_Idle VBUS_DIFF_D1 300 mV + VBUS_DIFF_Idle - VBUS_DIFF_Idle tBGE_BUS_Idle_Active tBUS_Active_Idle tBUS_Idle_Active - 300 mV VBUS_DIFF_D0 In NORMAL and RECEIVE-ONLY mode the transmitter drives on the bus Idle in case no data are transmitted. In STANDBY, GO-TO-SLEEP and SLEEP mode the transmitter drives Idle_LP on the bus pins. In POWER-OFF mode the bus pins shows Idle_HZ. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 29 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.18 Receiver The Receiver generates from the FlexRay differential bus voltage a digital signal on the RxD and RxEN pins. RxD shows the data (Data0 and Data1) and RxEN shows the bus idle and activity status received on the bus pins. The Receiver is only active in NORMAL and RECEIVE-ONLY mode. Figure 15. Timing characteristics of the bus signals to RxD and RxEN VBUS VBUSActiveHigh VData1 + VBUS_DIFF_Idle - VBUS_DIFF_Idle 300 mV VBUSActiveLow VData0 Data0: x * tBIT Data1: x * tBIT - 300 mV VRxEN tBUSActivityReaction tBUSIdleReaction 50% * VIO VRxD tBUS_RxD10 tBUS_RxD01 tRxD_RISE tRxD_FALL 80% * VIO 50% * VIO 20% * VIO 8.18.1 Bus Activity and Idle Detection (only in NORMAL and RECEIVE-ONLY mode) If the absolute differential bus voltage is higher than VBUSActiveLow and less than VBUSActiveHigh for a time longer than tBUSIdleDetection, bus Idle is detected, RxEN and RxD are switched to logical high after a time tBUSIdleReaction. If the absolute differential bus voltage is higher than VBUSActiveHigh or lower than VBUSActiveLow for a time loner than tBUSActivitiyDetection, bus Activity is detected, RxEN is switched to logical low and RxD shows the detected bus data according to Table 11 after the time tBUSActivityReaction. Table 11. Logic table for Receiver bus signal detection Receiver Operation mode Normal power modes (NORMAL and RECEIVE-ONLY mode) Bus signals Idle Data0 Data1 RxEN H L L RxD H L H 8.18.2 Bus Data Detection (only in NORMAL and RECEIVE-ONLY mode) If, after activity detection the differential bus voltage is higher than VData1, RxD will be high after a time tBUS_RxD01. If, after activity detection the differential bus voltage is lower than VData0, RxD will be low after a time tBUS_RxD10. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 30 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 16. Receiver characteristics (BUS → RxD, RxEN) VRxD VBUS VRxEN VBUS VBUS VBUSActiveLow VData0 Data0 Activity VBUSActiveHigh VData1 Data1 Activity VBUS Idle www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 31 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.18.3 Receiver Test Signal Figure 17. Receiver test signal V BUS 400 mV 22 ns 22 ns 300 mV -300 mV -400 mV tBIT RxD tBUS_RxD01 tBUS_RxD10 V BUS 400 mV 22 ns 22 ns 300 mV -300 mV -400 mV tBIT RxD tBUS_RxD10 tBUS_RxD01 www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 32 - 43 AS8221 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.19 Test Circuits Figure 18. Test Circuit for Automotive Transients ISO 7637 PULSE GENERATOR 10uF +5V 12V or 42V 100nF 14 VBAT 19 VCC 4 VIO RXD Transients in accordance with ISO7637: test pulses 1, 2, 3a, 3b, 4, 5 Test conditions: Normal mode bus idle, Normal mode bus active (TXD=5 MHz, TXEN=1kHz) 7 15pF AS8221 BP 18 1nF ISO 7637 PULSE GENERATOR BM 17 RL CL 1nF Figure 19. Test circuit for dynamic characteristics +12V 10uF +5V 100nF 14 VBAT 19 VCC 4 VIO 7 RXD 15pF AS8221 BP 18 BM 17 RL CL www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 33 - 43 AS8221 Data Sheet - A p p e n d i x 9 Appendix 9.1 FlexRay Functional Classes The AS8221 FlexRay Standard Transceiver has the following Bus Driver functional classes according the FlexRay Electrical Physical Layer Specification V2.1 Rev. B implemented: Functional Class: Chapter 8.13.1 “Bus Driver voltage regulator control” Functional Class: Chapter 8.13.2 “Bus Driver - Bus Guardian interface” Functional Class: Chapter 8.13.4 “Bus Driver logic level adaptation” 9.2 FlexRay Parameter Comparison The following table shows the comparison of conventions used in AS8221 datasheet and FlexRay Electrical Physical Layer Specification V2.1 Rev. B. Table 12. Comparison table AS8221 Datasheet Symbol Absolute Maximum Ratings Supply Voltage TAMB VCC - VIO IBAT ICC Ambient temperature Difference of supplies VBAT current consumption VCC current consumption T Ambient temperature Battery Supply Voltage (VBAT) Supply Voltage (VCC) Supply Voltage (VIO) DC Voltage at EN, STBN, ERRN, TxD, RxD, TxEN, BGE, RxEN DC Voltage on pin WAKE, INH1, INH2 DC Voltage at BP and BM Input current (latchup immunity) Electrostatic discharge at bus lines BP, BM, VBAT, WAKE Electrostatic discharge Transient voltage on BP, BM Transient voltage on VBAT Total power dissipation (all supplies and outputs) Storage temperature Junction temperature Package body temperature Humidity non-condensing uESDExt uESDint ESD protection on pins that lead to ECU external terminals ESD on all other pins Parameter FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name Description www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 34 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol IIO State Transitions tSTBN_RxD tSTBN_RxEN tSLEEP_INH1 tSTANDBY_INH2 tSLEEP Transmitter VBUS_DIFF_D0 VBUS_DIFF_D1 Differential bus voltage low in NORMAL mode (Data0) Differential bus voltage high in NORMAL mode (Data1) Matching between Data0 and Data1 differential bus voltage in NORMAL mode uBDTxactive uBDTxactive Absolute value of uBus while sending Absolute value of uBus while sending Delay STBN high to RxD high with wake flag set Delay STBN high to RxEN high with wake flag set Delay STBN high to INH1 high Delay STBN high to INH2 high GO-TO-SLEEP hold time Parameter VIO current consumption FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name Description - VBUS_DIFF - - VBUS_COM_D0 Common mode bus voltage in case of Data0 in non-low-power modes Common mode bus voltage in case of Data1 in non-low-power modes Matching between Data0 and Data1 common mode voltage Absolute differential bus voltage in idle mode Absolute max current when BP is shorted to BM Absolute max current when BP is shorted to GND Absolute max current when BM is shorted to GND Absolute max current when BP is shorted to -5 V Absolute max current when BM is shorted to 5V Absolute max current when BP is shorted to 27 V Absolute max current when BM is shorted to 27 V - - VBUS_COM_D1 - - ΔVBUS_COM VBUS_DIFF_Idle IBPBMShortMax IBMBPShortMax IBPGNDShortMax IBMGNDShortMax IBP-5VShortMax IBM-5VShortMax IBP27VShortMax IBM27VShortMax uBDTxidle IBPBMShortMax IBMBPShortMax IBPGNDShortMax IBMGNDShortMax IBP-5VShortMax IBM-5VShortMax IBPBAT27VShortMax IBMBAT27VShortMax Absolute value of uBus, while Idle Absolute maximum output current when BP shorted to BM Absolute maximum output current when shorted to GND Absolute maximum output current when shorted to GND Absolute maximum output current when shorted to -5V Absolute maximum output current when shorted to -5V Absolute maximum output current when shorted to 27V Absolute maximum output current when shorted to 27V www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 35 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol IBP48VShortMax IBM48VShortMax tTxD_BUS01 tTxD_BUS10 tTxD_MISMATCH tBUS10 tBUS01 tTxEN_BUS_Idle_Active tTxEN_BUS_Active_Idle tTxEN_MISMATCH tBGE_BUS_Idle_Active tBGE_BUS_Active_Idle tBUS_Idle_Active tBUS_Active_Idle tTxEN_timeout Receiver RBP, RBM RDIFF VBPidle, VBMidle VBPidle_low, VBMidle_low IBPidle IBMidle IBPleak, IBMleak BP, BM input resistance BP, BM differential input resistance Idle voltage in non-low-power modes on pin BP,BM Idle voltage in low-power modes on pin BP, BM Absolute idle output current on pin BP Absolute idle output current on pin BM Absolute leakage current, when not powered RCM1, RCM2 uBias uBias iBPLeak, iBMLeak Receiver common mode input resistance Bus bias voltage during BD_Normal mode Bus bias voltage during low-power modes Absolute leakage current, when not powered Parameter Absolute max current when BP is shorted to 48 V Absolute max current when BM is shorted to 48 V Delay time from TxD to BUS positive edge Delay time from TxD to BUS negative edge Delay time from TxD to BUS mismatch Fall time differential bus voltage Rise time differential bus voltage Delay time from TxEN to bus active Delay time from TxEN to bus idle Delay time from TxEN to bus mismatch Delay time from BGE to bus active Delay time from BGE to bus idle Differential bus voltage transition time: idle to active Differential bus voltage transition time: active to idle TxEN timeout FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name IBPBAT48VShortMax IBMBAT48VShortMax dBDTx10 dBDTx01 dTxAsym dBusTx10 dBusTx01 dBDTxia dBDTxai dBDTxDM dBDTxia dBDTXai dBusTxia dBusTxai Description Absolute maximum output current when shorted to 48V Absolute maximum output current when shorted to 48V Transmitter delay, negative edge Transmitter delay, positive edge Transmitter delay mismatch | dBDTx10 - dBDTx01 | Fall time differential bus voltage (80% ® 20%) Rise time differential bus voltage (20% ® 80%) Propagation delay idle ®active Propagation delay active ® idle | dBDTxia - dBDTxai | Propagation delay idle ® active Propagation delay active ® idle Transition time idle ® active Transition time active → idle - www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 36 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol VBUSActiveHigh VBUSActiveLow VData1 VData0 VDataErr Parameter Activity detection differential input voltage high Activity detection differential input voltage low Data1 detection differential input voltage Data0 detection differential input voltage Mismatch between Data0 and Data1 differential input voltage Max. common mode voltage range when receiving Delay from bus to RxD negative edge Delay from bus to RxD positive edge Bit time Delay time from bus to RxD mismatch Fall time RxD voltage Rise time RxD voltage Idle detection time Activity detection time Idle reaction time Activity reaction time FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name uBusActiveHigh uBusActiveLow uData1 uData0 uData Description Upper Receiver threshold for detecting activity Lower Receiver threshold for detecting activity Receiver threshold for detecting Data_1 Receiver threshold for detecting Data_0 Mismatch of Receiver thresholds VRECEIVE_COM tBUS_RxD10 tBUS_RxD01 tBIT tRxD_ASYM tRxD_FALL tRxD_RISE tBUSIdleDetection tBUSActivityDetection tBUSIdleReaction tBUSActivityReaction Wake-Up Detector tBWU_D0 uCM dBDRx10 dBDRx01 dRxAsym dRxSlope dRxSlope dIdleDetection dActivityDetection dBDRxai dBDRxia Common mode voltage range (with respect to GND) that does not disturb the receive function Receiver delay, negative edge Receiver delay, positive edge Receiver delay mismatch | dBDRx10 – dBDRx01 | Fall and rise time 20%-80% Fall and rise time 20%-80% Filter-time for idle detection Filter-time for activity detection Idle reaction time Activity reaction time Data0 detection time in remote wake-up pattern Idle or Data1 detection time in remote wakeup pattern dWU0Detect Acceptance timeout for detection of a Data_0 phase in wake-up pattern Acceptance timeout for detection of a Idle phase in wake-up pattern Acceptance timeout for wake-up pattern recognition - tBWU_Idle dWUIdleDetect tBWU_Detect VBWUTH VLWUTH Total remote wake-up detection time Bus wake-up detection threshold Local wake-up detection threshold dWUTimeout - www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 37 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol ILWUL ILWUH tLWUFilter Supply Voltage Monitor VBATTHH VBATTHL VCCTHH VCCTHL VIOTHH VIOTHL tUV_DETECT tUV_REC Bus Error Detection ITHL ITHH VSHORT Absolute bus current for low current detection Absolute bus current for high current detection Differential voltage on BP and BM for detecting short circuit between bus lines Bus error detection time Detection only required while actively transmitting a data frame, error indication to host latest when transmission stops. VBAT undervoltage recovery threshold VBAT undervoltage detection threshold VCC undervoltage recovery threshold VCC undervoltage detection threshold VIO undervoltage recovery threshold VIO undervoltage detection threshold Detection time for undervoltage at VBAT, VCC, VIO Detection time for undervoltage recovery at VBAT, VCC, VIO uUVBAT uUVCC uUVIO dUVBAT, dUVCC, dUVIO Undervoltage detection threshold Undervoltage detection threshold Undervoltage detection threshold Undervoltage reaction time Parameter Low level input current on local WAKE pin High level input current on local WAKE pin Local wake filter time VBAT operating range VBAT = +6.5 to + 50V FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name dWakePulseFilter Description Wake pulse filter time (spike rejection) VBAT for WU detector Battery voltage required for wake-up detector operation tBUS_ERROR Over Temperature OTTH OTTL - Over temperature threshold Over temperature hysteresis - www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 38 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol Power Supply Interface ΔVOINH | IIL | Communication Controller Interface VTxDIH Threshold for detecting TxD as on logical high uVIO-IN-HIGH Threshold for detecting a digital input as on logical high Threshold for detecting a digital input as on logical low Threshold for detecting a digital input as on logical high Threshold for detecting a digital input as on logical low Output voltage on a digital output, when in logical high state Output voltage on a digital output, when in logical low state High level voltage drop on INH1, INH2 Leakage current Parameter FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name Description VTxDIL ITxDIH ITxDIL VTxENIH Threshold for detecting TxD as on logical low TxD high level input current TxD low level input current Threshold for detecting TxEN as on logical high Threshold for detecting TxEN as on logical low TxEN high level input current TxEN low level input current RxD high level output voltage uVIO-IN-LOW uVIO-IN-HIGH VTXENIL ITxENIH ITxENIL VRxDOH uVIO-IN-LOW uVIO-OUT-HIGH VRxDOL Host Interface VSTBNIH RxD low level output voltage uVIO-OUT-LOW Threshold for detecting STBN as on logical high Threshold for detecting STBN as on logical low STBN high level input current STBN low level input current STBN de-bouncing time low-power modes STBN de-bouncing time non-low-power modes Threshold for detecting EN as on logical high uVIO-IN-HIGH Threshold for detecting a digital input as on logical high Threshold for detecting a digital input as on logical low Threshold for detecting a digital input as on logical high VSTBNIL ISTBNIH ISTBNIL tSTBN_DEB_LP tSTBN_DEB_NLP VENIH uVIO-IN-LOW uVIO-IN-HIGH www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 39 - 43 AS8221 Data Sheet - A p p e n d i x Table 12. Comparison table AS8221 Datasheet Symbol VENIL IENIH IENIL tEN_DEB_LP tEN_DEB_NLP VERRNOH Parameter Threshold for detecting EN as on logical low EN high level input current EN low level input current EN de-bouncing time low-power modes EN de-bouncing time non-low-power modes ERRN high level output voltage FlexRay Electrical Physical Layer Specification V2.1 Rev. B Name uVIO-IN-LOW uVIO-OUT-HIGH Description Threshold for detecting a digital input as on logical low Output voltage on a digital output, when in logical high state Output voltage on a digital output, when in logical low state VERRNOL Bus Guardian Interface VBGEIH ERRN low level output voltage uVIO-OUT-LOW Threshold for detecting BGE as on logical high uVIO-IN-HIGH Threshold for detecting a digital input as on logical high Threshold for detecting a digital input as on logical low Output voltage on a digital output, when in logical high state Output voltage on a digital output, when in logical low state VBGEIL IBGEIH IBGEIL VRXENOH Threshold for detecting BGE as on logical low BGE high level input current BGE low level input current RxEN high level output voltage uVIO-IN-LOW uVIO-OUT-HIGH VRXENOL Read Out Interface tRO_EN_ERRN tRO_EN_TIMEOUT RxEN low level output voltage uVIO-OUT-LOW Propagation delay falling edge EN to ERRN error-read-out time out - - www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 40 - 43 AS8221 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings Figure 20. AS8221 SSOP20 package Diagram Table 13. package Dimensions Symbol Min A 1.73 A1 0.05 A2 1.68 b 0.25 b1 0.25 C 0.09 C1 0.09 D E 5.20 e H 7.65 L 0.63 Typ 1.86 0.13 1.73 0.30 0.15 See Variations 5.30 0.65 BSC 7.80 0.75 Max 1.99 0.21 1.78 0.38 0.33 0.20 0.16 5.38 7.90 0.95 Symbol L1 N a R Min 0º 0.09 AA AB AC AD AE AF 6.07 6.07 7.07 8.07 10.07 10.07 Typ 1.25 REF See Variations 4º 0.15 Variations: D 6.20 6.20 7.20 8.20 10.20 10.20 Max 8º 6.33 6.33 7.33 8.33 10.33 10.33 N 14 16 20 24 28 30 Note: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angle is in degrees. 3. N is the total number of terminals. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 41 - 43 AS8221 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Revision History Table 14. Revision History Revision Number 1.0 1.1 Date Sep 01, 2009 Sep 14, 2009 Owner hgl hgl Description first version Made sentence corrections and converted the ‘Typ’ values of Table 3 in to standard format. No Technical Changes to the datasheet. www.austriamicrosystems.com/flexray/AS8221 Revision 1.1 42 - 43 AS8221 Data Sheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information Table 15. Ordering Information Ordering Code AS8221-ASSU AS8221-ASST Marking AS8221 AS8221 Description AS8221 FlexRay Standard Transceiver AS8221 FlexRay Standard Transceiver Delivery Form Tube Tape & Reel Package SSOP20 SSOP20 Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor Copyrights Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. 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