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Datasheet
AS1117
64 LED Driver for Mobile Applications with Error Detection
2 Key Features
The AS1117 is a compact LED driver for 64 single LEDs
or 8 digits of 7-segments. The devices can be programmed via an I²C compatible 2-wire interface. Every
segment can be individually addressed and updated
separately. Only one external resistor (RSET) is required
to set the current. LED brightness can be controlled by
analog or digital means.
3.4MHz
The devices include an integrated BCD code-B/HEX
decoder, multiplex scan circuitry, segment and display
drivers, and a 64-bit memory. Internal memory stores
the shift register settings, eliminating the need for continuous device reprogramming.
200nA
Table 1. Available Products
Supply
AS1115
AS1116
AS1117
AS1118
Individual
LED Segment Control
Readback
for 8 Keys plus Interrupt
and Shorted LED Error Detection
- Global or Individual Error Detection
Hexadecimal-
al
Open
or BCD-Code for 7-Segment
ment Displays
Digital
and Analog Brightness Control
Display
Driv
Drive
lv
Low-Power Shutdown Current (typ;
yp; data
retained)
Blanked on Power-Up
r-Up
Up
C
Common-Cathode
de LED Displays
ic a
al m
co s
nt AG
en
ts
til
Devices
I²C-Compatible Interface
id
1 General Description
RESET Input
Software
Interfaces
no
I²C
no
SPI
yes
I²C
yes
SPI
PI
Voltage
Vo
V
Range:
nge: 2.7V to 5.5V
Up
and Hardware
dware
are Reset
Rese
to 4 devices
ces
es cascadable
ca adable
dable
Op
Optional
O
External
rnal Clock
Cloc
Clo
Package:
age:
TQFN(4x4)TQFN(4x4)-24
3 Applications
Applic
Additionally the AS1117 offers a detailed
d error diagnostic
diagno
mode for easy and fast production testing
esting in critical
critica
critic
applications. The AS1117 featuress a low shutdown
curshutd
shutdo
rrent of typically 200nA, and an operational
erational
rational ccurrent of
typically 350μA. The number of digitss can be proo
grammed, the devices can be reset by software,
re, and an
external clock is also supported.
The AS11
AS
AS1117 is ideal for seven-segment or dot matrix
user interface
int
displays of mobile applications, set-top
boxes, VCRs, DVD-players, washing machines, micro
boxe
wave ovens, refrigerators and other white good or perw
sonal electronic applications.
The device is available in a TQFN(4x4)-24
package.
)-24
24 pac
pack
e
Te
ch
n
Figure 1. AS1117 - Typical Application
plication
ation Diagram
VDD
2.7V to 5.5
5.5V
VDD
9.53k:
9.53
9.
SDA
SCL
μP
IRQ
ISET
SDA
DIG0 to
DIG7
8
SEGA-DP
KEY0-7
8
AS1117
SCL
KEY
IRQ
RESETN
GND
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
1 - 23
AS1117
Datasheet - P i n o u t
4 Pinout
Pin Assignments
18 SEG E
DIG3 2
17 SEGC
GND 3
16 VDD
AS1117
DIG4 4
DIG5 5
15 SEGG
Exposed
Pad
8
9
RESETN
R
RES
10 11 12
14 SEGB
13 SEGF
SEGA
S
SCL
ISET
DIG7
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
il
7
KEY
DIG6 6
al
id
24 23 22 21 20 19
DIG2 1
lv
SEGDP
IRQ
SEGD
SDA
DIG0
DIG1
Figure 2. Pin Assignments (Top View)
Pin Descriptions
Table 2. Pin Descriptions
Pin Name
SDA
Pin Number
22
DIG0:DIG7
1, 2, 4, 5, 6, 7,
23, 24
GND
KEY
3
8
RESETN
9
ISET
10
SCL
IRQ
SEGA:SEGG,
SEGDP
11
21
12-15, 17-20
VDD
16
Exposed
E
Ex
Pad
Description
Descri
Serial-Data
Open drain
al-Data
l-Data I/O.
I/O O
rain digital I/O I²C data pin.
Lines. Eight
lines that sink current from the display
Digit Drive Li
L
ght digit drive lin
cathode. Keyscan
detection optional, but must be polled by the
common cca
can detect
detecti
μProzessor.
μProzes
Ground.
Grou
Keyscan Input.
ut. Keyscan lines for key readback. Can be used for self-adressing.
Resett Input.
In
Pull this pin to low to resest all registers (set to default values) and
to putt the device
d ce into
int shutdown. Connect this pin via a pull-up resistor to VDD for
normal
mal opera
operat
operation.
Set
et Segment Current. Connect to VDD or a reference voltage through RSET to
set the peak
pea segment current (see Selecting RSET Resistor Value and Using
External Drivers on page 19).
Serial-Clock Input. 3.4MHz maximum rate.
Seria
Interupt Request Output. Open drain pin.
In
Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives and
decimal point drive that source current to the display.
Positive Supply Voltage. Connect to +2.7V to +5.5V supply. Bypass this pin to
GND with a 0.1μF capacitor to avoid power supply ripple.
Exposed Pad. This pin also functions as a heat sink. Solder it to a large pad or to
the circuit-board ground plane to maximize power dissipation.
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
2 - 23
AS1117
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Input Voltage Range
Current
Min
Max
Units
VDD to GND
-0.3
7
V
All other pins to GND
-0.3
7 or
VDD + 0.3
V
DIG0:DIG7 Sink Current
500
mA
SEGA:SEGG, SEGDP
100
mA
85
%
Humidity
5
Non-condensing
-condens
-condensin
am
lc s
on A
te G
nt
st
i ll
Digital outputs
Notes
va
lid
Parameter
ESD
All other pins
Latch-Up Immunity
Thermal Resistance 4JA
1
kV
Norm: MIL 833 E method
meth 3015
±100
00
mA
m
EIA/JESD78
EIA/JES
30.5
ºC/W
on
o PCB
Ambient Temperature
-40
0
+85
+8
ºC
C
Storage Temperature
-55
55
150
1
ºC
C
+260
ºC
º
Te
ch
ni
ca
Package Body Temperature
The reflow peak soldering
temperature (body temperature)
specified is in accordance with IPC/
JEDEC J-STD-020D “Moisture/
Reflow Sensitivity Classification for
Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded
packages is matte tin (100% Sn).
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Revision 1.00
3 - 23
AS1117
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7V to 5.5V, RSET = 9.53k:, TAMB = -40°C to +85°C, typ. values @ TAMB = +25ºC and VDD = 5.0V (unless otherwise specified).
Table 4. Electrical Characteristics
Parameter
Conditions
Min
VDD
Operating Supply Voltage
IDDSD
Shutdown Supply Current
IDD
Operating Supply Current
fOSC
Display Scan Rate
8 digits scanned
0.48
IDIGIT
Digit Drive Sink Current
VOUT = 0.65V
320
ISEG
Segment Drive Source Current
ISEG
2.7
All digital inputs at VDD or
GND, TAMB = +25ºC
0.2
RSET = open circuit.
0.35
All segments and decimal
point on; ISEG = -40mA.
335
Max
Unit
5.5
V
2
μA
A
0.6
mA
ni
ca a
l c ms
on A
te G
nt
st
ill
v
'ISEG
Typ
al
id
Symbol
Segment Drive Current Matching
Segment Drive Source Current
VDD = 5.0V, VOUT
UT
T = (VDD -1V)
-35
0
0.96
6
kHz
kH
-47
mA
mA
-41
3
Average Current
ren
%
47
mA
Max
1
Unit
μA
Table 5. Logic Inputs/Outputs Characteristics
VOL(SDA)
Parameter
Input Current SDA, SCL
Logic High Input Voltage
SDA, SCL, RESETN
Logic Low Input Voltage
SDA, SCL, RESETN
SDA Output Low Voltage
tage
age
VKEYopen
Keyscan Open Input Voltage
VKEYshort
VOL(IRQ)
'VI
Keyscan Short Input Voltage
tag
Interrupt Output Low Voltage
ISINK = 3m
3mA
Hysteresis Voltage
DIN, C
CLK, LD/CS
Capacitive Load for Each
h Buss Line
Symbol
IIH, IIL
VIH
VIL
Conditions
Con
VIN = 0V or VDD
Min
-1
Typ
1.26
V
ISINK = 3mA
mA
0.54
V
0.4
V
0.8xVDD
1
0.7x
VDD
0.05x
VDD
Open Detection Level
vel Threshold
reshold
400
0.75x
VDD
0.1x
VDD
V
V
V
pF
0.8x
VDD
0.15x
VDD
V
V
Te
ch
Short Detection
n Level Threshold
Thresho
V
0.7x VDD
0.4
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Revision 1.00
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AS1117
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 6. Timing Characteristics
Symbol
fSCL
tBUF
Conditions
Min
Typ
0.1
Bus Free Time Between STOP and
START Conditions
Hold Time for Repeated
START Condition
SCL Low Period
Max
Unit
3.4
MHz
1.3
μs
160
ns
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
i ll
va
li d
tHOLDSTART
Parameter
SCL Frequency
tLOW
tHIGH
tSETUPSTART
SCL High Period
Setup Time for Repeated
START Condition
50
75
nss
50
75
ns
100
tSETUPDATA Data Setup Time
ns
10
tHOLDDATA
Data Hold Time
tRISE(SCL)
SCL Rise Time
SCL Rise Time after Repeated START
Condition and After an ACK Bit
tFALL(SCL)
ns
n
70
7
ns
10
40
ns
10
0
80
8
ns
SCL Fall Time
10
0
40
ns
tRISE(SDA)
SDA Rise Time
20
80
ns
tFALL(SDA)
SDA Fall Time
20
80
ns
tSETUPSTOP STOP Condition Setup Time
160
16
tRISE(SCL1)
tSPIKESUP Pulse Width of Spike Suppressed
Key Readback
Debounce Time
ns
50
ns
20
ms
Notes:
1. The Min / Max values of the Timing
ming Characteristics
Charac
Charact
are guaranteed
uaranteed by design.
2. All limits are guaranteed. The parameters
are guaranteed with production tests or SQC
pa
arameters
rameter with min and max values
valu
val
(Statistical Quality Control) methods.
ods.
ds
Figure 3. Timing Diagram
SDI
tBUFF
tHOLDSTART
tHIGH
tHOL
HOLDSTART
tR
tLOW
tSPIKESUP
tSETUPDATA
tF
tSETUPSTOP
tSETUPSTART
SCL
START
STOP S
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
tHOLDDATA
Repeated
START
Revision 1.00
5 - 23
AS1117
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
RSET = 9.53k:VRset = VDD;
Figure 5. Display Scan Rate vs. Temperature;
800
780
Vdd=2.7V
Vdd=4V
780
fosc (Hz) .
Vdd=5V
Vdd=5.5V
760
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
va
l
fosc (Hz) .
760
id
Figure 4. Display Scan Rate vs. Supply Voltage;
740
720
740
720
700
Tamb=-40°C
700
Tamb=+25°C
Tamb=+85°C
680
2.7
3.1
3.5
3.9
4.3
Vdd (V)
4.7
5.1
680
68
-40
5.5
Figure 6. Segment Current vs. Temperature;
Vseg
Vseg
Vseg
Vseg
40
0
Iseg (mA) .
40
30
20
Vseg
Vseg
Vseg
Vseg
10
85
= 1.7V; Vdd = 2.7V
= 1.7V; Vdd = 5V
= 3V; Vdd = 5V
= 4V; Vdd = 5V
= 4V; Vdd = 5V
= 3V; Vdd = 5V
= 2V; Vdd = 5V
= 1.7V; Vdd = 2.7V
30
20
10
0
-15
10
35
60
85
0
10
20
Tamb
amb (°C
(°C)
30
40
50
60
70
80
90
Rset (kOhm)
Figure 8. Segment Current
urrent
nt vs. Supply Voltage;
Figure 9. Segment Current vs. VDD; VRset = 2.8V
60
50
Vseg
Vseg
Vseg
Vseg
45
50
40
= 1.7V
= 2V
= 2.3V
= 3.1V
35
40
Iseg (mA) .
Iseg
seg (m
(mA) .
60
Tamb
mb (°C)
(°C
50
50
Iseg (mA) .
35
10
Figure 7.
7 Segment
mentt Current vvs. RSET;
60
0
-40
-15
30
3
20
25
20
15
Vseg = 1.7V
10
Vseg = 3V
10
30
Vseg = 4V
5
0
0
2.7
3.1
3.5
3.9
4.3
4.7
Vdd (V)
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
5.1
5.5
2.7
3
3.3
3.6
3.9
4.2
Vdd (V)
Revision 1.00
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AS1117
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 10. VDIGIT vs. IDIGIT
Figure 11. Input High Level vs. Supply Voltage
0.4
3.5
3
0.2
2
id
Vih (V) .
2.5
1.5
1
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
va
l
Vdig (V) .
0.3
Vdd
Vdd
Vdd
Vdd
Vdd
0.1
= 2.7V
= 3.3V
= 4V
= 5V
= 5.5V
0.5
0
0
0
0.05
0.1
0.15
0.2
0.25
Idig (A)
0.3
2.7
0.35
Figure 12. ISEG vs. VSEG; VDD = 5V
3.5
Rext
Rext
Rext
Rext
Rext
45
40
4.7
4.3
Vdd (V)
V)
5
50
= 10k
= 13k
= 18k
= 30k
= 56k
6k
5
5.1
Rext
Rext
Rext
Rext
Rext
45
4
40
35
5.5
= 8k2
= 10k
= 13k
= 18k
= 30k
Iseg (mA) .
35
30
30
25
25
20
20
2
15
15
10
10
5
5
0
0
2
2.5
3
3.5
4
4.5
5
1
1.5
2
Vseg (V)
50
40
3
3.5
4
Figure 15. ISEG vs. VSEG; VDD = 2.7V
Rext
Rext
Rext
Rext
Rext
45
2.5
Vseg (V)
Figure 14. ISEG vs. VSEG; VDD = 3.3V
= 6k8
= 8k2
= 10k
= 13k
= 18k
50
Rext
Rext
Rext
Rext
Rext
45
40
= 4k7
= 5k6
= 6k8
= 10k
= 13k
35
Iseg (mA) .
35
Iseg (mA) .
3.9
Figure
ure 13. ISEG vs. VSEG
G; VDD = 4V
50
Iseg (mA) .
3.1
30
30
25
25
20
20
15
15
10
10
5
5
0
0
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
1
Vseg (V)
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vseg (V)
Revision 1.00
7 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
Block Diagram
VDD
Open/Short
Detection
16
VDD
+
9
VDD
100nF
–
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
v
RESETN
al
id
Figure 16. AS1117 - Block Diagram
RSET
+
–
Oszillator
10
ISET
T
VDD
8
S
SEGA-G,
SEGDP
Digital Control
Logicc
21
IRQ
8
1,2,4,5,6,7,23,24
DIG0 to DIG7
(PWM, Debounce,....)
ebounce,....
VDD
12-15,
1 17-20
8
KEY
VDD
11
SCL
22
I²C
Interface
Registers
3
Data
ata - Registers
gisters
Control
ntrol - Registers
i t
Scan - Reg
Registers
SDA
GND
AS1117
Figure 17. ESD
SD
D Structure
VDD
valid for the pins:
- IRQ
- SCL
- SDA
- ISET
- SEGA-G, SEGDP
- KEY
- RESETN
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
VDD
valid for the pins:
- DIG0 to DIG7
Revision 1.00
8 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
I²C Interface
The AS1117 supports the I²C serial bus and data transmission protocol in high-speed mode at 3.4MHz. The AS1117
operates as a slave on the I²C bus. The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. Connections to the bus are made via
the open-drain I/O pins SCL and SDA.
1
0
8
0
0
0
0
A1
9
A0 R/W
1
8
D15 D14 D13 D12 D11 D10
D9
9
D8
Default values at power up: A1 = A0 = 0
am
lc s
on A
te G
nt
st
ill
Figure 19. Bus Protocol
va
l id
Figure 18. I²C Interface Initialisation
MSB
SDI
ACK from
Rec
Receiver
Slave Address
R/W
Direction Bit
ACK from
m
ver
Receiver
1
SCL
2
6
7
8
9
ACK
CK
START
1
2
3-8
8
9
ACK
Rep
Repe
Repeat
if More Bytes Transferred
STOP or
Repeated
START
The bus protocol (as shown in Figure 19) is defined
efined
ed as:
as
wh
e bus is not
n busy.
- Data transfer may be initiated only whe
when the
ca
e must
ust re
rem
- During data transfer, the data line
remain st
stable whenever the clock line is HIGH. Changes in the data line
e interprete
while the clock line is HIGH will be
interpreted as control signals.
The bus conditions are defined as:
remain HIGH.
- Bus Not Busy. Data and clock lines rre
ni
- Start Data Transfer
er. A change in tthe state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
on.
START condition.
ch
chan in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
- Stop Data Transfer. A change
he
e STOP condition.
condit
defines the
Te
id. The state of the data line represents valid data, when, after a START condition, the data line is stable
- Data Valid
or the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
for
Each
ch data transfer
trans is initiated with a START condition and terminated with a STOP condition. The number of data
bytes
ytes transferred
tran
transfe
between START and STOP conditions is not limited and is determined by the master device.
The
he inform
information is transferred byte-wise and each receiver acknowledges with a ninth-bit.
Within tthe I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.
W
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the recep- Ac
tion of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge
bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
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Revision 1.00
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AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line HIGH to enable the master to generate the STOP condition.
- Figure 19 on page 9 details how data transfer is accomplished on the I²C bus. Depending upon the state of the R/
W bit, two types of data transfer are possible:
- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by
a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
al
id
- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave
then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The
ed
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received
RT
T
byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START
and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a
repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
The AS1117 can operate in the following slave modes:
lv
y is received
yte
received, a
an
- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte
ng and end
e of a serial
se
s
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning
ess and direc
directi
transfer. Address recognition is performed by hardware after reception of the slave address
direction bit.
ch
ni
ca a
l c ms
on A
te G
nt
st
il
- Slave Transmitter Mode. The first byte (the slave address) iss received
rec
and handled as in the slave receiver
re
tr
n is reversed. Serial
Se
mode. However, in this mode the direction bit will indicate that the transfer
direction
data is
SC
S
T and
d STOP conditions
cond
transmitted on SDA by the AS1117 while the serial clockk iss input on SCL.
START
are recognized as the beginning and end of a serial transfer.
I²C Device Self Addressing
If this feature is used, 2 of the 8 key readback nodes can
n be
e left
lef open
op or shorted
ted for self-addressing.
self-a
selfThis is done with
des ccannot
not
ot be
b used for key-readback in this case. After startup all
KEY together with SEGG and SEGF. This two nodes
com
co
f-addressing will update all connected AS1117.
devices have the predefined adress 0000000. A single command
for self-addressing
th AS1117
117 gets disconnected
disconn
This command has to be done after startup orr everytime the
from the supply. The I²C
C detection is ex
e
address definition must be done with fixed connection, since I²C
excluded from debounce time of key registers.
I²C Device Address Byte
The address byte (see Figure 20) iss the first byte received
eceived
ved following the START condition from the master device.
Figure 20. I²C Device Address Byte
predefined address:
updated address:
MSB
6
5
4
3
2
1
LSB
0
0
0
0
0
0
0
R/W
MSB
6
5
4
3
2
1
LSB
0
0
0
0
0
A1
A0
R/W
Te
- The default slave address is factory-set to 0000000.
SB bits of the a
- The two LSB
address byte are the device select bits, A0 to A1, which can be set by the self-adress
and after startup
command
startup. A maximum of four devices with the same pre-set code can therefore be connected on
me bus at one
on time.
the same
st bit of the
t address byte (R/W) define the operation to be performed. When set to a 1 a read operation is
- The last
selected;
elected; whe
when set to a 0 a write operation is selected.
Following the S
ST
START condition, the AS1117 monitors the I²C bus, checking the device type identifier being transmitted.
Upon receivin
receiving the address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
10 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Command Byte
The AS1117 operation, (see Table 7) is determined by a command byte (see Figure 21 on page 11).
MSB
6
5
4
3
2
1
LSB
D15
D14
D13
D12
D11
D10
D09
D08
al
id
Figure 21. Command Byte
Figure 22. Command and Single Data Byte Received
From Master to Slave
AS1117 Registers
From Slave to Master
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ic a
al m
co s
nt AG
en
ts
til
lv
S
0
Slave Address
R/W A
A
Command Byte
A
Data Byte
P
1 Byte
yte
Acknowledge
from AS1117
wledg
Acknowledge
m AS1117
AS111
from
0
Acknowledge
from AS111
AS1117
0
0
Autoincrement
Memory Word
Address
Figure 23. Setting the Pointer to a Address Register to
o select
lect a Data
Da
Dat Register
sterr for a Read
Rea Operation
From Master to Slave
AS1117
7 Registers
Registe
From Slave to Master
S
0
Slave Address
D15
5 D14 D13
13 D
D12 D11 D10 D
D9
9
R/W
/W A
ge
e
Acknowledge
from AS1117
D8
A
Command Byte
yt
Ackno
ckn
Acknowledge
fro AS1117
from
0
P
0
Figure 24. Reading nBytes from AS1117
117
Autoincrement
Memory Word
Address
From Master to Slave
cknowledge
Acknowledge
AS11
from AS1117
Te
ch
n
From Slave to Master
ter
S
Slave Address
Add
Acknowledge
from Master
0
R/W A
1
D6
D5
D4
D3
D2
D1
AS1117 Registers
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Not Acknowledge
from Master
0
Revision 1.00
D0
1
n Bytes
A
First Data Byte
D7
Stop reading
/A
Second Data Byte
D7
D6
D5
D4
D3
D2
D1
P
D0
Autoincrement
to next address
11 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Initial Power-Up
On initial power-up, the AS1117 registers are reset to their default values, the display is blanked, and the device goes
into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control
Register (see page 17) is set to the minimum values.
lv
al
id
Shutdown Mode
The AS1117 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is
entered via a write to the Shutdown Register (see Table 8) or via pulling the pin RESTEN to logic low. When pin
RESETN is set to logic low an according write to the Shutdown Register is done internally. During shutdown mode the
Digit-Registers maintain their data.
Note: When pin RESETN is pulled to logic high again, a write to the Shutdown Register in necessary to leave
eave the
shutdown mode.
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
il
Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display
(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic inp
input should
be at GND or VDD (CMOS logic level).
es (all 0s) wh
When entering or leaving shutdown mode, the Feature Registerr is reset to its default values
when Shutdown
Register bit D7 (page 13) = 0.
Note: When Shutdown Register bit D7 = 1, the Feature
e Register is left
l unchanged
nged when
n entering
ent
or leaving shutal clock, Shutdown
S
gister bit
b D7 should be set to 1 when
down mode. If the AS1117 is used with an external
Register
writing to the Shutdown Register.
Digit- and Control-Registers
The AS1117 devices contain 8 Digit-Registers,11
ers,11 control-registers
contro
s and 10 diagnostic-registers,
diag
which are listed in Table
wo and communication
mmunication is done via the I²C interface.
7. All registers are selected using a 8-bitt address word,
Digit
Registers – These registerss are realized with an on-chip
n-chip 64-bit m
memory. Each digit can be controlled directly
ster conten
without rewriting the whole register
contents.
Control
Registers – These registers
ers co
consist of decode
ode mode, display
d
intensity, number of scanned digits, shutters.
down, display test and features selection registers.
Digit Register
Type
Table 7. Register Address Map
Register
Address
D7:D0
Page
D15:D13
D12
D11
D1
D10
D9
D8
Digit 0
000
0
0
0
0
1
N/A
Digit 1
000
0
0
0
1
0
N/A
Digit 2
000
0
0
0
1
1
(see Table 10 on page 14,
Table 11 on page 14 and
Table 12 on page 15)
N/A
Digit 3
000
0
0
1
0
0
Digitt 4
000
0
0
1
0
1
Digitt 5
000
0
0
1
1
0
N/A
Digit 6
000
0
0
1
1
1
N/A
Digit 7
000
0
1
0
0
0
N/A
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
N/A
N/A
12 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Address
Register
Page
D15:D13
D12
D11
D10
D9
D8
D7:D0
Decode-Mode
000
0
1
0
0
1
(see Table 9 on page 14)
13
Global Intensity
000
0
1
0
1
0
(see Table 18 on page 17)
17
Scan Limit
000
0
1
0
1
1
(see Table 20 on page 17)
17
Shutdown
000
0
1
1
0
0
(see Table 8 on page 13)
12
Self-Adressing
001
0
1
1
0
1
Feature
000
0
1
1
1
0
(see Table 21 on page 18)
18
14
ni
ca a
l c ms
on A
te G
nt
st
ill
va
li d
Keyscan/Diagnostic Register
Control Register
Type
Table 7. Register Address Map
N/A
/A
A
Display Test Mode
000
0
1
1
1
1
(see Table 15 on page 16))
DIG0:DIG1 Intensity
000
1
0
0
0
0
(see Table 19 on page 17)
DIG2:DIG3 Intensity
000
1
0
0
0
1
ag 17)
17
7)
(see Table 19 on page
DIG4:DIG5 Intensity
000
1
0
0
1
0
n page 17)
1
(see Table 19 on
9 on page 17)
17)
(see Table 19
DIG6:DIG7 Intensity
000
1
0
0
1
1
Diagnostic Digit 0
000
1
0
1
0
0
N/A
Diagnostic Digit 1
000
1
0
1
0
1
N/A
Diagnostic Digit 2
000
1
0
1
1
0
N/A
Diagnostic Digit 3
000
1
1
0
1
1
N/A
Diagnostic Digit 4
000
1
1
0
0
0
N/A
Diagnostic Digit 5
000
1
1
0
0
1
N/A
Diagnostic Digit 6
000
1
1
0
1
0
N/A
N/A
Diagnostic Digit 7
000
1
1
0
1
1
KEY
000
1
1
1
0
0
The Shutdown Register controls AS1117
S1117 shutd
shutdo
shutdown mode.
de.
Table 8. Shutdown Register Format
at (Addre
(Address (HEX)
X) = 0x0C))
Mode
Shutdown Mode,
Reset Feature Register to Default Settings
ings
Shutdown Mode, Feature Register
er Unchanged
nchanged
Normal Operation,
on,
Reset Feature Register to
o Default
efault Settings
Setting
Normal Operation, Feature
ure
e Register Unchanged
Un
Unch
HEX
EX Co
Code
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
0x00
0
X
X
X
X
X
X
0
0x80
1
X
X
X
X
X
X
0
0x01
0
X
X
X
X
X
X
1
0x81
1
X
X
X
X
X
X
1
Decode Enable Register
gister (0x09)
(0x09
ch
The Decode Enable
able Register sets
set the decode mode. BCD/HEX decoding (either BCD code – characters 0:9, E, H, L,
se
X code – chara
P, and -, or HEX
characters 0:9 and A:F) is selected by bit D2 (page 18) of the Feature Register. The Decode
egister
ter is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable RegisEnable Register
esponds
nds to its re
ter corresponds
respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so
le 10 on pag
on). Table
page 14 lists some examples of the possible settings for the Decode Enable Register bits.
Te
Note A logic high
Note:
h
enables decoding and a logic low bypasses the decoder altogether.
decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,
When
hen de
deco
disregarding
bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit
isregard
gard
D7 = 1 turns the decimal point on). Table 10 on page 14 lists the code-B font; Table 11 on page 14 lists the HEX font.
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
13 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the
AS1117. Table 12 on page 15 shows the 1:1 pairing of each data bit to the appropriate segment line.
Table 9. Decode Enable Register Format Examples
HEX Code
No decode for digits 7:0
Code-B/HEX decode for digit 0. No decode for digits 7:1
Code-B/HEX decode for digit 0:2. No decode for digits 7:3
Code-B/HEX decode for digits 0:5. No decode for digits 7:6
Code-B/HEX decode for digits 0,2,5.
No decode for digits 1, 3, 4, 6, 7
0x00
0x01
0x07
0x3F
D7
0
0
0
0
D6
0
0
0
0
0x25
0
0
Register Data
D5 D4 D3 D2
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
A
B
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
il
G
E
D
D0
0
1
1
1
0
1
lv
Figure 25. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking
F
D1
0
0
1
1
al
id
Decode Mode
C
DP
Table 10. Code-B Font
Register Data
Register
gist Data
Register Data
CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acte
acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
X
X
X
X
X
X
0
1
0
1
X
1
0
1
1
*
1
*
The decimal point can be enabled
ena
en
with every character by setting bit D7 = 1.
Table 11. HEX Font
ont
Register Data
Registe
Register Data
Register Data
CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
14 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 11. HEX Font
Register Data
Register Data
Register Data
CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
0
0
1
1
X
1
0
0
1
X
0
1
0
0
X
1
0
1
0
X
0
1
0
1
X
1
0
1
1
*
1
X
1
1
1
1
X
X
X
X
X
Te
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
va
lid
X
*
The decimal point can be enabled with every character by setting bit D7 = 1.
Table 12. No-Decode Mode Data Bits and Corresponding Segment Lines
Corresponding Segment Line
D7
DP
D6
A
D5
B
D4
C
D3
D
D2
2
E
D1
F
D0
G
I²C Self Addressing
If this feature is used, 2 of the 8 key readback nodes can
an be left open or shorted
d for
f self-addressing.
f-addres
f-address
This is done with
nnot be used
use for key-readback
y-readbac
eadba in this
thi case. After startup all
KEY together with SEGG and SEGF. This two nodes cannot
mman for
fo selfaddressing
ddressing
essing will u
devices have the predefined adress 0000000. A single command
update all connected AS1117.
y
ytim
he
e AS1117
AS
ets disconnected from the supply. The I²C
This command has to be done after startup or everytime
the
gets
ection, since
sin I²C detection
si
ection
on is exclude
address definition must be done with fixed connection,
excluded from debounce time of key registers.
Note: A short writes a logical “0” whereas
eas
as an open writes
w
a logical
cal “1” as address
ad
bit.
Table 13. Self Addressing Register (Address (HEX)
(HE = 0x2D))
x2D))
))
D7
X
X
Factory-set IC address
User-set IC address
D6
X
X
D5
X
X
D4
X
X
D3
X
X
D2
X
X
D1
X
X
D0
0
1
Keyscan Register
These two registers contain the result
lt of the keyscan
key
keysc input of the 8 keys. To ensure proper results the data in these
ogic data scanne
scanned is stable for 20ms (debounce time). A change of the data stored
registers are updated only if the logic
dicated
ted by a logic low on the IRQ pin. The IRQ is high-impedance if a read operation on
within these two registers is indicated
rted.
the key scan registers is started.
Table 14. LED Diagnostic
tic Register
egister Address
Addr
Register HEX Address
ss
0x1C
C
KEY
D7
DP
D6
A
D5
B
Segment
D4
D3
C
D
D2
E
D1
F
D0
G
Note: If I²C self addres
addressing is used segment G&F of KEY is used for the two LSB of the I²C address. In this case
nod cannot be used as a key. Additionally the debounce time is disabled for these two bits.
no
these two nodes
w
The data within
the keyscan register is updated continuously during every cycle (1/10 of refresh rate). Therefore, to get a valid readback of keys it is recommended to read out the keyscan registers immediately after the
Q is triggered. A short writes a logical “0” whereas an open writes a logical “1” as keyscan register bit.
IRQ
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Revision 1.00
15 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Display-Test Mode
The AS1117 can detect open or shorted LEDs. Readout of either open LEDs or short LEDs is possible, as well as a OR
relation of open and short.
Note: All settings of the digit- and control-registers are maintained.
Table 15. Testmode Register Summary
D6
RSET_short
D5
RSET_open
D4
LED_global
D3
LED_test
D2
LED_open
D1
LED_short
D0
DISP_test
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
va
lid
D7
X
Table 16. Testmode Register Bit Description (Address (HEX) = 0x0F))
Addr: 0x0F
Bit
Address
Bit Name
Default
Access
D7:D0
D0
DISP_test
0
W
Optical display test. (Testmode for external visual test.)
st.)
dig are
re
e tested
0: Normal operation; 1: Run display test (All digits
register.
independently from scan limit & shutdown register.)
D1
LED_short
0
W
e set together wi
w
Starts a test for shorted LEDs. (Can be
with D2)
pera
perati
tmode
mode
0: Normal operation;
1: Activate testmode
D2
LED_open
0
W
est for open
ope LEDs. (Can
n be set together
togethe with D1)
Starts a test
rmall operation; 1:
1 Activate
te testmode
estmode
0: Normal
D3
LED_test
0
R
dicates an ongoi
n/sh LED test
Indicates
ongoing open/short
0: No ongoing L
t; 1:: LED
LE testt in progress
LED test;
D4
LED_global
0
R
dicates
ates tha
ast open/short LED
L
Indicates
that the last
test has detected an error
0: No
o err
cted; 1: Error d
det
error detected;
detected
D5
RSET_open
0
R
SET is open
Chec
Ch
ernal
al resistor RS
Checks if external
orrect;
rrect; 1: RSET is open
0: RSET correct;
D6
RSET_short
0
R
s if external
xternal resi
resis
Checks
resistor RSET is shorted
0: RSET correct; 1: RSET is shorted
0
-
ed
Not used
D7
LED Diagnostic Registers
These eight registers contain the result of the
th LED
ED
D open/short
open/s
open/sh test for the individual LED of each digit.
Table 17. LED Diagnostic Register Address
ddress
ss
Register
HEX
Address
0x14
0x15
0x16
0x17
Segment
ment
Digit
D7
DIG0
DIG1
P
DP
DIG2
DIG3
D6 D5 D4 D3 D
D2 D1 D0
A
B
C
D
E
F
G
Register
HEX
Address
0x18
0x19
0x1A
0x1B
Segment
Digit
D7 D6 D5 D4 D3 D2 D1 D0
DIG4
DIG5
DP
DIG6
DIG7
A
B
C
D
E
F
G
Note: If one or more short
shor
sho occures in the LED array, detection of individual LED fault could become ambiguous.
Intensity
nsity
ty Control Register
R
(0x0A)
Te
The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog
means using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 19). The intensity can be
controlled gl
controll
globally for all digits, or for each digit individually. The global intensity command will write intensity data to all
our individual
indivi
ndiv
four
brightness registers, while the individual intesity command will only write to the associated individual
nsit register.
intensity
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
16 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the
Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 15/16
down to 1/16 of the peak current set by RSET.
Table 18. Intensity Register Format
1/16 (min on)
2/16
3/16
4/16
5/16
6/16
7/16
8/16
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
MSB
0
0
0
0
0
0
0
0
Register Data
D2
D1 LSB
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Duty Cycle
HEX Code
9/16
10/16
11/16
12/16
13/16
14/16
15/16
15/16 (max on)
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
MSB
1
1
1
1
1
1
1
1
Register Data
D2
D1 LSB
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
va
li d
HEX Code
ch
ni
ca a
l c ms
on A
te G
nt
st
ill
Duty Cycle
Table 19. Intensity Register Address
Register Data
ata
Register HEX Address
Type
Global
Digit
Digit
Digit
Digit
0x0A
0x10
0x11
0x12
0x13
D7:D4
7:D4
X
Digit 1 Intensity
Inte
Digit 3 Intensity
ty
Digit
D
Digi
5 Intensity
nsityy
Digit
D
7 Intensity
ntensity
sity
D3:D0
D
3
Glob
Global Intensity
Digit
D
0 Intensity
Digit 2 Intensity
Digit 4 Intensity
Digit 6 Intensity
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are
a to be displayed.
isplayed. When
Wh all 8 digits are to be displayed, the
numbe of digits
ts displayed is re
update frequency is typically 700Hz. If the number
reduced, the update frequency is increased.
sing 10 x fOSC/(N+2),
fO
+2), where
here N is the
th
t number of digits.
The frequency can be calculated using
Note: To avoid differences in brightness
ness this register
gister should not
n be used to blank parts of the display (leading zeros).
Table 20. Scan-Limit Register Format (Address
ss (HEX) = 0x0
0x0B))
Scan Limit
Scan Limit
Display digits 0:4
Display digits 0:5
Display digits 0:6
Display digits 0:7
Register Data
HEX
Code D7:D3 D2 D1 D0
0xX4
X
1
0
0
0xX5
X
1
0
1
0xX6
X
1
1
0
0xX7
X
1
1
1
Te
Display digit 0 only
Display digits 0:1
Display digits 0:2
Display digits 0:3
Register Data
Reg
HEX
Code D7:D3
3 D2 D1 D0
0xX0
0
X
0
0
0
0
1
0xX1
X
0
0
1
0
0xX2
X
0xX3
X
0
1
1
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
17 - 23
AS1117
Datasheet - D e t a i l e d D e s c r i p t i o n
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode,
applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, setting the blinking rate,
and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
ch
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va
li d
Table 21. Feature Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
blink_
start
sync
blink_
freq_sel
blink_en
NU
decode_sel
reg_res
en
clk_en
Table 22. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
Feature Register
Enables and disables various device features.
Bit Name
Default
Access
Bit Description
External clock active.
clk_en
ck..
0
R/W
0 = Internal oscillatorr is us
used for system clock.
e serial int
inte
es ass system clo
cloc
1 = Pin CLK of the
interface operates
clock input.
trol registers exc
e
ture Register
Registe
Resets all control
except the Feature
Register.
isabled. Normal operation.
0 = Reset Disabled.
reg_res
ontrol
trol registers ar
a reset to
o def
(
0
R/W
1 = All control
are
defaultt state (except
the Feature
r) identically
entically after
aft power-up.
er-up.
p.
Register)
Note: T
The Digit
git Reg
R
Registers maintain
ntain their da
data.
ects di
dis
d
g for the selected
selecte digits (Table 9 on page 14).
Selects
displayy decoding
decode_sel
0 = Enable Code-B
C
ecoding
ding (see Ta
T
decoding
Table 10 on page 14).
0
R/W
1 = Enable HEX decoding
ecoding
coding (see Ta
T
Table 11 on page 14).
use
us
NU
Not used
Ena
Enab
nking.
g.
Enables blinking.
blink_en
R/W
0
0 = Disable
ble blinking.
nking. 1 = Enable
E
blinking.
fre
Sets blinkk with low freq
frequency (with the internal oscillator enabled):
typ
blink_freq_sel
0 = Blink period ty
typically is 1 second (0.5s on, 0.5s off).
R/W
R/W
0
1 = Blink period is 2 seconds (1s on, 1s off).
ynchronizes
chronize blinking on the rising edge of pin LD/CS. The multiplex
Synchronizes
a
and blink ttiming counter is cleared on the rising edge of pin LD/CS. By
sync
R/W
0
set
sett
setting this bit in multiple devices, the blink timing can be synchronized
acro
acros
across all the devices.
St
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
blink_start
0
R/W
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
Addr: 0xXE
Bit
D0
D1
D2
D3
D4
D5
D6
Te
D7
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
18 - 23
AS1117
Datasheet - Ty p i c a l A p p l i c a t i o n
9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows into ISET defines the current that flows
through the LEDs.
id
Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED) are given in Table 23 & Table 24. The maximum current the AS1117 can
drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary
that the devices drive high currents.
Table 23. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V
VLED
VLED
VLED
1.5V
2.0V
2.5V
1.5V
2.0V
5k:
6.9k:
10.7k:
22.2k:
4.4k:
5.9k:
9.6k:
20.7k:
6.7k:
9.1k:
13.9k:
28.8k:
6.4k:
8.8k:
13.3k:
27.7k:
5.7k:
8.1k:
12.6k:
26k
6k:
7.5k:
10.18k:
15.6k:
31.9kk:
7.2kk:
9.8k:
15k:
31k:
VDD = 3.6V
2.0V
VDD = 3.3V
1.5V
2.5V
2
3.0V
3
6.6k:
9.2 :
9.2k
14.3k:
14
14.
29.5k:
5.5k:
7.5k:
13k:
27.3k:
am
lc s
on A
te G
nt
st
i ll
40
30
20
10
VDD = 2.7V
ISEG (mA)
va
l
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page
e 16).
16)).
Table 24. RSET vs. Segment Current and LED Forward
d Voltage, VDD = 4.0V & 5.0V
5.0
VLED
VDD = 4.0V
40
30
20
10
1.5V
2.0V
8.6k:
8.3k:
11.6k: 11.2k:
17.7k: 17.3k:
36.89k: 35.7k:
2.5V
VLED
3.0V
3.5V
7.9k:
7.6k: 5.2k:
10.8k: 9.9k: 7.8k:
16.6k: 15.6k
5.6k: 13.6k:
34.5k: 32.5k: 29
29.1k:
2
VDD = 5.0V
ISEG
(mA)
1.5V
2.0V
0V
11.35k:
15.4k
4k:
23.6k
3.6k:
48.9k:
11.12k
.12k:
15.1k:
23.1k:
47.8k
4
7 :
2.5V
2
.5V
3.0V
10.
10.84k
10
: 10.49k:
14.7k: 14.4k:
22.6k:
22k:
46.9k: 45.4k:
3.5V
4.0V
10.2k:
13.6k:
21.1k:
43.8k:
9.9k:
13.1k:
20.2k:
42k:
Calculating Power Dissipation
pation
ation
The upper limit for power dissipation (PD) for the
he AS1117 is determined
de
from the following equation:
PD = (VDD x 5m
5mA) + (V
VDD - VLED)(DUTY x ISEG x N)
Where:
(EQ 1)
ni
ca
VDD is the supply voltage.
DUTY is the duty cycle set byy intensity
ensity register
registe (page 17).
N is the number of segments
nts
ts driven (wor
(worst case is 8)
d voltage
age
VLED is the LED forward
ent set
et by RSET
ISEG = segment current
Dissipation Example:
mple:
(EQ 2)
PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W
(EQ 3)
ch
ISEG
EG = 4
40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V
Te
Thus,
us, for a TQFN(4x4)-24
TQFN(4
package 4JA = +30.5°C/W, the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x 4JA = 150°C = TAMB + 0.865W x 30.5°C/W
(EQ 4)
In
n thiss ex
example the maximum ambient temperature must stay below 123.61°C.
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
19 - 23
AS1117
Datasheet - Ty p i c a l A p p l i c a t i o n
8x8 Dot Matrix Mode
The application example in Figure 26 shows the AS1117 in the 8x8 LED dot matrix mode.
The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the
segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed
in Table 7 on page 12.
va
l id
The Decode Enable Register (see page 13) must be set to ‘00000000’ as described in Table 9 on page 14. Single
LEDs in a column can be addressed as described in Table 12 on page 15, where bit D0 corresponds to segment G and
bit D7 corresponds to segment DP.
Figure 26. Application Example as LED Dot Matrix Driver
VDD
2.7V to 5V
VDD
DIG0 to
DIG7
ISET
SEG A to G
SEP DP
Diode Arrangement
9.53k:
SDA
AS1117
Te
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i ll
SDA
SCL
μP
IRQ
SCL
IRQ
GND
RESETN
Keyscan
The key readback of the AS1117 can be used
d either for pu
p
push buttons
ons as well as s
sw
switches. If only a single key is
iodes are req
m
pressed (shorted) at a time no additional diodes
required. Iff a detection of multiple
simultaneous keystrokes is
hown in Figure
Figu 27, are required. Pre
required diodes within the keypath, as shown
Pressing multiple keys without the diodes
would result in ambiguous results.
Figure 27. Keyscan Configuration
n
SEGA
SEGB
S
SEGC
C
SEGD
SE
SEG
SEG E
SEGF
SEGG
SEGDP
KEY
IRQ
Diodes are optional and only required if multiple keystrokes must be
detected simultaneously.
If I²C Self-Adressing is used these two keys cannot be used for readback and must be either hard wired opened or shorted.
A short writes a logical “1” whereas an open writes a logical “0” as
address bit.
Supply
upply
ly Bypass
Bypassing and Wiring
In order to achieve
achiev
achi
optimal performance the AS1117 should be placed very close to the LED display to minimize effects
of electromagn
electromagnetic interference and wiring inductance.
Furthermo
herm
Furthermore,
it is recommended to connect a 10μF and a 0.1μF ceramic capacitor between pins VDD and GND to
oid p
avoid
power supply ripple (see Figure 16 on page 8).
www.austriamicrosystems.com/LED-Driver-ICs/AS1117
Revision 1.00
20 - 23
AS1117
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The AS1117 is available in the TQFN(4x4)-24 package.
Figure 28. TQFN(4x4)-24 Package
20
21
22
23
24
ch
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on A
te G
nt
st
ill
va
l id
19
18
1
17
2
16
3
15
4
14
5
13
6
12
11
10
9
8
7
m
m
Symbol
A
A1
A3
b
D
E
D2
E2
Min
0.50
0.00
0.18
2.70
2.70
.70
Typ
0.55
0.152REF
F
0.23
23
4.00BSC
00BSC
BSC
4.00BSC
2.80
2.80
Max
0.60
.6
0.05
0.28
2.90
2.90
Symb
Symbol
e
L
L1
aaa
bbb
ccc
ddd
eee
Min
0.30
0.00
Typ
0.50BSC
0.35
Max
0.40
0.10
0.10
0.10
0.10
0.05
0.08
Notes:Unilateral
lateral
ral coplanarit
coplanarity zone applies to the exposed heat sink slug as well as the terminals.
Te
1. All dimensions
sions are in millimeters; angles in degrees.
2. Dimension
to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip.
ension b applies
app
Dimension L
L1 represents terminal full back from package edge up to 0.1mm is acceptable.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius
Radiu on terminal is optional.
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Revision 1.00
21 - 23
AS1117
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 25.
Table 25. Ordering Information
Marking
AS1117-BQFT
ASSU
Description
64 LED Driver for Mobile
Applications with Error Detection
Delivery Form
Package
Tape and Reel
TQFN(4x4)-24
lv
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
al
Note: All products are RoHS compliant.
ct
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
id
Ordering Code
Te
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ms.com
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.00
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AS1117
Datasheet
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
id
Disclaimer
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on A
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
aring
ng
egarding
ding
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice..
ms AG for
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems
ns
s re
req
ring
ng
current information. This product is intended for use in normal commercial applications. Applications
requiring
s, such a
as military,
litar
extended temperature range, unusual environmental requirements, or high reliability applications,
dditional
ditional processing
proces
medical life-support or life-sustaining equipment are specifically not recommended without additional
by
s tha
nufacturing
ufacturing flow m
austriamicrosystems AG for each application. For shipments of less
than 100 parts the manufacturing
might show
loca
deviations from the standard production flow, such as test flow or test loc
location.
s believed
elieved to be
b correct and
d accurate. H
The information furnished here by austriamicrosystems AG is
However,
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es, including
includin
inclu
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but not limited to
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indirect
ndirect special, incidental or
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ou of the furnishing,
nishin performance
fo
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or use of the
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rty shall
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ormation
mation
Headquarters
ers
Te
microsystems
systems AG
austriamicrosystems
lbaderstrasse
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