AS3418-EWLM

Datasheet DS000507 AS3418 Low Noise ANC Solution v4-00 • 2020-Jan-23 Document Feedback AS3418 Content Guide Content Guide Key Benefits & Features .............................. 3 Applications .................................................. 4 Block Diagram .............................................. 4 6.8 6.9 6.10 6.11 6.12 Operation Modes ....................................... 33 VNEG Charge Pump .................................... 38 EEPROM .................................................... 39 Production Trimming Interface ................... 41 I2C Interface ............................................... 42 2 Ordering Information ..................... 5 7 Register Description ................... 47 3 Pin Assignment ............................. 6 3.1 3.2 Pin Diagram .................................................. 6 Pin Description ............................................. 6 7.1 7.2 Register Overview ...................................... 47 Detailed Register Description .................... 49 8 Application Information .............. 70 4 Absolute Maximum Ratings .......... 9 5 Electrical Characteristics ............ 10 8.1 8.2 Schematic .................................................. 70 External Components ................................ 72 6 Functional Description ................ 12 9 Package Drawings & Markings... 74 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Audio Line Input ......................................... 12 Microphone Inputs ...................................... 13 Microphone Supply .................................... 19 Headphone Amplifier .................................. 21 Music Bypass Switch ................................. 25 Operational Amplifier .................................. 28 System ....................................................... 30 10 Revision Information ................... 76 11 Legal Information ........................ 77 1 General Description....................... 3 1.1 1.2 1.3 Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 2 Document Feedback 1 AS3418 General Description General Description The AS3418 speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. They are intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. An internal EEPROM can be optionally used to store the microphones gain calibration settings. The AS3418 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs. The AS3418 targeting feed-forward topology is used to effectively reduce frequencies typically up to 23 kHz. The typical bandwidth for a feed-forward system is from 20Hz up to 3 kHz which is lower than the feed-forward systems. The filter loop for the system is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs. 1.1 Key Benefits & Features The benefits and features of AS3418, Low Noise ANC Solution, are listed below: Figure 1: Added Value of Using AS3418 Benefits Features Low Noise Floor Low Noise Amplifiers Integrated Music Bypass Switch Depletion mode transistors for passive music bypass Smallest ANC form factor WL-CSP package 2.645mm x 2.545mm; 0.4mm pitch Reprogrammable ANC settings EEPROM Memory for system settings Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 3 Document Feedback 1.2 Applications ● ● ● ● ● 1.3 AS3418 General Description Ear Pieces Headsets Hands-Free Kits Mobile Phones Voice Communicating Devices Block Diagram The functional blocks of this device are shown below: Figure 2 : Functional Blocks of AS3418 CFLY CVNEG CPP GND CPN VNEG VNEG QOP1L IOP1L MICACL CACL QMICL Left ANC Filter VBAT VMIC VBAT Charge Pump CMICL MICL Left ANC Microphone RMICL CVBAT BPL Music Bypass LINL MUTE TRSDA Music Input EEPROM TRSCL AS3418 HPL ANC Processing AGND Speaker Left HPR Speaker Right VBAT LINR BPR Music Bypass CMICR ANC/CSDA QOP1R IOP1R Right ANC Filter MODE/CSCL CACR QMICR On/Off/Monitor/PBO MICS I2C RMICR MIC Supply MICR MICACR Right ANC Microphone ILED LED MUTE VMIC MSUP CMSUP VMIC CMICS Button Control or I2C Communication Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 4 Document Feedback 2 AS3418 Ordering Information Ordering Information Ordering Code Package Marking Delivery Form Delivery Quantity AS3418-EWLT WL-CSP AS3418 Tape & Reel 6500 pcs/reel AS3418-EWLM WL-CSP AS3418 Tape & Reel 500 pcs/reel Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 5 Document Feedback 3 Pin Assignment 3.1 Pin Diagram AS3418 Pin Assignment Figure 3 : Pin Assignment AS3418 3.2 A1 IOP1R A2 QMICR A3 MICR A4 VNEG A5 GND A6 VBAT B1 BPR B2 HPR B3 MICACR B4 CPN B5 LINR B6 LINL C1 VNEG C2 QOP1R C3 QOP1L C4 CPP C5 ANC/ CSDA C6 MODE/ CSCL D1 BPL D2 HPL D3 MICACL D4 TRSDA D5 AGND D6 TRSCL E1 IOP1L E2 QMICL E3 MICL E4 MICS E5 MSUP E6 ILED Pin Description Figure 4: Pin Description of AS3418 Pin Number Pin Name Pin Type(1) Description A1 IOP1R ANA IN ANC filter OPAMP1 input - right channel. A2 QMICR ANA OUT ANC microphone preamplifier output - right channel. A3 MICR ANA IN ANC microphone preamplifier input - right channel. A4 VNEG SUP OUT VNEG charge pump output terminal. This output provides the negative amplifier supply voltage for all OPAMPs and the headphone amplifier. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 6 Document Feedback Pin Number Pin Name Pin Type(1) Description A5 GND ANA IN VNEG charge pump ground terminal. A6 VBAT SUP IN Positive supply terminal of AS3418. AS3418 Pin Assignment B1 BPR ANA IN Right audio bypass switch input. This pin features a music bypass function for the right audio channel in off mode operation in order to replace and external analog switch. B2 HPR ANA OUT Headphone amplifier output - right channel. B3 MICACR ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a typ. 10µF capacitor connected to AGND pin. B4 CPN ANA OUT VNEG charge pump negative terminal for flying capacitor B5 LINR ANA IN Line input - right channel. B6 LINL ANA IN Line input - left channel. C1 VNEG SUP OUT VNEG charge pump output terminal. This output provides the negative amplifier supply voltage for all OPAMPs and the headphone amplifier. C2 QOP1R ANA OUT ANC filter OPAMP1 output - right channel C3 QOP1L ANA OUT ANC filter OPAMP1 output - left channel C4 CPP ANA OUT VNEG charge pump positive terminal for flying capacitor C5 ANC/ CSDA DIG IN/OUT Serial interface data signal line for I2C interface and alternatively ANC control to enable/disable ANC. C6 MODE/ CSCL DIG IN Serial Interface clock signal line for I2C interface and alternatively control pin for power up/down and Monitor mode. D1 BPL ANA IN Left audio bypass switch input. This pin features a music bypass function for the left audio channel in off mode operation in order to replace and external analog switch. D2 HPL ANA OUT Headphone amplifier output - left channel. D3 MICACL ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a typ. 10µF capacitor connected to AGND pin. D4 TRSDA ANA IN Data input for production trimming. Can be connected to LINL pin to enable production trimming via 3.5mm audio jack. D5 AGND ANA IN Analog reference ground. Do not connect this pin to power or digital ground plane. D6 TRSCL ANA IN Clock input for production trimming. Can be connected to LINR pin to enable production trimming via 3.5mm audio jack. E1 IOP1L ANA IN ANC filter OPAMP1 input - left channel Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 7 Document Feedback AS3418 Pin Assignment Pin Number Pin Name Pin Type(1) Description E2 QMICL ANA OUT ANC microphone preamplifier output - left channel E3 MICL ANA IN ANC microphone preamplifier input - left channel E4 MICS SUP OUT Microphone Supply output to source analog ECM via a bias resistor or MEMs microphones. This pin needs an output blocking capacitor with 4.7µF. SUP IN/OUT In default configuration a charge pump output that provides the power for the low noise microphone supply LDO. The internal charge pump can also be disabled the MSUP serves as a supply input terminal to source the low noise microphone supply LDO. ANA IN Current sink input for on-indication LED. The Cathode of an LED can be directly connected to this terminal without the need of an external current limitation resistor. E5 MSUP E6 (1) ILED Explanation of abbreviations: ANA IN Analog Input ANA OUT Analog Output DIG IN Digital Input SUP IN/OUT Supply input or supply output pad SUP IN Supply input terminal SUP OUT Supply output terminal Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 8 Document Feedback 4 AS3418 Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5 Absolute Maximum Ratings of AS3418 Symbol Parameter Min Max Unit Comments Electrical Parameters VSUP_MAX Supply Voltage to Ground -0.5 2 V Applicable for pin VBAT VGND_MAX Ground Terminals -0.5 +0.5 V Applicable for pin AGND and GND VNEG_MAX Negative Terminals -2.0 0.5 V Applicable for pin VNEG VCP_MAX Charge Pump Terminals VNEG - 0.5 VPOS + 0.5 V Applicable for pins CPN and CPP VHP_MAX Headphone Pins VNEG - 0.5 VPOS + 0.5 V Applicable for pins HPR and HPL VANA_MAX Analog Pins VNEG - 0.5 VPOS + 0.5 V Applicable for pins LINL, LINR, MICL/R, HPR, HPL, QMICL/R, IOP1x, QOP1x, CPP, CPN, TRSCL, BPR, TRSDA, BPL, MICACL and MICACR VCON_MAX Control Pins VNEG - 0.5 5 V Applicable for pins ANC/CSDA and MODE/CSCL VOTHER_MAX Other Pins VNEG - 0.5 5 V Applicable for pins MICS and MICFB ISCR Input Current (latch-up immunity) ± 100 mA Class II JEDEC JESD78D ± 2000 V Norm: JS-001-2014 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM Temperature Ranges and Storage Conditions TJ Operating Junction Temperature TSTRG Storage Temperature Range TBODY Package Body Temperature RHNC Relative Humidity (noncondensing) MSL Moisture Sensitivity Level (1) - 55 5 1 85 °C 125 °C 260 °C 85 % IPC/JEDEC J-STD-020 (1) Unlimited floor lifetime The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pbfree leaded packages is “Matte Tin” (100% Sn) Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 9 Document Feedback 5 AS3418 Electrical Characteristics Electrical Characteristics VBAT = 1.4V to 1.8V, TA = -20ºC to 85ºC. Typical values are at VBAT = 1.6V, TA = 25ºC, unless otherwise specified. All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Electrical Characteristics of AS3418 Symbol Parameter TA Ambient Temperature Range Conditions Min Typ Max Unit -20 85 °C 0 0 V 1.8 V -1.8 -1.2 V Supply Voltages GND Reference Ground VBAT Battery Supply Voltage VNEG Charge Pump Voltage VDELTA Difference of Ground Supplies GND, AGND To achieve good performance, the negative supply terminals should be connected to a low impedance ground plane. -0.1 0.1 V VMICS Microphone Supply Voltage Applicable to MICS pin 0 3.6 V VANALOG Analog Pins MICACL, MICACR,LINR, LINL, HPR, HPL, QMICL, QMICR, IOP1x, and QOP1x VNEG VBAT V VCONTROL Control Pins Applicable to MODE/CSCL and ANC/CSDA pins 0 3.7 V VCP Charge Pump Pins Applicable to CPN and CPP pins VNEG VBAT V VTRIM Application Trim Pins Applicable to TRSCL and TRSDA pins VNEG 0.3 or -1.8 VBAT +0.5 or 1.8 V VBYP Bypass Pins Applicable to BPR and BPL pins VNEG 0.3 or -1.8 VBAT +0.5 or 1.8 V VMIC Microphone Inputs Applicable to MICL and MICR pins. VNEG VBAT V 5 µA Normal Operation 1.4 1.6 Other Pins Block Power Requirements IOFF ISYS IMIC Off mode current MODE/CSCL pin low, device switched off 1 VBAT = 1.8V; Bias generation, oscillator, POR and VNEG 1.45 mA VBAT = 1.4V; Bias generation, oscillator, POR and VNEG 1 mA VBAT = 1.8V; no signal, stereo, High quality mode 0.97 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.68 mA VBAT = 1.4V; no signal, stereo, High quality mode 0.92 mA Reference supply current Microphone gain stage current Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 10 Document Feedback Symbol IHP IOP1 IMICS IMICS_CP Parameter Conditions AS3418 Electrical Characteristics Min Typ Max Unit VBAT = 1.4V; no signal, stereo, ECO mode 0.63 mA VBAT = 1.8V; no signal, high quality mode 2.9 mA VBAT = 1.8V; no signal, ECO mode 2.4 mA VBAT = 1.4V; no signal, high quality mode 2.78 mA VBAT = 1.4V; no signal, ECO mode 2.32 mA VBAT = 1.8V; OP1L and OP1R enabled, High quality mode 1 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.7 mA VBAT = 1.8V; OP1L and OP1R enabled, High quality mode 0.95 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.65 mA VBAT = 1.8V; no load; high quality mode 0.69 mA VBAT = 1.4V; no load; high quality mode 0.67 mA VBAT = 1.8V; no load; ECO mode 0.33 mA VBAT = 1.4V; no load; ECO mode 0.32 mA VBAT = 1.8V; no load 0.3 mA VBAT = 1.4V; no load 0.26 mA VBAT = 1.8V; OP1L, OP1R enabled, 250µA microphone load; all amplifiers in high quality mode 15 mW VBAT = 1.4V; OP1L, OP1R enabled, 250µA microphone load; all amplifiers in high quality mode 10.7 mW VBAT = 1.8V; OP1L, OP1R enabled, 250µA microphone load; all amplifiers in ECO mode 12.4 mW VBAT = 1.4V; OP1L, OP1R enabled, 250µA microphone load; all amplifiers in ECO mode 8.8 mW Headphone stage current ANC Filter OPAMP current Microphone low noise LDO supply current Microphone supply charge pump current Typical System Power Consumption PFF PFF_ECO Typical power consumption feed forward application in high quality mode configuration Typical power consumption feed forward application in ECO mode configuration Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 11 Document Feedback 6 AS3418 Functional Description Functional Description This section provides a detailed description of the device related components. 6.1 Audio Line Input The chip features one stereo line input for music playback. In monitor mode the line inputs can also be muted in order to interrupt the music playback and increase speech intelligibility. Figure 7: Stereo Line Input MUTE to left headphone amplifier MUTE to right headphone amplifier LINL Music Left RLIN CLIN LINR Music Right CLIN RLIN If there is a high pass function desired in an application, to block very low frequencies that could harm the speaker or eliminate little offset voltages, a series capacitor CLIN can support this function. The implementation is shown in Figure 7. The correct capacitor value for the desired cut-off frequency can be calculated with the following formula: Equation 1: 𝐶𝐿𝐼𝑁 = 1 2 ∗ 𝜋 ∗ 𝑅𝐿𝐼𝑁 ∗ 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓 A typical cut-off frequency in an audio application is 20Hz. With an input impedance RLIN of typ. 1kΩ and a desired cut off frequency of 20Hz the input capacitor should be bigger than 8µF. Therefore a typical value of 10µF is recommended. 6.1.1 Parameter VBAT=1.65V, TA= 25ºC unless otherwise specified. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 12 Document Feedback AS3418 Functional Description Figure 8: Parameter of Line Input 6.2 Symbol Parameter VLIN Conditions Min Typ Max Unit Input Signal Level VBAT* 0.9 VBAT VPEAK RLIN Input Impedance 1 AMUTE Mute Attenuation 100 kΩ dB Microphone Inputs The AS3418 offers two low noise microphone inputs with full digital control and a dedicated DC offset cancellation pin for each microphone input. In total each gain stage offers up to 63 gain steps of 0.5dB resulting in a gain range from 0dB to +31dB. The microphone gain is stored digitally during production, in an EEPROM memory on the ANC chip. Besides the standard microphone gain register for left and right channel, the chip features also four additional microphone gain registers for Monitor- and Playback Only operation mode. Thus, in Monitor/Playback Only mode, a completely different gain setting for left and right microphone can be selected to implement voice filter functions in order to amplify the speech band for better intelligibility. Figure 9: Stereo Microphone Inputs MICL MUTE AGC QMICL AGC QMICR DISCHARGE MICACL MICACR DISCHARGE MICR MUTE To avoid unwanted start-up pop noise, a soft-start function is implemented for an automatic gain ramping of the device. In case of an overload condition on the microphone input (e.g. high sound pressure level) there is also an automatic gain control (AGC) function available which reduces the gain to a moderate level. For some designs it might be useful to switch off this feature. Especially in feedback systems infrasound can cause an overload condition of the microphone preamplifier that results in low frequency noise which can be avoided by disabling the AGC. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 13 Document Feedback 6.2.1 AS3418 Functional Description Input Capacitor Selection The microphone preamplifier needs a bias resistor (RBias) per channel as well as DC blocking capacitors (CMIC). The capacitors CAC are DC blocking capacitors to avoid DC amplification of the noninverting microphone preamplifier. This capacitor has an influence on the frequency response because the internal feedback resistors create a high pass filter. The typical application circuit is shown in Figure 10 with all necessary components. Figure 10: Microphone Capacitor Selection Circuit MICS RBIAS CMIC ANC Microphone MICL DISCHARGE RMICIN CAC MUTE AGC QMICL AGC QMICR R2 R1 MICACL MICACR CAC R1 RMICIN ANC Microphone CMIC DISCHARGE MICR R2 MUTE MICS RBIAS The corner frequency of this high pass filter is defined with the capacitor CAC and the gain of the headphone amplifier. Figure 11 shows an overview of typical cut-off frequencies with different microphone gain settings. Figure 11: Microphone Cut-Off Frequency Overview Microphone Gain R1 R2 fcut-off 0dB 22.2kΩ 0Ω 1.7Hz 3dB 15716Ω 6484Ω 1.9Hz 6dB 11126Ω 11074Ω 2.2Hz 9dB 7877Ω 14323Ω 2.7Hz 12dB 5576Ω 16623Ω 3.5Hz 15dB 3948Ω 18252Ω 4.5Hz Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 14 Document Feedback AS3418 Functional Description Microphone Gain R1 R2 fcut-off 18dB 2795Ω 19405Ω 6.1Hz 21dB 1979Ω 20221Ω 8.4Hz 24dB 1400Ω 20800Ω 11.5Hz 27dB 992Ω 21208Ω 16.3Hz 30dB 702Ω 21498Ω 22.7Hz It is important when doing the ANC filter simulations to include all microphone filter components to incorporate the gain and phase influence of these components. In the cut-off frequency overview, capacitor CAC was defined as 10µF which results in a rather low cut-off frequency for best ANC filter design. If a different capacitor value is desired in the application, the following formula defines the transfer function of the high pass circuit of the microphone preamplifier: Equation 2: |𝐴| = 2 ∗ 𝑓 2 ∗ (𝑅1 + 𝑅2 )2 ∗ 𝜋 2 + 1 √4 ∗ 𝐶𝐴𝐶 2 ∗ 𝑓 2 ∗ 𝑅12 ∗ 𝜋 2 + 1 √4 ∗ 𝐶𝐴𝐶 The simplified transfer function does not include the high pass filter defined by CMIC and RMICIN. With the recommended values of 2.2µF for CMIC and 22kΩ for RMICIN this filter can be neglected because of the very low cut-off frequency of 1.5Hz. The cut-off frequency for this filter can be calculated with the following formula: Equation 3: 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓 = 1 2 ∗ 𝜋 ∗ 𝑅𝑀𝐼𝐶𝐼𝑁 ∗ 𝐶𝑀𝐼𝐶 The simulated frequency response for the microphone preamplifier with the recommended component values is shown in Figure 12. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 15 Document Feedback AS3418 Functional Description Figure 12 : Simulated Microphone Frequency Response Frequency Response [dB] 35 30dB 30 25 24dB 20 18dB 15 12dB 10 6dB 5 0dB 0 -5 10 100 1k 10k f [Hz] In applications with PCB space limitations it is also possible to remove the capacitors CAC and connect MICACL and MICACR pins directly to AGND. In this configuration AC coupling of the QMICR and QMICL signals is recommended. 6.2.2 Parameter VBAT=1.8V, TA= 25ºC , CAC=10µF, CMIC=4.7µF and RMICIN=2.2kΩ unless otherwise specified. Figure 13: Microphone Parameter Symbol VMICIN_0 VMICIN_0 SNR Parameter Typical maximum Input Signal Level Signal to Noise Ratio Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 Conditions Min Typ Max Unit Preamplifier gain=0dB, THD < 0.1% 1050 mVRMS Preamplifier gain=20dB, THD < 0.1% 110 mVRMS 0dB gain, High quality mode, AGC disabled 119 dB 10dB gain, High quality mode, AGC disabled 109 dB 20dB gain, High quality mode, AGC disabled 106 dB 0dB gain, ECO mode, AGC disabled 117 dB 10dB gain, ECO mode, AGC disabled 108 dB 77 │ 16 Document Feedback Symbol VNOISE-A IMIC AMIC Parameter A-weighted output noise floor Block Current Consumption Programmable Gain Gain Step Size Gain Step Precision Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 Conditions AS3418 Functional Description Min Typ Max Unit 20dB gain, ECO mode, AGC disabled 105 dB 0dB gain, 20Hz – 20kHz bandwidth, high quality 1.3 µV 10dB gain, 20Hz – 20kHz bandwidth, high quality 4.5 µV 20dB gain, 20Hz – 20kHz bandwidth, high quality 13.7 µV 0dB gain, 20Hz – 20kHz bandwidth, ECO mode 1.4 µV 10dB gain, 20Hz – 20kHz bandwidth, ECO mode 5 µV 20dB gain, 20Hz – 20kHz bandwidth, ECO mode 15.7 µV VBAT = 1.8V; no signal, stereo, normal mode 1 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.7 mA VBAT = 1.4V; no signal, stereo, normal mode 0.9 mA VBAT = 1.4V; no signal, stereo, ECO mode 0.6 mA 0 31 0.5 dB dB 0.2 dB 77 │ 17 Document Feedback AS3418 Functional Description Figure 14 : Microphone Frequency Response (MICACx grounded; CMIC=10µF) Frequency Response [dB] 35 30dB 30 25 20dB 20 15 10dB 10 5 0dB 0 -5 10 100 1k 10k 100k f [Hz] Figure 15: Microphone THD+N vs. Vinput High Quality Mode (A-weighted) 1 THD+N [%] 0,1 0,01 0,001 0,0001 10 100 Vinput [mV] Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 18 Document Feedback AS3418 Functional Description Figure 16: Microphone THD+N vs. Vinput ECO Mode (A-weighted) 1 THD+N [%] 0,1 0,01 0,001 0,0001 10 100 Vinput [mV] 6.3 Microphone Supply The AS3418 features an integrated microphone supply voltage regulator and a charge pump to source the microphone LDO even with a 1.4V chip supply voltage in order to increase the sensitivity of the microphone. The microphone supply charge pump is in default configuration enabled and can be controlled in ANC and Monitor operation mode with register ANCMON_MICS_CP_ON bit. For PBO operation mode there is a dedicated control bit PBO_MICS_CP_ON. The output of the charge pump is directly connected to an internal microphone supply ultra-low noise voltage regulator. This low dropout (LDO) regulator is in default configuration enabled and can be controlled with ANCMON_MICS_ON bit. The default output voltage of the regulator is 2.9V. If there is a lower output voltage desired in an application the voltage level can be changed via register MICS_V_SEL register. If the AS3418 is connected to a 1.5V battery the input voltage will of course drop during operation because the battery is discharging during operation. In order to make sure the microphone supply LDO has enough headroom to regulate properly the device features an automatic output voltage adjustment feature. This function makes sure the voltage regulator has enough headroom and adjusts the output voltage of the LDO accordingly. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 19 Document Feedback AS3418 Functional Description Figure 17: Microphone Supply ANCM ON_M ICS_CP_BYP_EN M ICS_V_SEL M ICS_V_LEV MIC Charge Pump ANCM ON _ M ICS_ON to microphone BIAS resis tors MICS ANCM ON _M ICS_CP_ON VBAT MSUP CMICS LDO CMSUP The microphone supply charge pump is also used to switch off the integrated music bypass switch of the AS3418 in active mode. Therefore, during normal operation the microphone supply must not be switched off if the BPL and BPR pins are in use. 6.3.1 Parameter VBAT=1.8V, TA= 25ºC, CMSUP = 4.7µF and CMICS = 4.7µF unless otherwise specified. Figure 18: Microphone Supply Parameter Symbol VMICS VMSUP VNoise-A IMICS Parameter Microphone supply LDO output voltage Microphone supply charge pump output voltage Microphone Supply Noise at MICS output Current consumption low noise voltage regulator Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 Conditions Min Typ Max Unit VBAT= 1.8V; no load; charge pump activated 2.9 V VBAT=1.4V; no load; charge pump activated 2.5 V VBAT= 1.8V; no load; MICS voltage regulator off 3.15 V VBAT= 1.4V; no load; MICS voltage regulator off 2.7 V High quality mode enabled; 1mA load; A-weighted 1.7 µV High quality mode disabled; 1mA load; A-weighted 2.2 µV VBAT = 1.8V; no load; HIQ_EN_MICS_LDO = 1 0.69 mA VBAT = 1.4V; no load; HIQ_EN_MICS_LDO = 1 0.67 mA 77 │ 20 Document Feedback Symbol IMICS_CP IOUT Parameter AS3418 Functional Description Conditions Current consumption microphone supply charge pump Output current Min Typ Max Unit VBAT = 1.8V; no load; HIQ_EN_MICS_LDO = 0 0.33 mA VBAT = 1.4V; no load; HIQ_EN_MICS_LDO = 0 0.32 mA VBAT= 1.8V; MICS voltage regulator off; no load 0.3 mA VBAT= 1.8V; MICS voltage regulator off; 1mA load 3.5 mA VBAT= 1.4V; MICS voltage regulator off; no load 0.26 mA VBAT= 1.4V; MICS voltage regulator off; 1mA load 3.33 mA Charge pump activated 2 mA Figure 19: Microphone Supply Load Characteristic VMICS [V] 3 2 1 VBAT=1,4V VBAT=1.8V 0 1 2 3 4 Iload [mA] 6.4 Headphone Amplifier The headphone amplifier is a true ground output using VNEG as negative supply. It is designed to feature an output power of 2x34mW @ 32Ωload. For higher output requirements, the headphone amplifier is also capable of operating in bridged mode. In this mode the left output is carrying the inverted signal of the right output shown in Figure 21. With a VBAT voltage of 1.8V, a maximum output power of 100mW can be achieved. This is necessary for over- and on ear headsets with higher output power requirements. The amplifier itself features various input sources. The line input signal is directly connected to the headphone amplifier. The input multiplexer supports three different input signals Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 21 Document Feedback AS3418 Functional Description which can be configured according in the ANC_HPH_MUX, MON_HPH_MUX and PBO_HPH_MUX registers independently for each operation mode. The “Open” setting is being used to disable the active noise cancelling function. Figure 20: Headphone Amplifier Single Ended XXX_HPH_MUX 1kΩ MUX QMICR QOP1R 1kΩ open LINE_MUTE 1kΩ LINR HPR RLI N AGND RLI N HPL LINE_MUTE LINL 1kΩ MUX QMICL QOP1L open 1kΩ 1kΩ 1k 1k XXX_HPH_MUX Figure 21: Headphone Amplifier Differential XXX_HPH_MUX MUX QMICL QOP1L open LINR 1k LINE_MUTE HPR RLI N AGND HPL 1k Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 1k 77 │ 22 Document Feedback 6.4.1 AS3418 Functional Description Parameter VBAT =1.8V, TA= 25ºC, unless otherwise specified. Figure 22: Microphone Supply Parameter Symbol Parameter RL_HP Load Impedance CL_HP Load Capacitance PHP PBRIDGE IHPH PSRRHP SNR Nominal Output Power Stereo Mode Nominal Output Power Differential Mode Supply Current Power Supply Rejection Ratio Signal to Noise Ratio Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 Conditions Min Typ Stereo Operation Mode 16 32 Mono Operation Mode 32 Max Unit Ω Ω Per channel 100 pF VBAT= 1.8V; 32Ω load; THD PWR_UP_BUT_TIME 6.8.2 ON > MON_TIME > MON_TIME > SHUTDOWN_DELAY Slider Mode Slider Mode is similar to Full Slider Mode with the only difference that it is possible to use a push button (S3) to enable and disable the Monitor Mode. In order to enable this operation mode, register UI_MODE has to be set to ‘d1’. The typical connection of the slide switches and push button is shown in Figure 45. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 35 Document Feedback AS3418 Functional Description Figure 45: Slider Mode VBAT MODE/CSCL S1 S2 S3 ON Control Logic ANC/CSDA 22kΩ 22kΩ MONITOR OFF ANC PBO The advantage of this mode compared to Full Slider Mode is the automatic hold function of the Monitor Mode. Once the push button S3 is pressed, the device enters monitor mode. This mode stays active until the user pushes the button again. Figure 46: Slider Mode Timing Diagram Operation Mode OFF ON MONITOR ON VBAT >=1.65V MODE/CSCL Pin OFF 45% - 55% VBAT PWR_UP_BUT_TIME 6.8.3 > MON_TIME > MON_TIME > SHUTDOWN_DELAY Push Button Mode Push Button mode allows the user to control the device with a single normally open (NO) push button. A simple key press (>PWR_UP_BUT_TIME) powers up the AS3418. Once the device is running, a long key press (>PWR_DOWN_BUT_TIME) the device down. The device features two configuration registers (PWR_UP_BUT_TIME and PWR_DOWN_BUT_TIME) that allows the user to re-configure the power up- and power down button press time. Monitor Mode can be activated with a second, short key press. To avoid unwanted change of operation mode it is also possible to configure the button press time (MON_TIME) to enter monitor mode. A timing diagram of this function is shown in Figure 48. If the monitor mode function is not desired, it is possible to deactivate the monitor mode by clearing the bit MON_EN in register 0x0F. The typical connection of the push button to the AS3418 is shown in Figure 47. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 36 Document Feedback AS3418 Functional Description Figure 47: Push Button Mode VBAT MODE/CSCL ANC/CSDA Control Logic S2 S4 22k ANC ON/OFF/MONITOR PBO Figure 48: Push Button Timing Diagram Operation Mode OFF ANC MONITOR ANC OFF >65% VBAT MODE/CSCL Pin PWR_UP_BUT_TIME 6.8.4 > MO N_TIME > MO N_TIME >PW R_DOWN_BUT_TIME Playback Only Mode The active noise cancelling feature of the AS3418 can also be disabled with the ANC/CSDA pin. The ANC/CSDA pin has to be pulled high to enable the ANC function during startup (ANC MODE). If the pin is connected to ground, the chip enters playback only mode (PBO MODE) in which the ANC function can be disabled or an alternative monitor/ANC mode is configured. The functional blocks in this operation mode can be controlled in registers PBO_MODE0 and PBO_MODE1. Typically only the line input amplifiers and the headphone amplifier are enabled in the playback only mode. If this function is not desired you just need to pull the pin high with an external 22kΩ resistor. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 37 Document Feedback AS3418 Functional Description Figure 49: Playback Only Mode Timing Diagram Operation Mode ANC ON Playback Only Mode ANC ON >65% VBAT ANC/CSDA Pin EE_RE ADY PWR_UP_BUT_TIME ON_DELAY HIQ_EN _MICS_ LDO HIQ_EN _HPH HIQ_EN _MIC HIQ_EN _OPAM P MON_ILED - ANC_LED_MODE< 1:0> ANC_ILED - - - ANC_O P1L_O N ANC_O P1R_O N 0 0 MON_O P1L_O N MON_O P1R_O N - - MON_HPH_MUX< 1:0> ANC Mode Control Registers 0x0A ANC_MODE_REG ANC_HPH_MUX LIN_MU TE 0x0B ANC_MIC_LEFT_GAI N - ANC_MIC_LEFT_GAIN 0x0C ANC_MIC_RIGHT_G AIN - ANC_MIC_RIGHT_GAIN Monitor Mode Control Registers 0x0D MONITOR_MODE0 MON_E N 0 MON_LI N_MUT E 0x0E MONITOR_MODE1 - - MON_TIME Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 MON_M IX_EN 77 │ 47 Document Feedback AS3418 Register Description Addr Name 0x0F MON_MIC_LEFT_GA IN - MON_MIC_LEFT_GAIN 0x10 MON_MIC_RIGHT_G AIN - MON_MIC_RIGHT_GAIN PBO_E N - PBO_LI N_MUT E PBO_M IX_EN - - PBO_O P1L_O N PBO_O P1R_O N PBO_M ICS_CP _BYP_ EN PBO_M ICS_LD O_ON PBO_M ICS_CP _ON PBO_M IC_ON AGC_RELEASE_L EVEL AGC_M UTE_E N PBO Mode Control Registers 0x11 PBO_MODE0 0x12 PBO_MODE1 - HPH_O N/DIS_ BYPAS S 0x13 PBO_MIC_LEFT_GAI N - PBO_MIC_LEFT_GAIN 0x14 PBO_MIC_RIGHT_G AIN - PBO_MIC_RIGHT_GAIN AGC_ATTACK_LE VEL PBO_HPH_MUX AGC Control Registers 0x15 AGC_CONTROL0 ZERO_ CROSS _EN 0x16 AGC_ATTACK_RELE ASE_TIME AGC_RELEASE_TIME AGC_ATTACK_TIME 0x17 AGC_HOLD ZERO_TIMEOUT HOLD_TIME 0x18 AGC_START_TIME - - - - - NEG_A TT_EN AGC_E N - - START_RAMP_TIME SHUTDOWN_DEL AY - MODE_SWITCH_D ELAY GAIN_J UMP_U P_EN GAIN_J UMP_D OWN_E N - - - EEPRO M_UPL OAD_T EST EEPRO M_UPL OAD EEPRO M_DO WNLOA D Operation Mode Control Register 0x1A MODE_SWITCH_CO NTROL EEPROM Control Register 0x34 EEPROM_CONTROL Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 - 77 │ 48 Document Feedback 7.2 Detailed Register Description 7.2.1 System Registers AS3418 Register Description Figure 67: ID Register Description Addr: 0x00 ID Bit Bit Name Default Access Bit Description 7:4 DESIGN_VER SION 0110 R Design version number to identify the design version of the AS3418. 0110: Chip Version 3.0 3:0 CHIP_ID 0001 R This register represents the chip ID number of AS3418. 0001: AS3418 Figure 68: SYSTEM_STATUS Register Description Addr: 0x01 SYSTEM_STATUS Bit Default 4 3 1 0 Bit Name EE_WR_TEST _OK EE_READY PWRUP_COM PLETE PWR_HOLD Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 - - 1 1 Access Bit Description R This register reports if an EEPROM upload test was successfully finished. This bit is also used for the EEPROM-Program-Test (together with EEPROM_UPLOAD_TEST), where a “dummy-write” can be initialized to check the power-supply 0: EEPROM upload TEST failed 1: EEPROM upload TEST successful R This registers indicates the status after a read/write command of the EEPROM. 0: EEPROM busy 1: EEPROM ready R This bit indicates the Power-Up sequencer status of AS3418. The signal goes high after all amplifiers are enabled but before the microphone signal is faded in. 0: Power-up sequence incomplete 1: Power-up sequence completed R/W This bit allows an MCU, using the I2C interface, to power down the AS3418. A start condition on the I2C interface will wake up the device again. This function 77 │ 49 Document Feedback Addr: 0x01 SYSTEM_STATUS Bit Default Bit Name Access AS3418 Register Description Bit Description works only if the I2C_MODE bit is set. In case I2C_MODE is low, the register content is ignored. 0: Power up hold is cleared and chip powers down 1: Device remains powered on Figure 69: MODE_REG0 Register Description Addr: 0x02 MODE_REG0 Bit Default 6 5 4:3 2 1 Bit Name EN_ZERO_C ROSS DELAY_HPH_ MUX UI_MODE MICS_DC_EN HPH_MODE Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 1 0 01 1 0 Access Bit Description R/W This bit activates zero cross detection while switching between music bypass switch and headphone amplifier. 0: Zero cross detection is disabled. 1: Zero cross detection is enabled. R/W This register controls the startup delay setting before the ANC_HPH_MUX setting is applied to the system. This function can help to reduce pop noise during startup of the device especially if there are components with long charging times involved. This bit is only valid during initial startup. 0: Headphone MUX delay disabled 1: Headphone MUX delay enabled R/W This register defines the user interface operation mode of AS3418. For a detailed description of the different user interface modes please refer to chapter Operation Modes. 00: Push Button Operation Mode 01: Slider Operation Mode 10: Full Slider Operation 11: Do not use R/W This bit enables the internal microphone supply discharge function if the microphone supply is switched off. The MICS_LDO pin is discharged within ~ 10ms. 0: MICS_LDO discharge disabled 1: MICS_LDO discharge enabled R/W This register controls the operation mode of the headphone amplifier. The headphone amplifier supports single ended mode and differential mode. In differential output mode the right audio signal path is the active input signal for the headphone amplifier. 77 │ 50 Document Feedback Addr: 0x02 MODE_REG0 Bit Default Bit Name Access AS3418 Register Description Bit Description 0: Stereo single ended mode 1: Mono differential mode 0 I2C_MODE 0 R/W All registers can be read and written by the I2C interface independent on the level of I2C_MODE bit but I2C_MODE controls whether the main modes of AS3418 (MON/ANC/PBO/ON/OFF) are controlled by the MON_MODE_EN, PBO_MODE_EN bits and SYSTEM_STATUS registers or by the buttons and switches. Once the bit is set and the system powers up because there’s an I2C start condition applied to the CSCL and CSDA pins, the user has to write the PWR_HOLD bit within SHUTDOWN_DELAY, otherwise AS3418 powers down again. This can be done either over the CSDA/CSCL or over the application trimming interface. 0: I2C mode control functions disabled 1: I2C mode control functions enabled Figure 70: MODE_REG1 Register Description Addr: 0x03 MODE_REG1 Bit Default 7 6 4 Bit Name PBO_MODE_ EN MON_MODE_ EN ANCMON_MI CS_BYP_EN Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0 0 0 Access Bit Description R/W In case I2C_MODE bit is not set, the register content is ignored but can be read and written. In case I2C_MODE bit is set, this bit controls the operation mode of AS3418 (ANC, MON, PBO). In case the PBO_MODE_EN is 1, MON_MODE_EN has to be 0. 0: ANC Mode 1: PBO Mode R/W In case I2C_MODE bit is not set, the register content is ignored but can be read and written. In case I2C_MODE bit is set, this bit controls the operation mode of AS3418 (ANC, MON, PBO). In case the PBO_MODE_EN is 1, MON_MODE_EN has to be 0. 0: ANC Mode 1: MON Mode R/W This bit enables the automatic VBAT to MICS bypass function when the microphone supply charge pump is switched off. This function has to be activated in case the microphone supply voltage regulator is supplied externally via MICS_CP pin. 77 │ 51 Document Feedback Addr: 0x03 MODE_REG1 Bit Default Bit Name Access AS3418 Register Description Bit Description 0: MIC charge pump bypass function disabled 1: MIC charge pump bypass function enabled 3 ANCMON_MI CS_CP_ON 1 R/W This bit controls the microphone supply charge pump. The microphone charge pump has a second function besides the bias voltage generation for microphones. It is also used to disable the integrated music bypass switch if the AS3418 is active. In case the integrated bypass switch is used in an application this bit must not be set to ‘0’. 0: Microphone supply charge pump disabled 1: Microphone supply charge pump enabled WARNING: Microphone supply is also used for disabling the Bypass switch. If Microphone supply is disabled an external supply is required. 2 ANCMON_MI CS_LDO_ON 1 R/W This bit controls the microphone supply. In case this bit is set to ‘1’ the microphone supply voltage regulator (MICS output pin) is powered up. 0: Microphone supply switched off 1: Microphone supply switched on 1 ANCMON_MI C_ON 1 R/W This bit powers up the microphone preamplifier. 0: Microphone preamplifier disabled 1: Microphone preamplifier enabled R/W This bit allows the user to power down headphone amplifier in case it is not used in the final application in order to save system power. 0: Headphone amplifier disabled 1: Headphone amplifier enabled 0 ANCMON_HP H_ON 1 Figure 71: MICS_VOLTAGE Register Description Addr: 0x04 MICS_VOLTAGE Bit Bit Name Default 7 MICS_LDO_C V_MODE 6 MICS_LDO_C D_MODE Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 - - Access Bit Description R Signals if the MICS_LDO is in constant voltage mode. 1: Constant voltage mode active 0: Constant voltage mode inactive R Signals if the microphone supply is in constant drop mode 1: Constant drop mode active 0: Constant drop mode inactive 77 │ 52 Document Feedback Addr: 0x04 MICS_VOLTAGE Bit Default 3:0 Bit Name MICS_V_SEL 1011 AS3418 Register Description Access Bit Description R/W This register controls the output voltage of the integrated microphone supply regulator. 0000: 1.6V 0001: 1.7V 0010: 1.8V 0011: 1.9V 0100: 2.0V 0101: 2.1V 0110: 2.2V 0111: 2.3V 1000: 2.4V 1001: 2.5V 1010: 2.6V 1011: 2.7V(default) 1100: 2.8V 1101: 2.9V 1110: Do not use … 1111: Do not use Figure 72: PUSH_DELAY Register Description Addr: 0x05 PUSH_DELAY Bit Default 5:3 Bit Name PWR_DOWN_ BUT_TIME Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 111 Access Bit Description R/W This register controls the hold time for the push button in order to power down the AS3418. Depending on the register setting the power down push button time can be programmed accordingly. This delay is applied for button, slider and full slider mode. 000: 5ms 001: 500ms 010: 1000ms 011: 1500ms 100: 2000ms 101: 2500ms 110: 2500ms 111: 2500ms 77 │ 53 Document Feedback Addr: 0x05 PUSH_DELAY Bit Default 2:0 Bit Name PWR_UP_BU T_TIME 000 AS3418 Register Description Access Bit Description R/W This register controls the hold time for the push button in order to power up the AS3418. Depending on the register setting the power up push button time can be programmed accordingly. This delay is applied for button, slider and full slider mode. 000: 5ms 001: 500ms 010: 1000ms 011: 1500ms 100: 2000ms 101: 2500ms 110: 2500ms 111: 2500ms Figure 73: ON_DELAY Register Description Addr: 0x06 ON_DELAY Bit Default 5:3 2:0 Bit Name LDO_BOOST ON_DELAY Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 001 000 Access Bit Description R/W This register controls the pre-charge time of the microphone supply LDO. LDO_BOOST is effective not only during startup but also whenever the LDO is enabled after startup. 000: 0ms 001: 150ms 010: 400ms 011: 600ms 100: 800ms 101: 1000ms 110: 1200ms 111: 1500ms R/W This register controls the power on delay setting. If this register is set, the device powers up but stays in a Mute mode with the integrated bypass switches deactivated to block unwanted noise at the line input. 000: 0ms 001: 200ms 010: 400ms 011: 600ms 100: 800ms 101: 1200ms 77 │ 54 Document Feedback Addr: 0x06 ON_DELAY Bit Default Bit Name Access AS3418 Register Description Bit Description 110: 1600ms 111: 2000ms Figure 74: ECO_MODE_REG Register Description Addr: 0x07 ECO_MODE_REG Bit Default 7:6 3 2 1 0 Bit Name HIQ_ECO_PR ESET HIQ_EN_MIC S_LDO HIQ_EN_HPH HIQ_EN_MIC HIQ_EN_OPA MP Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 00 1 1 1 1 Access Bit Description R/W This register allows the device to achieve best offset performance. Depending on the quality settings of headphone amplifier, microphone pre-amplifier and OP1 the correct preset from the table below has to be configured to ensure lowest offset values. 00: HPH->HIQ; MIC->HIQ; OP1->HIQ 01: HPH->HIQ; MIC->ECO; OP1->ECO 10: HPH->HIQ; MIC->HIQ; OP1->ECO 11: HPH->ECO; MIC->ECO; OP1->ECO R/W This bit enables the high quality mode of the microphone LDO. 0: High quality function disabled 1: High quality function enabled R/W This bit enables the high quality mode of the headphone amplifier. 0: High quality function disabled 1: High quality function enabled R/W This bit enables the high quality mode of the microphone amplifier. 0: High quality function disabled 1: High quality function enabled R/W This bit enables the high quality mode of the operational amplifier amplifiers for ANC filter design. 0: High quality function disabled 1: High quality function enabled 77 │ 55 Document Feedback AS3418 Register Description Figure 75: LED_MON Register Description Addr: 0x08 LED_MON Bit Default 4:2 1:0 Bit Name MON_LED_M ODE MON_ILED 000 00 Access Bit Description R/W This register controls blinking time of LED in MON mode. 000: LED always on 001: 80ms PWM active / 80ms off 010: 80ms PWM active / 160ms off 011: 80ms PWM active / 240ms off 100: 80ms PWM active / 320ms off 101: 80ms PWM active / 400ms off 110: 80ms PWM active / 480ms off 111: 80ms PWM active / 560ms off R/W This register controls the integrated LED driver current sink of the AS3418 in Monitor operation mode. 00: ILED current sink switched off 01: 25% duty cycle (4µs on/ 14µs off) 10: 50% duty cycle (9µs on/ 9µs off) 11: 100% duty cycle (18µs on/ 0µs off) Access Bit Description Figure 76: LED_ANC Register Description Addr: 0x09 LED_ANC Bit Default 6:5 3:2 Bit Name PBO_LED_M ODE ANC_LED_M ODE Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 00 00 R/W R/W Defines the blinking scheme if PBO mode is active. Please note that PBO mode has not an individual LED control register. Therefore this setting uses hardcoded 25% PWM duty cycle for brightness. 00: LED always off 01: Blinking scheme as in ANC mode 10: Blinking scheme as in MON mode 11: LED always on (=PWM always active) This register controls the different LED effects for ANC mode with various on/off times as well as different flash frequencies. 00: LED always on 01: 80ms on / 1s off 10: 80ms on / 1.5s off 77 │ 56 Document Feedback Addr: 0x09 LED_ANC Bit Default Bit Name Access AS3418 Register Description Bit Description 11: 80ms on / 2.5s off 1:0 ANC_ILED 00 R/W This register controls the integrated LED driver current sink of the AS3418 in ANC operation mode. The typical PWM frequency is 1/18µs=55.6kHz. 00: ILED current sink switched off 01: 25% duty cycle (4µs on/ 14µs off) 10: 50% duty cycle (9µs on/ 9µs off) 11: 100% duty cycle (18µs on/ 0µs off) 7.2.2 ANC Mode Control Registers Figure 77: ANC_MODE_REG Register Description Addr: 0x0A ANC_MODE_REG Bit Default 7:6 Bit Name ANC_HPH_M UX 5 LIN_MUTE 1 ANC_OP1L_O N 0 ANC_OP1R_ ON Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 11 0 0 0 Access Bit Description R/W This register selects the ANC input source for the headphone amplifier in ANC mode. Depending on the register, setting different outputs are routed to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use this setting 11: Nothing connected to HPH input except line input in case it is enabled. R/W This bit mutes the line input signal. If the bit is set the line input signal is disconnected from the headphone amplifier in ANC operation mode. 0: Line input signal enabled 1: Line input signal muted R/W This register enables the left channel of OPAMP 1 in ANC operation mode. 0: Left OP1 is switched off 1: Left OP1 is switched on R/W This register enables the right channel of OPAMP 1 in ANC operation mode. 0: Right OP1 is switched off 77 │ 57 Document Feedback Addr: 0x0A ANC_MODE_REG Bit Default Bit Name Access AS3418 Register Description Bit Description 1: Right OP1 is switched on Figure 78: ANC_MIC_LEFT_GAIN Register Description Addr: 0x0B ANC_MIC_LEFT_GAIN Bit Default 6:0 Bit Name ANC_MIC_LE FT_GAIN 101 0111 Access Bit Description R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for ANC operation mode. 000 0000: 0dB 000 0001: 0.5dB gain 000 0010: 1.0dB gain 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: Do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) Figure 79: ANC_MIC_RIGHT_GAIN Register Description Addr: 0x0C ANC_MIC_RIGHT_GAIN Bit Default Bit Name Access Bit Description Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for ANC operation mode. 6:0 ANC_MIC_RI GHT_GAIN 101 0111 R/W 000 0000: 0dB 000 0001: 0.5dB gain 000 0010: 1.0dB gain 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: Do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 58 Document Feedback Addr: 0x0C ANC_MIC_RIGHT_GAIN Bit Default Bit Name Access AS3418 Register Description Bit Description 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) 7.2.3 Monitor Mode Control Registers Figure 80: MONITOR_MODE0 Register Description Addr: 0x0D MONITOR_MODE0 Bit Default Bit Name 7 MON_ EN 5 MON_LIN_MU TE 1 0 MON_OP1L_ ON MON_OP1R_ ON 1 1 0 0 Access Bit Description R/W This bit disables the monitor mode function in all operation modes. 0: Monitor mode disabled 1: Monitor mode enabled R/W This bit enables mute function for the line input in monitor more. 0: Line input enabled in Monitor mode 1: Line input muted in Monitor mode R/W This register enables the left channel of OPAMP 1 in MON operation mode. 0: Left OP1 is switched off 1: Left OP1 is switched on R/W This register enables the right channel of OPAMP 1 in MON operation mode. 0: Right OP1 is switched off 1: Right OP1 is switched on Figure 81: MONITOR_MODE1 Register Description Addr: 0x0E MONITOR_MODE1 Bit Default 5:4 Bit Name MON_TIME 00 Access Bit Description R/W Time needed to press the monitor switch until monitor mode is activated. 00: 25ms 01: 200ms Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 59 Document Feedback Addr: 0x0E MONITOR_MODE1 Bit Default Bit Name Access AS3418 Register Description Bit Description 10: 400ms 11: 600ms 1:0 MON_HPH_M UX 00 R/W This register selects the ANC input source for the headphone amplifier in Monitor mode. Depending on the register setting different outputs are routed to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use (reserved for OP2) 11: QMIC, OP1 are disconnected from HPH Figure 82: MON_MIC_LEFT_GAIN Register Description Addr: 0x0F MON_MIC_LEFT_GAIN Bit Default 6:0 Bit Name MON_MIC_LE FT_GAIN Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 101 0111 Access Bit Description R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for Monitor operation mode. 000 0000: 0dB 000 0001: 0.5dB gain 000 0010: 1.0dB gain 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: Do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) 77 │ 60 Document Feedback AS3418 Register Description Figure 83: MON_MIC_RIGHT_GAIN Register Description Addr: 0x10 MON_MIC_RIGHT_GAIN Bit Default Bit Name Access Bit Description Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for Monitor operation mode. 000 0000: 0dB 000 0001: 0.5dB gain 6:0 7.2.4 MON_MIC_RI GHT_GAIN 101 0111 R/W 000 0010: 1.0dB gain 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) PBO Mode Control Registers Figure 84: PBO_MODE0 Register Description Addr: 0x11 PBO_MODE0 Bit Default Bit Name 7 PBO_EN 5 PBO_LIN_MU TE 1 PBO_OP1L_O N Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 1 0 0 Access Bit Description R/W This bit disables the Playback Only mode function in all modes. No external pull up resistor is required on ANC / CSDA pin if this bit is set to ‘0’. 0: Playback only mode disabled 1: Playback only mode enabled R/W This bit mutes the line input in Playback Only operation mode. 0: Line input enabled 1: Line input muted R/W This register enables the left channel of OPAMP 1 in playback only mode. 0: Left OP1 is switched off 1: Left OP1 is switched on 77 │ 61 Document Feedback Addr: 0x11 PBO_MODE0 Bit Bit Name Default 0 PBO_OP1R_ ON 0 AS3418 Register Description Access Bit Description R/W This register enables the right channel of OPAMP 1 in playback only mode. 0: Right OP1 is switched off 1: Right OP1 is switched on Figure 85: PBO_MODE1 Register Description Addr: 0x12 PBO_MODE1 Bit Default Bit Name Access Bit Description R/W This register disables the headphone amplifier in Playback Only mode and enables the integrated music bypass switch. 0: Headphone amplifier disabled/ Bypass enabled 1: Headphone amplifier enabled R/W This bit disables the automatic charge pump bypass function if the microphone supply charge pump is in off mode. 0: Charge Pump bypass disabled 1: Charge Pump bypass enabled 0 6 HPH_ON/DIS_ BYPASS 0 5 PBO_MICS_C P_BYP_EN 1 4 PBO_MICS_L DO_ON This bit enables the microphone LDO in Playback Only operation mode. R/W 1 3 PBO_MICS_C P_ON R/W This bit controls the microphone supply charge pump. Please mind that disabling the charge pump automatically activates the integrated music bypass switch. 0: Microphone supply charge pump disabled 1: Microphone supply charge pump enabled R/W This register controls the microphone preamplifier in Playback Only operation mode. 0: Microphone preamplifier disabled 1: Microphone preamplifier enabled R/W This register selects the input source of the headphone amplifier in Playback Only operation mode. Depending on register setting the microphone 0 2 PBO_MIC_ON 1:0 PBO_HPH_M UX Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0: Microphone Supply voltage LDO regulator disabled 1: Microphone Supply voltage LDO regulator enabled 11 77 │ 62 Document Feedback Addr: 0x12 PBO_MODE1 Bit Default Bit Name Access AS3418 Register Description Bit Description preamplifier or OPAMP1 can be connected to the headphone amplifier input. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use 11: Nothing connected to HPH input except line input. Figure 86: PBO_MIC_LEFT_GAIN Register Description Addr: 0x13 PBO_MIC_LEFT_GAIN Bit Default Bit Name Access Bit Description Volume settings for left microphone input, adjustable in 63 steps of 0.5dB for PBO operation mode. 000 0000: 0dB 000 0001: 0.5dB gain 6:0 PBO_MIC_LE FT_GAIN 101 0111 R/W 000 0010: 1.0dB gain 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) Figure 87: PBO_MIC_RIGHT_GAIN Register Description Addr: 0x14 PBO_MIC_RIGHT_GAIN Bit Default 6:0 Bit Name PBO_MIC_RI GHT_GAIN Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 101 0111 Access R/W Bit Description Volume settings for right microphone input, adjustable in 63 steps of 0.5dB for PBO operation mode. 000 0000: 0dB 000 0001: 0.5dB gain 000 0010: 1.0dB gain 77 │ 63 Document Feedback Addr: 0x14 PBO_MIC_RIGHT_GAIN Bit Default Bit Name Access AS3418 Register Description Bit Description 000 0011: 1.5dB gain … 011 1110: 31dB gain 011 1111: do not use 101 0111: MUTE (Mute code if NEG_ATT_EN bit set) 111 1111: MUTE (Mute code if NEG_ATT_EN bit not set) 7.2.5 AGC Control Registers Figure 88: AGC_CONTROL0 Register Description Addr: 0x15 AGC_CONTROL0 Bit Default 7 6:5 4:3 2 Bit Name ZERO_CROS S_EN ATTACK_LEV EL RELEASE_LE VEL AGC_MUTE_ EN Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0 0 00 0 Access Bit Description R/W This register disables the zero cross detection function of the AGC. 0: Zero cross detection disabled 1: Zero cross detection enabled R/W R/W R/W This register controls the attack level threshold voltage of the AGC. 00: 0.277* VBAT attack level 01: 0.333* VBAT attack level 10: 0.395* VBAT attack level 11: 0.463* VBAT attack level This register controls the release level threshold voltage of the AGC. 00: 0.200* VBAT release level 01: 0.250* VBAT release level 10: 0.304* VBAT release level 11: 0.364* VBAT release level This bit enables the mute function for the automatic gain control. 0: AGC mute function disabled 1: AGC mute function enabled 77 │ 64 Document Feedback Addr: 0x15 AGC_CONTROL0 Bit Default 1 0 Bit Name NEG_ATTEN_ EN AGC_EN 0 0 AS3418 Register Description Access Bit Description R/W This bit enables negative the negative gain option for the microphone preamplifier in case of a microphone overload condition. The gain can go down to -40dB. In case the AGC_MUTE_EN bit is not. If the AGC_MUTE_EN bit is set the preamplifier goes to 40dB and eventually mutes the output. 0: Negative attenuation disabled 1: Negative attenuation enabled R/W This bit enables/disabled the automatic gain control function of AS3418. This setting is valid for ANC, Monitor and PBO operation mode. 0: AGC disabled 1: AGC enabled Figure 89: AGC_ATTACK_RELEASE_TIME Register Description Addr: 0x16 AGC_ATTACK_RELEASE_TIME Bit Default Bit Name Access Bit Description This register controls the AGC release time. 0000: 0ms 0001: 0.5ms 7:4 AGC_RELEAS E_TIME 0001 R/W 0010: 1ms 0011: 2ms 0100: 4ms 0101: 8ms 0110: 10ms 0111: 12ms 1000: 16ms 1001: 20ms 1010: 24ms 1011: 28ms 1100: 32ms 1101: 64ms 1110: 128ms 1111: 256ms 3:0 AGC_ATTACK _TIME Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0000 R/W This register controls the AGC attack time. 0000: 0.5µs 0001: 1µs 0010: 2µs 77 │ 65 Document Feedback Addr: 0x16 AGC_ATTACK_RELEASE_TIME Bit Default Bit Name Access AS3418 Register Description Bit Description 0011: 4µs 0100: 8µs 0101: 12µs 0110: 16µs 0111: 24µs 1000: 32µs 1001: 64µs 1010: 128µs 1011: 256µs 1100: 512µs 1101: 1000µs 1110: 2000µs 1111: 4000µs Figure 90: AGC_HOLD Register Description Addr: 0x17 AGC_HOLD Bit Default Bit Name Access Bit Description 7:4 ZERO_TIMEO UT 0000 R/W This register controls the timeout of the zero cross detection. 0000: 0 (no timeout) 0001: 20ms 0010: 40ms 0011: 80ms 0100: 120ms 0101: 160ms 0110: 240ms 0111: 320ms 1000: 400ms 1001: 480ms 1010: 560ms 1011: 640ms 1100: 800ms 1101: 960ms 1110: 1120ms 1111: 1280ms 3:0 HOLD_TIME 0000 R/W This register controls the AGC hold time. 0000: 0 (no hold time) Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 66 Document Feedback Addr: 0x17 AGC_HOLD Bit Default Bit Name Access AS3418 Register Description Bit Description 0001: 20ms 0010: 40ms 0011: 80ms 0100: 120ms 0101: 160ms 0110: 240ms 0111: 320ms 1000: 400ms 1001: 480ms 1010: 560ms 1011: 640ms 1100: 800ms 1101: 960ms 1110: 1120ms 1111: 1280ms Figure 91: AGC_START_TIME Register Description Addr: 0x18 AGC_START_TIME Bit Default Bit Name Access Bit Description This register controls the AGC gain ramp up step time only during startup of the device. 000: 1ms/step 2:0 START_RAM P_TIME 000 R/W 001: 2ms/step 010: 4ms/step 011: 8ms/step 100: 16ms/step 101: 32ms/step 110: 64ms/step 111: 128ms/step Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 67 Document Feedback 7.2.6 AS3418 Register Description Operation Mode Control Register Figure 92: MODE_SWITCH_CONTROL Register Description Addr: 0x1A MODE_SWITCH_CONTROL Bit Default 6:5 Bit Name SHUTDOWN_ DELAY Access Bit Description This register controls the shutdown delay function of AS3418. 00: 10ms(default after reset) 00 R/W 01: 80ms 10: 200ms 11: 400ms 3:2 MODE_SWIT CH_DELAY 11 R/W Defines the time switching from ANC to PBO and PBO to MONITOR operation mode. During this mode switching delay the headphone amplifier multiplexer is not connected to any source. 00: 5ms 01: 100ms 10: 200ms 11: 400ms 1 0 GAIN_JUMP_ UP_EN GAIN_JUMP_ DOWN_EN Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0 0 R/W This bit is independent of AGC_EN bit. The gain after a gain register write is not immediately set but is stepped up from old to new value if it is lower than the old gain setting. Gain change will follow AGC_RELEASE_TIME register setting. 0: Gain Jump up disabled 1: The gain is immediately set after a gain register write if it is higher than the old gain setting R/W This bit is independent of AGC_EN bit. The gain after a gain register write is not immediately set but is stepped down from old to new value if it’s lower than the old gain setting. Gain change will follow AGC_ATTACK_TIME register setting. 0: Gain Jump down disabled 1: Gain jump down enabled 77 │ 68 Document Feedback 7.2.7 AS3418 Register Description EEPROM Control Registers Figure 93: EEPROM_CONTROL Register Description Addr: 0x34 EEPROM_CONTROL Bit Default 2 1 0 Bit Name EEPROM_UP LOAD_TEST EEPROM_UP LOAD EEPROM_DO WNLOAD Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 0 0 0 Access Bit Description R/W The register bit supports an EEPROM upload test function which simulates an EEPROM write without executing the actual write in order to check if the supply voltage is high enough for proper EEPROM programming. Once the bit is set, the test is started automatically and cleared after the test in finished. The result, if the test was positive, can be read out in register EE_WR_TEST_OK. 0: EEPROM upload test disabled 1: EEPROM upload test started R/W This register triggers the EEPROM upload function which copies all register content of AS3418 to the AS3418 to store it permanently to the device. Once the upload is completed the bit is cleared automatically. The success of the EEPROM upload can be read out in register EE_READY. 0: EEPROM upload function disabled 1: EEPROM upload function started R/W This register triggers the EEPROM download function which copies all EEPROM content to the AS3418 configuration regsiters. Once the download is completed the bit is cleared automatically. The success of the EEPROM download can be read out in register EE_READY. 0: EEPROM upload function disabled 1: EEPROM upload function started 77 │ 69 Document Feedback 8 AS3418 Application Information Application Information The following chapters provide application specific information like schematic examples and a summary of external components. 8.1 Schematic Figure 94 shows an example of a Feed Forward ANC headset in Push Button operation mode. Figure 94: Push Button Operation Mode – Application Example Left ANC Filter MICS R1 2k2 C1 MIC1 C3 VN EG 1uF C2 VN EG 10µF Left ANC MIC 2.2µF C4 10uF R2 GND C1 AGND D4 D6 R 2 GND 1 R3 R4 150 150 B5 B1 A3 GND VN EG QOP1L IOP1L QMICL VN EG VBAT AS3418 TRSDA HPL WL-CSP TRSCL AGND LINR HPR BPR MSUP MICR ANC/CSDA 4.7µF LINL MICS C6 2.2µF B4 4.7µF C4 A6 GND D5 B2 E5 E4 C9 AGND AGND Speaker Right 4.7µF C5 E6 C6 C2 A2 A1 B3 MICS AGND Speaker Left D2 ILED C8 B6 QOP1R 4.7µF MODE/CSCL C7 CPP MICACR L 3 C5 CPN BPL QMICR U2 MICL IOP1R E3 MICACL U1 D1 Music Line Input VBAT GND A5 C3 A4 D3 E1 AGND E2 2k2 AGND VBAT AGND 10k R5 C11 GND C12 MICS 10uF 4.7µF AGND R6 MIC2 2k2 C13 Right ANC Filter AGND 1uF VBAT Right ANC MIC R7 2k2 AGND AGND S1 Push Button On / Off / Monitor Figure 95 shows an application example of a Feed Forward ANC headset in Slider operation mode. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 70 Document Feedback AS3418 Application Information Figure 95: Slider Operation Mode – Application Example Left ANC Filter MICS R1 2k2 C1 MIC1 C3 VN EG 1uF C2 VN EG 10µF Left ANC MIC 2.2µF C4 10uF R2 GND 4.7µF D4 D6 R 2 GND 1 R3 R4 150 150 B5 B1 A3 C1 A4 E1 E2 A5 GND VN EG VN EG QOP1L IOP1L QMICL BPL CPP LINL VBAT AS3418 TRSDA HPL WL-CSP TRSCL AGND LINR HPR BPR MSUP MICR MICS C6 2.2µF B4 4.7µF C4 A6 GND D5 B2 E5 E4 C9 Speaker Right 4.7µF E6 C5 AGND VBAT AGND R5 C11 10k GND C12 MICS 10uF 2k2 C13 4.7µF Right ANC Filter AGND R6 MIC2 C6 C2 A1 B3 AGND A2 MICS AGND Speaker Left D2 ILED C8 B6 C5 CPN ANC/CSDA 4.7µF MODE/CSCL C7 QOP1R L 3 IOP1R U2 MICL QMICR D1 MICACL U1 E3 Music Line Input VBAT GND AGND MICACR AGND D3 AGND C3 2k2 AGND 1uF Right ANC MIC R7 2k2 R9 AGND S3 S2 GND ON MO NITOR AGND VBAT R8 22k GND OFF Figure 96 shows an application example of a Feed Forward ANC headset in Full Slider operation mode. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 71 Document Feedback AS3418 Application Information Figure 96: Full Slider Operation Mode – Application Example Left ANC Filter MICS R1 2k2 C1 MIC1 C3 C2 VN EG 1uF VN EG 10µF Left ANC MIC 2.2µF C4 10uF R2 GND C8 R3 Music Line Input 4.7µF B5 R4 150 B1 A3 150 C1 A4 C3 E1 A5 GND VN EG VN EG QOP1L IOP1L QMICL AS3418 TRSDA HPR BPR MSUP B2 E5 E4 MICS C9 Speaker Right 4.7µF E6 C5 AGND VBAT AGND 10k R5 C11 GND C12 MICS 10uF 2k2 C13 4.7µF Right ANC Filter AGND R6 MIC2 C6 C2 A2 B3 AGND A1 MICS AGND Speaker Left D5 AGND LINR GND D2 HPL WL-CSP TRSCL MICR A6 VBAT ILED D6 4.7µF C4 CPP LINL ANC/CSDA D4 C5 C6 2.2µF B4 CPN BPL MODE/CSCL B6 QOP1R 4.7µF IOP1R C7 L 3 MICL QMICR D1 U2 MICACL U1 E3 R 2 GND 1 VBAT GND AGND MICACR AGND D3 AGND E2 2k2 AGND 1uF Right ANC MIC VBAT R7 R8 22k 2k2 AGND R9 22k AGND GND OFF 8.2 ON R10 1M GND MON External Components This chapter provides detailed information about recommended external components. Figure 97: Useful Caption Parameter Temp. Characteristic Min. Rated Voltage Max. Tolerance Min. Nominal Capacitance / Resistance Recommended typ. Component Value CVBAT Input Capacitor Y5R; X5R 4V ±20% 1.6µF 4.7µF CFLY VNEG charge pump flying capacitor Y5R; X5R 4V ±20% 0.97µF 2.2µF CACR, CACL AC coupling capacitor Y5R; X5R 4V ±10% 5.6µF 10µF CVNEG Output Capacitor Y5R; X5R 4V ±20% 3.4µF 10µF Symbol Capacitors Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 72 Document Feedback AS3418 Application Information Symbol Parameter Temp. Characteristic Min. Rated Voltage Max. Tolerance Min. Nominal Capacitance / Resistance Recommended typ. Component Value CMICS Output Capacitor microphone supply Y5R; X5R 4V ±20% 0.94µF 4.7µF CMSUP Output Capacitor microphone charge pump Y5R; X5R ±20% 0.94µF 4.7µF CMICL, CMICR AC coupling capacitor; value depends on ANC filter design Y5R; X5R ±10% - - CFILTER ANC filter related capacitors Y5R; X5R ±10% - - Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 73 Document Feedback 9 AS3418 Package Drawings & Markings Package Drawings & Markings ccc 40 80 2600 300 400±15 400±15 2000 400±15 typ. 270 ±1 0 400±15 400±15 300 80 25 ±5 600 ± 30 375 ± 15 200 ± 20 Figure 98: WL-CSP Package Outline Drawing 450 400±15 400±15 400±15 400±15 450 1600 Notes: Pin 1 = A1 ccc Coplanarity All dimensions are in µm UBM size = 235µm Die size after cutting: 2645x2545 ± 20µm 2500 RoHS (1) (2) (3) (4) Green All dimensions are in µm. Angles in degrees. Dimensioning and tolerancing conform to ASME Y14.5M-1994. This package contains no lead (Pb). This drawing is subject to change without notice. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 74 Document Feedback AS3418 Package Drawings & Markings Figure 99: Package Marking/Code AS3418 XXXXX Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 XXXXX Encoded Tracecode 77 │ 75 Document Feedback 10 AS3418 Revision Information Revision Information ● ● Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Changes from previous version to current revision v4-00 Page Figure 94 update of ball number of pin QOP1L 70 Figure 95 update of ball number of pin QOP1L 71 Figure 96 update of ball number of pin QOP1L 72 Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. Correction of typographical errors is not explicitly mentioned. Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 76 Document Feedback 11 AS3418 Legal Information Legal Information Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. RoHS Compliant & ams Green Statement RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters Please visit our website at www.ams.com ams AG Buy our products or get free samples online at www.ams.com/Products Tobelbader Strasse 30 Technical Support is available at www.ams.com/Technical-Support 8141 Premstaetten Provide feedback about this document at www.ams.com/Document-Feedback Austria, Europe For sales offices, distributors and representatives go to www.ams.com/Contact Tel: +43 (0) 3136 500 0 For further information and requests, e-mail us at ams_sales@ams.com Datasheet • PUBLIC DS000507 • v4-00 • 2020-Jan-23 77 │ 77