AS7000-AAM

AS7000 Biosensor General Description The AS7000 device provides a flexible analog front end for light sensing applications. The photodiode input circuit can be configured in different ways to guarantee best tradeoff between speed and sensitivity for a large number of different sensing applications. Ordering Information and Content Guide appear at end of datasheet. Key Benefits and Features The benefits and features of AS7000, Biosensor are listed below: Figure 1: Added Value of Using AS7000 Benefits Features • Allows smallest application size e.g. narrow HRM measurement band • Single device integrated optical solution • Integrated 32bit Cortex-M0 processor • Good HRM measurement quality • Low noise analog optical front end • Additional information for end user • Analog electrical front end (e.g. for NTC or GSR) • Long operating time • Hardware sequencer to offload processor • Adjustable LED driver with current control • Works reliably with ambient light • Synchronous detector Applications The device is suitable for optical sensor platform. ams Datasheet [v1-12] 2018-Feb-26 Page 1 Document Feedback AS7000 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: Application Schematic AS7000-AA LED Supply VD1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 CLDO 2.2µF VDD V_LDO GND ON=0, off by sotftware UART, SPI, I2C LDO Optical Frontend 14 bit ADC Biasing SIGREF AGND VD2 VD3 AS7000-AA Page 2 Document Feedback GPIO8 GPIO7 GPIO6 GPIO5 Cortex M0 4kByte RAM 32kByte EEPROM Electrical Frontend VDD 2.6V-3.6V CVDD 2.2µF VD4 if not used connect to GND Optical barrier CSIGREF 2.2µF LED Supply ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Pin Assignments Pin Assignments Figure 3: Optical Module Pinout (Top View) – AS7000-AA Optical Module Pinout: This drawing is not to scale GND 10 9 VDD VD1 GPIO0 11 8 GPIO8 GPIO1 12 7 GPIO7 GPIO2 13 6 GPIO6 GPIO3 14 Sensor 5 V_LDO GPIO4 15 4 AGND GPIO5 16 3 SIGREF VD1 17 2 VD4 VD2 VD3 18 1 VD2 Figure 4: Pin Description Pin Number Pin Name Description 1 VD2 Supply voltage for LED D2 – connect unused current sinks to GND 2 VD4 Supply voltage for LED D4 – connect unused current sinks to GND 3 SIGREF Analog reference output. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 from Murata – needs to have >1μF specified for 1.0V voltage bias); do not load externally The typical operating voltage on this pin is 0.6V (sigref_en=1) 4 AGND Analog ground. Connect to low noise GND 5 V_LDO 1.9V output voltage. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 from Murata – needs to have >1μF with 1.0V voltage bias); do not load externally 6 GPIO6 General purpose input/output 7 GPIO7 General purpose input/output 8 GPIO8 General purpose input/output 9 VDD Supply voltage. 10 GND Power supply ground. All voltages are referenced to GND. ams Datasheet [v1-12] 2018-Feb-26 Page 3 Document Feedback AS7000 − Pin Assignments Pin Number Pin Name 11 GPIO0 General purpose input/output 12 GPIO1 General purpose input/output 13 GPIO2 General purpose input/output 14 GPIO3 General purpose input/output 15 GPIO4 General purpose input/output 16 GPIO5 General purpose input/output 17 VD1 Supply voltage for LED D1 – connect unused current sinks to GND 18 VD3 Supply voltage for LED D3 – connect unused current sinks to GND Page 4 Document Feedback Description ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings (1) Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply voltage to ground 3.63V V V_LDO Supply voltage to ground 1.98V max. VDD+0.3V V Input pin voltage to ground, all pins except VD1/VD2/VD3/VD4 -0.3 VDD+0.3V max. 3.8V V VIN-VD1-4 Input pin voltage to ground, pins VD1/VD2/VD3/VD4 -0.3 5.5 V VINLDO Input pin voltage to ground, pin SIGREF -0.3 V_LDO+0.3V max. 1.98V V ISCR Input current (latch-up immunity) -100 100 mA JEDEC JESD78 Electrostatic discharge HBM: JEDEC JESD22-A114F VIN Electrostatic Discharge ESDHBM All pins except VD1/VD2/VD3 and VD4 ±1.0 kV Pins VD1/VD2/VD3 and VD4 ±350 V ams Datasheet [v1-12] 2018-Feb-26 Page 5 Document Feedback AS7000 − Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Temperature Ranges and Storage Conditions TAMB Operating temperature -30 70 °C TSTRG Storage temperature range -40 85 °C TBODY Package body temperature RHNC Relative humidity non-condensing MSL Moisture sensitivity level 5 260 °C 85 % 3 IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” Maximum floor life time of 168h Note(s): 1. All optical customer designs shall be reviewed by ams before production. Page 6 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Electrical Characteristics Electrical Characteristics VDD=2.6 to 3.6V, typ. values are at TAMB=25°C (unless otherwise specified). All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Operating Conditions Symbol Parameter Conditions VDD Supply voltage VLED LED Supply voltage VD1, VD2, VD3, VD4 if a LED is used VLDO LDO voltage, generated by AS7000 Pin V_LDO TAMB Operating free-air temperature Min Typ Max Unit 2.6 3.3 3.6 V 5.0 V 1.9 −30 Supply current 70 °C CPU + EEPROM running at 16MHz; from 1.8V supply; all periphery blocks off 1.4 mA CPU in sleep mode, 16MHz oscillator running; all periphery blocks off 360 μA 2 mA Photodiode amplifier and Optical front end 430 μA Electrical front end 180 μA LED current sink per channel 25mA range 210 μA LED current sink per channel 50mA and 100mA range 340 μA Deep sleep mode (1), (2) 512Hz oscillator running, LDO operating, processor powered 25 μA Power down (3) GPIO8=VDD. 0.8 μA ADC 14bit; only during conversion IDD V VOL GPIO0-8 output low voltage With 3 mA load With 6 mA load 0 0 0.4 0.8 V VOH GPIO0-8 output high voltage With 6 mA load, VDD>3.0V 2.4 VDD V ams Datasheet [v1-12] 2018-Feb-26 Page 7 Document Feedback AS7000 − Electrical Characteristics Symbol Parameter VIH GPIO0-8 input high voltage VIL GPIO0-8 input low voltage RPULLUP RPULLDOWN Conditions Min Typ Max 1.25 Unit V 0.54 V Pullup Resistor to VDD On GPIO0…8 if bit gpioX_ pd=1 where X=0…8 75 kΩ Pulldown Resistor to GND On GPIO0…8 if bit gpioX_ pd=2 where X=0…8 75 kΩ ILEAK1 GPIO0-8 −1 ILEAK2 VD1-4 pins At 5.0 V, TAMB=25ºC E_f16M Tolerance of internal 16MHz oscillator TAMB>0ºC E_f3k2 Tolerance of internal 512Hz oscillator 1 μA 2 μA -2 +2 % -35 +25 % EEPROM nCYCLES tRETENTION Number of write cycles Data retention time 100 cycles At maximum 65ºC 10 years I²C Mode Timings (SCL / SDA Programmable to GPIO Pins – See I²C Mode) fSCLK SCL clock frequency tBUF Bus free time between a STOP and START condition 1.3 kHz Hold time (repeated) START condition(3) 0.6 μs tLOW LOW period of SCL clock 1.3 μs tHIGH HIGH period of SCL clock 0.6 μs tSU:STA Setup time for a repeated START condition 0.6 μs tHD:DAT Data hold time (4) tSU:DAT Data Setup Time (5) 100 tR Rise time of both SDA and SCL signals 20 300 ns tF Fall time of both SDA and SCL signals 20 300 ns tSU:STO Setup time for STOP condition 0.6 tHD:STA CB Capacitive load for each bus Line Page 8 Document Feedback 0 0 CB — total capacitance of one bus line in pF 400 0.9 μs ns μs 400 pF ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Electrical Characteristics Symbol CI/O Parameter Conditions Min I/O capacitance (SDA, SCL) Typ Max Unit 10 pF Note(s): 1. Deep sleep mode. Use ams SDK (software development kit) to enter deep sleep, wakeup with low on GPIO8 pin (if gpio8_wakeup_ en=1) or high on GPIO7 (if gpio7_wakeup_en=1) or 512Hz oscillator sleep_timer. 2. GPIO0-8 configured to draw minimum current (software dependent). 3. Power down mode. Entered by setting enter_powerdown=1; No oscillator running. Wakeup with low on GPIO8 pin (always) or high on GPIO7 (if gpio7_wakeup_en=1). 4. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t R max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Figure 7: I²C Mode Timing Diagram SDA tBUF tLOW tR tHD:STA tF SCLK tHD:STA tSU:STA tHD:DAT STOP tHIGH tSU:STO tSU:DAT REPEATED START START I²C Mode Timing Diagram: This figure shows the different timings required for I²C communication. Note(s): 1. SCL / SDA Programmable to GPIO Pins – See I²C ams Datasheet [v1-12] 2018-Feb-26 Mode . Page 9 Document Feedback AS7000 − Detailed Description Detailed Description Optical Analog Front End Figure 8: Optical Analog Front End – AS7000-AA Configuration pdoffx pd_ampres pd1 pd_ampcap Synchronous Demodulator sd_en sd_byp pd2 * pd_amp_en pdi_0 aa_freq adc_sel=0 pd4 sd_bw 200Hz TIA ADC gain_g gain_byp gain_en Gain Stage -1/0/+1 High Pass Filter sample hp_freq hp_byp hp_en adc_sel=1 pdi_1 reset VD1 VD2 GPIO7 GPIO6 pd3 VD4 VD3 Sequencer Note(s): 1. Dual Green LED Configuration is shown. The number of LEDs inside the module depends on the application – Figure 8 shows 2 LEDs. If a LED is not populated, the current sink is connected directly to the pin (VD3 and VD4 in above figure). Page 10 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description LEDs AS7000-AA Dual Green LED Configuration Two green LEDs are used (pins VD1/VD2). The other two current sinks are available on pins VD3 and VD4. LED Characteristics Figure 9: LED Characteristics at TAMB =25°C Symbol Parameter Conditions Min Typ Max Unit 50 mA 100 mA Green LED (AS7000-AA) Allowed operating LED current range (1) Continuous VFLED_GREEN Forward voltage (2) ILED=20mA VFLED+DRIVER Voltage on VD1/VD2 where operation of the LED and current source is guaranteed ILED= 10mA 3.6 ILED= 50mA 4.5 ILED_GREEN _GREEN λp_GREEN Δλ½_GREEN 0 1/10 duty cycle @ 1 kHz 2.9 3.2 V V Dominant wavelength 527 nm Spectral halfwidth 35 nm Note(s): 1. The maximum allowed LED current (DC and peak) is specified for 25°C. Lower values apply for higher temperatures. 2. Add 280mV and use LED current range ≤100mA for designing the VD1/VD2 LED supply (DC-DC converter). ams Datasheet [v1-12] 2018-Feb-26 Page 11 Document Feedback AS7000 − Detailed Description LED-Driver The four LED-driver outputs can be controlled manually or by the built in sequencer. See Optical Front End Operating Modes Figure 10: LED Drivers VD1 VD2 D1 D2 VD3 D3 max. compliance ledX_en man_mode VD4 D4 R S SET CLR Q Q ledX_supply _low write ‘1’ to register ledX_supply_low currX imaxX (set currX range) man_sw_ledX Sequencer ledX_mode X=1 X=2 X=3 X=4 Note(s): 1. Dual Green LED Configuration. Figure 11: Operating Characteristics of Each LED Current Sink, VDD=3V, TAMB=25°C (unless otherwise noted) Symbol Parameter LED output current range ILED1/2/3/4 Tolerance Conditions Min Typ Max Unit mA mA mA imax1/2/3/4 = 00 imax1/2/3/4 = 01 imax1/2/3/4 = 10 0 0 0 25 50 100 25mA range imax1/2/3/4 = 00 -5 5 50mA range imax1/2/3/4 = 01 -10 10 100mA range (1) imax1/2/3/4 = 10 -10 10 V_Dmin Output voltage compliance Voltage compliance of current sinks D1,D2,D3,D4 V_Dmax Output voltage maximum Pins VD1, VD2, VD3 and VD4 0.28 5 % V 5.5 V Note(s): 1. Not production tested. Only guaranteed by lab characterization. Page 12 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description LED Configuration Registers For ledX_supply_low registers see register AFE_PD_CFG. Figure 12: AFE_LED_CFG 0x00: AFE_LED_CFG Field Name Rst Type Description 18 sigref_en 0 RW Signal reference: Is required for all analog blocks 0...Disable signal reference 1...Enable signal reference 11 led4_en 0 RW 0...Disables LED4 output source. 1...Enables LED4 output source. 10 led3_en 0 RW 0...Disables LED3 output source. 1...Enables LED3 output source. 9 led2_en 0 RW 0...Disables LED2 output source. 1...Enables LED2 output source. 8 led1_en 0 RW 0...Disables LED1 output source. 1...Enables LED1 output source. Defines IMAX of LED4. 7:6 imax4 1 Setting IMAX 0 25mA 1 50mA 2 100mA 3 Do not use RW 5:4 imax3 1 RW Defines IMAX of LED3. same encoding as imax4 3:2 imax2 1 RW Defines IMAX of LED2. same encoding as imax4 1:0 imax1 1 RW Defines IMAX of LED1. same encoding as imax4 The LED_CFG register is used to configure the operating mode of the LED outputs. ams Datasheet [v1-12] 2018-Feb-26 Page 13 Document Feedback AS7000 − Detailed Description AFE_LED_CURR Register (Addr: 0x04) The AFE_LED_CURR defines the LED output current. Figure 13: AFE_LED_CURR Register Addr: 0x04 AFE_LED_CURR Bit Bit Name Default Access 31:24 curr4 0x00 R/W LED4 output current – do not use code=0 (will generate no output current) ILED4 = (curr4 + 1) * imax4 / 256 23:16 curr3 0x00 R/W LED3 output current – do not use code=0 (will generate no output current) ILED3 = (curr3 + 1) * imax3 / 256 15:8 curr2 0x00 R/W LED2 output current – do not use code=0 (will generate no output current) ILED2 = (curr2 + 1) * imax2 / 256 7:0 curr1 0x00 R/W LED1 output current – do not use code=0 (will generate no output current) ILED1 = (curr1 + 1) * imax1 / 256 Page 14 Document Feedback Description ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 14: AFE_MAN_SEQ_CFG 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type Description 26 man_mode 0 RW 0...Enables Sequencer 1...Enables Manual control of optical front end 23 man_sw_itg 0 RW If man_mode=1 0...All integrator capacitors are shorted. Integrator is reset 1...Integrator capacitors are charging up. Integrator is running 22 man_sw_led4 0 RW If man_mode=1 0...LED output D4 disabled. (High impedance) 1...LED output D4 enabled 21 man_sw_led3 0 RW If man_mode=1 0...LED output D3 disabled. (High impedance) 1...LED output D3 enabled 20 man_sw_led2 0 RW If man_mode=1 0...LED output D2 disabled. (High impedance) 1...LED output D2 enabled 19 man_sw_led1 0 RW If man_mode=1 0...LED output D1 disabled. (High impedance) 1...LED output D1 enabled 18:17 diode_ctrl ams Datasheet [v1-12] 2018-Feb-26 0 RW Connection of Photodiodes PD1, PD2, PD3, PD4 to the photodiode amplifier. 0...PD1-PD4 are connected 1...PD1 synchronous to LED1, PD2 sync/to LED2, PD3 sync/to LED3, PD4 sync/to LED4 2...PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to LED2, PD4 sync/to LED2 3...PD1 synchronous to LED1, PD2 sync/to LED1, PD3 sync/to LED4, PD4 sync/to LED4 Note that AFE_PD_CFG.pdX takes precedence - to turn OFF one photo diode, the respective bit (pd1…pd4) has to be de-asserted in the AFE_PD_CFG register. AFE_PD_ CFG.pdX diode_ ctrl Photo Diode1 Photo Diode2 Photo Diode3 Photo Diode4 0 xx OFF OFF OFF OFF 1 00 ON ON ON ON 1 01 LED1 LED2 LED3 LED4 1 10 LED1 LED1 LED2 LED2 1 11 LED1 LED1 LED4 LED4 Page 15 Document Feedback AS7000 − Detailed Description 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type 13 dma_disable 0 RW Description ADC DMA disable 1...ADC result has to be read from adc_data 0...ADC result(s) is/are written to memory LED4 mode Setting 12:10 led4_mode 0 RW Behavior 0 Always OFF 1 Always ON when sequencer is active 2 Controlled by sequencer 3 Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc. 4 Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc. 5 Controlled by sequencer, only ON in every fourth iteration, starting at 3: 3, 7, 11 etc. LED3 mode Setting 9:7 led3_mode Page 16 Document Feedback 0 RW Behavior 0 Always OFF 1 Always ON when sequencer is active 2 Controlled by sequencer 3 Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc. 4 Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc. 5 Controlled by sequencer, only on in every fourth iteration, starting at 2: 2, 6, 10 etc. ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description 0x20: AFE_MAN_SEQ_CFG Field Name Rst Type Description LED2 mode Setting 6:4 led2_mode 0 RW Behavior 0 Always OFF 1 Always ON when sequencer is active 2 Controlled by sequencer 3 Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc. 4 Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc. 5 Controlled by sequencer, only ON in every fourth iteration, starting at 1: 1, 5, 9 etc. LED1 mode Setting 3:1 0 led1_mode seq_en ams Datasheet [v1-12] 2018-Feb-26 0 0 RW RW Behavior 0 Always OFF 1 Always ON when sequencer is active 2 Controlled by sequencer 3 Controlled by sequencer, only ON in even iterations: 0, 2, 4 etc. 4 Controlled by sequencer, only ON in odd iterations: 1, 3, 5 etc. 5 Controlled by sequencer, only ON in every fourth iteration, starting at 0: 0, 4, 8 etc. 0...Disables sequencer 1...Enables sequencer Page 17 Document Feedback AS7000 − Detailed Description Photodiode Selection In order to have flexible arrangement of the use photodiodes, PD1-PD4 can be individually connected to the photodiode amplifier input. The optional offset current allows cancellation of constant light sources like sunlight. In case of an external photodiode or any other sensor with (low) current output, the pins GPIO6 and GPIO7 can be used as input. Additionally the sequencer can control the diodes – see diode_ ctrl described in register AFE_MAN_SEQ_CFG . Figure 15: Photodiode Selection pdoffx pd1 pd2 pd3 to TIA (Trans-Impedance-Amplifier) pd4 GPIO6 GPIO7 Page 18 Document Feedback pdi_0 pdi_1 ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE_PD_CFG Register (Addr: 0x08) The AFE_PD_CFG register is used to configure the input to the photo amplifier. Figure 16: AFE_PD_CFG Register Addr: 0x08 Bit Bit Name AFE_PD_CFG Default Access Description 25 sd_hld 0 R/W SD hold 0 …Output of synchronous demodulator is forced to SIGREF if not set to +1 or -1 1… Output of synchronous demodulator is tristated if not set to +1 or -1 23 led4_ supply_low 0 SC_WS (1) If this bit is cleared, LED4 current sink voltage was below its compliance voltage 22 led3_ supply_low 0 SC_WS (1) If this bit is cleared, LED3 current sink voltage was below its compliance voltage. 21 led2_ supply_low 0 SC_WS (1) If this bit is cleared, LED2 current sink voltage was below its compliance voltage. 20 led1_ supply_low 0 SC_WS (1) If this bit is cleared, LED1 current sink voltage was below its compliance voltage. 15:8 pdoffx 0x00 R/W Input offset current Ioffset = pdoffx*10nA 00000000…Offset source is turned OFF 5 pd4 0 R/W 0 …Photodiode PD4 is disconnected from photo amplifier 1 …Photodiode PD4 is connected to photo amplifier (as defined in diode_ctrl) 4 pd3 0 R/W 0 …Photodiode PD3 is disconnected from photo amplifier 1 …Photodiode PD3 is connected to photo amplifier (as defined in diode_ctrl) 3 pd2 0 R/W 0 …Photodiode PD2 is disconnected from photo amplifier 1 …Photodiode PD2 is connected to photo amplifier (as defined in diode_ctrl) 2 pd1 0 R/W 0 …Photodiode PD1 is disconnected from photo amplifier 1 …Photodiode PD1 is connected to photo amplifier (as defined in diode_ctrl) 1 pdi_1 0 R/W 0 …GPIO7-input is disconnected from photo amplifier 1 …GPIO7-input is connected to photo amplifier 0 pdi_0 0 R/W 0 …GPIO6-input is disconnected from photo amplifier 1 …GPIO6-input is connected to photo amplifier Note(s): 1. SC_WS: Self clear, write sets: These registers are reset by the hardware. Set to ‘1’ before using them. ams Datasheet [v1-12] 2018-Feb-26 Page 19 Document Feedback AS7000 − Detailed Description Photodiode Characteristics Figure 17: Photodiode Arrangement VD1 1mm PD1 PD3 Sensor 1mm PD4 PD2 VD2 Note(s): 1. Orientation as in Figure 115 or Figure 3. Figure 18: AS7000-AA Photodiode Sensitivity (Solid Black) and LED Emission Spectrum (Dotted Green) – Dual Green LED Configuration 100% 90% 70% 60% LED SPD Response (normalized) 80% 50% 40% 30% 20% 10% 0% 300 400 500 600 700 800 900 1000 1100 Wavelength (nm) Note(s): 1. Perpendicular light source. 2. LEDs and Filters are shown for Dual Green LED Configuration. Page 20 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 19: Operating Characteristics of Each Photodiode, VDD=3V, TAMB=25°C (unless otherwise noted) Symbol Parameter Conditions Re Irradiance responsivity λP=525nm, 4 photodiodes used pd1/2/3/4=1, gain_g=4x, gain_en=1, pd_ampres=7MΩ dual green LED configuration filters Id Dark current Ee=0 Ios Extrapolated offset current Min Typ Max Unit mV/ (μW /cm2) 76 0 1 nA −1 1 nA Note(s): 1. For monochromatic light of 555nm, one lux corresponds to 0.146 μW/cm2. That is, one obtains 6.5 lux per μW/cm2 ams Datasheet [v1-12] 2018-Feb-26 Page 21 Document Feedback AS7000 − Detailed Description Photodiode Trans-Impedance Amplifier (TIA) The photodiode amplifier can be configured in three different modes: • Photocurrent to frequency converter • Photocurrent to voltage converter • Photocurrent integrator Figure 20: Trans-Impedance-Amplifier (TIA) pd_ampres pd_ampcap from photodiodes to synchronous demodulator pd_amp_en man_mode man_sw_itg Sequencer The integration time tINT is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mode=1. Page 22 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 21: Settings for the Programming of the TIA pd_ampres pd12341 pd_ampcap pd_ampcomp pd_ampvo Gain 1 1…4 13 1 15 1V/μA 2 1…4 7 1 15 2V/μA 3 1…4 5 1 15 3V/μA 1…2 2 0 15 5V/μA 3…4 3 1…2 2 0 15 7V/μA 3…4 3 1 1 0 15 10V/μA 2…4 2 1…2 1 0 15 15V/μA 3…4 2 15 7V/μA 4 5 6 7 Low Bandwidth Mode 5 1…4 31 3 Integrating Mode (pd_ampres=0) 0 1…4 10 3 15 1V/pQ 0 1…4 20 3 15 1/2V/pQ 0 1…4 30 3 15 1/3V/pQ Note(s): 1. pd1234 … number of active photodiodes (for example, pd1=1, pd2=0, pd3=1, pd4=0 -> pd1234=2) ams Datasheet [v1-12] 2018-Feb-26 Page 23 Document Feedback AS7000 − Detailed Description AFE_PD_AMPCFG Register (Addr: 0x0c) The AFE_PD_AMPCFG register is used to configure the operating mode of the photo-amplifier Figure 22: AFE_PD_AMPCFG Register Addr: 0x0c AFE_PD_AMPCFG Bit Bit Name Default Access Description 31 pd_amp_en 0 R/W 0…Activates power down mode of photo-amplifier 1…Enables photo-amplifier 13:10 pd_amp_vo 15 R/W Opamp offset. Use ams device drivers – these automatically configure this register. 9:8 pd_ ampcomp 3 R/W Opamp compensation. Use ams device drivers – these automatically configure this register. 7:5 pd_ampres 0x0 R/W Feedback resistor 000…No resistor in feedback of amplifier 001…1MΩ 010…2MΩ 011…3MΩ 100…5MΩ 101…7MΩ 110…10MΩ 111…15MΩ 4:0 pd_ampcap 0x0 R/W Feedback capacitor – automatically set by ams device drivers for modes using pd_ampres not 000b. Capacitor = pd_ampcap*0.1pF For registers man_mode and man_sw_itg see AFE_MAN_SEQ_ CFG . Page 24 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Voltage Mode of the Photodiode Amplifier The output voltage of the photodiode amplifier is depending on the feedback component: (EQ1) Feedback resistor: Uout = I photo ⋅ Rfb (EQ2) INT Feedback capacitor: U out = I photo ⋅ --------- t C fb Note(s): The integration time t INT is defined either by the sequencer (man_mode=0) of manually through the bit sw_itg if man_mode=1. For the synchronous demodulator only use the resistive feedback. Figure 23: Difference Between Resistive and Capacitive Feedback ams Datasheet [v1-12] 2018-Feb-26 Page 25 Document Feedback AS7000 − Detailed Description Optical Front End Operating Modes Once the photodiode amplifier is configured the measurement can be done in two different ways. Either the LED-outputs, the photodiode amplifier and the ADC are controlled manually by means of register bits, or they are controlled by a built in sequencer. Manual Operation of The Optical Frontend: The optical front end can be manually controlled via the AFE_ MAN_SEQ_CFG register using man_mode=1. Figure 24: Manual Operation of the Optical Frontend and LED pdoffx pd1 pd_ampres pd_ampcap adc_sel=0 pd2 ADC pd3 pd4 pd_amp_en Start conversion: seq_en=1 End of conversion: seq_en returns to 0 GPIO6 pdi_0 GPIO7 man_sw_itg pdi_1 Note(s): 1. Applies only if man_mode=1. For manual operation of the LEDs and its current sinks see LED-Driver. Page 26 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Sequencer In order to synchronize the LED-currents, the integration time and the ADC-sampling time, a built in sampling Sequencers can be used. The sequencer generates the 16 bit-timings based on a 1μs clock. The results of the analog to digital conversion are automatically stored in a pipeline buffer or in register adc_data. The timings can be programmed with following registers (apply for man_mode=0): Figure 25: Sequencer Control Registers Overview Register Description seq_div Divider of the 1μs input clock seq_count Number of measurements in one sequence seq_start Writing 1 starts the sequencer, 0 stops the sequencer seq_period Time of one measurement cycle seq_led_start Start time of the LED drivers within one cycle seq_led_stop Stop time of the LED drivers within one cycle seq_itg_start Start time of the integrator seq_itg_stop Stop time of the integrator seq_sdp_start Start time of the synchronous demodulator’s positive multiplication seq_sdp_stop Stop time of the synchronous demodulator’s positive multiplication seq_sdm1_start Start time of the synchronous demodulator’s negative multiplication 1 seq_sdm1_stop Stop time of the synchronous demodulator’s negative multiplication 1 seq_sdm2_start Start time of the synchronous demodulator’s negative multiplication 2 seq_sdm2_stop Stop time of the synchronous demodulator’s negative multiplication 2 seq_adc, seq_adc_fract Sampling position of the ADC in single steps / in 1/16th steps seq_adc_inc, seq_adc_inc_fract Increment of the sampling position of the ADC after each measurement in single steps / in 1/16th steps sd_subs Subsampling ratio between sequencer frequency and ADC sampling frequency – use for adjusting the ADC sampling frequency at a lower speed than the sequencer cycle frequency Note(s): 1. The lowest data value of all registers except seq_count, seq_div, seq_adc_inc, seq_adc_inc_fract and seq_adc_fract is 1. ams Datasheet [v1-12] 2018-Feb-26 Page 27 Document Feedback AS7000 − Detailed Description Figure 26: Block Diagram of Sequencer pdoffx pd_ampres pd1 pd_ampcap Synchronous Demodulator sd_en sd_byp pd2 pdi_0 adc_sel=0 aa_freq pd_amp_en reset sd_bw 200Hz TIA ADC hp_freq hp_byp hp_en gain_g gain_byp gain_en High Pass Filter Gain Stage -1 +1 seq_itg_start S SET Q R CL R S Q seq_sdp_stop clk VD1 VD2 +1 -1 seq_sdp_start seq_itg_stop R SET CL R Q Q clk register diode_ctrl seq_sdm1_start S seq_sdm1_stop VD4 VD3 sample pdi_1 adc_sel=1 GPIO7 GPIO6 pd4 adc_data * pd3 R SET CL R Q Q clk led_x_mode x=1...4 seq_sdm2_start S seq_sdm2_stop seq_led_start S seq_led_stop R SET CL R Q R SET CL R Q Q clk Synchronous Demodulator control Q clk seq_adc_frac_inc seq_adc_frac + sd_subs z-1 clk init + z init clk*16 seq_div 1µs Sequencer Page 28 Document Feedback div div -1 Counter 0...seq_period-1 ADC control Run / Stop Logic Run/Reset clk read status seq_adc_inc seq_adc seq_count cycles seq_start ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Sequencer Registers For registers man_mode, man_sw_sdmult, man_sw_sdpol, man_sw_itg, man_sw_led4, man_sw_led3, man_sw_led2, man_sw_led1, diode_ctrl, dma_disable, led4_mode, led3_ mode, led2_mode and led1_mode,seq_en see AFE_MAN_SEQ_CFG . For register sd_subs see AFE_SC_CFG . AFE_SEQ_DIV_CNT Register (Addr: 0x24) The AFE_SEQ_DIV_CNT register sets the input divider for the main clock. Figure 27: AFE_SEQ_DIV_CNT Register Addr: 0x24 Bit Bit Name AFE_SEQ_DIV_CNT Default Access Description Divider value; Sequencer time increment 23:8 seq_div 0x0000 R/W 7:0 seq_count 0x00 R/W tclk = (seq_div + 1) * 1μs Number of measurements in one sequence. IF seq_count = 0x00 the sequencer is running continuously. AFE_SEQ_START Register (Addr: 0x28) In AFE_SEQ_START register the configured sequencer can be started. Figure 28: AFE_SEQ_START Register Addr: 0x28 Bit 0 Bit Name seq_start ams Datasheet [v1-12] 2018-Feb-26 AFE_SEQ_START Default 0 Access Description R/W 1…Starts the sequencer. Sequencer is running according to the configurations in the sequencer registers Writing 0 stops the sequencer(s). In manual mode, writing 1 starts one ADC conversion. Reading returns 1 if the sequencer is running (sequencer mode), respectively if the ADC is converting (manual mode) and it returns to 0 once the ADC has finished its conversion Page 29 Document Feedback AS7000 − Detailed Description AFE_SEQ_PER Register (Addr: 0x2C) The AFE_SEQ_PER register sets one measurement cycle of the sequencer. Figure 29: AFE_SEQ_PER Register Addr: 0x2C AFE_SEQ_PER Bit Bit Name Default Access 15:0 seq_period 0x0000 R/W Description Sequencer period T = seq_period * seq_div * 1μs AFE_SEQ_LED Register (Addr: 0x30) The AFE_SEQ_LED register sets the LED drive timing. Data is stored as 16-bit value Figure 30: AFE_SEQ_LED Register Addr: 0x30 AFE_SEQ_LED Bit Bit Name Default Access Description 31:16 seq_led_start 0x0000 R/W LED start time; the LED starts one cycle later to allow the analog biasing to settle before the current is enabled. 15:0 seq_led_stop 0x0000 R/W LED stop time AFE_SEQ_ITG Register (Addr: 0x34) The AFE_SEQ_ITG register sets the photoamplifier integration time if using capacitive feedback respectively removes the short of the resistive feedback. Data is stored as 16-bit value Figure 31: AFE_SEQ_ITG Register Addr: 0x34 Bit Bit Name AFE_SEQ_ITG Default Access Description 31:16 seq_itg_start 0x0001 R/W Integrator start time (start time=1 and stop time=0 means that it's - by default always ON) Turning OFF the integrator actually means discharge the capacitor for capacitive integration mode, without the synchronous demodulator. 15:0 seq_itg_stop 0x0000 R/W Integrator stop time Page 30 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE_SEQ_SDP Register (Addr: 0x38) The AFE_SEQ_SDP register sets the synchronous demodulator positive multiplication time. Data is stored as 16-bit value Figure 32: AFE_SEQ_SDP Register Addr: 0x38 AFE_SEQ_SDP Bit Bit Name Default Access Description 31:16 seq_sdp_start 0x0000 R/W Positive multiplication start time 15:0 seq_sdp_stop 0x0000 R/W Positive multiplication stop time AFE_SEQ_SDM1 Register (Addr: 0x3C) The AFE_SEQ_SDM1 register sets the synchronous demodulator negative multiplication time 1. Data is stored as 16-bit value Figure 33: AFE_SEQ_SDM1 Register Addr: 0x3C AFE_SEQ_SDM1 Bit Bit Name Default Access Description 31:16 seq_sdm1_start 0x0000 R/W Negative multiplication start time 1 15:0 seq_sdm1_stop 0x0000 R/W Negative multiplication stop time 1 AFE_SEQ_SDM2 Register (Addr: 0x40) The AFE_SEQ_SDM2 register sets the synchronous demodulator negative multiplication time 2. Data is stored as 16-bit value Figure 34: AFE_SEQ_SDM2 Register Addr: 0x40 AFE_SEQ_SDM2 Bit Bit Name Default Access 31:16 seq_sdm2_start 0x0000 R/W Negative multiplication start time 2 15:0 seq_sdm2_stop 0x0000 R/W Negative multiplication stop time 2 ams Datasheet [v1-12] 2018-Feb-26 Description Page 31 Document Feedback AS7000 − Detailed Description AFE_SEQ_ADC Register (Addr: 0x44) The AFE_SEQ_ADC register defines the time when the ADC starts sampling during each measurement cycle. The fraction setting permits a definition of the sampling point as a 1/16 fraction of a sequencer cycle. If seq_div=0 (1us sequencer clock), then one unit is equivalent to 62.5ns. If, e.g. seq_div=4 (5us) then the resolution of the fract register is 62.5ns*5=312.5ns Figure 35: AFE_SEQ_ADC Register Addr: 0x44 AFE_SEQ_ADC Bit Bit Name Default Access Description 31:28 seq_adc_inc_fract 0x0 R/W ADC delay increment : seq_adc_inc_fract/16 fractional 27:24 seq_adc_fract 0x0 R/W ADC start delay: seq_adc_fract/16 fractional 23:16 seq_adc_inc 0x00 R/W ADC increment to the adc sample time after each conversion. 15:0 seq_adc 0x0000 R/W ADC Sampling time; changes of this register have no effect as long as the sequencer is running (seq_ en=1). AFE_SEQ_COUNTER Register (Addr: 0x80) The AFE_SEQ_COUNTER register shows the counter value of the sequence counter and period counter Figure 36: AFE_SEQ_COUNTER Register Addr: 0x80 AFE_SEQ_COUNTER Bit Bit Name Default Access 31:24 subs_counter 0x00 R Current subsampling counter value 23:16 sequence_counter 0x00 R Current sequence counter value 15:0 cycle_counter 0x0000 R Current cycle counter value Page 32 Document Feedback Description ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE_ADC_COUNTER Register (Addr: 0x84) The AFE_ADC_COUNTER register shows the current value of the ADC counter Figure 37: AFE_ADC_COUNTER Register Addr: 0x84 AFE_ADC_COUNTER Bit Bit Name Default Access 7:0 adc_counter 0x00 R Description Current ADC counter value Example Sequencer Configurations Used adc_clock = 0 and adc_highres=0 for the examples to shorten the ADC settling time. As seq_div = 1 and seq_ period=40, one sequence is 80μs. Example 1 Making 4 measurements with LED1 only. Integration time is 20 cycles. LED is turned on 10 cycles before integration starts to avoid current bouncing errors. Figure 38: Sequencer Example 1 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 40 20 40 39 0 2 0 Figure 39: Sequencer Example 1 Waveform ams Datasheet [v1-12] 2018-Feb-26 Page 33 Document Feedback AS7000 − Detailed Description Example 2 Making 4 measurements with LED2 only. Integration time is 20 cycles. LED is turned ON 10 cycles before integration starts to avoid current bouncing errors. Figure 40: Sequencer Example 2 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 40 20 40 39 0 0 2 Figure 41: Sequencer Example 2 Waveform Page 34 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Example 3 Making 4 measurements, switching between LED1 and LED2. Integration time is 20 cycles. LED is turned ON 10 cycles before integration starts to avoid current bouncing errors. Figure 42: Sequencer Example 3 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 40 20 40 39 0 3 4 Figure 43: Sequencer Example 3 Waveform ams Datasheet [v1-12] 2018-Feb-26 Page 35 Document Feedback AS7000 − Detailed Description Example 4 Making 4 measurements, switching LED1 and LED2 simultaneously. Integration time is 20 cycles. LED is turned ON 10 cycles before integration starts to avoid current bouncing errors. Figure 44: Sequencer Example 4 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 40 20 40 39 0 2 2 Figure 45: Sequencer Example 4 Waveform Page 36 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Example 5 Making 4 measurements with LED1 only and subsampling. Integration time is 20 cycles. LED is turned ON 10 cycles before integration starts to avoid current bouncing errors. ADC sampling starts 5 cycles delayed every measurement. Figure 46: Sequencer Example 5 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 40 20 40 25 4 2 0 Figure 47: Sequencer Example 5 Waveform ams Datasheet [v1-12] 2018-Feb-26 Page 37 Document Feedback AS7000 − Detailed Description Example 6 Making 4 measurements with LED1 only and subsampling. Integration time is 20 cycles. LED is turned OFF 10 cycles before integration starts to measure fluorescent response of a sensor. ADC sampling starts 5 cycles delayed every measurement. Figure 48: Sequencer Example 6 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 40 1 4 10 19 20 40 25 4 2 0 Figure 49: Sequencer Example 6 Waveform Page 38 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Example 7 Making 8 measurements with LED1 only. Reduced cycle time to 40μs. Integration time is 5 cycles. LED is turned ON 5 cycles before integration starts to avoid current bouncing errors. Figure 50: Sequencer Example 7 seq_ period seq_ div seq_ count seq_ led_ start seq_ led_ stop seq_ itg_ start seq_ itg_ stop seq_ adc seq_ adc_inc led1_ mode led2_ mode 20 1 8 10 20 15 20 19 0 2 0 Figure 51: Sequencer Example 7 Waveform ams Datasheet [v1-12] 2018-Feb-26 Page 39 Document Feedback AS7000 − Detailed Description Optical Signal Conditioning Synchronous Demodulator High Pass Filter sd_en adc_sel=0 Figure 52: Optical Signal Conditioning Gain Stage sd_byp ADC aa_freq sd_bw 200Hz hp_freq hp_byp hp_en Sequencer gain_g gain_byp gain_en adc_sel=1 * from TIA Synchronous Demodulator An optional synchronous demodulator can be used to detect small optical signals in the presence of large unwanted noise (ambient light). Since the detector synchronizes to the LED frequency, the demodulator can only be used of the measurement sequencer is running. It includes input filer (high pass at 200Hz, adjustable low pass) and an 2nd order adjustable output low pass. The demodulator itself multiplies the signal by +1 / 0 / -1 with a timing which is controlled by the sequencer. Note(s): The optical signal conditioning stage need sigref_ en=1 for operation. High Pass Filter An optional high pass filter can be used to remove unwanted DC-components from the signal and allows further amplification. In order to guarantee fast settling times of the filter, four cutoff frequencies can be chosen. Gain Stage An optional gain stage can be used to amplify the signal after the DC-component has been removed. Page 40 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Optical Signal Conditioning Registers Register bit sigref_en see register AFE_LED_CFG. Figure 53: AFE_SC_CFG 0x70: AFE_SC_CFG Field Name Rst Type Description 26 sd_pol_init 0 RW The low level driver shall ensure that this register is 0 if one of the seq_sdm pulses is first, and is 1 if the seq_sdp is first within a sequence. Anti-aliasing filter cut-off frequency 25:24 20:13 aa_freq sd_subs 0 0 Setting Signal 0 10kHz 1 20kHz 2 40kHz 3 60kHz RW RW Synchronous demodulator subsampling ratio between sequencer frequency and ADC sampling frequency. ADC-Fsample = Sequencyer_Frequency/(sd_subs+1) When setting to 0, then in every sequencer iteration the ADC will run. When setting to 1, then the first sequencer iteration will not trigger the ADC, but the second one will. Setting to N will make N iterations without ADC, followed by one iteration with the ADC measurement executed. It is recommended to use the ADC interrupt in this case and not the sequencer interrupt. Synchronous demodulator low pass filter. 12:11 sd_bw 0 Setting Frequency 0 10Hz 1 20Hz 2 40Hz 3 80Hz RW 10 hp_en 0 RW 0...Power down of the high pass filter 1...Enable high pass filter 9 hp_byp 0 RW 0...HP filter is used 1...HP filter is bypassed ams Datasheet [v1-12] 2018-Feb-26 Page 41 Document Feedback AS7000 − Detailed Description 0x70: AFE_SC_CFG Field Name Rst Type Description High pass filter cutoff frequency 8:7 hp_freq 0 Setting Cutoff frequency 0 0.33Hz 1 1.32Hz 2 5.28Hz 3 10.56Hz RW 6 sd_en 0 RW 0...Power down of the synchronous demodulator 1...Enable synchronous demodulator 5 sd_byp 0 RW 0...Synchronous demodulator is used 1...Synchronous demodulator is bypassed 4 gain_en 0 RW 0...Power down of the Gain stage 1...Enable Gain stage 3 gain_byp 0 RW 0...Gain stage is used 1...Gain stage is bypassed Gain 2:0 gain_g Page 42 Document Feedback 0 Setting Gain 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 don‘t use RW ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Sync Demodulator Example LED1 and LED2 should be modulated with 2kHz Demodulated signal should be sampled with 20Hz for 1 second. Calculation of sequencer values: 1. Modulation Frequency = 2kHz. Period = 500us. 2. Set sequencer period to 250us. -> seq_div=0, seq_period=500 3. Operation of LEDs between 0us and 100us (depends on LED and Amp-settings) -> seq_led_start=1, seq_led_stop=100 4. Operation of photo-amplifier and synchronous demodulator multipl. by +1 between 50us and 100us -> seq_sdp_start=50, seq_sdp_stop=100 5. Operation of photo-amplifier and synchronous demodulator multipl. by -1 between 300us and 350us -> seq_sdm1_start=300, seq_sdm1_stop=350 6. Sampling position at 495us + settling -> seq_adc=490 7. ADC should only sample at 20Hz (50ms). This means sampling at every 50ms/500us = 100th sequencer run. sd_subs=100 8. ADC values should be stored for 1 second. This means 1s/50ms = 20 samples must be stored. ->seq_count=20 ams Datasheet [v1-12] 2018-Feb-26 Page 43 Document Feedback AS7000 − Detailed Description Figure 54: Sync Demodulator Example Detail Page 44 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 55: Sync Demodulator Example ams Datasheet [v1-12] 2018-Feb-26 Page 45 Document Feedback AS7000 − Detailed Description Electrical Analog Front End The electrical analog front end consists of three identical signal paths with independent settings of bias condition, gain and offset. Figure 56: Electrical Analog Front End Internal Circuit SIGREF 1.9V dac_value 1 DAC opamp & DAC enabled automatically 0 sigref_on_dac_buf 160kΩ T-gates: 250Ω 1 2 3 4 5 1 2 3 4 5 0 0 gpio_r_bias 0 gpio_bias_current gpio_i_bias 00b … off 01b … 10µ A 10b … 100µA 11b … 1mA gpio_dac T-gates: 10kΩ 1 2 3 4 5 VDD 1 2 3 4 5 GPIO4 GPIO5 GPIO6 GPIO1 GPIO0 measure_dac gpio_gst_in 0 T-gates: 50kΩ on adc_sel=2 gpio_gst_in measure_dac Vref=1.6V ADC 50kΩ 128kΩ AGND SIGREF don’t use 0 1 2 3 gst_ref gst_gain AGND 0 … 1x 1 … 2x 2 … 4x 3 … 8x 4 … 16x 5 … 32x 6 … 64x 7 … don’t use Note(s): 1. Resistor / T-gates resistance values are given as indication – do not rely on absolute values Input Pins Five general purpose pins can be used either as configurable GPIO for the processor or as analog input pins for the electrical analog front end. The analog inputs can be configured to setup different amplifier topologies. Page 46 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description AFE Registers Figure 57: AFE_LED_CFG 0x00: AFE_LED_CFG Field Name Rst Type 18 sigref_en 0 RW Description Signal reference: Is required for all analog blocks 0...Disable signal reference 1...Enable signal reference Figure 58: AFE_EAF 0x90: AFE_EAF Field Name Rst Type Description 25 sigref_on_dac_ buf 0 RW If asserted, connect SIGREF to DAC buffer. 24 measure_dac 0 RW If this bit is asserted, the DAC output is connected to the gain stage input (independent of gpio_gst_in selection, therefore the DAC output is measureable on the GPIO pin) DAC on GPIO 18:16 gpio_dac ams Datasheet [v1-12] 2018-Feb-26 0 Setting Meaning 0 No DAC biasing 1 DAC on GPIO4 2 DAC on GPIO5 3 DAC on GPIO6 4 DAC on GPIO1 5 DAC on GPIO0 RW Page 47 Document Feedback AS7000 − Detailed Description 0x90: AFE_EAF Field Name Rst Type Description Resistive biasing 15:13 gpio_r_bias 0 Setting Meaning 0 No resistive biasing 1 Resistive biasing on GPIO4 2 Resistive biasing on GPIO5 3 Resistive biasing on GPIO6 4 Resistive biasing on GPIO1 5 Resistive biasing on GPIO0 RW Current biasing 12:10 gpio_i_bias 0 Setting Meaning 0 No current biasing 1 Current biasing on GPIO4 2 Current biasing on GPIO5 3 Current biasing on GPIO6 4 Current biasing on GPIO1 5 Current biasing on GPIO0 RW Current setting of gpio current bias 9:8 gpio_bias_ current Page 48 Document Feedback 0 Setting Current 0 OFF 1 10μA 2 100μA 3 1mA RW ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description 0x90: AFE_EAF Field Name Rst Type Description Gain stage input selection 7:5 gpio_gst_in 0 Setting Meaning 0 Not connected 1 GPIO4 2 GPIO5 3 GPIO6 4 GPIO1 5 GPIO0 RW Gain stage reference voltage 4:3 gst_ref 0 Setting Meaning 0 AGND 1 DAC buffer 2 SIGREF 3 Reserved – do not use RW Gain stage gain 2:0 gst_gain ams Datasheet [v1-12] 2018-Feb-26 0 Setting Meaning 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 Reserved – do not use RW Page 49 Document Feedback AS7000 − Detailed Description The AFE_EAF register is used to configure the electrical frontend Figure 59: AFE_EAF_DAC 0x94: AFE_EAF_DAC Field Name Rst Type 9:0 dac_value 0 RW Description DAC value (10 bit) 0x000 … 0V 0x1FF … 1.9V The AFE_EAF_DAC register is used to configure the dac value Page 50 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Possible Configurations of Every Amplifier Stage Figure 60: Non Inverting Amplifier With Offset and Input Voltage Divider (Temperature Sensor) Figure 61: Non Inverting Amplifier With Current Source and Offset (Temperature Sensor) ams Datasheet [v1-12] 2018-Feb-26 Page 51 Document Feedback AS7000 − Detailed Description Figure 62: Non Inverting Amplifier With Current Source and Reference Path (Temperature Sensor) Figure 63: Non Inverting Amplifier High Impedance, GND Referenced Page 52 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 64: Non Inverting Amplifier With DC-Blocking, Referenced to V_ADCRef/2 Figure 65: Non Inverting Amplifier With DC-Blocking and Fast Settling Time, Referenced to ADCRef /2 ams Datasheet [v1-12] 2018-Feb-26 Page 53 Document Feedback AS7000 − Detailed Description ADC The ADC is a 14bit successive-approximation register (SAR) type. It supports 12 bit with very fast conversion time up to 1Msps and 14bit with moderate conversion time up to 250ksps. The ADC is started by the sequencer and its timing or in manual mode (man_mode=1) by setting seq_start=1 (seq_start stays ‘1’ as long as the conversion runs). The AS7000 can be configured to trigger an interrupt upon end of conversion. Figure 66: ADC Internal Circuit and Multiplexer V_LDO LDO CPU enable VDD POR R gpio7_wakeup_en GPIO8 GPIO7 Q sleep_timer S For best accuracy the ADC needs to recalibrate itself – use ams SDK to initiate the calibration procedure. Page 54 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 67: Operating Characteristics of the ADC, VDD=3V, TAMB=25°C (unless otherwise noted) Symbol Vref TCvref Parameter Conditions Min Typ Max Unit Reference voltage V_ADCRef 1.6 V Reference voltage temperature coefficient ±50 ppm/°C Resolution adc_clock ≤ 1MHz Otherwise 14 12 Bit INL Relative accuracy -8 8 LSB DNL Differential nonlinearity ±2 LSB Offset error ±8 LSB Gain error ±8 LSB SNR Signal-to-noise ratio Fsample = 1kHz, Fsignal=100Hz 80 dB THD Total harmonic distortion Fsample = 1kHz, Fsignal=100Hz -70 dB Conversion rate 12 bit resolution Tconv Vin Input voltage range 1 0 μs Vref V Figure 68: ADC Output Codes (12 Bit Resolution Setting Range) ADC Output Codes: For 14 bit resolution the output data range is 0 to 16383, one LSB represents Vref/16384. ams Datasheet [v1-12] 2018-Feb-26 Page 55 Document Feedback AS7000 − Detailed Description ADC Registers Figure 69: AFE_ADC_DATA 0x88: AFE_ADC_DATA Field Name Rst Type 13:0 adc_data 0 RO Description Current ADC output signals The ADC_DATA register shows the current raw output of the ADC. Figure 70: AFE_ADC_CFG 0xa4: AFE_ADC_CFG Field 21 20 Name adc_selfpd adc_discharge Page 56 Document Feedback Rst 1 1 Type Description RW 1…Power down ADC when not converting; use this to conserve power, but set adc_settling_time to minimum 64μs to permit settling of the ADC reference buffer. 0 … Always enabled ADC RW 0…Suppress ADC capacitor discharging 1…Discharge ADC capacitor before tracking If asserted, the capacitor is discharged before the tracking phase. If zero, the discharge phase is suppressed and the tracking phase is started one cycle earlier. ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description 0xa4: AFE_ADC_CFG Field Name Rst Type Description ADC settling time: Do not use in interleaved mode. It defines the number of ADC clock cycles the sampling window is kept open additionally to its 4 ADC clock cycles. If the gain stage in the optical frontend is used (gain_ byp=0), set this to minimum 8μs. If adc_selfpd=1, set this to minimum 64μs and set adc_discharge=1. 19:17 adc_settling_ time 5 RW Setting Periods μs (@4MHz) μs (@2MHz) μs (@1MHz) 0 0 0 0 0 1 4 1 2 4 2 8 2 4 8 3 16 4 8 16 4 32 8 16 32 5 64 16 32 64 6 128 32 64 128 7 256 64 128 256 If adc_discharge=0 and adc_selfpd=0 and the TIA is connected directly to the ADC using following minimum settling times: ams Datasheet [v1-12] 2018-Feb-26 pd_ampres minimum adc_settling_time 1MΩ 1μs 2MΩ-7MΩ 2μs 10MΩ-15MΩ 3μs Page 57 Document Feedback AS7000 − Detailed Description 0xa4: AFE_ADC_CFG Field Name Rst Type Description ADC clock divider: The ADC clock is freely configurable. Note that values other than 4MHz, 2MHz, 1MHz and 500kHz will make the resulting timing very confusing for the human observer. 15:12 adc_clock 7 RW Setting Periods ns kHz 0 2 125 8000 1 4 250 4000 2 6 375 2666 3 8 500 2000 4 10 625 1600 5 12 750 1333 6 14 875 1142 7 16 1000 1000 8 18 1125 888 9 20 1250 800 10 22 1375 727 11 24 1500 666 12 26 1625 615 13 28 1750 571 14 30 1875 533 15 32 2000 500 11 adc_calibration 0 RW To activate self calibration, this bit must be asserted, and an ADC “conversion” has to be started in manual mode (man_mode=1) by asserting seq_start. It is suggested to let the CPU sleep and wait for the ADC interrupt. Also, a slow ADC clock should be used. 10 adc_interleave 0 RW Interleave mode RW 0...Reset ADC 1...Enable ADC Warning: In reset state the ADC clears its calibration data. Re-calibration is necessary next time it is enabled again. 9 adc_en Page 58 Document Feedback 0 ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description 0xa4: AFE_ADC_CFG Field Name Rst Type Description ADC Input Select 0… Trans impedance amplifier – see Figure 8 1… Optical frontend – see Figure 8 8:6 adc_sel 0 RW 2… Electrical front end – see Figure 56 3… Do not use 4… Do not use 5… Temperature sensor (diode with approx. -2mV/K) 6… Do not use 7… Do not use ADC resolution depending on the Sampling speed 4 adc_highres 1 Setting Selection 0 12 bit 1 14 bit RW Defines number of samples that are taken in multimode (adc_multimode =1) 3:1 adc_multi_n ams Datasheet [v1-12] 2018-Feb-26 0 RW Setting Sample Period 0 2 1 4 2 8 3 16 4 32 5 48 6 64 7 96 Page 59 Document Feedback AS7000 − Detailed Description 0xa4: AFE_ADC_CFG Field 0 Name adc_multimode Page 60 Document Feedback Rst 0 Type Description RW 0...If ADC is started one sample is measured 1...If ADC is started multiple samples are measured with "adc_multi_fs" interval and stored to memory by the DMA controller. The number of samples is defined with adc_ multi_n. In interleaved mode, the sampling time is 4x higher than in non-interleave mode. In non-interleave mode, if adc_multimode=0, only 1 sample is taken. In interleave mode, if adc_multimode=0, then ADC conversions are executed until the end of the sequencer period. If adc_multimode=1, then adc_multi_n is always taken into account. ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Power Management and Operating Modes After the supply (VDD) is asserted the AS7000 automatically starts up. It is up to the application software into which operating mode the AS7000 is changed (e.g. to power down mode). The AS7000 can operate in following modes: Figure 71: AS7000 Operating Modes Mode Internal LDO (V_ LDO) 512Hz Oscillator 16MHz Oscillator CPU Wake Up CPU to Active Mode By Entered By Active    Running - - Sleep mode    Idle Any interrupt (any timer, GPIO) __WFI() command of CPU 512Hz sleep_counter, GPIO7(1) and GPIO8(2) Use ams SDK for entering deep sleep GPIO7(1) and GPIO8(3) enter_ powerdown= 1  Deep sleep mode    = reset; registers keep content  Power down    = reset; registers are reset Note(s): 1. Wakeup by GPIO7=high if gpio7_wakeup_en=1; applies for power down and deep sleep mode. 2. Wakeup by GPIO8=low if gpio8_wakeup_en=1. 3. In power down mode the AS7000 will always wakeup if GPIO8=low independent of previous setting of gpio8_wakeup_en. ams Datasheet [v1-12] 2018-Feb-26 Page 61 Document Feedback AS7000 − Detailed Description For operation of the sequencer the 16MHz oscillator is required, therefore the sequencer only operates in active or wait for interrupt mode. Clock Control Unit (CCU) for Peripheral Blocks All peripheral block have a reset bit and a clock enable bit. The purpose of these register bits is to disable clock to them when they are not used and therefore reduce power consumption. Note(s): Access to the register is not possible if the clock to the peripheral is disabled or reset is asserted. e.g. to access any register of AFE (like optical analog front end) set the register bits afe_resetn=1 and afe_enable=1. Wake-Up From Power Down Mode Figure 72: Wake-Up Logic From Power Down Mode V_LDO LDO CPU enable VDD POR R gpio7_wakeup_en GPIO8 GPIO7 Page 62 Document Feedback Q sleep_timer S ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Power Management And Operating Modes Registers In order to operate the different blocks inside the AS7000, the block has to be enabled (e.g. gpio_enable=1) and the reset de-asserted (e.g. gpio_resetn=1). Figure 73: CCU_DEVICEID 0x00: CCU_DEVICEID Field Name Rst Type Description 31:16 device_id 0 RO Reads back 0x1b58 (decimal 7000) ("AS7000") 3:0 revision 0 RO Reads back the silicon revision Figure 74: CCU_GPIO 0x20: CCU_GPIO Field Name Rst Type Description 0 gpio_resetn 0 RW 0=reset 1=running 1 gpio_enable 0 RW 0=clock OFF 1=clock ON Figure 75: CCU_I2CM 0x2c: CCU_I2CM Field Name Rst Type 0 i2cm_resetn 0 RW 0=reset 1=running 1 i2cm_enable 0 RW 0=clock OFF 1=clock ON ams Datasheet [v1-12] 2018-Feb-26 Description Page 63 Document Feedback AS7000 − Detailed Description Figure 76: CCU_I2CS 0x30: CCU_I2CS Field Name Rst Type Description 0 i2cs_resetn 0 RW 0=reset 1=running 1 i2cs_enable 0 RW 0=clock OFF 1=clock ON Figure 77: CCU_UART 0x34: CCU_UART Field Name Rst Type Description 0 uart_resetn 0 RW 0=reset 1=running 1 uart_enable 0 RW 0=clock OFF 1=clock ON Figure 78: CCU_TMR 0x38: CCU_TMR Field Name Rst Type Description 0 tmr_resetn 0 RW 0=reset 1=running 1 tmr_enable 0 RW 0=clock OFF 1=clock ON Figure 79: CCU_AFE 0x3c: CCU_AFE Field Name Rst Type 0 afe_resetn 0 RW 0=reset 1=running 1 afe_enable 0 RW 0=clock OFF 1=clock ON Page 64 Document Feedback Description ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 80: CCU_WD_CTRL 0x40: CCU_WD_CTRL Field Name Rst Type Description 0 wd_en 0 RW Enable watchdog timer 1 wd_irq_msk 0 RW If 1, pass wd_irq to system NMI input 2 wd_reset_msk 0 RW If 1, then reset system in case of wd_reset Figure 81: CCU_WD_STATUS 0x44: CCU_WD_STATUS Field Name Rst Type Description 0 wd_irq 0 SS_WC Watchdog timer has reached interrupt level 1 wd_reset 0 SS_WC Watchdog has reached zero 2 wd_irq_intr 0 RO NMI is currently asserted by watchdog Figure 82: CCU_WD_VAL 0x48: CCU_WD_VAL Field Name Rst Type 23:0 wd_value 0 R_PUSH Description Reload the watchdog counter with this value. The watchdog counter counts down, and it triggers a system reset as soon as it reaches zero. Figure 83: CCU_WD_IRQVAL 0x4c: CCU_WD_IRQVAL Field Name Rst Type 23:0 wd_irq_value 0 RW ams Datasheet [v1-12] 2018-Feb-26 Description If the watchdog counter reached this value, it will trigger an NMI as an early warning, if wd_irq_msk is set. Page 65 Document Feedback AS7000 − Detailed Description Figure 84: CCU_LP_CFG 0x60: CCU_LP_CFG Field Name Rst Type Description 15:0 sleep_counter 0 RW When going into low power sleep, this the sleep counter start value in slow clock ticks. As soon as it reaches zero, the CPU will wake up (if the register was written with a non zero value) 16 gpio7_wakeup_ en 0 RW If asserted, setting GPIO7 to high can wake up the chip as well (from both sleep and powerdown) 17 gpio8_wakeup_ en 0 RW If asserted, setting GPIO8 to low can wake up the chip from deep sleep (GPIO8=low always wakes up from powerdown) The CCU_LP registers controls the low power modes Figure 85: CCU_LP_CTRL 0x64: CCU_LP_CTRL Field Name Rst Type Description 0 enter_sleep 0 W Writing a 1 here makes the system enter deep sleep mode (wakeup by counter reaching zero) (1) 1 enter_ powerdown 0 W Writing a 1 here makes the system enter power down mode (wakeup by GPIO) Note(s): 1. Only use ams SDK to enter deep sleep mode, do not set bit directly. Page 66 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description MCU The MCU is a 32-bit ARM Cortex-M0-based RISC processor with 32kB of EEPROM memory and 4kB of RAM data memory. Details of the core processor can be found under infocenter.arm.com. The MCU offers the following features: • System: • ARM Cortex M0 processor with single cycle 32 bit multiplication instruction • System tick timer • Hardware protection to disable the read or read/write of the internal EEPROM and SRAM • Unique ID for every device delivered • Memory: • 32kByte EEPROM memory • 4kByte RAM • Peripherals: • 9 general-purpose (GPIO) pins with configurable output structure • UART • I²C Master • I²C Slave • 14 bit ADC • Watchdog timer • 2 general purpose 16 bit timer • Clock: • Internal 16MHz RC oscillator • Internal 512Hz watchdog oscillator and timer • Debug: • Serial wire Debug • Power control: • Reduced power modes Sleep, Stop • Power ON reset ams Datasheet [v1-12] 2018-Feb-26 Page 67 Document Feedback AS7000 − Detailed Description Figure 86: CPU Internal Block Diagram Clock generation Power control Reset RTC EEPROM SRAM ARM Cortex-M0 32-bit RISC AHB - APB Bridge Debug interface SWD MUX GPIO ADC SCL I2C Master 2x 16 bit Timer SDA SCL I2C Slave WDT GPIO0/8 SDA TxD UART Optical/electrical Front end RxD SWD ams delivers a SDK (Software Development Kit) for easy access of the internal digital and analog blocks. The SDK includes detailed documentation of the hardware (like I²C, UART) and includes low level drivers. For accessing of the peripheral registers, a base address needs to added. The base address depends on the block used (see also ams provided SDK – software development kit). Base Address Page 68 Document Feedback Function 0x40000000 CCU: Chip control unit 0x40010000 GPIO 0x40040000 I2CM: I2C Master 0x40050000 I2CS: I2C Slave 0x40060000 UART 0x40070000 Timers 0x40080000 AFE: Analog frontend controller ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Debug – SWD Figure 87: Program/Debug Optical barrier GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 VDD VDD V_LDO GND VD4 GPIO8 GPIO7 GPIO6 GPIO5 M0 CPU + RAM/ EEPROM & Interfaces LDO Ref SIGREF AGND VD2 VD3 AS7000 ON=0,off by software 10kΩ Serial SWCLK SWDIO Wire Debug Press on startup for debug s VD1 ac tiv a te LED Supply 10Ω LED Supply Note(s): 1. Press debug button on power-up (VDD ON). During power up of the AS7000 the device checks if the pin SIGREF is shorted to GND (e.g. by a resistance of 10Ω) – see Figure 87. If this condition is detected and the security bit is not set, a monitor mode is entered. In this monitor mode the AS7000 waits 5s where a debugger can be connected. If the 10s expires without a debugger connected, the AS7000 continues startup. If a debugger is connected, the debugger can control AS7000 as required. Note(s): If the security bit is set inside the EEPROM the debugger is bypassed even if SIGREF is shorted to GND upon startup. ams Datasheet [v1-12] 2018-Feb-26 Page 69 Document Feedback AS7000 − Detailed Description GPIO Pins and Output Switch Matrix A flexible output switch matrix allows dynamic assignment of the internal digital blocks to the GPIO pins: Figure 88: Output Switch Matrix securitybit Wake up from deep sleep mode SWD Serial Wire Debug INT , WA K E, in 0 INT , WA K E, in 1 INT , WA K E, in 2 INT , WA K E, in 3 INT , WA K E, in 4 INT , WA K E, in 5 INT , WA K E, in 6 INT , WA K E, in 7 INT , WA K E, in 8 Out 0 Out 0 Out 2 Out 3 Out 4 Programming mode bit: enable_swd GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Page 70 Document Feedback GPIO Out 5 Out 6 Out 7 Out 8 Selector M_S DA Controlled by gpioX_func; X=0...9 M _S CL S _S DA S _S CL Tx D Rx D I2C Master I2C Slave UART ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 89: Selector Assignments Interface GPIO I²C Master I²C Slave UART Analog gpioX_func; X=0…8 000 011 100 101 111 GPIO0 I/O M_SDA S_SDA TxD Ana0 GPIO1 I/O M_SCL S_SCL RxD Ana1 GPIO2 I/O M_SDA S_SDA TxD Ana2 GPIO3 I/O M_SCL S_SCL RxD Ana3 GPIO4 I/O M_SDA S_SDA TxD Ana4 GPIO5 I/O M_SCL S_SCL RxD Ana5 GPIO6 I/O M_SDA S_SDA TxD Ana6 GPIO7 I/O M_SCL S_SCL RxD Ana7 GPIO8 I/O M_SDA S_SDA TxD Ana8 Each of the GPIO pins is capable of adding a pullup and/or pulldown: Figure 90: GPIO Internal Circuit AS7000 VDD } GPIO0...8 to/from digital control enable if gpioX_func is not analog to analog GND ams Datasheet [v1-12] 2018-Feb-26 pullup/pulldown controlled by gpioX_pd Page 71 Document Feedback AS7000 − Detailed Description I²C Mode The AS7000 includes an I²C master and slave (independent) hardware block. The pins name SDA and SCL in this section can be mapped during runtime to the GPIO pins according to Figure 89. ams SDK operates the I²C slave on GPIO2 (=SDA) and GPIO3 (=SCL) and uses a default I²C address of 0x30 (7-bit format; R/W bit has to be added) respectively 60h (8-bit format for writing) and 61h (8-bit format for reading). It expects external pullup resistors. I²C Serial Control Interface I²C Feature List: Fast mode (400kHz) and standard mode (100kHz) support 7+1-bit addressing mode Write formats: Single-Byte-Write, Page-Write Read formats: Current-Address-Read, Random-Read, Sequential-Read SDA input delay and SCL spike filtering by integrated RC-components I²C Protocol Figure 91: I²C Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 0110 0000b (60h) DR Device address for read R 0110 0001b (61h) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R During acknowledge I²C Symbol Definition: Shows the symbols used in the following mode descriptions. Page 72 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description I²C Write Access Byte Write and Page Write formats are used to write data to the slave. Figure 92: I²C Byte Write S DW A WA A reg_data A P write register WA++ I²C Byte Write: Shows the format of an I²C byte write access. Figure 93: I²C Page Write S DW A WA A reg_data 1 A reg_data 2 write register W A++ A write register W A++ ... reg_data n A P write register W A++ I²C Page Write: Shows the format of an I²C page write access. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. ams Datasheet [v1-12] 2018-Feb-26 Page 73 Document Feedback AS7000 − Detailed Description I²C Read Access Random, Sequential and Current Address Read are used to read data from the slave. Figure 94: I²C Random Read S DW A WA A Sr DR A data read register W A++ N P W A++ I²C Random Read: Shows the format of an I²C random read access. Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 95: I²C Sequential Read S DW A WA A Sr DR A read register W A++ data N P W A++ I²C Sequential Read: Shows the format of an I²C sequential read access. Page 74 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 96: I²C Current Address Read S DW A WA A Sr DR A read register W A++ data N P W A++ I²C Current Address Read: Shows the format of an I²C current address read access. To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. ams Datasheet [v1-12] 2018-Feb-26 Page 75 Document Feedback AS7000 − Detailed Description GPIO, SWD and Security Registers Figure 97: GPIO_DATA 0x00: GPIO_DATA Field Name Rst Type 12:0 gpio_d 0 R_PUSH Description Read/write pin data directly. A read always returns the value at the pin. (1) Note(s): 1. The upper 4 bits are routed to the LED pins. This way the software can output data conveniently and quickly. The AFE module has to be turned ON and the LED have to be enabled for this to work. Figure 98: GPIO_OE 0x04: GPIO_OE Field Name Rst Type 8:0 gpio_oe 0 R_PUSH Description Output enable (1=output 0=input) Figure 99: GPIO_WMASK 0x08: GPIO_WMASK Field 8:0 Name gpio_wmask Page 76 Document Feedback Rst 0x1ff Type Description RW All subsequent writes to GPIO_DATA and GPIO_OE will affect only those bits that are asserted in this mask register. This way a driver can set and clear bits with one access without affecting any other bits. This can be used for bit banging implementations of serial protocols. ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 100: GPIO_INTTYPE 0x10: GPIO_INTTYPE Field Name Rst Type 8:0 gpio_inttype 0 RW Description Interrupt type (0=level 1=edge sensitive). Level sensitive interrupts are asserted as long the interrupt condition is true. Edge level interrupt have to be cleared explicitly. Figure 101: GPIO_INTPOL 0x14: GPIO_INTPOL Field Name Rst Type 8:0 gpio_intpol 0 RW Description Interrupt polarity (0=interrupt when '0' / nedgedge, 1=when '1' / posedge) Figure 102: GPIO_STATUS 0x20: GPIO_STATUS Field Name Rst Type 8:0 gpio_status 0 R_PUSH Description Interrupt condition fulfilled (edge interrupt has to be cleared by writing a '1' here) Figure 103: GPIO_INTMASK 0x24: GPIO_INTMASK Field Name Rst Type 8:0 gpio_intmsk 0 RW ams Datasheet [v1-12] 2018-Feb-26 Description Interrupt mask: a '1' enables the interrupt Page 77 Document Feedback AS7000 − Detailed Description Figure 104: GPIO_INTR 0x28: GPIO_INTR Field Name Rst Type 8:0 gpio_intr 0 RO Description These bits are OR'ed together and generate the interrupt signal Figure 105: GPIO_D_SET 0x30: GPIO_D_SET Field Name Rst Type 12:0 gpio_o_set 0 PUSH Description Setting one or more bit(s) of the GPIO_DATA register directly without affecting the others Figure 106: GPIO_OE_SET 0x34: GPIO_OE_SET Field Name Rst Type Description 12:0 gpio_oe_set 0 PUSH Setting one or more bit(s) of the GPIO_OE registers directly without affecting the others Figure 107: GPIO_D_CLR 0x38: GPIO_D_CLR Field Name Rst Type 12:0 gpio_o_clr 0 PUSH Page 78 Document Feedback Description Clearing one or more bit(s) of the GPIO_DATA register directly without affecting the others ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 108: GPIO_OE_CLR 0x3c: GPIO_OE_CLR Field Name Rst Type 12:0 gpio_oe_clr 0 PUSH Description Clearing one or more bit(s) of the GPIO_OE registers directly without affecting the others Figure 109: CCU_IOFUNC0 0x50: CCU_IOFUNC0 Field Name Rst Type 2:0 gpio0_func 0 RW Please refer to Figure 110 4:3 gpio0_pd 0 RW Please refer to Figure 111 5 gpio0_sr 0 RW Slew rate: 0=fast 1=slow 10:8 gpio1_func 0 RW Please refer to Figure 110 12:11 gpio1_pd 0 RW Please refer to Figure 111 13 gpio1_sr 0 RW Slew rate: 0=fast 1=slow 18:16 gpio2_func 0 RW Please refer to Figure 110 20:19 gpio2_pd 0 RW Please refer to Figure 111 21 gpio2_sr 0 RW Slew rate: 0=fast 1=slow 26:24 gpio3_func 0 RW Please refer to Figure 110 28:27 gpio3_pd 0 RW Please refer to Figure 111 29 gpio3_sr 0 RW Slew rate: 0=fast 1=slow ams Datasheet [v1-12] 2018-Feb-26 Description Page 79 Document Feedback AS7000 − Detailed Description The CCU_IOFUNC0/1/2 gpioX_func register defines the multiplexing mode of each pin. Figure 110: gpioX_func Codings (X=0…8) gpioX_func Description 0 GPIO 3 I²C Master 4 I²C Slave 5 UART 7 Analog The CCU_IOFUNC0/1/2 gpioX_pd fields define the pullup/pulldown configuration Figure 111: gpioX_pd Codings (X=0…8) Page 80 Document Feedback gpioX_pd Description 0 None 1 Weak Pull Up 2 Weak Pull Down 3 Keeper ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Detailed Description Figure 112: CCU_IOFUNC1 0x54: CCU_IOFUNC1 Field Name Rst Type Description 2:0 gpio4_func 0 RW Please refer to Figure 110 4:3 gpio4_pd 0 RW Please refer to Figure 111 5 gpio4_sr 0 RW Slew rate: 0=fast 1=slow 10:8 gpio5_func 0 RW Please refer to Figure 110 12:11 gpio5_pd 0 RW Please refer to Figure 111 13 gpio5_sr 0 RW Slew rate: 0=fast 1=slow 18:16 gpio6_func 0 RW Please refer to Figure 110 20:19 gpio6_pd 0 RW Please refer to Figure 111 21 gpio6_sr 0 RW Slew rate: 0=fast 1=slow 26:24 gpio7_func 0 RW Please refer to Figure 110 28:27 gpio7_pd 0 RW Please refer to Figure 111 29 gpio7_sr 0 RW Slew rate: 0=fast 1=slow Figure 113: CCU_IOFUNC2 0x58: CCU_IOFUNC2 Field Name Rst Type 2:0 gpio8_func 0 RW Please refer to Figure 110 4:3 gpio8_pd 0 RW Please refer to Figure 111 5 gpio8_sr 0 RW Slew rate: 0=fast 1=slow ams Datasheet [v1-12] 2018-Feb-26 Description Page 81 Document Feedback AS7000 − Detailed Description Figure 114: CCU_RETENTION 0xfc: CCU_RETENTION Field Name Rst Type 30 enable_swd 1 RW 31 securitybit 0 Description Enable SWD interface on GPIO7/8 (overrides any gpio7_ func/gpio8_func setting). WS_SC securitybit, to disable access through the SWD interface in the final product. The bit can only be written to 1, not reset. If enabled by the factory or in EEPROM, the bootloader sets this bit before booting the user software. Therefore the image inside the EEPROM is protected against external access. The CCU_RETENTION register is the only register that is not affected by powerdown, Only a power cycle will reset these bits. Page 82 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Application Information The AS7000 has a built-in I²C master and host device. Therefore it allows to connect an accelerometer used for motion artefact compensation in two ways: Application Information 1. Connected through the host and data provided by the host to the AS7000 via the AS7000 I²C slave 2. Connected directly to the AS7000 and the AS7000 I²C master retrieves the data from the accelerometer. Following two figures show the different configurations. Figure 115: Measurement System With Motion Artefact Compensation VD1 to LED Supply GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 VDD 2.6V-3.6V ON=0 GPIO8 GPIO7 GPIO6 GPIO5 M0 CPU + RAM/ EEPROM & Interfaces GND VDD VDD V_LDO GND LDO Ref SIGREF AGND INT SDA SCL VDD VD4 Optical barrier VBAT VD2 VD3 VDD LDO VBAT 3V AS7000 LED Supply (DCDC) on on GPIO2=SDA GPIO3=SCL I2C to AS7000 VD3/VD4: if not used connect to GND Accelerometer Host Processor PMIC VBAT +Charger Note(s): 1. Accelerometer data provided by host. In above configuration the host needs to send the accelerometer data to the AS7000 via the I²C interface. ams Datasheet [v1-12] 2018-Feb-26 Page 83 Document Feedback AS7000 − Application Information Figure 116: Measurement System With Motion Artefact Compensation Using AS7000 Dedicated Accelerometer VD1 to LED Supply SDA Accelerometer SCL VD4 Optical barrier GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 VDD ON=0 GPIO8 GPIO7 GPIO6 GND GPIO5 M0 CPU + RAM/ EEPROM & Interfaces VDD VDD V_LDO GND LDO Ref SIGREF AGND INT 2.6V-3.6V VBAT VD2 VD3 VDD LDO 3V AS7000 VBAT LED Supply (DCDC) on on GPIO2 GPIO3 I2C to AS7000 LCD VD3/VD4: if not used connect to GND Host Processor PMIC VBAT +Charger Bluetooth Note(s): 1. Accelerometer connected directly In above configuration, the AS7000 I²C master is used to poll the data from the accelerometer. The AS7000 has internal protection diodes on all GPIO pins connected to VDD. If VDD is switched off, all GPIO pins are clamped to this VDD supply plus one diode voltage (typically 0.6V). Therefore connect the periphery supply of these pins (example: I²C pins from host in above example connected to GPIO2/3), which are connected to the AS7000 GPIO pins to the same VDD supply as the AS7000. If this is not possible, ensure that these pins are at logic 0 if the VDD supply of AS7000 is switched off. Page 84 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Application Information Due to the integration of the optical diode / optical frontend / analog processing / ADC and microprocessor a heart-rate measurement application can be built with very small PCB area as shown in following figure: Figure 117: Typical Form Factor Including VDD LDO External Components Figure 118: External Components Part Number AS1383 AS1369-BWLT-30 GRM153R60J225ME95 LIS2DH12 ams Datasheet [v1-12] 2018-Feb-26 Parameter or Type DC-DC converter 200mA, 3.5MHz Voltage Rating Size n/a 1.17x0.77x0.6mm Comment DC-DC converter for VLED supply on pin VD1/VD2 VOUT=3.0V 0.97x0.97x0.6mm Ultra Small LDO for VDD supply C=2.2μF, min. 1μF at 1.0V bias 6.3V 0402 (1.0x0.5x0.5mm) On pin VDD, V_LDO and SIGREF Accelerometer n/a 2x2x1mm 200mA LDO Manufacturer ams www.ams.com Murata www.murata.com ST www.st.com Page 85 Document Feedback AS7000 − Package Drawings & Mark ings Package Drawings & Markings Figure 119: Package Drawings XXXXX RoHS Green Note(s): 1. XXXXX - Tracecode backside marking (upside down) Page 86 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Ordering & Contact Information Ordering & Contact Information Figure 120: Ordering Information Ordering Code Type LED Configuration Marking Delivery Form Delivery Quantity AS7000-AA AS7000 Green/Green XXXXX(1) Tape & Reel 5000 pcs/reel AS7000-AAM AS7000 Green/Green XXXXX(1) Tape & Reel 500 pcs/reel Note(s): 1. XXXXX - Tracecode backside marking Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30 8141 Premstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com ams Datasheet [v1-12] 2018-Feb-26 Page 87 Document Feedback AS7000 − RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Page 88 Document Feedback ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. ams Datasheet [v1-12] 2018-Feb-26 Page 89 Document Feedback AS7000 − Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) Page 90 Document Feedback Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs ams Datasheet [v1-12] 2018-Feb-26 AS7000 − Revision Information Revision Information Changes from 1-10 (2017-Feb-28) to current revision 1-12 (2018-Feb-26) Page 1-10 (2017-Feb-28) to 1-11 (2017-Sep-28) Added note under Absolute Maximum Ratings figure 5 1-11 (2017-Sep-28) to 1-12 (2018-Feb-26) Removed AS7000AB related content Note(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. ams Datasheet [v1-12] 2018-Feb-26 Page 91 Document Feedback AS7000 − Content Guide Content Guide Page 92 Document Feedback 1 1 1 2 General Description Key Benefits and Features Applications Block Diagram 3 5 7 Pin Assignments Absolute Maximum Ratings Electrical Characteristics 10 10 11 12 18 20 22 25 26 26 27 29 33 40 40 40 40 41 43 46 46 47 51 54 56 61 62 62 63 67 69 70 72 76 Detailed Description Optical Analog Front End LEDs LED-Driver Photodiode Selection Photodiode Characteristics Photodiode Trans-Impedance Amplifier (TIA) Voltage Mode of the Photodiode Amplifier Optical Front End Operating Modes Manual Operation of The Optical Frontend: Sequencer Sequencer Registers Example Sequencer Configurations Optical Signal Conditioning Synchronous Demodulator High Pass Filter Gain Stage Optical Signal Conditioning Registers Sync Demodulator Example Electrical Analog Front End Input Pins AFE Registers Possible Configurations of Every Amplifier Stage ADC ADC Registers Power Management and Operating Modes Clock Control Unit (CCU) for Peripheral Blocks Wake-Up From Power Down Mode Power Management And Operating Modes Registers MCU Debug – SWD GPIO Pins and Output Switch Matrix I²C Mode GPIO, SWD and Security Registers 83 85 Application Information External Components 86 87 88 89 90 91 Package Drawings & Markings Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information ams Datasheet [v1-12] 2018-Feb-26