AS7024-AB

AS7024 Biosensors General Description The AS7024 device provides a flexible analog front end for light sensing applications. The photodiode input circuit can be configured in different ways to guarantee best tradeoff between speed and sensitivity for a large number of different sensing applications. AS7024 is targeted for wearables (fitness band, smart watch). Ordering Information and Content Guide appear at end of datasheet. Key Benefits and Features The benefits and features of AS7024, Biosensors are listed below: Figure 1: Added Value of Using AS7024 Benefits Features • Allows smallest application size e.g. narrow HRM measurement band • Single device integrated optical solution • Good HRM measurement quality • Low noise analog optical front end • Additional information for end user • Analog electrical front end (e.g. for temperature sensing using a NTC or galvanic skin resistivity (GSR)) • Long operating time • Hardware sequencer to offload processor • Adjustable LED driver with current control • Works reliably with ambient light • Synchronous demodulator ams Datasheet [v1-04] 2018-Sep-11 Page 1 Document Feedback AS7024 − General Description Applications The device is suitable for optical sensor platform. Figure 2: Application Schematic AS7024 LED1 VD1 LED4 IR VD4 Optical barrier ECG_INP ECG_INN ECG_REF SDA SCL INT VBAT 2.7V-5.5V VDD V_LDO GND ENABLE GPIO3 GPIO2 GPIO1 GPIO0 I2C, Optical & Electrical Frontend, ECG Amp. LDO Ref SIGREF AGND Optical barrier VD3 Page 2 Document Feedback LED2 AS7024 VD2 ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Pin Assignments Pin Assignments Figure 3: AS7024 Optical Module Pinout (Top View) Optical Module Pinout: This drawing is not to scale VD1 1 LED 1 LED 4 20 VD4 VD3 2 19 VD2 GND 3 18 SIGREF ECG_INP 4 17 AGND ECG_INN 5 ECG_REF 6 16 V_LDO Sensor 15 GPIO3 ENABLE 7 14 GPIO2 13 GPIO1 INT 8 SCL 9 LED 2 SDA 10 12 GPIO0 11 VDD Figure 4: Pin Description Pin No. Pin Name 1 VD1 Supply voltage for LED D1 2 VD3 Connection to current sink 3 3 GND Power supply ground. All voltages are referenced to GND. 4 ECG_INP ECG amplifier positive input 5 ECG_INN ECG amplifier negative input 6 ECG_REF ECG amplifier reference output 7 ENABLE Enable input for AS7024. Active high. Setting this input to low resets all internal registers and the AS7024 enters power down mode. Setting it high allows operation of the AS7024. If ENABLE is not used (AS7024 always enabled), connect to VDD. 8 INT Open drain interrupt output pin. Active low. 9 SCL I²C serial clock input terminal – the device does not use clock stretching therefore SCL is only an input terminal. ams Datasheet [v1-04] 2018-Sep-11 Description Page 3 Document Feedback AS7024 − Pin Assignments Pin No. Pin Name 10 SDA I²C serial data I/O terminal – open drain. 11 VDD Supply voltage. Connect a 2.2μF capacitor to GND. 12 GPIO0 General purpose input/output 13 GPIO1 General purpose input/output 14 GPIO2 General purpose input/output 15 GPIO3 General purpose input/output 16 V_LDO 1.9V output voltage. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized GRM033R60J225ME47 from Murata – needs to have >1μF with 1.0V voltage bias); do not load externally 17 AGND Analog ground. Connect to low noise GND 18 SIGREF Analog reference output. Connect 2.2μF capacitor to GND (e.g. 0402 sized capacitor GRM153R60J225ME95 or 0201 sized GRM033R60J225ME47 from Murata – needs to have >1μF specified for 1.0V voltage bias); do not load externally The typical operating voltage on this pin is 0.6V (sigref_en=1) 19 VD2 Supply voltage for LED D2 20 VD4 Supply voltage for LED D4 Page 4 Document Feedback Description ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings (1) Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply Voltage to Ground VIN Input Pin Voltage to Ground pins GPIO0/1/2/3 VIN-OTHER Input Pin Voltage to Ground pins SCL/SDA/INT/ENABLE and VD1/VD2/VD3/VD4 VVD1/2/3/4_ INTERNAL 6V V -0.3 VDD+0.3V max. 6V V Diode to VDD -0.3 5.5 V No internal diode to VDD or V_LDO VDD+0.3V V Internal diode between current source (internal node at anode of the LED if the pin has a LED otherwise VD1/2/3/4 pin) and VDD Voltage between internal pin of VD1-VD4 to VDD VIN-LDO Input Pin Voltage to Ground for pin V_LDO -0.3 VDD+0.3V max. 6V V Diode to VDD VIN-LDO_ Input Pin Voltage to Ground pins for ECG_INP/ECG_ INN/ECG_REF/SIGREF -0.3 V_LDO+0.3V max. 6V V Diode to V_LDO VGND-AGND Analog to power ground voltage difference -0.3 +0.3 V ISCR Input Current (latch-up immunity) DIODE -100 100 mA JEDEC JESD78 Connect specified capacitor on SIGREF and V_LDO during latchup test kV JS-001-2014 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ams Datasheet [v1-04] 2018-Sep-11 ±2.0 Page 5 Document Feedback AS7024 − Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Temperature Ranges and Storage Conditions TSTRG Storage Temperature Range TBODY Package Body Temperature RHNC Relative Humidity (non-condensing) MSL Moisture Sensitivity Level -40 85 5 °C 260 °C 85 % 3 IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.” Maximum floor life time of 168h Note(s): 1. All optical customer designs shall be reviewed by ams before production. Page 6 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Electrical Characteristics Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. VDD=2.7 to 5.5V, typ. values are at TAMB=25°C (unless otherwise specified). Figure 6: Operating Conditions Symbol Parameter Conditions Min Typ Max Unit 3.8 5.5 V 70 °C VDD Supply voltage 2.7 TAMB Operating free-air temperature −30 ams Datasheet [v1-04] 2018-Sep-11 Page 7 Document Feedback AS7024 − Electrical Characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Unit ENABLE=VDD, ldo_en=0; osc_en=0; internal LDO operating in low power mode – only I²C communication possible, no blocks shall be enabled (1) 22 μA ENABLE=VDD, ldo_en=1; osc_en=0; internal LDO operating and bandgap running – I²C communication possible, analog blocks can be enabled (1) 32 μA ENABLE=VDD, ldo_en=1, osc_en=1; internal LDO operating and bandgap and oscillator running – I²C communication possible, analog blocks can be enabled(1) 86 μA SIGREF buffer (sigref_en=1) 52 μA transimpedance amplifier (pd_amp_en=1) 110 μA Optical front end operating (one channel) 200 μA Gain stage (ofe1_gain_en=1 or ofe2_gain_en=1) 75 μA ADC sampling at 20Hz with 64μs settling time 4.5 μA ECG amplifier and frontend (need SIGREF enabled) 190 μA ECG leakage compensation (ecg_ low_leakage_en=1), low pass filter, high pass filter and gain stage 151 μA Power down, no I²C communication possible (2) ENABLE=GND 0.5 μA VOL GPIO0-3, INT, SDA output low voltage With 3 mA load With 6 mA load 0 0 0.4 0.8 V VOH GPIO0-3 output high voltage With 3 mA load 2.3 VDD V VIH GPIO0-3, SCL, SDA, ENABLE input high voltage Page 8 Document Feedback 1.25 V ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit 0.54 V VIL GPIO0-3, SCL, SDA, ENABLE input low voltage ILEAK1 GPIO0-3, SCL, SDA, ENABLE, INT −1 1 μA ILEAK2 VD1, VD23 pins −1 1 μA Tolerance of internal 2MHz oscillator 0ºC to 70ºC, VDD1) adc_channel_mask_tia adc_channel_mask_ofe1/ sd1/ofe2/sd2 PreFilter OFE V_LDO Vref=1.6V ADC_DATAH/L ADC AGND TIA adc_channel_mask_temp vtemp GPIOs ECG_ REF 4 FiFo 64x16 bit entries adc_channel_mask_afe Electrical Frontend adc_channel_mask_pregain adc_channel_mask_ecgo from ECG GPIO3 GPIO2 adc_channel_mask_ecgi adc_channel_mask_gpio3 adc_channel_mask_gpio2 For best accuracy, the ADC can be optionally calibrated. Note(s): If GPIO2 or GPIO3 is used as ADC input, there is no anti-aliasing filter in front of the ADC (needs to be added externally). ams Datasheet [v1-04] 2018-Sep-11 Page 75 Document Feedback AS7024 − Detailed Description ADC Threshold At the output of the ADC converter a digital threshold can be enabled. If the output of the ADC exceeds the threshold adc_threshold, it triggers an interrupt. This mechanism can be used to identify if an object is in proximity of the sensor and then to interrupt the host. In cases where no object is detected, the host can be sleeping therefore reducing power consumption of the system. For detailed description of the threshold calculation see the register ADC_THRESHOLD and ADC_THRESHOLD_CFG description. ADC Registers Figure 111: ADC_THRESHOLD Register 0x68: ADC_THRESHOLD Field 7:0 Name adc_threshold Rst 0xff Type Description RW If the ADC returns a value above adc_threshold (not equal), then the adc_threshold interrupt can be triggered. Note that when comparing, only the upper 8 bits are compared, the lower 6 bits are ignored. A value of 0xff can therefore never trigger the interrupt. Figure 112: ADC_THRESHOLD_CFG Register 0x69: ADC_THRESHOLD_CFG Field Name 1 adc_thresh_ differential 0 adc_thresh_ tiaonly Page 76 Document Feedback Rst 0 0 Type Description RW If adc_thresh_tiaonly is asserted and any of seq_adc[23]tia is non-zero, meaning that there are two or three ADC TIA measurements in one sequencer period, then the second is subtracted from the first, and the difference is being compared to the adc_threshold. RW Normally, the adc_threshold works regardless of the adc channel. If this bit is set, then the threshold is only checked if the adc channel is TIA. ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 113: ADC_CFGA Register 0x88: ADC_CFGA Field Name Rst Type Description Defines number of samples that are taken in multimode (adc_multimode =1) (1) 3:1 0 adc_multi_n adc_multimode 0 0 RW RW Setting Number of Samples per ADC Conversion Command 0 2 1 4 2 8 3 16 4 32 5 48 6 64 7 96 0 … If ADC is started one sample is measured 1 … If ADC is started multiple samples are stored in sequence in the FIFO. The number of samples is defined with "adc_multi_n". Note(s): 1. If the ADC is triggered with the sequencer, the very first ADC conversion after seq_en=1 stores the number of samples according to above table. All subsequent samples use one sample less (e.g. 7 instead of 8). The ADC_CFGA,B,C register is used to configure the ADC operation. ams Datasheet [v1-04] 2018-Sep-11 Page 77 Document Feedback AS7024 − Detailed Description Figure 114: ADC_CFGB Register 0x89: ADC_CFGB Field Name Rst Type Description ADC clock divider: The ADC clock is freely configurable. 5:3 adc_clock 0 Setting Periods μs kHz 0 2 1 1000 1 4 2 500 2 6 3 333 3 8 4 250 4 10 5 200 5 12 6 167 6 14 7 143 7 16 8 125 RW 2 adc_calibration 0 RW To activate the optional self calibration, this bit must be asserted, and an ADC “conversion” has to be started in manual mode (man_mode=1) by asserting seq_start. 1 ulp 0 RW Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses and powers off the TIA in all sequences but the one where the TIA is sampled. RW 0 … Reset ADC 1 … Enable ADC Warning: In reset state the ADC clears its calibration data. Re-calibration is necessary next time it is enabled again. 0 adc_en Page 78 Document Feedback 0 ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 115: ADC_CFGC Register 0x8a: ADC_CFGC Field 4 3 Name adc_selfpd adc_discharge Rst 1 1 Type Description RW 1 … Power down the ADC when not converting; use this to conserve power, but set adc_settling_time to minimum 64us to permit settling of the ADC reference buffer. 0 … Always enable ADC RW 0: Suppress ADC capacitor discharging – use with caution 1: Discharge ADC capacitor before tracking If asserted, the capacitor is discharged before the tracking phase. If zero, the discharge phase is suppressed and the tracking phase is started one cycle earlier. ADC settling time: Use with synchronous demodulator. It defines the number of ADC clock cycles the sampling window is kept open additionally. If the gain stage in the optical frontend is used (gain_ byp=0), set this to minimum 8μs. If adc_selfpd=1, set this to minimum 64μs. 2:0 adc_settling_ time ams Datasheet [v1-04] 2018-Sep-11 0 RW Setting Periods μs (@500kHz) μs (@250kHz) 0 0 0 0 1 4 8 16 2 8 16 32 3 16 32 64 4 32 64 128 5 64 128 256 6 128 256 512 7 256 512 1ms Page 79 Document Feedback AS7024 − Detailed Description Figure 116: ADC_CHANNEL_MASK_L Register 0x8b: ADC_CHANNEL_MASK_L Field Name Rst Type Description 7 adc_channel_ mask_pregain 0 RW Pregain channel selection 6 adc_channel_ mask_afe 0 RW Electrical front end 5 adc_channel_ mask_temp 0 RW Temperature measurement 4 adc_channel_ mask_sd2 0 RW Synchronous modulator 2 output just before the gain stage 3 adc_channel_ mask_ofe2 0 RW Synchronous modulator 2 output after the gain stage 2 adc_channel_ mask_sd1 0 RW Synchronous modulator 1 output just before the gain stage 1 adc_channel_ mask_ofe1 0 RW Synchronous modulator 1 output after the gain stage 0 adc_channel_ mask_tia 0 RW Transimpedance amplifier output The adc channel is chosen automatically from the bits within the adc_channel_mask_* set. It starts from right and finishes left (LSB->MSB) and wraps back from the most significant asserted bit to the least significant of the asserted bits. After every ADC conversion it switches to the next enabled channel, (except around the adc2tia/adc3tia cases). See register description FIFOH and FIFOL for encoding of the first channel in the data stream. This applies to both, manual mode and sequencer mode. In sequencer mode, it starts with the smallest channel when the sequencer is being started. In manual mode, the adc_sel is reset with every write to either ADC_CHANNEL_MASK_L or ADC_CHANNEL_MASK_H Page 80 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 117: ADC_CHANNEL_MASK_H Register 0x8c: ADC_CHANNEL_MASK_H Field Name 3 adc_channel_ mask_gpio2 2 adc_channel_ mask_gpio3 1 0 Rst Type Description RW GPIO2 input – set gpio2_a=1 and Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 0 RW GPIO3 input – set gpio3_a=1 and Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 adc_channel_ mask_ecgi 0 RW ECG amplifier input – use for leads off detection adc_channel_ mask_ecgo 0 RW ECG amplifier output – amplified ECG signal 0 Figure 118: ADC_DATA_L Register 0x8e: ADC_DATA_L Field Name Rst Type 7:0 adc_data[7:0] 0 RO Description Current ADC output: low byte. The ADC_DATA register shows the current raw output of the ADC Figure 119: ADC_DATA_H Register 0x8f: ADC_DATA_H Field 5:0 Name adc_data[13:8] ams Datasheet [v1-04] 2018-Sep-11 Rst 0 Type Description RO Current ADC output: high byte warning: there is no latch mechanism implemented to guarantee consistency if the ADC is possibly running when reading this register, then the data can be corrupted - use the FIFO to guarantee data consistency. Page 81 Document Feedback AS7024 − Detailed Description FIFO Registers Figure 120: FIFO_CFG Register 0x78: FIFO_CFG Field 5:0 Name fifo_threshold Rst 19 Type RW Description FIFO threshold. The fifo_threshold interrupt is flagged if there are more than this many entries in the FIFO. 0 … Interrupt with 1 (16bit) entry in FIFO 63 … Interrupt when FIFO is full but one; note that the FIFO is 64 entries deep Figure 121: FIFO_CNTRL Register 0x79: FIFO_CNTRL Field 0 Name fifo_clear Rst 0 Type Description PUSH1 Write a 1 here to clear the FIFO can be useful when switching from one sequencer mode to another to make sure that there are no old FIFO entries left Figure 122: FIFOSTATUS Register 0xa3: FIFOSTATUS Field Name Rst Type 7 fifooverflow 0 RO FIFO overflow indicator 6:0 fifolevel 0 RO FIFO fill level (0 …64) Page 82 Document Feedback Description ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 123: FIFOL Register 0xfe: FIFOL Field Name Rst Type Description 7:0 fifol 0 PUSHPOP Low byte of FIFO FIFOL can be read out with single reads (2 consecutive I²C addresses have to be read to get one FIFO entry) or with block-read (up to 2 x fifo_depth values can be read in a single block-read) Upon reading of FIFOH, it automatically advances the internal read pointer and decreases FIFO level. If reading beyond end of FIFO, data will return 00h. There is no underrun flag, this is not an error condition. Use ams SDK functions to read from the FIFO register to keep the reading in synchronization with the ADC channel selection. If synchronization is no concern use [fifoh[7:0] : fifol[7:2]] as ADC result as the ADC data is multiplied by x4 before it is pushed in to the FIFO. FIFOl[0] is used as an ADC first channel indication. The first channel indication bit toggles upon every new entry unless the first ADC channel is transmitted. Then toggling can be stopped for up to 5 FIFO entries and the very first stopping indicates the first ADC channel. To allow encoding of any number of ADC channels, the first ADC channel encoding is dropped from time to time. Figure 124: FIFOH Register 0xff: FIFOH Field Name Rst Type 7:0 fifoh 0 PUSHPOP Description High byte of FIFO See Interrupts for the actual FIFO interrupt. ams Datasheet [v1-04] 2018-Sep-11 Page 83 Document Feedback AS7024 − Detailed Description Digital Interface Power Management After setting the pin ENABLE=1 the AS7024 registers can be accessed by the I²C interface. Before enabling any additional function (current source, TIA, ADC…) set the bit ldo_en=1 to set the internal LDO to normal mode. For operating the ADC or the sequencer enable the oscillator by setting osc_en=1. GPIO Pins Each of the GPIO pins can be digitally controlled and is capable of adding a pullup and/or pulldown: Figure 125: GPIO Internal Circuit VDD gpio_o enabled if gpio_e=1 gpio_i GPIO0...3 enabled if gpio_a=0 to analog GND pullup/pulldown controlled by gpio_p Interrupts An interrupt output pin INT can be used to interrupt the host. Following interrupt sources are possible irq_adc: End of ADC conversion irq_sequencer: End of sequencer sequence reached. irq_ltf: A light-to-frequency conversion is finished. irq_adc_threshold: ADC threshold triggered – see ADC Threshold. irq_fifothreshold: FIFO almost full (as defined in register fifo_threshold) irq_fifooverflow: FIFO overflow (error condition, data is lost) irq_clipdetect: TIA output and/or SD output exceeded threshold– see details in CLIPSTATUS irq_led_supply_low: led supply low comparator triggered – see details in LEDSTATUS Page 84 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Depending on the setting in register INTENAB each of the above interrupt source can assert INT output pin (active low). I²C The AS7024 includes an I²C slave using an I²C address of 0x30 (7-bit format; R/W bit has to be added) respectively 60h (8-bit format for writing) and 61h (8-bit format for reading). It expects external pullup resistors. I²C Serial Control Interface I²C Feature List Fast mode (400kHz) and standard mode (100kHz) support 7+1-bit addressing mode Write formats: Single-Byte-Write, Page-Write Read formats: Current-Address-Read, Random-Read, Sequential-Read SDA input delay and SCL spike filtering by integrated RC-components I²C Protocol Figure 126: I²C Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 0110 0000b (60h) DR Device address for read R 0110 0001b (61h) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R During acknowledge I²C Symbol Definition: Shows the symbols used in the following mode descriptions. ams Datasheet [v1-04] 2018-Sep-11 Page 85 Document Feedback AS7024 − Detailed Description I²C Write Access Byte Write and Page Write formats are used to write data to the slave. Figure 127: I²C Byte Write S DW A WA A reg_data A P write register WA++ I²C Byte Write: Shows the format of an I²C byte write access. Figure 128: I²C Page Write S DW A WA A reg_data 1 A reg_data 2 write register WA++ A write register WA++ ... reg_data n A P write register WA++ I²C Page Write: Shows the format of an I²C page write access. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. Page 86 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description I²C Read Access Random, Sequential and Current Address Read are used to read data from the slave. Figure 129: I²C Random Read S DW A WA A Sr DR A data read register WA++ N P WA++ I²C Random Read: Shows the format of an I²C random read access. Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 130: I²C Sequential Read S DW A WA A Sr DR A read register WA++ data N P WA++ I²C Sequential Read: Shows the format of an I²C sequential read access. ams Datasheet [v1-04] 2018-Sep-11 Page 87 Document Feedback AS7024 − Detailed Description Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 131: I²C Current Address Read S DW A WA A Sr DR A read register WA++ data N P WA++ I²C Current Address Read: Shows the format of an I²C current address read access. To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. Page 88 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Power, GPIO, ID and Interrupt Registers Figure 132: CONTROL Register 0x00: CONTROL Field 1 0 Name osc_en ldo_en Rst 0 0 Type Description RW Enable the oscillator. The oscillator must be enabled for any analog block (ADC, sequencer, optical frontend, sequencer); not mandatory for current sinks or ECG amplfier RW If the EN input is not asserted, the chip is in reset If asserted, I²C transactions are possible. Upon assertion of ldo_en, the reference and the LDO are enabled The LDO must be enabled for anything but plain I²C register read/write Figure 133: GPIO_A Register 0x08: GPIO_A Field 3 Name gpio3_a Rst 0 Type Description RW 1=Put GPIO3 in analog mode; set this bit when used for an analog function e.g. the electrical frontend. If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence: Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 2 gpio2_a 0 RW 1=Put GPIO2 in analog mode If set execute following I²C commands (otherwise an internal pulldown will be enabled) in this sequence: Write 0x47 to register 0xC6 Write 0x0C to register 0xC2 Write 0x0C to register 0xC3 1 gpio1_a 0 RW 1=Put GPIO1 in analog mode(1) 0 gpio0_a 0 RW 1=Put GPIO0 in analog mode(1) Note(s): 1. No further I²C commands are required (different to GPIO2/3). ams Datasheet [v1-04] 2018-Sep-11 Page 89 Document Feedback AS7024 − Detailed Description Figure 134: GPIO_E Register 0x09: GPIO_E Field Name Rst Type Description 3 gpio3_e 0 RW GPIO3 output enabled if set 2 gpio2_e 0 RW GPIO2 output enabled if set 1 gpio1_e 0 RW GPIO1 output enabled if set 0 gpio0_e 0 RW GPIO0 output enabled if set Figure 135: GPIO_O Register 0x0a: GPIO_O Field Name Rst Type Description 3 gpio3_o 0 RW If gpio3_e=1, gpio3_o defines the output state of GPIO3 2 gpio2_o 0 RW If gpio2_e=1, gpio2_o defines the output state of GPIO2 1 gpio1_o 0 RW If gpio1_e=1, gpio1_o defines the output state of GPIO1 0 gpio0_o 0 RW If gpio0_e=1, gpio0_o defines the output state of GPIO0 Figure 136: GPIO_I Register 0x0b: GPIO_I Field Name Rst Type 3 gpio3_i 0 RO The digital value sensed on GPIO3 2 gpio2_i 0 RO The digital value sensed on GPIO2 1 gpio1_i 0 RO The digital value sensed on GPIO1 0 gpio0_i 0 RO The digital value sensed on GPIO0 Page 90 Document Feedback Description ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 137: GPIO_P Register 0x0c: GPIO_P Field Name Rst Type Description 7 gpio3_pd 0 RW GPIO3 pulldown configuration 0: No pulldown on GPIO3 1: Pulldown to GND on GPIO3 6 gpio3_pu 0 RW GPIO3 pullup configuration 0: No pullup on GPIO3 1: Pullup to VDD on GPIO3 5 gpio2_pd 0 RW GPIO2 pulldown configuration 4 gpio2_pu 0 RW GPIO2 pullup configuration 3 gpio1_pd 0 RW GPIO1 pulldown configuration 2 gpio1_pu 0 RW GPIO1 pullup configuration 1 gpio0_pd 0 RW GPIO0 pulldown configuration 0 gpio0_pu 0 RW GPIO0 pullup configuration Figure 138: GPIO_SR Register 0x0d: GPIO_SR Field Name Rst Type 3 gpio3_sr 0 RW GPIO3 slew rate configuration 0: Default slew rate 1: Increased slew rate 2 gpio2_sr 0 RW GPIO2 slew rate configuration 1 gpio1_sr 0 RW GPIO1 slew rate configuration 0 gpio0_sr 0 RW GPIO0 slew rate configuration ams Datasheet [v1-04] 2018-Sep-11 Description Page 91 Document Feedback AS7024 − Detailed Description Figure 139: SUBID Register 0x91: SUBID Field Name Rst Type Description 7:3 subid NA RO Defines product version. Do not rely on bits defined as ‘X’. 1XXXXb 2:0 Revision NA RO Reserved. Do no use and do not rely that the content stays the same for each device. Internal information: At least one bit is set on subid. Figure 140: ID Register 0x92: ID Field Name Rst Type Description Part Number Identification. 7:2 1:0 id id_reserved Page 92 Document Feedback 0 0 RO RO Value Meaning 110011 AS7024 Reserved. Do no use and do not rely that the content stays the same for each device. ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 141: STATUS Register 0xa0: STATUS Field Name Rst Type Description 7 irq_led_supply_ low 0 R_PUSH1 Check LEDSTATUS 6 irq_clipdetect 0 R_PUSH1 Check CLIPSTATUS 5 irq_fifooverflow 0 R_PUSH1 FIFO overflow (error condition, new data is lost) 4 irq_fifothreshold 0 R_PUSH1 FIFO is almost full (as defined in fifo_threshold, usually 3/4) 3 irq_adc_ threshold 0 R_PUSH1 The ADC value was above the programmed adc_threshold register setting 2 irq_ltf 0 R_PUSH1 LTF measurement is done. check LTFSTATUS (or ignore it) 1 irq_sequencer 0 R_PUSH1 All configured sequencer iterations have finished 0 irq_adc 0 R_PUSH1 ADC has finished The STATUS register shows the current state of the interface. Some bits in here can trigger an interrupt. An asserted bit can be cleared by writing a '1' to it - in case of irq_led_supply_low and irq_clipdetect, this also clears the underlying condition in the CLIPSTATUS and LEDSTATUS registers. The FIFO threshold interrupt cannot be cleared directly, but only by lowering the FIFO level. The FIFO overflow interrupt is sticky and must be cleared explicitly. Figure 142: CLIPSTATUS Register 0xa1: CLIPSTATUS Field Name Rst Type Description 3 pd_clipdetect_l 0 RO If this bit is asserted, photo diode amplifer has been below the lower threshold 2 pd_clipdetect_h 0 RO If this bit is asserted, photo diode amplifer has been above the upper threshold 1 sd_clipdetect_l 0 RO If this bit is asserted, photo diode amplifer has been below the lower threshold 0 sd_clipdetect_h 0 RO If this bit is asserted, photo diode amplifer has been above the upper threshold ams Datasheet [v1-04] 2018-Sep-11 Page 93 Document Feedback AS7024 − Detailed Description An asserted bit can be cleared by writing a '1' to the irq_ clipdetect. Figure 143: LEDSTATUS Register 0xa2: LEDSTATUS Field Name Rst Type Description 3 led4_supply_low 0 RO If this bit is asserted, LED4 voltage has been too low. 2 led3_supply_low 0 RO If this bit is asserted, LED3 voltage has been too low. 1 led2_supply_low 0 RO If this bit is asserted, LED2 voltage has been too low. 0 led1_supply_low 0 RO If this bit is asserted, LED1 voltage has been too low. An asserted bit can be cleared by writing a '1' to the irq_led_ supply_low bit. Figure 144: INTENAB Register 0xa8: INTENAB Field Name Rst Type Description 7 irq_led_supply_ low_enab 0 RW 1 … Enable led supply low interrupt 6 irq_clipdetect_ enab 0 RW 1 … Enable clipdetect interrupt 5 irq_fifooverflow_ enab 0 RW 1 … Enable fifooverflow interrupt 4 irq_ fifothreshold_ enab 0 RW 1 … Enable fifothreshold interrupt 3 irq_adc_ threshold_enab 0 RW 1 … Enable irq_adc_threshold as an interrupt source 2 irq_ltf_enab 0 RW 1 … Enable LTF as an interrupt source 1 irq_sequencer_ enab 0 RW 1 … Enable irq_sequencer as an interrupt source 0 irq_adc_enab 0 RW 1 … Enable irq_adc as an interrupt source Each of the STATUS register bits can cause an interrupt (register INTR) if the respective bit is asserted in the INTENAB register. Page 94 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Detailed Description Figure 145: INTR Register 0xa9: INTR Field Name Rst Type 7 irq_led_supply_ low_intr 0 RO 6 irq_clipdetect_ intr 0 RO 5 irq_fifooverflow_ intr 0 RO 4 irq_ fifothreshold_intr 0 RO 3 irq_adc_ threshold_intr 0 RO 2 irq_ltf_intr 0 RO 1 irq_sequencer_ intr 0 RO 0 irq_adc_intr 0 RO Description The INTR registers shows the bit or bits that are responsible for an asserted interrupt. Effectively, these bits are OR-ed together to drive the interrupt pin INT low (open drain output). ams Datasheet [v1-04] 2018-Sep-11 Page 95 Document Feedback AS7024 − Application Information Application Information The following figure shows the complete integration of the AS7024 in a mobile optical measurement system for HRM, SpO2, GSR (galvanic skin resistivity) and skin temperature using an NTC. The device can be powered directly by a LiIon battery as it has its own power management. Nevertheless the I²C interface can be powered by 1.8V circuitry. Figure 146: Optical HRM Measurement System for Wrist-Based Application ECG Electrodes LED Supply VD1 ECG_INP ECG_INN ECG_REF SDA SCL INT VDD V_LDO GND ENABLE GPIO3 GPIO2 GPIO1 GPIO0 I2C, Optical & Electrical Frontend, ECG Amp. LDO Ref AS7024 ON=0,OFF=1 NTC SIGREF AGND VD2 VD3 connect unused current sinks to GND VBAT GSR Electrodes VBAT VDD VD4 Optical barrier LED Supply VBAT to ENABLE for on/off Accelerometer Page 96 Document Feedback Host Processor PMIC VBAT +Charger ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Package Drawings & Markings Package Drawings & Markings Figure 147: Package Drawing RoHS ams Datasheet [v1-04] 2018-Sep-11 Green Page 97 Document Feedback AS7024 − Ordering & Contact Information Ordering & Contact Information Figure 148: Ordering Information Ordering Code Type Marking Delivery Form Delivery Quantity AS7024-AB AS7024 NA Tape and Reel 5000 pcs/reel Buy our products or get free samples online at: www.ams.com/Products Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/Contact Headquarters ams AG Tobelbader Strasse 30 8141 Premstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Page 98 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. ams Datasheet [v1-04] 2018-Sep-11 Page 99 Document Feedback AS7024 − Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Page 100 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) ams Datasheet [v1-04] 2018-Sep-11 Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Page 101 Document Feedback AS7024 − Revision Information Revision Information Changes from 1-03 (2017-Sep-27) to current revision 1-04 (2018-Sep-11) Page Removed “Confidential” from footer Note(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. Page 102 Document Feedback ams Datasheet [v1-04] 2018-Sep-11 AS7024 − Content Guide Content Guide ams Datasheet [v1-04] 2018-Sep-11 1 1 2 General Description Key Benefits and Features Applications 3 5 7 Pin Assignments Absolute Maximum Ratings Electrical Characteristics 14 14 14 15 16 24 25 27 29 31 33 34 34 35 38 46 46 46 46 47 54 55 61 62 62 62 67 70 71 75 76 76 82 84 84 84 84 85 86 87 89 Detailed Description Optical Analog Front End LEDs LED-Driver LED Configuration Registers Photodiode Selection Photodiode Registers Photodiode Characteristics Photodiode Trans-Impedance Amplifier (TIA) Photodiode TIA Registers Voltage Mode of the Photodiode Amplifier Optical Front End Operating Modes Manual Operation of the Optical Frontend: Sequencer Sequencer Registers Optical Signal Conditioning Synchronous Demodulator High Pass Filter Gain Stage Optical Signal Conditioning Registers Light-to-Frequency Mode Light-to-Frequency Mode Registers Electrical Analog Front End DAC Switching Input Pins EAF (Electrical Analog Frontend) Registers Possible Configurations of Every Amplifier Stage ECG Amplifier ECG Lead OFF Detection ADC and FIFO ADC Threshold ADC Registers FIFO Registers Digital Interface Power Management GPIO Pins Interrupts I²C I²C Write Access I²C Read Access Power, GPIO, ID and Interrupt Registers 96 97 Application Information Package Drawings & Markings Page 103 Document Feedback AS7024 − Content Guide 98 99 100 101 102 Page 104 Document Feedback Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information ams Datasheet [v1-04] 2018-Sep-11