PEEL22CV10ASI-15

PEEL™ 22CV10A -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features High Speed/Low Power - Speeds ranging from 7ns to 25ns - Power as low as 30mA at 25MHz Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development/Programmer Support - Third party software and programmers - Anachip PLACE Development Software Architectural Flexibility - 132 product term X 44 input AND array - Up to 22 inputs and 10 outputs - Up to 12 configurations per macrocell - Synchronous preset, asynchronous clear - Independent output enables - 24-pin DIP/SOIC/TSSOP and 28-pin PLCC Application Versatility - Replaces random logic - Pin and JEDEC compatible with 22V10 - Enhanced Architecture fits more logic than ordinary PLDs General Description The PEEL™22CV10A is a Programmable Electrically Erasable Logic (PEEL™) device providing an attractive alternative to ordinary PLDs. The PEEL™22CV10A offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 1), with speeds ranging from 7ns to 25ns and with power consumption as low as 30mA. EE-reprogrammability provides the conve- nience of instant reprogramming for development and a reusable production inventory, minimizing the impact of programming changes or errors. EE-reprogrammability also improves factory testability, thus ensuring the highest quality possible. The PEEL™22CV10A is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by using the “+” software/programming option (i.e., 22CV10A+ & 22CV10A++). The additional macrocell configurations allow more logic to be put into every design. Programming and development support for the PEEL™22CV10A are provided by popular third-party programmers and development software. Anachip also offers free PLACE development software. Figure 1. Pin Configuration I/CLK I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Figure 2. Block Diagram DIP TSSOP PLCC *Optional extra ground pin for -7/I-7 speed grade. 9 SOIC This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 1.0 Dec 16, 2004 1/10 Anachip Corp. www.anachip.com.tw 2/10 Rev. 1.0 Dec 16, 2004 Function Description The PEEL™22CV10A implements logic functions as sumof-products expressions in a programmable-AND/ fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. Userconfigurable output structures in the form of I/O macrocells further increase logic flexibility. programming selected connections in the AND array. (Note that PEEL™ device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.) Variable Product Term Distribution The PEEL™22CV10A provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14 and 16 to form logical sums (see Figure 3). This distribution allows optimum use of device re-sources. Architecture Overview The PEEL™22CV10A architecture is illustrated in the block diagram of Figure 2. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed OR array. With this structure, the PEEL™22CV10A can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is an I/O macrocell which can be independently programmed to one of 4 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either active-high or active-low polarity. Programmable I/O Macrocell The output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PEEL™22CV10A to the precise requirements of their designs. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a Dtype flip-flop and two signal-select multiplexers. The configuration of each macrocell is determined by the two EEPROM bits controlling these multiplexers (refer to Table 1). These bits determine output polarity and output type (registered or non-registered). Equivalent circuits for the four macro-cell configurations are illustrated in Figure 5. AND/OR Logic Array The programmable AND array of the PEEL™22CV10A (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: 44 Input Lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14 and 16) used to form logical sums 10 output enable terms (one for each I/O) 1 global synchronous present term 1 global asynchronous clear term At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term which is connected to both the true and complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a “don’t care” state exists and that term will always be TRUE. When programming the PEEL™22CV10A, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is then configured to perform the user-defined function by Anachip Corp. www.anachip.com.tw 3/10 Output Type The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flipflop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bidirectional I/O. Opening every connection on the output Rev. 1.0 Dec 16, 2004 enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically false and the I/O will function as a dedicated input. Design Security The PEEL™22CV10A provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step after the device has been programmed. Once the security bit is set, it is impossible to verify (read) or program the PEEL™ until the entire device has first been erased with the bulk-erase function. Input/Feedback Select When configuring an I/O macrocell to implement a registered function (configurations 1 and 2 in Figure 5), the Q output of the flip-flop drives the feedback term. When configuring an I/O macrocell to implement a combinatorial function (configurations 3 and 4 in Figure 5), the feedback signal is taken from the I/O pin. In this case, the pin can be used as a dedicated input or a bi-directional I/O. (Refer also to Table 1.) Signature Word The signature word feature allows a 24-bit code to be programmed into the PEEL™22CV10A if the PEEL™22CV10A+ software option is used. Also, the signature word feature allows a 64-bit code to be programmed into the PEEL™22CV10A if the PEEL™22CV10A++ software option is used. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. Additional Macro Cell Configurations Besides the standard four-configuration macrocell shown in Figure 5, each PEEL™22CV10A provides an additional eight configurations that can be used to increase design flexibility. The configurations are the same as provided by the PEEL™18CV8 and PEEL™22CV10AZ. However, to maintain JEDEC file compatibility with standard 22V10 PLDs the additional configurations can only be utilized by specifying the PEEL™22CV10A+ and PEEL22CV10A++ for logic assembly and programming. To reference these additional configurations please refer to the specifications at the end of this data sheet. Figure 4. Block Diagram of the PEEL™ 22CV10A I/O Macrocell. Anachip Corp. www.anachip.com.tw 4/10 Rev. 1.0 Dec 16, 2004 Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell Table 1. PEEL™ 22CV10A Macrocell Configuration Bits Configuration # 1 2 3 4 A 0 1 0 1 B 0 0 1 1 Input/Feedback Select Register Feedback Output Select Register Active Low Active High Active Low Active High Bi-Directional I/O Combinatorial Anachip Corp. www.anachip.com.tw 5/10 Rev. 1.0 Dec 16, 2004 Additional Macrocell Configurations Besides the standard four-configuration macrocells, each PEEL™22CV10A provides an additional eight configurations (twelve total) that can be used to increase design flexibility (see Figure 6 and Table 2). For logic assembly of all twelve specify PEEL™22CV10A+ and configurations, PEEL22CV10A++. Figure 6. Twelve Configurations of the PEEL™22CV10A+ and PEEL22CV10A++ I/O Macrocell Table 2. PEEL™ 22CV10A+ & A++ Macrocell Configuration Bits # 1 2 3 4 5 6 7 8 9 10 11 12 Configuration ABCD 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Input/Feedback Select Register Bi-Directional I/O Output Select Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Active Low Active High Combinatorial Register Combinatorial Feedback Combinatorial Register Register Feedback Combinatorial Anachip Corp. www.anachip.com.tw 6/10 Rev. 1.0 Dec 16, 2004 Table 6. Absolute Maximum Ratings Symbol VCC VI , VO IO TST TLT This device has been designed and tested for the recommended operating conditions. Improper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Parameter Supply Voltage Voltage Applied to Any Pin Output Current Storage Temperature Lead Temperature 2 Conditions Relative to Ground Relative to Ground Per pin (IOL, IOH) Soldering 10 second 1 Ratings -0.5 to +7.0 -0.5 to VCC+0.6 ±25 -65 to +150 +300 Unit V V mA o o C C Table 7. Operating Ranges Symbol VCC TA TR TF TRVCC Parameter Supply Voltage Ambient Temperature Clock Rise Time Clock Fall Time VCC Rise Time Industrial Conditions Commercial Commercial Industrial See Note 3 See Note 3 See Note 3 Min 4.75 4.5 0 -40 Max 5.25 5.5 +70 +85 20 20 250 Unit V o C ns ns ms Table 8. D.C. Electrical Characteristics over the recommended operating conditions Symbol VOH VOHC VOL VOLC VIH VIL IIL IOZ Parameter Output HIGH Voltage Output HIGH Voltage-CMOS Output LOW Voltage-TTL Output LOW Voltage-CMOS Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current VCC Current (See CR-1 for typical ICC) 13 13 Conditions VCC=Min, IOH=-4.0mA VCC=Min, IOH=-10µA VCC=Min, IOL=-16mA VCC=Min, IOH=-10µA Min 2.4 VCC-0.3 Max 0.5 0.15 Unit V V V V V V µA µA 2.0 -0.3 VCC=Max, VIN=GND δ VIN ₤ VCC I/O=High-Z, GND δ VO δ VCC VIN=0V or 3V f=25MHz All outputs diabled o 4 VCC+0.3 0.8 ±10 ±10 90/100 90/100 135/145 30/40 6 12 -7/I-7 10/I-10 -15/I-15 -25/I-25 ICC 10 mA CIN 7 7 Input Capacitance Output Capacitance TA=25 C, VCC=5.0V @f=1MHz pF pF COUT Anachip Corp. www.anachip.com.tw 7/10 Rev. 1.0 Dec 16, 2004 Table 9. A.C. Electrical Characteristics Over the Operating Range8,11 -1/I-7 -10/I-10 -15/I-15 Symbol Parameter Min Max Min Max Min Max tPD tOE tOD tCO1 tCO2 tCF tSC tHC tCL, tCH tCP fMAX1 fMAX2 fMAX3 tAW tAP tAR tRESET Input to non-registered output Input to output enable 5 5 6 6 5 -25/I-25 Min Max 25 25 25 15 35 9 15 0 13 30 41.6 33.3 38.4 25 Unit ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns 7.5 7.5 7.5 5.5 10 3.5 3 0 8 10 10 10 6 12 4 5 0 4 11 111 909 125 10 8 0 6 18 76.9 62.5 83.3 15 10 10 5 15 15 15 8 17 5 Input to output disable Clock to Output Clock to comb. output delay via internal registered feedback Clock to Feedback Input or Feedback Setup to Clock Input Hold After Clock Clock Low Time, Click High Time Min Clock Period Ext(tSC+tCO1) Internal Feedback (1tSC+tCF) External Feedback (1/tCP) No Feedback (1/tCL+tCH) 5 12 12 12 5 5 3 8.5 142 117 166 7.5 7.5 7.5 5 Asynchronous Reset Pulse Width Input to Asynchronous Reset Asynch. Reset recovery time Power-on Reset Time for registers in Clear State 15 15 5 25 25 5 ns ns ns Switching Waveforms Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs Notes 1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for periods less than 20ns. 2. VI and VO are not specified for program/verify operation. 3. Test points for Clock and VCC in tR, tF are referenced at 10% and 90% levels. 4. I/O pins are 0V and 3V. 5. “Input” refers to an Input pin signal. 6. tOE is measured from input transition to VREF ± 0.1V, tOD is measured from input transition to VOH -0.1V or VOL +0.1V; VREF =VL see test loads in Section 5 of the Data Book. 7. Capacitances are tested on a sample basis. 8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 9. Test one output at a time for a duration of less than 1sec. 10. ICC for a typical application: This parameter is tested with the device programmed as an 8-bit Counter. 11. PEEL™ Device test loads are specified in Section 6 of this Data Book. 12. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design or process modification which may affect operational frequency. 13. Available only for 22CV10A -15/I-15/-25/I-25 grades. Anachip Corp. www.anachip.com.tw 8/10 Rev. 1.0 Dec 16, 2004 Table 6. Ordering Information Part Number PEEL22CV10AP-7 (L) PEEL22CV10API-7 (L) PEEL 22CV10AJ-7 (L) PEEL 22CV10AJI-7 (L) PEEL 22CV10AS-7 (L) PEEL 22CV10ASI-7 (L) PEEL 22CV10AT-7 (L) PEEL 22CV10ATI-7 (L) PEEL 22CV10AP-10 (L) PEEL 22CV10API-10 (L) PEEL 22CV10AJ-10 (L) PEEL 22CV10AJI-10 (L) PEEL 22CV10AS-10 (L) PEEL 22CV10ASI-10 (L) PEEL 22CV10AT-10 (L) PEEL 22CV10ATI-10 (L) PEEL 22CV10AP-15 (L) PEEL 22CV10API-15 (L) PEEL 22CV10AJ-15 (L) PEEL 22CV10AJI-15 (L) PEEL 22CV10AS-15 (L) PEEL 22CV10ASI-15 (L) PEEL 22CV10AT-15 (L) PEEL 22CV10ATI-15 (L) PEEL 22CV10AP-25 (L) PEEL 22CV10API-25 (L) PEEL 22CV10AT-25 (L) PEEL 22CV10ATI-25 (L) PEEL 22CV10AJ-25 (L) PEEL 22CV10AJI-25 (L) PEEL 22CV10AS-25 (L) PEEL 22CV10ASI-25 (L) Speed 7.5ns Temperature C I C I C I C I C I C I C I C I C I C I C I C I C I C I C I C I Package P24 7.5ns J28 7.5ns S24 7.5ns T24 10ns P24 10ns J28 10ns S24 10ns T24 15ns P24 15ns J28 15ns S24 15ns T24 25ns P24 25ns T24 25ns J28 25ns S24 Anachip Corp. www.anachip.com.tw 9/10 Rev. 1.0 Dec 16, 2004 Part Number Device Suffix PEELTM22CV10A PI-25X Lead Free Package P = Plastic 300 mil DIP J = Plastic (J) Leaded Chip Carrier (PLCC) S = SOIC T = TSSOP Speed -7 = 7.5ns tpd -10 = 10ns tpd -15 = 15ns tpd -25 = 25ns tpd Blank : Normal L : Lead Free Package Temperature Range andowe Options (Blank) = Commercial 0 to 70oC I = Industrial -40 to +85oC Anachip Corp. Head Office , 2F, No. 24-2, Industry E. Rd. IV, Science-Based Industrial Park, Hsinchu, 300, Taiwan Tel: +886-3-5678234 Fax: +886-3-5678368 Email: sales_usa@anachip.com Website: http://www.anachip.com ©2004 Anachip Corp. Anachip USA 780 Montague Expressway, #201 San Jose, CA 95131 Tel: (408) 321-9600 Fax: (408) 321-9696 Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life support devices or systems. Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp. Anachip Corp. www.anachip.com.tw 10/10 Rev. 1.0 Dec 16, 2004