APW7046

APW7046 Dual Advanced PWM and Source-Sink Linear Controller Features • 3 Regulated Voltages are provided General Description The APW7046 provides the power controls and protections for three output voltages on AGP/PCI Graphic Card applications. It integrates two PWM controllers , one SOURCE-SINK linear controller, as well as the monitor and protection functions into a single package. One PWM converter (PWM1) supplies the VCORE(1.5V) for the GPU with a standard buck converter. The other standard buck converter (PWM2) regulates the VMEM(2.5V) for the power of DDR memory. The SOURCE-SINK linear controller control two external MOSFETs to be a linear regulator with the capability of sourcing and sinking current. It regulates the VTT (1.25V) power for DDR Termination voltage. Additional built-in over-voltage protection (OVP) will be started when the VCORE or VMEM output is above 115% of each DAC setting (VCORE and VMEM). OVP function will shutdown the all output voltages until re-powering on the IC. For each PWM converter, the over-current function monitors the output current by sensing the voltage drop across the MOSFET‘s rDS(ON) , eliminating the need for a current sensing resistor. − Standard Buck Converter for VCORE (1.15~1.50V) − Standard Buck Converter for VMEM (2.40~3.15V) −Linear Controller with SOURCE-SINK Regulation for VTT(1.25V) • • Simple Single-Loop Control Design − Voltage-Mode PWM Control Excellent Output Voltage Regulation − VCORE Output : ±1% Over Temperature − VMEM Output : ±1.5% Over Temperature − VTT Output : 1/2 VIN ±25mV Over Temperature Min. VIN = 1.7V • Fast Transient Response − Built-in Feedback Compensation − Full 0% to 100% Duty Ratio • • • Over-Voltage and Over-Current Fault Monitor Constant Frequency Operation(200kHz) 24 pins, SOIC Package Pin Description VCC 1 24 BOOT 23 UGATE 2 22 PHASE2 21 PG ND 20 MEM2 19 MEM1 18 MEM0 17 CORE2 16 CORE1 15 CORE0 14 OCSET2 13 VSE N2 UGATE 1 2 Applications • • • M/B DDR Power Regulation AGP/PCI Graphics Power Regulation SSTL-2 Termination PHASE1 3 SS SD 4 5 SO URCE 6 SINK FB VIN 7 8 9 OCSET1 10 VSE N1 11 GND 12 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright  A NPEC Electronics Corp. Rev.A.2 - Mar., 2002 1 www.anpec.com.tw APW7046 Ordering and Marking Information APW 7046 L e a d F re e C o d e H a n d lin g C o d e Tem p. R ange P ackage Code V o lta g e C o d e V o lta g e C o d e A : V C O R E (1 .1 5 ~ 1 .5 0 V ) V M E M (2 .4 0 ~ 2 .7 5 V ) B : V C O R E (1 .1 5 ~ 1 .5 0 V ) V M E M (2 .8 0 ~ 3 .1 5 V ) P ackage Code K : S O P -2 4 Tem p. R ange C : 0 to 7 0 ° C H a n d lin g C o d e TU : Tube TR : Tape & Reel L e a d F re e C o d e L : L e a d F re e D e v ic e B la n k : O rig in a l D e v ic e X X X X X - D a te C o d e A PW 7046K : A PW 7046 XXXXX Block Diagram VCC SS O CSET1 BO OT VCC OC1 28µ A PW M1 4 .5 V OVP1 SD EA1 T h e rm a l P r o t e c t io n S o ft- S ta rt a n d F a u lt L o g ic 200µA IN H IB IT P ow er O n R eset 115% V c o re G a te C o n tro l UG ATE1 PHASE1 VSEN1 V CORE T T L D /A C o n v e rte r CORE0 CORE1 CORE2 VSEN2 O s c illa t o r EA2 V IN H IB IT MEM T T L D /A C o n v e rte r MEM0 MEM1 MEM2 SOURCE IN H IB IT OVP2 115% V MEM OC2 50% R e s is t o r D iv id e r BO OT PW M2 G a te C o n tro l UG ATE2 PGND PHASE2 GND FB S IN K 200uA B u ffe r V IN O CSET2 Absolute Maximum Ratings Symbol VCC VI , VO TA TJ TSTG TS Supply Voltage Input , Output or I/O Voltage Operating Ambient Temperature Junction Temperature Storage Temperature Soldering Temperature 2 Parameter Rating 15 GND -0.3 V to VCC +0.3 Range 0 to 70 Range 0 to 125 Range -65 to +150 300 ,10 seconds Unit V V °C °C °C °C www.anpec.com.tw Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 APW7046 Thermal Characteristics Symbol R JA Parameter Thermal Resistance in Free Air SOIC SOIC (with 3in2 of Copper) Value 75 65 Unit °C/W Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=VBOOT=12V and TA=0~70°C. Typical values refer to TA=25°C. Sym bol Supply C urrent IC C I C C SD N om inal S upply C urrent Shutdow n Supply C urrent R ising VC C Threshold Falling VC C Threshold SD Input High Voltage SD Input Low Voltage O scillator F O SC Free Running Frequency 185 200 1.9 215 kH z V ∆ V O SC R am p Am plitude PW M Controller R eference Voltage PW M 1 R eference Voltage V CORE Accuracy C O R E0-C O R E2 Input H igh Voltage C O R E0-C O R E2 Input Low Voltage PW M 2 R eference Voltage V M EM Accuracy M EM 0-M EM 2 Input H igh Voltage M EM 0-M EM 2 Input Low Voltage SO U RC E-SIN K Linear Controller V FB FB R egulation Voltage V F B a ccuracy M ax. SO U RC E Pin Drive C urrent M ax. S IN K Pin D rive Current Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 3 Param eter Test Conditions SD =0V, UG ATE1,UG ATE 2 , SO U RC E, and SIN K O pen SD =5V Vocset=3V Vocset=3V M in. A PW 7046 Typ. M ax. U nit 8 2.7 4.2 3.6 2.0 0.8 4.6 mA Power-on Reset V V V V -1 2.0 +1 % V 0.8 -1.5 2.0 0.8 R egulator Sourcing or Sinking C urrent -25 ¡ 0 .8 Ó ¡ 0 .8 Ó +1.5 V % V V 0.5VIN +25 V mV mA mA www.anpec.com.tw APW7046 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=VBOOT=12V and TA=0~70°C. Typical values refer to TA=25°C. Symbol Parameter Test Conditions VIN=2.5V VCC=VBOOT=12V, VUGATE1,2=6V VCC=12V,VUGATE1,2=6V APW7046 Typ. Max. 2 Unit uA Min. IVIN VIN Input Bias Current PWM Controllers Gate Drivers IUGATE RGATE Protection VSEN1,2 OVP trip point (VSEN1/VCORE and VSEN2/VMEM ) VSEN1,2 O.V. Hysteresis IOCSET ISS Ocset Current Source Soft start Current UGATE1,2 Source UGATE Sink 0.74 3 4 A Ω VSEN Rising 115 2 120 % Vocset=3V 170 200 28 230 uA Functional Pin Description VCC (Pin 1) Provide a +12V bias supply for the IC to this pin. This pin also provides the gate bias charge for the MOSFETs of the SOURCE-SINK regulator. The voltage at this pin is monitored for Power-On Reset (POR) purposes. UGATE1 (Pin 2) Connect this pin to the MOSFET gate of the PWM1 converter. This pin provides the gate drive for the MOSFET. PHASE1 (Pin 3) Connect this pin to the PWM1 converter’s MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-current protection. SS (Pin 4) Connect a capacitor from this pin to ground.This capacitor, along with an internal 28uA current source, Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 4 sets the soft-start interval of all power controls and preventing the outputs from overshoot as well as limiting the input current . SD (Pin 5) The pin shuts down all power outputs. A TTL compatible , logic level high signal applied at this pin immediately discharges the soft-start capacitor,disabling all power outputs. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. SOURCE (Pin 6) Connect this pin to the upper MOSFET gate drive of the SOURCE-SINK regulator. This pin drives the upper external MOSFET as a sourcing regulator. SINK (Pin 7) Connect this pin to the lower MOSFET gate drive of www.anpec.com.tw APW7046 Functional Pin Description (Cont.) the SOURCE-SINK regulator. This pin drives the lower external MOSFET as a sinking regulator. FB (Pin 8) Connect this pin to output of the SOURCE-SINK regulator. This pin provides the voltage feedback path for the sourcing and sinking regulators. This pin is internally connected to the negative input of the SOURCE controller, and also connected to the positive input of the SINK controller. VIN (Pin 9) Connect this pin to VMEM or a fixed voltage source. Two voltages, about 0.5VIN, are generated by an internal resistor divider as the reference voltages of the sourcing and sinking regulators. The sinking regulation voltage is higher than the sourcing one to prevent a direct current path through the upper and lower MOSFETs. OCSET1 (Pin 10) Connect a resistor (ROCSET ) from this pin to the drain of the PWM1 converter’s MOSFET. ROCSET, an internal 200uA current source (IOCSET ), and the MOSFET’s onresistance(rDS(ON)) set the converter’s over-current (OC) trip point according to the following equation: I OCSET x RO CS ET r DS( ON) GND (Pin 12) Signal ground for the IC. All voltage levels are measured with respect to this pin. VSEN2 (Pin 13) This pin is connected to the PWM2 converter’s output voltage to provide the voltage feedback path. The overvoltage protection(OVP) comparator uses this pin to monitor the output voltage for over- voltage protection. OCSET2 (Pin 14) Connect a resistor (ROCSET ) from this pin to the drain of the PWM2 converter’s MOSFET. The function of this pin is similar to OCSET1(pin 10) for OC detection and POR purposes. CORE0-2 (Pin 15-17) CORE0-2 are TTL-compatible logic level input pins to the 3-bit DAC. The states of the three pins set the internal reference voltage (VCORE) for the PWM1 converter and also set the OVP threshold voltage for PWM1 converter. MEM0-2 (Pin 18-20) MEM0-2 are TTL-compatible logic level input pins to the other 3-bit DAC. The states of the three pins set the internal reference voltage (VMEM) for the PWM2 converter and also set the OVP threshold voltage for PWM2 converter. PGND (Pin 21) Connect this pin to the anode of the flywheel diodes of the two PWM converters. PHASE2 (Pin 22) Connect this pin to the PWM2 converter’s MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-current protection. IPEAK = An over-current trip cycles the soft-start function. The voltage at this pin is monitored for Power-On Reset (POR) purposes. VSEN1 (Pin 11) This pin is connected to the PWM1 converter’s output voltage to provide the voltage feedback path. The overvoltage protection(OVP) comparator uses this pin to monitor the output voltage for over- voltage protection Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 5 www.anpec.com.tw APW7046 Functional Pin Description UGATE2 (Pin 23) Connect this pin to the MOSFET gate of the PWM2 converter. This pin provides the gate drive for the MOSFET. BOOT (Pin 24) Connect this pin to +12V. This pin provides bias voltage to the MOSFET drivers. Table 1 DAC Table APW7046 - A APW7046 - B CORE2 0 0 0 0 1 1 1 1 MEM2 0 0 0 0 1 1 1 1 Pin Name CORE1 CORE0 0 0 1 1 0 0 1 1 Pin Name MEM1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MEM0 0 1 0 1 0 1 0 1 V CORE Voltage 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 V MEM Voltage 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 CORE2 0 0 0 0 1 1 1 1 MEM2 0 0 0 0 1 1 1 1 Pin Name CORE1 CORE0 0 0 1 1 0 0 1 1 Pin Name MEM1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MEM0 0 1 0 1 0 1 0 1 V CORE Voltage 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 V MEM Voltage 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 6 www.anpec.com.tw APW7046 Simplified Power System Diagram +5V Q2 S tandard B uck C o n v erter (PW M2) VM EM APW 7046 Q1 S tandard B uck C o n v erter (PW M1) +3.3V V CORE Q3 VTT SOURCE-SINK Linear C onverter Q4 Typical Application Circuit C2 1uF L1 1uH R1 10 C3 10uF C2 200pF R2 1.5K R3 5.1 10 + 12V C1 1uF 1 24 C11 200pF R8 1.5K 14 23 L3 1uH + 3.3V C5 10uF C4 330uF C12 10uF C13 330uF C14 10uF VC C OC SET 1 B OOT OC SET 2 U GA T E2 PH A SE2 + 5V L2 4.7uH Q1 A PM9410 2 3 R9 5.1 U GA T E1 PH A SE1 Q2 A PM9410 D2 MBRD835L L4 7.8uH V CORE C7 330uF C6 330uF R4 3 R5 1K R6 10K VMEM 21 D1 MBRD835L PGN D 11 VSEN 1 VSEN 2 13 R10 0 R11 NC C15 330uF 20 M EM 2 9 VIN M EM 1 M EM 0 19 18 VMEM C8 330uF Q3 A PM3055 R7 NC MEM2 MEM1 MEM0 CORE2 CORE1 CORE0 C9 0.1uF 6 C OR E2 SOU R C E C OR E1 C OR E0 7 SIN K EN 17 16 15 V TT C10 330uF Q4 A PM3055 5 SS GN D 8 FB 4 C16 0.68uF C4, C6, C7, C8 , C10, C13, C15 : 330uF/6.3V S M D Low E S R tantalum Capac itor 12 Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 7 www.anpec.com.tw APW7046 Typical Performance 1. SOURCE-SINK Linear Regulator Transient Response - The output capacitor is 330uF (Low ESR tantalum capacitor) - Define the output cerrent (IVTT) sourcing from the regulator to be positive. - The interval of current transitions in figures 1 and 2 are all smaller than 1uS. - In figure 1, the IVTT transition is from -0.2A to 4A. - In figure 2, the IVTT transition is from 0.2A to -4A. Figure 1 Figure 2 Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 8 www.anpec.com.tw APW7046 Packaging Information SO – 300mil ( Reference JEDEC Registration MS-013) D N H E GAUGE PLANE 1 2 3 A e B A1 L 1 Millimeters Dim A A1 B D E e H L N φ1 Min. 2.35 0.10 0.33 7.40 10 0.40 0° Max. 2.65 0.30 0.51 7.60 10.65 1.27 8° Variations- D Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 10.10 11.35 12.60 15.20 17.70 8.80 Max. 10.50 11.76 13 15.60 18.11 9.20 Dim A A1 B D E e H L N φ1 Inches Min. Variations- D Max. Variation Min. Max. SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 0.398 0.447 0.496 0.599 0.697 0.347 0.413 0.463 0.512 0.614 0.713 0.362 0.093 0.1043 0.004 0.0120 0.013 0.020 See variations 0.2914 0.2992 0.050BSC 0.394 0.016 0° 0.419 0.050 8° See variations 1.27BSC See variations See variations Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 9 www.anpec.com.tw APW7046 Physical Specifications Terminal Material Lead Solderability P ackaging Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. 1000 devices per reel for SO-16 , 2500 devices per reel for SSOP-16. Reflow Condition TP (IR/Convection or VPR Reflow) tp C ritical Zone T L to T P R am p-up T e m p e ra tu re TL T sm ax tL T sm in R am p-down ts Preheat 25 t 25 °C to Peak Classificatin Reflow Profiles Profile Feature T im e Sn-Pb Eutectic Assembly Large Body Small Body Pb-Free Assembly Large Body Small Body 3°C/second max. 150°C 200°C 60-180 seconds 3°C/second max 217°C 60-150 seconds 245 +0/-5°C 250 +0/-5°C 10-30 seconds 20-40 seconds 6°C/second max. 8 minutes max. www.anpec.com.tw Average ramp-up rate 3°C/second max. (TL to TP) Preheat - Temperature Min (Tsmin) 100°C - Temperature Mix (Tsmax) 150°C - Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL - Temperature(TL) 183°C - Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5°C Time within 5°C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6°C/second max. 6 minutes max. Time 25°C to Peak Temperature Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 10 Note: All temperatures refer to topside of the package. Measured on the body surface. APW7046 Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245° C , 5 SEC 1000 Hrs Bias @ 125 °C 168 Hrs, 100 % RH , 121 °C -65°C ~ 150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 1 00mA Carrier Tape & Reel Dimensions t E Po P P1 D F W Bo Ao D1 T2 Ko J C A B T1 Application A 330±1 B 62 ±1.5 D C 12.75 ± 0.15 D1 J 2 ± 0.6 Po 4.0 ± 0.1 T1 24.4 ± 0.2 P1 T2 2± 0.2 Ao W 24 ± 0.3 Bo P 12 ± 0.1 Ko E 1.75± 0.1 t SOP- 24 F 11.5 ± 0.1 1.55 +0.1 1.5+ 0.25 2.0 ± 0.1 10.9 ± 0.1 15.9± 0.1 3.1± 0.1 0.35±0.05 (mm) Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 11 www.anpec.com.tw APW7046 Cover Tape Dimensions Application SOP- 16 / 20 / 24 / 28 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 1000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright  ANPEC Electronics Corp. Rev. A. Rev.A.2 - Mar., 2002 12 www.anpec.com.tw