APW7060KC-TR

APW7060 Dual Controllers - Step Down Synchronous PWM and Linear Controller Features • Provides Two Regulated Voltages - One Synchronous DC/DC Buck Controller - One Linear Controller General Description The APW7060 integrates a synchronous buck PWM controller and a linear controller to provide two regulated voltages in a single package. The PWM controller drives external N-channel MOSFETs and operates at a fixed 600kHz frequency. When the input supply drops close to the output, the upper MOSFET remains on, achieving 100% duty cycle. Internal loop compensation is optimized for fast transient response, eliminating external compensation network. The linear controller drives an external N-channel MOSFET to form a linear regulator. The internal 0.8V reference makes this part suitable for a wide variety of low voltage applications. The APW7060 has an undervoltage lockout circuitry to ensures that both the 5VCC and 12VCC must be present before its internal circuitry is power up. Soft start is internally set to 2ms and will bring both outputs into regulation in a controlled manner. When either output goes into short, soft start will be initiated. If the short condition still remains after three cycles, both regulators will be shut down. To restart both regulators, recycle the voltage at 5VCC or 12VCC pin or momentarily pull the FB2 pin above 1.28V. The APW7060 can be shutdown by pulling the FB2 pin above 1.28V. In shutdown, all gate drive signals will be low. This dual controller is available in SO-14 package. • 0.8V Internal Reference Voltage - Both Controllers: 0.8V ± 2% Line, Load and Temp. • Output Voltage Range - PWM Controller : 0.8V to VIN - Linear Controller : 0.8V to (12VCC-VGSpass) • Full Duty Cycle Range for PWM Controller - 0% to 100% • Internal Loop Compensation for PWM Controller • Internal 2ms Soft Start and Short Circuit Protec tion for both Controllers • Both Controllers Drive N-Channel MOSFETs • Small Converter Size - 600kHz Constant Switching Frequency - Simple SO-14 Package • Shutdown Control Applications • • • • • Motherboard Graphics Cards 12V, 5V and 3.3V Inputs DC-DC Converter DSP Supplies Embedded processor and I/O supplies Pinouts LGATE GND GND 5VCC DRIVE2 FB2 NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 UGATE 12VCC NC NC NC FB NC ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 1 www.anpec.com.tw APW7060 Ordering and Marking Information APW 7060 H a n d lin g C o d e Tem p. R ange P a ck ag e C o d e P ackage C ode K : S O P -1 4 O p e ra tin g J u n c tio n T e m p . R a n g e C : 0 to 7 0 ° C H a n d lin g C o d e TU : Tube TR : Tape & R eel A P W 7060 K : A P W 7060 XXXXX X X X X X - D a te C o d e Block Diagram 5VCC 12VCC Under Voltage Lockout UVLO PW M UGATE 0.5V UVP1 Soft-Start and Fault Logic Gate Control 5VC C LGATE Inhibit / Soft-Start UVP2 FB Error Am plifier VREF 0.8V C O MP FB2 0.5V 12VC C Shutdown 1.28V Linear C ontroller DRIVE2 Oscillator F O SC 600kH z GND .ECKH/Figure 1. Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 2 www.anpec.com.tw APW7060 Typical Application R4 +12 V C8 1uF 13 4 +5V C1 1uF 5VC C L2 1uH 2. 2 VIN 2 +3.3V C 10 470uF Q3 12VC C C4 4. 7uF Q1 VIN 1 +3.3V C 2, C 3 2 x 470uF UGATE 5 D R IVE2 14 L1 1uH R 10 6. 8k C9 470pF 1 LGA TE D1 Q2 R1 590 U1 AP W 7060 9 FB 6 FB2 C 5, C 6 2 x 470uF VOU T1 +1.26 3 V /10 A VOU T2 +2.5V/3A C 11 470uF R7 2. 37k R8 1. 13k GN D GN D R2 1. 02k C7 68nF Q1 : APM2014N UC Q2 : APM2014N UC Q3 : APM2055N UC D1 : 3A Schottky Diode C2, C3, C5, C6, C10, C11 : 470uF/6.3V, ESR=30mΩ .ECKH/Figure 2. Absolute Maximum Ratings Symbol 5V CC 12V CC Parameter 5VCC Supply Voltage (5VCC to GND) 12VCC Supply Voltage (12VCC to GND) UAGTE, DRIVE2 to GND LGATE, FB, FB2 to GND Maximum Junction Temperature T STG T SDR V ESD Storage Temperature Maximum Soldering Temperature, 10 Seconds Minimum ESD Rating (Human body model) Rating -0.3 ~ 7 -0.3 ~ 15 -0.3 ~ 12V CC -0.3 ~ 5V CC 150 -65 ~ 150 300 ±2 Unit V V V V o o o 2 3 C C C KV Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in free air (SOP-14) 3 Value 160 Unit o C/W Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 www.anpec.com.tw APW7060 Recommended Operating Conditions Symbol 5V CC 12V CC V OUT1 V IN1 V OUT2 V IN2 TA TJ 5VCC Supply Voltage 12VCC Supply Voltage Output Voltage of the Buck converter Input Voltage of the Buck converter Output Voltage of the Linear Regulator Input Voltage of the Linear Regulator Ambient Temperature Junction Temperature Parameter (Note) Range 5 ± 5% 12 ± 1 0% 0.8 ~ 3.3 3.3/5 ± 5 % 0.8 ~ 3.3 3.3/5 ± 5 % 0 ~ 70 0 ~ 125 Unit V V V V V V o o C C Note : Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over 5VCC=5V, 12VCC=12V and TA= 0~70 oC. Typical values are at TA=25oC. APW7060 Symbol SUPPLY CURRENT ICC 5VCC Supply Current 12VCC Supply Current UNDER VOLTAGE LOCKOUT Rising 5VCC Threshold Falling 5VCC Threshold Rising 12VCC Threshold Falling 12VCC Threshold OSCILLATOR FOSC Free Running Frequency Ramp Upper Threshold Ramp Lower Threshold ∆VOSC VREF Ramp Amplitude Reference Voltage System Accuracy  Over Line, Load and Temperature -2 REFERENCE VOLTAGE 0.8 +2 V % 550 600 2.85 0.95 1.9 650 kHz V V VP-P 12VCC=12V 12VCC=12V 5VCC=5V 5VCC=5V 4.0 3.5 9.6 9.3 4.2 3.7 9.7 4.4 3.9 10.2 V V V V LGATE Open, FB2=DRIVE2 UGATE Open 2.5 2.5 mA mA Parameter Test Conditions Min Typ Max Unit 10.3 10.8 Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 4 www.anpec.com.tw APW7060 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over 5VCC=5V, 12VCC=12V and TA= 0~70 oC. Typical values are at TA=25oC. APW7060 Symbol Parameter Test Conditions Min Typ 75 10 1 0 100 0.1 VUAGTE=1V VUGATE=1V VLGATE=1V VLGATE=1V 0.6 7.3 0.6 1.8 50 78 1.6 1 0.1 VFB2=VREF-20mV, VDRIVE2=7V VFB2=VREF+20mV, VDRIVE2=3V DRIVE2 Open DRIVE2 Open FB or FB2 Falling 9.8 2.6 11.7 0.01 0.5 15 Max BUILT-IN PWM FEEDBACK COMPENSATION DC Gain FP FZ First Pole Frequency First Zero Frequency UGATE Duty Range FB Input Current PWM CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink TD Dead Time DC Gain Gain Bandwidth Product FB Input Current DRIVE2 Source Current DRIVE2 Sink Current DRIVE2 Output High Voltage DRIVE2 Output Low Voltage UNDER-VOLTAGE PROTECTION UVFB FB/FB2 Under-Voltage Level FB/FB2 Under-Voltage Hysteresis SOFT-START AND SHUTDOWN T SS Soft-Start Interval FB2 Shutdown Threshold FB2 Shutdown Hysteresis FB2 Rising 2 1.28 30 mS V mV V mV CL=0.5nF CL=1nF LINEAR CONTROLLER dB MHz µA mA mA V V A Ω A Ω nS dB Hz kHz % µA Unit Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 5 www.anpec.com.tw APW7060 Functional Pin Description LGATE (Pin 1) This pin provides the gate drive signal for the low side MOSFET . GND (Pin 2, 3) Signal and power ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to the ground plane through the lowest impedance connection available. 5VCC (Pin 4) This is the main bias supply for the DC/DC controller and its low side MOSFET driver. Must be closely decoupled to GND (Pin 2,3). The voltage at this pin is monitored for undervoltage lockout (UVLO) purposes. DO NOT apply a voltage greater than 5.5V to this pin. DRIVE2 (Pin 5) This pin provides the gate drive voltage for the linear regulator N-channel MOSFET pass transistor. It also provides a means of compensating the linear controller for applications where the user needs to optimize the regulator transient response. FB2 (Pin 6) Connect this pin to the output (VOUT2) of the linear regulator via a proper sized resistor divider. The voltage at this pin is regulated to 0.8V and the VOUT2 is determined using the following formula : R7 VOUT2=0.8V x (1+ R8 ) where R7 is the resistor connected from VOUT2 to FB2, and R8 is the resistor connected from FB2 to GND. This pin is also monitored for under-voltage events. Pulling and holding FB2 above 1.28V shuts down both regulators. Releasing FB2 initiates soft-start on both regulators. NC (Pin 7, 8, 10, 11, 12) No internal connection. FB (Pin 9) This pin is the inverting input of the internal error amplifier of the buck controller. Connect this pin to the output (VOUT1) of the DC/DC converter via a proper sized resistor divider to form a complete feedback loop. The VOUT1 is determined using the following formula : R1 VOUT1=0.8V x (1+ R2 ) where R1 is the resistor connected from VOUT1 to FB, and R2 is the resistor connected from FB to GND. This pin is also monitored for under-voltage events. 12VCC (Pin 13) This pin provides the supply voltage to the high side MOSFET driver and the linear controller. A voltage no greater than 13V can be connected to this pin. The voltage at this pin is monitored for undervoltage lockout (UVLO) purposes. UGATE (Pin 14) This pin provides gate drive for the high-side MOSFET. Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 6 www.anpec.com.tw APW7060 Typical Characteristics Reference Voltage vs. Junction Temperature 0.816 650 Switching Frequency vs. Junction Temperature Switching Frequency, FOSC (kHz) 640 630 620 610 600 590 580 570 560 550 -50 -25 0 25 50 75 100 125 150 Reference Voltage, VREF (V) 0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Junction Temperature (°C) Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 7 www.anpec.com.tw APW7060 Operating Waveforms - IOUT1 slew rate = ±10A/µS IOUT = 0A -> 10A VOUT1 (Refer to the typical application circuit) 1.VOUT1 Load Transient Response : IOUT = 0A -> 10A -> 0A IOUT = 0A -> 10A -> 0A VOUT1 IOUT = 10A -> 0A VOUT1 VUGATE 10A VUGATE IOUT1 0A IOUT1 IOUT1 Ch1 : VOUT1, 100mV/Div, DC, Offset = 1.25V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT1, 5A/Div Time : 5µS/Div BW = 20MHz Ch1 : VOUT1, 100mV/Div, DC, Offset = 1.25V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT1, 5A/Div Time : 5µS/Div BW = 20MHz Ch1 : VOUT1, 100mV/Div, DC, Offset = 1.25V Ax1 : IOUT1, 5A/Div Time : 100µS/Div BW = 20MHz 2.VOUT2 Load Transient Response : IOUT = 0.2A -> 3A -> 0.2A - IOUT2 slew rate = ±3A/µS IOUT = 0.2A -> 3A IOUT = 0.2A -> 3A -> 0.2A IOUT = 3A -> 0.2A VOUT2 VOUT2 3A VOUT2 IOUT2 IOUT2 0.2A IOUT2 Ch1 : VOUT2, 50mV/Div, DC, Offset = 2.50V Ax1 : IOUT2, 1A/Div Time : 1µS/Div BW = 20MHz Ch1 : VOUT2, 50mV/Div, DC, Offset = 2.50V Ax1 : IOUT2, 1A/Div Time : 50µS/Div BW = 20MHz Ch1 : VOUT2, 50mV/Div, DC, Offset = 2.50V Ax1 : IOUT2, 1A/Div Time : 1µS/Div BW = 20MHz Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 8 www.anpec.com.tw APW7060 Operating Waveforms (Cont.) 3. Powering ON / OFF Soft-start at Powering ON +12V +5V +12V +5V Powering OFF VOUT2 VOUT1 VOUT2 VOUT1 Ch1 : +5V, 1V/Div, DC Ch2 : +12V, 2V/Div, DC Ch3 : VOUT1, 1V/Div, DC Ch4 : VOUT2, 1V/Div, DC Time : 1mS/Div BW = 20MHz Ch1 : +5V, 1V/Div, DC Ch2 : +12V, 2V/Div, DC Ch3 : VOUT1, 1V/Div, DC Ch4 : VOUT2, 1V/Div, DC Time : 5mS/Div BW = 20MHz 4. UGATE and LGATE UGATE Rising IOUT=10A VUGATE VUGATE UGATE Falling IOUT=10A VLGATE VLGATE Ch1 : VUGATE, 2V/Div, DC Ch2 : VLGATE, 2V/Div, DC Time : 50nS/Div BW = 500MHz Ch1 : VUGATE, 2V/Div, DC Ch2 : VLGATE, 2V/Div, DC Time : 50nS/Div BW = 500MHz Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 9 www.anpec.com.tw APW7060 Application Information Soft Start Soft start can be initiated in several ways. One way is when the input bias supply to the 5VCC and 12VCC is above 4.2V and 10.2V respectively. The other way is when the part comes out of shutdown. In both ways, the soft start cycle will last for 2ms. During this period, the reference to the error amplifier of the PWM controller and linear controller will gradually slew up to its final value of 0.8V. This effectively will force both output voltages to track this reference ramp rate. Hence both outputs will reach regulation at the same time. Figure 3 illustrates this graphically. Maximum Output Voltage of Linear Controller The maximum drive voltage at DRIVE2 is determined by the applied voltage at 12VCC pin. Since this pin drives an external N-channel pass MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the required gate-to-source voltage to sustain the load current. VOUT2MAX = 12VCC - VGSpass Component Selection Guidelines PWM Regulator Output Capacitor The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor between 0.1uF to 1uF can be connected between 5VCC and ground pin. 10 www.anpec.com.tw Soft-start at Powering ON +12V +5V VOUT2 VOUT1 Ch1 : +5V, 1V/Div, DC Ch2 : +12V, 2V/Div, DC Ch3 : VOUT1, 1V/Div, DC Ch4 : VOUT2, 1V/Div, DC Time : 1mS/Div BW = 20MHz .ECKH/Figure 3. Linear Regulator Transient Response Optimization The linear regulator is stable over all load current. However, the transient response can be further enhanced by connecting a RC network between the FB2 and DRIVE2 pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. A good starting point for the resistor value is 6.8kΩ and 470pF for the capacitor. Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 APW7060 Application Information Inductor Selection The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current and ripple voltage can be approximated by: VIN - VOUTV OUT × Fs× L V IN PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS PLOWER = Iout2 (1+ TC)(RDS(ON))(1-D) where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss.The switching internal, tsw, is a function of the reverse transfer capacitance CRSS. Figure 4 illustrates the switching waveform of the MOSFET. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Linear Regulator Input/Output Capacitor Selection The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor will momentarily supply the required transient current. A 1uF ceramic capacitor will be sufficient in most applications. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. Linear Regulator MOSFET Selection In addition to choosing the pass MOSFET for its ability to sustain the load current requirement (see Maximum Output Voltage of Linear Controller), another criteria is its efficiency of heat removal. The power dissipated by the MOSFET is given by: Pdiss = Iout * (VIN - VOUT2) IRIPPLE = ∆VOUT = IRIPPLE x ESR where Fs is the switching frequency of the regulator. There is a tradeoff exists between the inductor’s ripple current and the regulator load transient response time A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some type of inductors, especially core that is make of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. PWM Regulator MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following : Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 11 www.anpec.com.tw APW7060 Application Information where Iout is the maximum load current Vout2 is the nominal output voltage In some applications, heatsink maybe required to help maintain the junction temperature of the MOSFET below its maximum rating. V DS • The ground return of CIN must return to the combine COUT (-) terminal. • Capacitor CHFis to improve noise performance and a small 1uF ceramic capacitor will be sufficient. Place this capacitor close of the drain of Q1. • Inductor L1 should be connected closely to the PHASE node. • Bypass capacitors, CBP, should be placed as close to the 5VCC and 12VCC pins. Voltage across drain and source of MOSFET VIN CHF 5VCC 5VCC CBP GND GND t sw Time CBP 12VCC CIN + 12VCC UGATE LGATE Figure 4. Switching waveform across MOSFET Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 5 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: Q1 PHASE Q2 + L1 C OUT APW7060 V OUT Figure 5. Recommended Layout Diagram • Keep the switching nodes (UGATE, LGATE and the PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. There fore keep traces to these nodes as short as possible. • Decoupling capacitor CIN provides the bulk capaci tance and needs to be placed close to the drain of Q1. Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 12 www.anpec.com.tw APW7060 Package Information SOP – 14 (150mil) 0 . 01 5 x 4 5 A 0 . 0 10 L D Ee B Dim A A1 B C D E e H L θ° Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0° 6.215 1.274 8° 0.228 0.015 0° Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 A1 A H E Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8° Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 13 www.anpec.com.tw APW7060 Physical Specifications Terminal Material Lead Solderability Packaging Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. 2500 devices per reel (IR/Convection or VPR Reflow) Reflow Condition temperature Reference JEDEC Standard J-STD-020A APRIL 1999 Peak temperature 183°C Pre-heat temperature Time Classification Reflow Profiles Convection or IR/ Convection 3 °C/second max. 120 seconds max. 60 ~ 150 seconds 10 ~ 20 seconds 220 +5/-0 °C or 235 +5/-0 °C 6 °C /second max. 6 minutes max. VPR 10 °C /second max. Average ramp-up rate(183 °C to Peak) Preheat temperature 125 ± 25 °C) Temperature maintained above 183 °C Time within 5 °C of actual peak temperature Peak temperature range Ramp-down rate Time 25 °C to peak temperature 60 seconds 215~ 219 °C or 235 +5/-0 °C 10 °C /second max. Package Reflow Conditions pkg. thickness ≥ 2.5mm and all bags Convection 220 +5/-0 °C VPR 215-219 °C IR/Convection 220 +5/-0 °C pkg. thickness < 2.5mm and pkg. volume ≥ 350 mm pkg. thickness < 2.5mm and pkg. volume < Convection 235 +5/-0 °C VPR 235 +5/-0 °C IR/Convection 235 +5/-0 °C Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 14 www.anpec.com.tw APW7060 Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C , 5 SEC 1000 Hrs Bias @ 125 °C 168 Hrs, 100 % RH , 121 °C -65°C ~ 150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 1 00mA Carrier Tape & Reel Dimension t Po P P1 D E F W Ao D1 Ko T2 J C A B T1 Application SOP-14 (150mil) A 330REF F 7.5 C 13.0 + 0.5 100REF - 0.2 D D1 φ0.50 + 0.1 φ1.50 (MIN) B J 2 ± 0.5 Po 4.0 T1 T2 16.5REF 2.5 ± 025 P1 2.0 Ao 6.5 W 16.0 ± 0.3 Ko 2.10 P 8 t 0.3±0.05 E 1.75 (mm) Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 15 www.anpec.com.tw APW7060 Cover Tape Dimensions Application SOP- 14 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright  ANPEC Electronics Corp. Rev. A.3 - Oct., 2003 16 www.anpec.com.tw