APW7063KC-TR

APW7063 Synchronous Buck PWM and Linear Controller Features • Provide Two Regulated Voltages - Synchronous Rectified Buck PWM Controller - Linear Controller General Description The APW7063 integrates PWM and linear controller, as well as the monitoring and protection functions into a single package. The synchronous PWM cont roller which drives dual N-channel MOSFETs, which provides one controlled power outputs with under-voltage and over-current protect ions . Linear cont roller drives an ext ernal N-c hannel MOS FE T with under-volt age protection. APW7063 provides excellent regulation for output load variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the various low output voltage applications . A PW 7063 inc ludes a 250kHz free-running t riangle-wave osc illator that is adjust able from below 70KHz to over 800KHz. A power-on-reset (POR) circuit limits the VCC minimum opearting s upply voltage to ass ure the c ontroller working well. Over current protec tion is achieved by monit oring t he volt age drop ac ros s the low s ide MOSFET, eliminating the need for a current sensing resistor and short circuit condition is detected through the FB pin. The over-current protection t riggers the soft -start function until the fault events be removed, but Under-voltage protection will shutdown IC directly. Pull the COMP pin below 0.4V will shutdown t he controller, and both gate drive signals will be low. • • Fast Transient Response - 0~85% Duty Ratio Excellent Output Voltage Regulation - 0.8V Internal Reference - ±1% Over Line Voltage and Temperature • • • Over Current Protection - Sense Low-Side MOSFET’ RDS(ON) s Under Voltage Lockout Small Converter Size - 250KHz Free-Running Oscillator - Programmable From 70kHz to 800kHz • • 14-Lead SOIC Package Lead Free Available (RoHS Compliant) Applications • • • • • Graphic Cards Memory Power Supplies DSL or Cable MODEMs Set Top Boxes Low-Voltage Distributed Power Supplies Pinouts RT SS VREG FB COMP GND PHASE 1 2 3 4 5 6 7 14 13 12 11 10 9 8 FBL DRIVE VCC LGATE PGND BOOT UGATE ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 1 www.anpec.com.tw APW7063 Ordering and Marking Information APW7063 Lead Free Code Handling Code Temp. Range Package Code Package Code K : SOP - 14 Operating Ambient Temp. Range C : 0 to 70 ° C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code APW7063 K : APW7063 XXXXX No te : ANPEC lea d-fre e p ro ducts co ntain mo ld ing comp oun ds /di e attach m ate ri als and 100 % matte ti n p la te te rmin atio n fi nish ; wh ich are full y compl iant with Ro HS and compa tibl e wi th both SnPb an d le ad-free sold ieri ng op era tio ns. AN PEC le ad-free produ cts me et or exceed th e l ead -free req uireme nts of IPC /JEDEC J STD -02 0C fo r MSL classi ficati on at lea d-fre e p eak re flo w temp era ture. Block Diagram VCC SS vcc Power-On Reset 5.8V ISS 10uA BOOT Gate Control vcc UGATE IOCSET 250uA GND Soft Start and Fault Logic PHASE VCC 50%V REF :2 U.V.P Comparator O.C.P Comparator LGATE PGND FBL 50%V REF Error Amp PWM Comparator VCC :2 VCC VREF Oscillator Triangle Wave Regulator V REF DRIVE FB COMP RT VREG C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 2 www.anpec.com.tw APW7063 Application Circuit 1. Boot-Strap - Use Internal Regulator C1 5V 12V 1uF + C2 470uF 6.3V 25mR 2 1N4148 R1 2R2 VIN R2 R3 NC NC C4 0.1uF 1 1 2 3 4 5 6 7 U1 APW7063 14 RT FBL 13 SS DRIVE 12 VREG VCC 11 FB LGATE 10 COMP PGND 9 GND BOOT 8 PHASE UGATE C11 /SHDN + C9 470uF 6.3V 25mR C10 4.7uF R5 3.125KF 1% R6 820R 0.1uF 8 7 6 5 R9 0R 4 1 2 3 Q3 APM4220 C8 1uF 8 7 6 5 4 1 2 3 L2 2.2uH R7 100R R10 2.32KF 1% C17 0.1uF + C12 1000uF 6.3V 30mR + C13 1000uF 6.3V 30mR Q2 APM4220 2.5V C3 4.7uF + C5 470uF 16V 25mR + C6 470uF 16V 25mR L1 VIN 1uH + C7 470uF 16V 25mR D1 12V Q1 APM3055L 3V3 3 R4 0R R8 1KF 1% C16 56pF D2 SR24 2A/40V C14 4.7uF C15 0.01uF R11 20K R12 1.07KF 1% 2. Boot-Strap - Use External Power 12V C1 5V 1uF + C3 470uF 6.3V 25mR 2 C2 1uF R2 2R2 VIN R1 R3 NC NC C7 0.1uF 1 1 2 3 4 5 6 7 U1 APW7063 RT FBL SS DRIVE VREG VCC FB LGATE COMP PGND GND BOOT PHASE UGATE 14 13 12 11 10 9 8 C12 /SHDN + C10 470uF 6.3V 25mR C11 4.7uF R5 3.125KF 1% R6 620R 0.1uF 8 7 6 5 R9 0R 4 1 2 3 Q3 APM4220 D1 1N4148 C8 1uF 8 7 6 5 4 1 2 3 L2 2.2uH R8 100R R10 2.32KF 1% C18 0.1uF + C13 1000uF 6.3V 30mR + C14 1000uF 6.3V 30mR Q2 APM4220 2.5V C4 4.7uF + C5 470uF 16V 25mR 12V L1 VIN 1uH + C9 470uF 16V 25mR + C6 470uF 16V 25mR Q1 APM3055L 3V3 3 R4 0R R7 1KF 1% C17 56pF D2 SR24 2A/40V C15 4.7uF C16 0.01uF R11 20K R12 1.07KF 1% C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 3 www.anpec.com.tw APW7063 Absolute Maximum Ratings Symbol VCC LGATE DRIVE UGATE VBOOT VCC to GND LGATE to GND DRIVE to GND UGATE to GND BOOT to GND PHASE to GND Operating Junction Temperature T STG TSDR VESD Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating Parameter Rating 30 30 30 30 30 30 0~150 -65 ~ 150 300 ±2 Unit V V V V V V o o o C C C KV Recommended Operating Conditions Symbol VCC VBOOT Supply Voltage Boot Voltage Parameter Min. 7 Nom. 12 Max. 19 26 Unit V V Thermal Characteristics Symbol θJA Parameter Junction to Ambient Resistance in free air (SOP-14) Value 160 Unit o C/W Electrical Characteristics Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPE N and TA = 0 ~ 70oC. Typlcal values are at TA = 25oC. Symbol SUPPLY CURRENT ICC Parameter Test Conditions APW7063 Min Typ 3 7.0 6.6 7.2 6.8 250 7.4 7.0 2 80 +15 1.7 Max Unit VCC Nominal Supply Rising VCC Threshold Falling VCC Threshold UGATE and LGATE Open mA V V kHz % VP-P POWER-ON-RESET OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 R T = OPEN, VCC = 12V 6KΩ < RT to GND < 200K Ω R T = OPEN 4 220 - 15 www.anpec.com.tw APW7063 Electrical Characteristics (Cont.) Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPE N and TA = 0 ~ 70oC. Typlcal values are at TA = 25oC. Symbol REFERENCE VREF Parameter Test Conditions APW7063 Min Typ 0.80 -1 75 0 85 0.1 +1 Max Unit Reference Voltage Reference Voltage Tolerance V % dB % uA PWM EEEOR AMPLIFIER DC Gain UGATE Duty Range FB Input Current GATE DRIVERS IUGATE RUGATE ILGATE RLGATE TD Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink Dead Time VBOOT = 12V, VUGATE = 6V IUGATE = 0.3A VCC = 12V, VLGATE = 6V ILGATE = 0.3A 550 650 800 4 700 4 50 8 8 mA Ω mA Ω nS LINEAR REGULATOR Reference Voltage Regulation Output Drive Current PROTECTION FB Under Voltage Level FBL Under Voltage Level OCSET Source Current VREG VREG IOUT T SS ISS Output Voltage Accuracy Output Current Capacity Internal Soft-Start Interval Soft-Start Charge Current Shutdown Threshold Shutdown Hysteresis COMP Falling VCC > 12V VCC = 12V C SS = 0uF 8 5.5 6 20 2 10 0.4 50 12 6.5 V mA mS uA V mV 50 50 250 % % µA VDRIVE = 4V 8 0.8 2 10 12 V % mA SOFT START and SHUTDOWN C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 5 www.anpec.com.tw APW7063 Functional Pin Description RT (Pin 1) This pin can adjust the switching frequency. Connect a resistor from RT to VCC for decreasing the switching frequency, Conversely, connect a resistor from RT to GND for increasing the s witc hing frequency (see Ty pical Characteristics). SS (Pin 2) Connect a capacitor from this pin t o GND to set the soft -start interval of t he converter. An internal 10µ A current source charges this capacitor to 5.2V. The SS voltage clamps the reference voltage to the SS voltage, and Figure1 shows the soft-start interval. At t0, the internal sourc e current starts to charge the capacitor and the internal 0.8V reference also starts to rise and follows the SS. Until the internal reference reaches to 0.8V at t2, the soft-st art interval is completed. This method provides a rapid and controlled output voltage ris e. The way of the Soft-Start of the output 2 is the same as the output1, but it starts from the SS at 2.2V to 3.0V. The A PW 7063 als o provides t he int ernal S oft-S tart whic h is fix ed to 2ms (t 0 t o t 1). If the ex ternal Soft-Start interval is slower than the internal S oft -S t art int erval (C SS < 0. 025uF) or no ex ternal capacitor, the Soft-S tart will follow t he internal SoftSt art. VREG (Pin 3) An internal regulator will s upply 6V for boost voltage, a 1uF capacitor to GND is recommended for stability. If the VREG voltage has variation by other interference, the IC can not work normally. W hen the VCC< 8V, don’ use the VREG for BOOST voltage. t FB (Pin 4) FB pin is the inverting input of the error amplifier, and it receives the feedback voltage from an external resistive divider across the output (VOUT). The output voltage is determined by : VOUT = 0.8V × 1+ t0 t1 t2 t3 VOLTAGE V SOFT START V OUT2 V OUT1 FB FBL TIME Figure 1. Soft-Start Interval C SS × 0.8V TSoft-Start = t1 - t0 = ISS C SS × 0.8V t3 = t2 + I SS Where: CSS = external Soft-Start capacitor ISS = Soft-Start current = 10µA t2 =   ROUT   RGND  where ROUT is the resistor connected from VOUT to FB, and RGND is the resistor connected from FB to GND. When the FB voltage is under 50% Vref, it will cause the under voltage protection, and shutdown the device. Remove the condition and restart the V CC voltage or pull the COMP from low to high once, will enable the device again. C SS ISS × 2.2V C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 6 www.anpec.com.tw APW7063 Functional Pin Description (Cont.) COMP (Pin 5) This pin is t he output of t he error amplifier. Add an external resis tor and capacitor network to provide the loop compens ation for t he P W M c onvert er (see A pplic at ion Information). Pull this pin below 0.4V will shutdown the controller, forcing the UGATE and LGATE signals to be 0V. A soft start cycle will be initiated upon the release of this pin. GND (Pin 6) Signal ground for the IC. PHASE (Pin 7) A resistor (ROCSET) is connected bet ween this pin and the drain of the low-side MOSFET will determine the over current limit. An internally generated 250uA current source will flow through this resistor, creating a voltage drop. This voltage will be compared with the voltage ac ross the low-side MOSFET. The threshold of t he over current limit is therefore given by : DRIVE (Pin 13) Connect this pin to the gate of an external N-channel MOS FET transis tor. This pin provides the gate voltage for the linear regulator pass transistor. It also provides a means of compensating the linear controller for applications where the user needs to optimize the regulator transient response. FBL (Pin 14) Connec t this pin to the out put of the linear regulator via a proper s ized resistor divider. The voltage at this pin is regulat ed to 0.8V and the output voltage is determined using the following formula : VOUT = 0.8V × 1 + PGND (Pin 10) Power ground for t he gate diver. Connect t he lower MOSFET source to this pin. LGATE (Pin 11) This pin provides the gate drive signal for the low side MOSFET. VCC (Pin 12) This pin provides a supply voltage for the device, when VCC is above the rising threshold 4.2V, It turns on the device is turned on, and conversely, VCC is below the falling threshold 3.9V, the device is turned off. A 1uF decoupling capacitor to GND is recommended. R OCSET = ILIMIT × R DS(ON) 250uA An over current condit ion will c yc le t he s oft st art func tion unt il the over current condition is removed. Because of the comparator delay time, so the on time of the low-side MOSFET must be longer than 800ns to have the over current protection work. UGATE (Pin 8) This pin provides gate drive for the high-side MOSFET. BOOT (Pin 9) This pin provides the supply voltage to the high side MOS FE T driver. For driving logic level N-channel MOSEFT, a boots trap circuit can be use to create a suitable driver’ supply. s   ROUT   RGND  where ROUT is the resistor connected from VOUT to FBL, and RGND is the resistor connected from FBL to GND. This pin also monitores the under-voltage events, if the linear regulator is not used, tie the FBL to VREG. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 7 www.anpec.com.tw APW7063 Typical Characteristics Power Up Power Down V CC=VIN1=12V V IN2=5V, CSS=0.1µF VCC(10V/div) VCC=VIN1 =12V VIN2=5V, CSS=0.1µF VCC(10V/div) SS(5V/div) SS(5V/div) VOUT1(2V/div) VOUT1(2V/div) VOUT2(2V/div) VOUT2(2V/div) Time (10ms/div) Time (10ms/div) Enable (COMP is left open) VCC =VIN1=12V VIN2 =5V, CSS=0.1µF Shutdown (COMP is pulled to GND) V CC=VIN1=12V V IN2=5V, CSS=0.1µF VOUT2(2V/div) VOUT2(2V/div) VOUT1(2V/div) VOUT1(2V/div) COMP(1V/div) COMP(1V/div) SS(5V/div) SS(5V/div) Time (10ms/div) Time (2ms/div) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 8 www.anpec.com.tw APW7063 Typical Characteristics (Cont.) UGATE Falling VCC=2V, VIN=12V UGATE Rising VCC=2V, VI N=12V LGATE(10V/div) LGATE(10V/div) PHASE(10V/div) PHASE(10V/div) UGATE(10V/div) UGATE(10V/div) Time (50ns/div) Time (50ns/div) Under Voltage Protection (PWM) VCC=12,VIN=12V VOUT=3.3V, L=2.2mH Under Voltage Protection (Linear) IL(10A/div) SS(5V/div) VCC=12V, VIN=5V VOUT2=2.5V SS(5V/div) VOUT1 (2V/div) UGATE (10V/div) VOUT2(2V/div) DRV(5V/div) Time (5us/div) Time (5us/div) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 9 www.anpec.com.tw APW7063 Typical Characteristics (Cont.) PWM Load Transient VCC=12V VIN=12V VOUT=3.3V COUT =470mFx2 ESR=22.5mW L=1.5mH f=400kHz Linear Load Transient VCC=12V VIN=12V VOUT=2.5V COUT=470mF VOUT2(100mV/div) VOUT1(100mV/div) IOUT2(1A/div) IOUT1(5A/div) Time (20us/div) Time (10us/div) UGATE Source Current vs. UGATE Voltage 1.4 UGATE Sink Current vs. UGATE Voltage 1.2 UGATE Source Current (A) 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 VBOOT=12V VBOOT=12V UGATE Sink Current (A) 1 0.8 0.6 0.4 0.2 0 8 10 12 0 2 4 6 8 10 12 UGATE Voltage (V) UGATE Voltage (V) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 10 www.anpec.com.tw APW7063 Typical Characteristics (Cont.) LGATE Source Current vs. LGATE Voltage 1.4 LGATE Sink Current vs. LGATE Voltage 1.2 LGATE Source Current (A) VCC=12V 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 VCC=12V LGATE Sink Current (A) 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 LGATE Voltage (V) LGATE Voltage (V) Over Current Protection VCC=12V,VIN=12V, VOUT=2.5V, ROCSET=1kW RDS(ON)=16mW, L=2.2mH, IOUT=15A Switching Frequence vs. RT Resistance 10000 IL(10A/div) RT Resistance (k Ω ) 1000 RT pull up to 12V SS(5V/div) 100 UGATE(20V/div) 10 RT pull down to GND VOUT1(2V/div) 1 10 100 1000 Time (5us/div) Switching Frequency (kHz) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 11 www.anpec.com.tw APW7063 Typical Characteristics (Cont.) Comp Sink Current vs. Comp Voltage 150 VCC=12V Comp Source Current vs. Comp Voltage 150 VCC=12V 125 125 Source Current (µA) 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current (µA) 100 75 50 25 0 100 75 50 25 0 1 1.5 2 2.5 3 3.5 4 Comp Voltage (V) Comp Voltage (V) Drive Sink Current vs. Drive Voltage 10 VCC=12V Drive Source Current vs. Drive Voltage 40 VCC=12V 8 6 Source Current (mA) 30 Sink Current (mA) 20 4 2 10 0 0 2 4 6 8 10 12 0 0 2 4 6 8 10 12 Drive Voltage (V) Drive Voltage (V) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 12 www.anpec.com.tw APW7063 Typical Characteristics (Cont.) VREG Voltage vs. Supply Voltage 6 VREG Voltage vs. Load Current 6.5 VCC=12V VREG Voltage (V) 0 2 4 6 8 10 12 14 16 18 VREG Voltage (V) 5.5 6.25 5 6 4.5 5.75 4 5.5 0 5 10 15 20 Supply Voltage (V) Load Current (mA) Supply Current vs. Supply Voltage 4 3.5 0.8 Reference Voltage vs. Temperature Reference Voltage (V) Supply Current (mA) 3 2.5 2 1.5 1 0.5 0 0 2 4 6 ICC 0.798 0.796 ICC(SHDN) 0.794 0.792 8 10 12 0.79 -40 -20 0 20 40 60 80 100 120 Supply Voltage (V) Temperature (°C) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 13 www.anpec.com.tw APW7063 Application Information Component Selection Guidelines Output Capacitor Selection The select ion of COUT is determined by the required effective series resistanc e (ES R) and voltage rat ing rat her t han the ac t ual c apac it anc e requirement . Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufac turer. Input Capacitor Selection The input capacitor is chosen based on the volt age rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than t he maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic c apacitor between 0.1uF to 1uF can be connected between VCC and ground pin. Inductor Selection The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the lower the inductor’ current ripple. This will translate s into lower output ripple voltage. The ripple current and ripple voltage can be approximated by: VIN - VOUT VOUT IRIPPLE = x VIN Fs x L where Fs is the switching frequency of the regulator. ∆VOUT = IRIPPLE x ESR C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 14 www.anpec.com.tw There is a tradeoff exists between the inductor’ ripple s current and the regulator load transient response time A smaller inductor will give the regulator a faster load trans ient res ponse at the expens e of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the induct ance value has been chosen, s elect an inductor that is capable of carrying the required peak current without going into s aturation. In s ome ty pe of induc tors, es pec ially core that is make of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Compensation The output LC filter of a step down converter introduces a double pole, which contributes with –40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network between COMP pin and ground should be added. The simplest loop compensation network is shown in Fig. 5. The out put LC filter consist s of the output induc tor and output capacitors. The transfer function of the LC filter is given by: GAINLC = 1+ s× ESR× COUT s × L × COUT + s × ESR× COUT + 1 2 The poles and zero of this transfer function are: FLC = = 1 2 × π × L × COUT 1 2 × π × ESR × COUT FESR The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. APW7063 Application Information (Cont.) Compensation (Cont.) PHASE L COUT ESR Output The compens ation circuit is shown in Figure 5. R3 and C1 introduce a zero and C2 introduces a pole to reduce t he switching noise. The transfer function of error amplifier is given by: GAINAMP = gm × Zo = gm ×  R3 +   1 1 //  sC1  sC2  Figure 2. The Output LC Filter FLC -40dB/dec FESR Gain -20dB/dec = gm × 1   s +  R3 × C1   s× s +   C1 + C2 R3 × C1 × C2    × C2 The pole and zero of the compensation network are: 1 FP = C1× C2 2 × π × R3 × C1+ C2 1 FZ = 2 × π × R3 × C1 V OUT Frequency Error Amplifier FB R2 V REF + COMP R3 C2 C1 Figure 3. The LC Filter Gain & Frequency The PWM modulator is shown in Figure. 4. The input is the output of the error amplifier and the output is the P HA SE node. The trans fer func tion of t he PW M modulator is given by: GAINPWM = R1 V IN ∆ V OSC Driver VIN Figure 5. Compensation Network The c losed loop gain of the converter c an be written as: GAINLC x GAINPWM x PWM Comparator VOSC Output of Error Amplifier Driver PHASE R2 R1+ R2 x GAINAMP Figure 6 shows the converter gain and the following guidelines will help t o des ign the c ompens at ion network. 1.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS > FO>FZ Use the following equation to calculate R3: Figure 4. The PWM Modulator C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 15 www.anpec.com.tw APW7063 Application Information (Cont.) Compensation (Cont.) losses in the MOSFET have two components: conduction s R3 = Where: ∆V OSC V IN × F ESR F LC 2 × R1 + R2 R2 × FO gm loss and t rans it ion loss. For t he upper and lower MOSFET, t he losses are approximately given by the following : PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS 2 gm = 900uA/V 2.Place the zero FZ before the LC filter double poles FLC: FZ = 0.75 x FLC Calculate the C1 by the equation: PLOWER = Iout (1+ TC)(RDS(ON))(1-D) 2 where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss. The switching internal, tsw, is a function of the reverse transfer capac it anc e CRSS. Figure 7 illustrat es t he switching waveform internal of the MOSFET. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs FZ =0.75FLC 20 ⋅log(gm⋅R3) C1 = 1 2 × π × R1 × 0.75 × FLC 3. Set the pole at the half the switching frequency: FP = 0.5xFS Calculate the C2 by the equation: C2 = C1 π × R3 × C1 × F S − 1 Temperature” curve of the power MOSFET . FP=0.5FS Linear Regulator Input/Output Capacitor Selection The input capacitor is chos en based on it s voltage rating. Under load transient condition, the input capacitor will momentarily supply the required transient current. Compensation Gain Gain FLC 20 ⋅ log VIN ? VOSC FO FESR PWM & Filter Gain Converter Gain A 1uF ceramic c apac it or will be sufficient inmost applications. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. Linear Regulator MOSFET Selection Frequency Figure 6. Converter Gain & Frequency MOSFET Selection The maximum DRIVE voltage is determined by the VCC. The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum out put current requirement.The Since this pin drives an external N-channel MOSFET, therefore t he max imum output volt age of the linear regulator is dependent upon the VGS. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 16 www.anpec.com.tw APW7063 Application Information (Cont.) MOSFET Selection (Cont.) VOUT2MAX = VCC- VGS Another criteria is its efficiency of heat removal. The Voltage across drain and source of MOSFET VDS power dissipated by the MOSFET is given by: Pdiss = Iout * (VIN - VOUT2) where Iout is the maximum load current Vout2 is the nominal output voltage In some applications, heatsink maybe required to help maint ain the junction temperature of the MOSFET below its maximum rating. Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, int erconnec ting impedanc es should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane cons truction or single point grounding. Figure 8 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: t sw Time Figure 7. Switching waveform across MOSFET VIN APW7063 PGND 11 C IN + LGATE 12 U 9 1 UGATE PHASE 8 C OUT Q1 Q2 L1 + • Keep t he switching nodes (UGATE, LGATE and PHA SE) away from s ensit ive small signal nodes since these nodes are fast moving signals. Therefore keep traces to these nodes as short as possible. L O A D VO U T Figure 8. Recommended Layout Diagram • The ground return of CIN must return to the combine COUT (-) terminal. • Capacitor CBOOT s hould be connected as close to the BOOT and PHASE pins as possible. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 17 www.anpec.com.tw APW7063 Package Information SOP – 14 (150mil) 0 . 0 1 5 x4 5 A 0.010 L D Ee B Dim A A1 B C D E e H L θ° Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0° 6.215 1.274 8° 0.228 0.015 0° Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 A1 A H E Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8° C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 18 www.anpec.com.tw APW7063 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. (IR/Convection or VPR Reflow) Reflow Condition TP Ramp-up tp Critical Zone T L to T P TL Temperature tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 C to Peak ° Time Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate 3°C/second max. 3°C/second max. (TL to T P) Preheat 100°C 150°C - Temperature Min (Tsmin) 150°C 200°C - Temperature Max (Tsmax) 60-120 seconds 60-180 seconds - Time (min to max) (ts) Time maintained above: 183°C 217°C - Temperature (TL) 60-150 seconds 60-150 seconds - Time (t L) Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5 °C of actual 10-30 seconds 20-40 seconds Peak Temperature (tp) Ramp-down Rate 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25 °C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 19 www.anpec.com.tw APW7063 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures Package Thickness Volume mm3