APW7068QAE-TRL

APW7068 Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage Features • Two Regulated Voltages and REF_OUT - Synchronous Buck Converter - Linear Regulator - REF_OUT = 0.8V±1% with 3mA source current General Description The APW7068 integrates synchronous buck PWM, linear controller, and 0.8V Reference Out Voltage, as well as the monitoring and protection functions into a single package. The fixed 300KHz switching frequency synchronous PWM controller drives dual N-channel MOSFETs, which provides one controlled power output with over-voltage and over-current protections. Linear controller drives an external N-channel MOSFET with under-voltage protection. The APW7068 provides excellent regulation for output load variation. An internal 0.8V temperaturecompensated reference voltage is designed to meet the requirement of low output voltage applications. The APW7068 with excellent protection functions: POR, OCP, OVP and UVP. The Power-On Reset (POR) circuit can monitor VCC12 supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides both outputs with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the lower MOSFET’ RDS(ON), s comparing with the voltage of OCSET pin. When the output current reaches the trip point, the controller will • • Single 12V Power Supply Required Excellent Both Output Voltage Regulation - 0.8V Internal Reference - ±1% Over Line Voltage and Temperature • • • • • • • • Integrated Soft-Start for PWM and Linear Outputs 300KHz Fixed Switching Frequency Voltage Mode PWM Control Design and Up to 89%(Typ.) Duty Cycle Under-Voltage Protection Monitoring Linear Output Over-Voltage Protection Monitoring PWM Output Over-Current Protection for PWM Output - Sense Low-side MOSFET’ RDS(ON) s SOP-14, QSOP-16 and QFN-16 packages Lead Free Available (RoHS Compliant) Applications • Graphic Cards shutdown the IC directly, and latch the converter’ s output. The Under-Voltage Protection (UVP) monitors the voltage of FBL pin for short-circuit protection. When the VFBL is less than 50% of VREF, the controller will shutdown the IC directly. The Over-Voltage Protection (OVP) monitors the voltage of FB. When the VFB is over 135% of V REF, the controller will make Lowside gate signal fully turn on until the fault events are removed. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 1 www.anpec.com.tw APW7068 Pinouts FS_DIS UGATE 14 PHASE 13 12 Metal GND Pad (Bottom) 11 10 9 5 AGND 6 DGND 7 VCC12 8 VCC12 BOOT 15 16 BOOT FS_DIS COMP FB DRIVE FBL GND 1 2 3 4 5 6 7 14 UGATE 13 PHASE 12 PGND 11 LGATE 10 OCSET 9 8 REF_OUT VCC12 BOOT FS_DIS COMP FB DRIVE FBL GND GND SOP-14 TOP VIEW 1 2 3 4 5 6 7 8 16 UGATE 15 PHASE 14 PGND 13 LGATE 12 OCSET 11 REF_OUT 10 VCC12 9 VCC12 DRIVE FBL 3 4 COMP FB 1 2 PGND LGATE OCSET REF_OUT QSOP-16 TOP VIEW QFN-16 TOP VIEW Ordering and Marking Information APW7068 Lead Free Code Handling Code Temp. Range Package Code APW7068 K : APW7068 M : APW7068 XXXXX APW7068 XXXXX APW7068 XXXXX Package Code K : SOP - 14 M : QSOP - 16 QA : QFN - 16 Temp. Range E : -20 to 70 °C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code XXXXX - Date Code APW7068 Q : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 2 www.anpec.com.tw APW7068 Block Diagram VCC12 OCSET IOCSET 40uA REF_OUT Reference Buffer Regulator Power-On Reset BOOT GND VREF (0.8V) 135%VREF X1.35 10V Soft Start and Fault Logic O.C.P Comparator UGATE O.V.P Comparator PHASE Sense Low Side Gate Control LGATE Error Amp 1 PGND PWM Comparator U.V.P Comparator 10V :2 50%VREF FBL VREF Oscillator Sawtooth Wave (300KHz) VREF Error Amp 2 DRIVE FB COMP FS_DIS Absolute Maximum Ratings Symbol VCC12 BOOT UGATE LGATE PHASE DRIVE VCC12 to GND BOOT to PHASE UGATE to PHASE LGATE to PGND PHASE to GND DRIVE to GND 400ns pulse width 400ns pulse width 400ns pulse width Parameter Rating -0.3 to +16 -0.3 to +16 -5 to BOOT+5 -0.3 to BOOT+0.3 -5 to VCC12+5 -0.3 to VCC12+0.3 -5 to +21 -0.3 to 16 12 -0.3 to 7 Unit V V V V V V V www.anpec.com.tw FB, FBL, COMP, FB, FBL, COMP, FS_DIS to GND FS_DIS C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 3 APW7068 Absolute Maximum Ratings (Cont.) Symbol PGND TJ TSTG TSDR VESD PGND to GND Junction Temperature Range Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating Parameter Rating -0.3 to +0.3 -20 to +150 -65 ~ 150 300 ±2 Unit V °C °C °C KV NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE2: The device is ESD sensitive. Handling precautions are recommended. Recommended Operating Conditions Symbol VCC12 VIN1 VOUT1 IOUT1 IOUT2 TA TJ IC Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Linear Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 to 13.2 2.9 to 13.2 0.9 to 5 0 to 30 0 to 3 -20 to 70 -20 to 125 Unit V V V A A °C °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7068 Min Typ Max Unit INPUT SUPPLY CURRENT VCC12 Supply Current (Shutdown mode) VCC12 Supply Current POWER-ON RESET Rising VCC12 Threshold Falling VCC12 Threshold OSCILLATOR Accuracy FOSC VOSC Duty Oscillator Frequency Ramp Amplitude Maximum Duty Cycle 4 ICC12 UGATE, LGATE and DRIVE open; FS_DIS=GND UGATE, LGATE and DRIVE open 7.7 7.2 4 8 6 12 mA mA 7.9 7.4 8.1 7.6 V V -15 255 (nominal 1.2V to 2.7V) (NOTE3) 300 1.5 89 +15 345 % KHz V % C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 www.anpec.com.tw APW7068 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol REFERENCE VREF Parameter Test Conditions APW7068 Min Typ Max Unit Reference Voltage Reference Voltage Tolerance PWM Load Regulation Linear Load Regulation for Error Amp1 and Amp2 IOUT1=0 to 10A IOUT2=0 to 3A RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) VFB=0.8V 0.792 0.80 0.808 -1 +1 1 1 93 20 8 0.1 5 0 1 V % % % dB MHz V/us uA V V mA mA A A A A Ω Ω Ω Ω nS dB MHz V/us PWM ERROR AMPLIFIER Gain GBWP SR VCOMP VCOMP ICOMP ICOMP Open Loop Gain Open Loop Bandwidth Slew Rate FB Input Current COMP High Voltage COMP Low Voltage COMP Source Current COMP Sink Current COMP=2V COMP=2V BOOT=12V, UGATE-PHASE = 2V VCC12=12V, LGATE=2V 12 12 2.5 2 2.5 3.5 2.25 3.375 0.7 0.4 20 1.05 0.6 2.25 3.375 GATE DRIVERS IUGATE Upper Gate Source Current IUGATE ILGATE ILGATE RUGATE RUGATE RLGATE RLGATE TD Gain GBWP SR VDRIVE VDRIVE IDRIVE IDRIVE Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current Upper Gate Sink Impedance Lower Gate Sink Impedance Dead Time Open Loop Gain Open Loop Bandwidth Slew Rate FBL Input Current DRIVE High Voltage DRIVE Low Voltage DRIVE Source Current DRIVE Sink Current Upper Gate Source Impedance BOOT=12V, IUGATE=0.1A BOOT=12V, IUGATE=0.1A VCC12=12V, ILGATE=0.1A Lower Gate Source Impedance VCC12=12V, ILGATE=0.1A LINEAR REGULATOR RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) RL=10k, CL=10pF (NOTE3) VFBL=0.8V 70 19 6 0.1 10 0 DRIVE=5V DRIVE=5V 4 3 1 uA V V mA mA C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 5 www.anpec.com.tw APW7068 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol PROTECTION Parameter Test Conditions APW7068 Min Typ 135 50 36 40 8.5 0.792 0.800 0.808 -8 1.5 0.25 0.4 3 0.5 1 2.2 +8 44 Max Unit VFB-OV FB Over Voltage Protection Trip Point IOCSET TSS OCSET Current Source Internal Soft-Start Interval (NOTE3) Percent of VREF % % uA ms V mV mA mA uF VFBL-UV FBL Under Voltage Protection Trip Point Percent of VREF SOFT START FOSC=300kHz REF_OUT VREF_OUT Output Voltage Offset Voltage IREF_OUT Source Current Sink Current Output Capacitance NOTE3: Guaranteed by design. Typical Application Circuit C1 2.2nF Q3 R2 3.9K 2N7002 ON/OFF Q1 APM2509 CIN1 470uFx2 VIN1 12V C2 0.01uF C4 R1 0.1uF 1.5K L 1uH VOUT1 1.2V VOUT1 R3 22Ω C3 22nF 1 2 3 BOOT FS_DIS COMP FB DRIVE FBL GND UGATE PHASE 14 13 C6 2.2nF VIN2 3.3V RGND1 3K COUT1 470uFx2 PGND 12 Q2 LGATE OCSET REF_OUT VCC12 11 10 9 8 C8 1uF APM2506 CIN2 470uF Q4 APM3055 4 5 C5 R5 6 7 2.2Ω R6 R4 VOUT2 2.5V 2.5K APW7068 RGND2 1.17K R7 12V R8 2.2Ω COUT2 470uF C7 1uF * C5, R5 for specific application C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 6 www.anpec.com.tw APW7068 Function Pin Descriptions VCC12 Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. BOOT This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal diode, and the power supply valtage VCC12, generates the bootstrap voltage for the upper gate diver (UGATE). PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the lower MOSFET for over-current protection. GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for over-voltage protection. When the FB voltage is over 135% of reference voltage, the controller will make Low-side gate signal fully turn on until the fault events are removed. UGATE This pin is the gate driver for the upper MOSFET of PWM output. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 7 www.anpec.com.tw LGATE This pin is the gate driver for the lower MOSFET of PWM output. DRIVE This pin drives the gate of an external N-channel MOSFET for linear regulator. It is also used to set the compensation for some specific applications,for example, with low values of output capacitance and ESR. FBL This pin is the inverting input of the linear regulator error amplifier. It is used to set the output voltage. This pin is also monitored for under-voltage protection. When the FBL voltage is under 50% of reference voltage (0.4V), both outputs will be shutdown immediately. OCSET Connect a resistor (Rocset) from this pin to GND, an internal 40uA current source will flow through this resistor and create a voltage drop. When VCC12 reaches the POR rising threshold voltage, the voltage drop of Rocset will be memoried and compared with the voltage across the lower MOSFET. The threshold of the over current limit is therefore given by: ILIMIT = IOCSET × ROCSET RDS(ON)(LOW − Side) REF_OUT This pin provides a buffed voltage, which is from internal reference voltage. It is recommended that a 1uF capacitor is connected to ground for stability. FS_DIS This pin provides shutdown function. Use an open drain logic signal to pull this pin low to disable both outputs, leave open to enable both outputs. APW7068 Typical Characteristics Power On VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH Power Off VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 10ms/div CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 10ms/div EN VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH Shutdown(FS_DIS=GND) VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 10ms/div CH4 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 10ms/div C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 8 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) UGATE Rising Vcc12=12V, Vin1=12V, Vo1=1.2V UGATE Falling Vcc12=12V, Vin1=12V, Vo1=1.2V CH1 CH1 CH2 CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div OVP_PWM Controller (FB > 135% VREF) Vcc12=12V, Vin1=12V Vo1=1.2V, Vo2=2.5V,L=1uH UVP_Linear Regulator (FBL< 50% VREF) VCC12=12V, Vin2=3.3V Vo2=2.5V, Io2=3A CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH1: VCC (20V/div) CH2: LG (10V/div) CH3: Vo1 (500mV/div) CH4: Vo2 (2V/div) Time: 10ms/div CH1: FBL (1V/div) CH2: Drive (5V/div) CH3: Vo2 (2V/div) Time: 100us/div C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 9 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) Load Transient Response(PWM Controller) - VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz - Io1 slew rate= ± 10 A/us Io1=0Aà10A Io1=0Aà10Aà0A Io1=10Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH3 CH3 CH3 CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 50us/div CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div Load Transient Response(Linear Regulator) - VCC12=12V, Vin2=3.3V, Vo2=2.5V - Io2 slew rate= ± 3A/us Io2=0Aà3A Io2=0Aà3Aà0A Io2=3Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 10us/div CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 10 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) Over Current Protection VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1KΩ , Rds(on)=4mΩ Short Test after Power Ready VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1KΩ , Rds(on)=4mΩ CH1 CH2 CH1 CH2 CH3 CH3 CH4 CH4 CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div Short Test before Power On VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH 0.804 VREF vs. Junction Temperature COUT=470uFx2 0.8035 Reference Voltage(V) CH1 0.803 CH2 0.8025 0.802 CH3 VREF 0.8015 0.801 CH4 0.8005 -40 -20 0 20 40 60 80 100 120 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 2ms/div C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 Junction Temperature (°C ) 11 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 3.5 3 UGATE Source Current (A) 2.5 VBOOT=12V 3 VBOOT=12V UGATE Sink Current (A) PHASE=0V PHASE=0V 2.5 2 1.5 1 0.5 0 2 1.5 1 0.5 0 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 UGATE Voltage (V) UGATE Voltage (V) LGATE Source Current vs. LGATE Voltage 3 LGATE Sink Current vs. LGATE Voltage 7 6 LGATE Source Current (A) 2.5 VCC=12V VCC=12V LGATE Sink Current (A) 0 2 4 6 8 10 12 5 4 3 2 1 0 0 1 2 3 4 2 1.5 1 0.5 0 LGATE Voltage (V) LGATE Voltage (V) C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 12 www.anpec.com.tw APW7068 Function Descriptions Power On Reset (POR) The Power-On Reset (POR) function of APW7068 continually monitors the input supply voltage (VCC12), ensures the supply voltage exceed its rising POR threshold voltage. The POR function initiates soft-start interval operation while VCC12 voltages exceed their POR threshold and inhibits operation under disabled status. Soft-Start Figure 1. shows the soft-start interval. When VCC12 reaches the rising POR threshold voltage, the internal reference voltage is controlled to follow a voltage proportional to the soft-start voltage. The soft-start interval is variable by the oscillator frequency. The formulation is given by: T SS = ∆ (t 2 − t1 ) = 1 × 2 560 F OSC Voltage(V) FB t0 t1 t2 Time VOUT1 VOUT2 POR VCC12 Voltage(V) Figure 1. Soft-Start Interval 20mV 32/Fosc FBL Figure 2. shows more detail of the FB and FBL voltage ramps. The FB and FBL voltage soft-start ramps are formed with many small steps of voltage. The voltage of one step is about 20mV in FB and FBL, and the period of one step is about 64/FOSC. This method provides a controlled voltage rise and prevents the large peak current to charge output capacitor. The FB voltage compares the FBL voltage to shift to an earlier time the establishment as Figure2. The voltage estabilishment time difference for FB and FBL is variable by the oscillator. The formulation is given by: Over-Current Protection t3 t4 32/Fosc 20mV Time Figure 2. The Controlled Stepped FB and FBL Voltage during Soft-Start Connect a resistor (Rocset) from this pin to GND, an internal 40uA current source will flow through this resistor and create a voltage drop, which will be compared with the voltage across the lower MOSFET. ∆(t4 − t3) = 1 1 × 640 = × TSS FOSC 4 When the voltage across the lower MOSFET exceeds the voltage drop across the ROCSET, an over-current condition is detected and the controller will shutdown the IC directly, and the converter's output is latched. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 13 www.anpec.com.tw APW7068 Function Descriptions Over-Current Protection (Cont.) The threshold of the over current limit is therefore given by: voltage is over 135% of the reference voltage, the controller will make Low-Side gate signal fully turn on until the fault events are removed. ILIMIT = IOCSET × ROCSET RDS(ON)(LOW − Side) Under Voltage Protection The FBL pin is monitored during converter operation by its own Under Voltage(UV) comparator. If the FBL voltage drop below 50% of the reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both highside and low-side MOSFET and the converter’ outs put is latched to be floating. The controller will shutdown the IC directly. Shutdown and Enable Pulling the FS_DIS voltage to GND by an open drain transistor, shown in typical application circuit, shutdown the APW7068 PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. ·The MOSFET’ RDS(ON) is varied by temperature and s gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’ datasheet. s · The minimum IOCSET (36uA) and minimum ROCSET should be used in the above equation. · Note that the ILIMIT is the current flow through the lower MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. Over Voltage Protection The FB pin is monitored during converter operation by its own Over Voltage(OV) comparator. If the FB Application Information Output Voltage Selection The output voltage of PWM converter can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: The linear regulator output voltage VOUT2 is also set by means of an external resistor divider. The FBL pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by:  R1   VOUT1 = 0.8 ×  1 + R  GND1   Where R1 is the resistor connected from VOUT1 to FB and RGND1 is the resistor connected from FB to GND. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 14  R4 VOUT2 = 0.8 ×  1 +  R GND2      Where R4 is the resistor connected from VOUT2 to FBL and RGND2 is the resistor connected from FBL to GND. www.anpec.com.tw APW7068 Application Information (Cont.) Linear Regulator Input/Output Capacitor Selection The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor will momentarily supply the required transient current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. Linear Regulator Input/Output MOSFET Selection The maximum DRIVE voltage is about 10V when VCC12 is equal 12V. Since this pin drives an external N-channel MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the VGS. V OUT2MAX = 10 - VGS Another criterion is its efficiency of heat removal. The power dissipated by the MOSFET is given by: PHASE L OUTPUT1 loop. A compensation network among COMP, FB and VOUT1 should be added. The compensation network is shown in Fig. 9. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by: GAINLC = 1 + s × ESR × COUT1 s × L × COUT1 + s × ESR × COUT1 + 1 2 The poles and zero of this transfer functions are: FLC = 1 2 × π × L × C OUT1 FESR = 1 2 × π × ESR × C OUT1 The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. Pd = IOUT2 x (VIN – V OUT2 ) Where IOUT2 is the maximum load current, VOUT2 is the nominal output voltage. In some applications, heatsink might be required to help maintain the junction temperature of the MOSFET below its maximum rating. Linear Regulator Compensation Selection The linear regulator is stable over all loads current. However, the transient response can be further enhanced DRIVE pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 15 Frequency(Hz) GAIN (dB) FLC -40dB/dec COUT1 ESR Figure 6. The Output LC Filter by connecting a RC network between the FBL and FESR -20dB/dec Figure 7. The LC Filter GAIN and Frequency www.anpec.com.tw APW7068 Application Information (Cont.) PWM Compensation (Cont.) The PWM modulator is shown in Figure 8. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: V OUT1 R1 FB V REF V COMP R3 C3 R2 C1 C2 GAINPWM = VIN1 ∆VOSC Driver Figure 9. Compensation Network VIN The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP PHASE OSC ΔVOSC PWM Comparator Output of Error Amplifier Driver Figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: R2 = ∆VOSC FO × × R1 VIN FLC Figure 8. The PWM Modulator The compensation network is shown in Figure 9. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: VCOMP VOUT1 1 1 //  R2 +  sC1  sC2  = 1  R1// R3 +  sC3   GAINAMP =  1 1    s +  × s + (R1 + R3 ) × C3  R2 × C2   R1 + R3    = × C1 + C2   1 R1 × R3 × C1   s s +  × s +  R2 × C1 × C2   R3 × C3   3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the equation: C2 = 1 2 × π × R2 × FLC × 0.75 The poles and zeros of the transfer function are: 1 F Z1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3 ) × C3 1 FP1 =  C1 × C2  2 × π × R2 ×    C1 + C2  FP2 = 1 2 × π × R3 × C3 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C1 = 16 C2 2 × π × R2 × C2 × FESR − 1 www.anpec.com.tw C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 APW7068 Application Information (Cont.) PWM Compensation (Cont.) 5.Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations: R3 = R1 FS −1 2 × FLC and ripple voltage can be approximated by: IRIPPLE = VIN1 − VOUT1 VOUT1 × FS × L VIN1 ∆VOUT1 = IRIPPLE × ESR where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor’ ripple current and the s regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. 1 C3 = π × R3 × FS F Z1 F Z2 F P1 F P2 Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. GAIN (dB) 20log (R2/R1) 20log (VIN /Δ V OSC ) Compensation Gain F LC F ESR PWM & Filter Gain Frequency(Hz) Converter Gain Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested 17 www.anpec.com.tw Figure 10. Converter Gain and Frequency Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor’ ripple current and s induces lower output ripple voltage. The ripple current C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 APW7068 Application Information (Cont.) Output Capacitor Selection (Cont.) by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT1/2, where IOUT1 is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT1/2, where IOUT1 is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 18 capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D) Where IOUT1 is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW , is a function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Layout Considerations In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz or above, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit genwww.anpec.com.tw APW7068 Application Information (Cont.) Layout Considerations (Cont.) erates a large voltage spike during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. Figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - The metal plate of the bottom of the packages (QFN-16) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG, DRIVE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and REF_OUT capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 19 www.anpec.com.tw the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN1 and PHASE nodes) should be a large plane for heat sinking. APW7068 VIN1 VCC12 VIN2 BOOT DRIVE VOUT2 L O A D UGATE PHASE L O A D FBL LGATE REF_OUT VOUT1 Figure 11. Layout Guidelines APW7068 Package Information SOP – 14 (150mil) E H 0.015 x 45 D C A e B GAUGE PLANE SEATING PLANE A1 0.010 L Dim A A1 B C D E e H L θ° Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0° 6.215 1.274 8° 0.228 0.015 0° Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8° C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 20 www.anpec.com.tw APW7068 Package Information QSOP-16 D E E1 GAUGE PLANE 1 2 3 A e b A1 L 1 Millimeters Dim A A1 b D E E1 e L φ1 Min. 1.35 0.10 0.20 4.80 5.79 3.81 0.635 TYP. 0.41 0° 1.27 8° 0.016 0° Max. 1.75 0.25 0.30 5.00 6.20 3.99 Min. 0.053 0.004 0.008 0.189 0.228 0.150 Inches Max. 0.069 0.010 0.012 0.197 0.244 0.157 0.025 TYP. 0.050 8° C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 21 www.anpec.com.tw APW7068 Packaging Information QFN-16 D e b E E2 L D2 A2 A3 Dim A A1 A2 A3 D E b D2 E2 e L C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 A A1 Millimeters Min. 0.76 0.00 0.57 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.650 BSC 0.50 0.60 0.002 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.0257BSC 0.024 Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.008 REF. 0.161 0.161 0.014 0.085 0.085 Inches Max. 0.033 0.0015 0.025 22 www.anpec.com.tw APW7068 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition TP (IR/Convection or VPR Reflow) tp Critical Zone T L to T P Ramp-up Temperature TL Tsmax tL Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 23 www.anpec.com.tw APW7068 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 P ackage Thickness Volum e m m Volume mm < 350 ≥ 350 < 2.5 m m 240 +0/-5 ° C 225 +0/-5 ° C ≥ 2.5 m m 225 +0/-5 ° C 225 +0/-5 ° C T able 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 P ackage Thickness Volume mm Volume mm Volume mm < 350 3 50-2000 > 2000 < 1.6 m m 260 +0 ° C* 260 +0 ° C* 260 +0 ° C* 1 .6 m m – 2.5 m m 260 +0 ° C* 250 +0 ° C* 245 +0 ° C* ≥ 2.5 m m 250 +0 ° C* 245 +0 ° C* 245 +0 ° C* * Tolerance: The device manufacturer/supplier s hall a ssure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 ° C. For example 260 ° C+0 ° C) at the rated MSL level. Reliability Test Program Test item S OLDERABILITY H OLT P CT T ST E SD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125 °C 168 Hrs, 100 % RH, 121°C -65°C~150 °C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 1 00mA Carrier Tape & Reel Dimensions t P P1 D Po E F W Bo Ao Ko D1 C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 24 www.anpec.com.tw APW7068 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application SOP-14 (150mil) Application A 330REF F 7.5 A 330 ± 1 B 100REF D C 13.0 + 0.5 - 0.2 D1 J 2 ± 0.5 Po 4.0 J T1 16.5REF P1 2.0 T1 12.4 ± 0.2 P1 T2 W P 8 t 0.3±0.05 P 8± 0.1 Ko E 1.75 2.5 ± 025 16.0 ± 0.3 Ao 6.5 T2 2 ± 0.2 Ao 6.4 ± 0.1 Ko 2.10 W 12± 0. 3 Bo 5.2± 0. 1 φ0.50 + 0.1 φ1.50 (MIN) B 62 +1.5 D 1.55 +0.1 C E 1.75±0.1 t 12.75+ 0.15 2 ± 0.5 D1 Po QSOP- 16 F 5.5± 1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 2.1± 0.1 0.3±0.013 (mm) 4x4 Shipping Tray C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 25 www.anpec.com.tw APW7068 4x4 Shipping Tray (Cont.) Cover Tape Dimensions Application SOP- 14 QSOP- 16 Carrier Width 24 12 Cover Tape Width 21.3 9.3 Devices Per Reel 2500 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 C opyright © A NPEC Electronics Corp. Rev. A.2 - Jun., 2006 26 www.anpec.com.tw